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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tahiti -fp-contract=on < %s | FileCheck -check-prefixes=SI,SI-STRICT %s3; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=verde -fp-contract=on < %s | FileCheck -check-prefixes=SI,SI-STRICT %s4; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tahiti -fp-contract=fast < %s | FileCheck -check-prefixes=SI,SI-CONTRACT %s5; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=verde -fp-contract=fast < %s | FileCheck -check-prefixes=SI,SI-CONTRACT %s6; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global -fp-contract=on < %s | FileCheck -check-prefixes=VI,VI-STRICT %s7; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global -fp-contract=fast < %s | FileCheck -check-prefixes=VI,VI-CONTRACT %s8 9define amdgpu_kernel void @fmuladd_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1, ptr addrspace(1) %in2, ptr addrspace(1) %in3) #0 {10; SI-LABEL: fmuladd_f64:11; SI: ; %bb.0:12; SI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x913; SI-NEXT: s_mov_b32 s11, 0xf00014; SI-NEXT: s_mov_b32 s10, -115; SI-NEXT: s_mov_b32 s14, s1016; SI-NEXT: s_mov_b32 s15, s1117; SI-NEXT: s_waitcnt lgkmcnt(0)18; SI-NEXT: s_mov_b32 s12, s219; SI-NEXT: s_mov_b32 s13, s320; SI-NEXT: s_mov_b32 s16, s421; SI-NEXT: s_mov_b32 s17, s522; SI-NEXT: s_mov_b32 s18, s1023; SI-NEXT: s_mov_b32 s19, s1124; SI-NEXT: s_mov_b32 s4, s625; SI-NEXT: s_mov_b32 s5, s726; SI-NEXT: s_mov_b32 s6, s1027; SI-NEXT: s_mov_b32 s7, s1128; SI-NEXT: buffer_load_dwordx2 v[0:1], off, s[12:15], 029; SI-NEXT: buffer_load_dwordx2 v[2:3], off, s[16:19], 030; SI-NEXT: buffer_load_dwordx2 v[4:5], off, s[4:7], 031; SI-NEXT: s_mov_b32 s8, s032; SI-NEXT: s_mov_b32 s9, s133; SI-NEXT: s_waitcnt vmcnt(0)34; SI-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[4:5]35; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 036; SI-NEXT: s_endpgm37;38; VI-LABEL: fmuladd_f64:39; VI: ; %bb.0:40; VI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x2441; VI-NEXT: s_mov_b32 s11, 0xf00042; VI-NEXT: s_mov_b32 s10, -143; VI-NEXT: s_mov_b32 s14, s1044; VI-NEXT: s_mov_b32 s15, s1145; VI-NEXT: s_waitcnt lgkmcnt(0)46; VI-NEXT: s_mov_b32 s12, s247; VI-NEXT: s_mov_b32 s13, s348; VI-NEXT: s_mov_b32 s16, s449; VI-NEXT: s_mov_b32 s17, s550; VI-NEXT: s_mov_b32 s18, s1051; VI-NEXT: s_mov_b32 s19, s1152; VI-NEXT: s_mov_b32 s4, s653; VI-NEXT: s_mov_b32 s5, s754; VI-NEXT: s_mov_b32 s6, s1055; VI-NEXT: s_mov_b32 s7, s1156; VI-NEXT: buffer_load_dwordx2 v[0:1], off, s[12:15], 057; VI-NEXT: buffer_load_dwordx2 v[2:3], off, s[16:19], 058; VI-NEXT: buffer_load_dwordx2 v[4:5], off, s[4:7], 059; VI-NEXT: s_mov_b32 s8, s060; VI-NEXT: s_mov_b32 s9, s161; VI-NEXT: s_waitcnt vmcnt(0)62; VI-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[4:5]63; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 064; VI-NEXT: s_endpgm65 %r0 = load double, ptr addrspace(1) %in166 %r1 = load double, ptr addrspace(1) %in267 %r2 = load double, ptr addrspace(1) %in368 %r3 = tail call double @llvm.fmuladd.f64(double %r0, double %r1, double %r2)69 store double %r3, ptr addrspace(1) %out70 ret void71}72 73define amdgpu_kernel void @fmul_fadd_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1, ptr addrspace(1) %in2, ptr addrspace(1) %in3) #0 {74; SI-STRICT-LABEL: fmul_fadd_f64:75; SI-STRICT: ; %bb.0:76; SI-STRICT-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x977; SI-STRICT-NEXT: s_mov_b32 s11, 0xf00078; SI-STRICT-NEXT: s_mov_b32 s10, -179; SI-STRICT-NEXT: s_mov_b32 s14, s1080; SI-STRICT-NEXT: s_mov_b32 s15, s1181; SI-STRICT-NEXT: s_waitcnt lgkmcnt(0)82; SI-STRICT-NEXT: s_mov_b32 s12, s283; SI-STRICT-NEXT: s_mov_b32 s13, s384; SI-STRICT-NEXT: s_mov_b32 s16, s485; SI-STRICT-NEXT: s_mov_b32 s17, s586; SI-STRICT-NEXT: s_mov_b32 s18, s1087; SI-STRICT-NEXT: s_mov_b32 s19, s1188; SI-STRICT-NEXT: buffer_load_dwordx2 v[0:1], off, s[12:15], 089; SI-STRICT-NEXT: buffer_load_dwordx2 v[2:3], off, s[16:19], 090; SI-STRICT-NEXT: s_mov_b32 s4, s691; SI-STRICT-NEXT: s_mov_b32 s5, s792; SI-STRICT-NEXT: s_mov_b32 s6, s1093; SI-STRICT-NEXT: s_mov_b32 s7, s1194; SI-STRICT-NEXT: buffer_load_dwordx2 v[4:5], off, s[4:7], 095; SI-STRICT-NEXT: s_mov_b32 s8, s096; SI-STRICT-NEXT: s_mov_b32 s9, s197; SI-STRICT-NEXT: s_waitcnt vmcnt(1)98; SI-STRICT-NEXT: v_mul_f64 v[0:1], v[0:1], v[2:3]99; SI-STRICT-NEXT: s_waitcnt vmcnt(0)100; SI-STRICT-NEXT: v_add_f64 v[0:1], v[0:1], v[4:5]101; SI-STRICT-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0102; SI-STRICT-NEXT: s_endpgm103;104; SI-CONTRACT-LABEL: fmul_fadd_f64:105; SI-CONTRACT: ; %bb.0:106; SI-CONTRACT-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x9107; SI-CONTRACT-NEXT: s_mov_b32 s11, 0xf000108; SI-CONTRACT-NEXT: s_mov_b32 s10, -1109; SI-CONTRACT-NEXT: s_mov_b32 s14, s10110; SI-CONTRACT-NEXT: s_mov_b32 s15, s11111; SI-CONTRACT-NEXT: s_waitcnt lgkmcnt(0)112; SI-CONTRACT-NEXT: s_mov_b32 s12, s2113; SI-CONTRACT-NEXT: s_mov_b32 s13, s3114; SI-CONTRACT-NEXT: s_mov_b32 s16, s4115; SI-CONTRACT-NEXT: s_mov_b32 s17, s5116; SI-CONTRACT-NEXT: s_mov_b32 s18, s10117; SI-CONTRACT-NEXT: s_mov_b32 s19, s11118; SI-CONTRACT-NEXT: s_mov_b32 s4, s6119; SI-CONTRACT-NEXT: s_mov_b32 s5, s7120; SI-CONTRACT-NEXT: s_mov_b32 s6, s10121; SI-CONTRACT-NEXT: s_mov_b32 s7, s11122; SI-CONTRACT-NEXT: buffer_load_dwordx2 v[0:1], off, s[12:15], 0123; SI-CONTRACT-NEXT: buffer_load_dwordx2 v[2:3], off, s[16:19], 0124; SI-CONTRACT-NEXT: buffer_load_dwordx2 v[4:5], off, s[4:7], 0125; SI-CONTRACT-NEXT: s_mov_b32 s8, s0126; SI-CONTRACT-NEXT: s_mov_b32 s9, s1127; SI-CONTRACT-NEXT: s_waitcnt vmcnt(0)128; SI-CONTRACT-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[4:5]129; SI-CONTRACT-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0130; SI-CONTRACT-NEXT: s_endpgm131;132; VI-STRICT-LABEL: fmul_fadd_f64:133; VI-STRICT: ; %bb.0:134; VI-STRICT-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x24135; VI-STRICT-NEXT: s_mov_b32 s11, 0xf000136; VI-STRICT-NEXT: s_mov_b32 s10, -1137; VI-STRICT-NEXT: s_mov_b32 s14, s10138; VI-STRICT-NEXT: s_mov_b32 s15, s11139; VI-STRICT-NEXT: s_waitcnt lgkmcnt(0)140; VI-STRICT-NEXT: s_mov_b32 s12, s2141; VI-STRICT-NEXT: s_mov_b32 s13, s3142; VI-STRICT-NEXT: s_mov_b32 s16, s4143; VI-STRICT-NEXT: s_mov_b32 s17, s5144; VI-STRICT-NEXT: s_mov_b32 s18, s10145; VI-STRICT-NEXT: s_mov_b32 s19, s11146; VI-STRICT-NEXT: buffer_load_dwordx2 v[0:1], off, s[12:15], 0147; VI-STRICT-NEXT: buffer_load_dwordx2 v[2:3], off, s[16:19], 0148; VI-STRICT-NEXT: s_mov_b32 s4, s6149; VI-STRICT-NEXT: s_mov_b32 s5, s7150; VI-STRICT-NEXT: s_mov_b32 s6, s10151; VI-STRICT-NEXT: s_mov_b32 s7, s11152; VI-STRICT-NEXT: buffer_load_dwordx2 v[4:5], off, s[4:7], 0153; VI-STRICT-NEXT: s_mov_b32 s8, s0154; VI-STRICT-NEXT: s_mov_b32 s9, s1155; VI-STRICT-NEXT: s_waitcnt vmcnt(1)156; VI-STRICT-NEXT: v_mul_f64 v[0:1], v[0:1], v[2:3]157; VI-STRICT-NEXT: s_waitcnt vmcnt(0)158; VI-STRICT-NEXT: v_add_f64 v[0:1], v[0:1], v[4:5]159; VI-STRICT-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0160; VI-STRICT-NEXT: s_endpgm161;162; VI-CONTRACT-LABEL: fmul_fadd_f64:163; VI-CONTRACT: ; %bb.0:164; VI-CONTRACT-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x24165; VI-CONTRACT-NEXT: s_mov_b32 s11, 0xf000166; VI-CONTRACT-NEXT: s_mov_b32 s10, -1167; VI-CONTRACT-NEXT: s_mov_b32 s14, s10168; VI-CONTRACT-NEXT: s_mov_b32 s15, s11169; VI-CONTRACT-NEXT: s_waitcnt lgkmcnt(0)170; VI-CONTRACT-NEXT: s_mov_b32 s12, s2171; VI-CONTRACT-NEXT: s_mov_b32 s13, s3172; VI-CONTRACT-NEXT: s_mov_b32 s16, s4173; VI-CONTRACT-NEXT: s_mov_b32 s17, s5174; VI-CONTRACT-NEXT: s_mov_b32 s18, s10175; VI-CONTRACT-NEXT: s_mov_b32 s19, s11176; VI-CONTRACT-NEXT: s_mov_b32 s4, s6177; VI-CONTRACT-NEXT: s_mov_b32 s5, s7178; VI-CONTRACT-NEXT: s_mov_b32 s6, s10179; VI-CONTRACT-NEXT: s_mov_b32 s7, s11180; VI-CONTRACT-NEXT: buffer_load_dwordx2 v[0:1], off, s[12:15], 0181; VI-CONTRACT-NEXT: buffer_load_dwordx2 v[2:3], off, s[16:19], 0182; VI-CONTRACT-NEXT: buffer_load_dwordx2 v[4:5], off, s[4:7], 0183; VI-CONTRACT-NEXT: s_mov_b32 s8, s0184; VI-CONTRACT-NEXT: s_mov_b32 s9, s1185; VI-CONTRACT-NEXT: s_waitcnt vmcnt(0)186; VI-CONTRACT-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[4:5]187; VI-CONTRACT-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0188; VI-CONTRACT-NEXT: s_endpgm189 %r0 = load double, ptr addrspace(1) %in1190 %r1 = load double, ptr addrspace(1) %in2191 %r2 = load double, ptr addrspace(1) %in3192 %tmp = fmul double %r0, %r1193 %r3 = fadd double %tmp, %r2194 store double %r3, ptr addrspace(1) %out195 ret void196}197 198define amdgpu_kernel void @fmul_fadd_contract_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1, ptr addrspace(1) %in2, ptr addrspace(1) %in3) #0 {199; SI-LABEL: fmul_fadd_contract_f64:200; SI: ; %bb.0:201; SI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x9202; SI-NEXT: s_mov_b32 s11, 0xf000203; SI-NEXT: s_mov_b32 s10, -1204; SI-NEXT: s_mov_b32 s14, s10205; SI-NEXT: s_mov_b32 s15, s11206; SI-NEXT: s_waitcnt lgkmcnt(0)207; SI-NEXT: s_mov_b32 s12, s2208; SI-NEXT: s_mov_b32 s13, s3209; SI-NEXT: s_mov_b32 s16, s4210; SI-NEXT: s_mov_b32 s17, s5211; SI-NEXT: s_mov_b32 s18, s10212; SI-NEXT: s_mov_b32 s19, s11213; SI-NEXT: s_mov_b32 s4, s6214; SI-NEXT: s_mov_b32 s5, s7215; SI-NEXT: s_mov_b32 s6, s10216; SI-NEXT: s_mov_b32 s7, s11217; SI-NEXT: buffer_load_dwordx2 v[0:1], off, s[12:15], 0218; SI-NEXT: buffer_load_dwordx2 v[2:3], off, s[16:19], 0219; SI-NEXT: buffer_load_dwordx2 v[4:5], off, s[4:7], 0220; SI-NEXT: s_mov_b32 s8, s0221; SI-NEXT: s_mov_b32 s9, s1222; SI-NEXT: s_waitcnt vmcnt(0)223; SI-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[4:5]224; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0225; SI-NEXT: s_endpgm226;227; VI-LABEL: fmul_fadd_contract_f64:228; VI: ; %bb.0:229; VI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x24230; VI-NEXT: s_mov_b32 s11, 0xf000231; VI-NEXT: s_mov_b32 s10, -1232; VI-NEXT: s_mov_b32 s14, s10233; VI-NEXT: s_mov_b32 s15, s11234; VI-NEXT: s_waitcnt lgkmcnt(0)235; VI-NEXT: s_mov_b32 s12, s2236; VI-NEXT: s_mov_b32 s13, s3237; VI-NEXT: s_mov_b32 s16, s4238; VI-NEXT: s_mov_b32 s17, s5239; VI-NEXT: s_mov_b32 s18, s10240; VI-NEXT: s_mov_b32 s19, s11241; VI-NEXT: s_mov_b32 s4, s6242; VI-NEXT: s_mov_b32 s5, s7243; VI-NEXT: s_mov_b32 s6, s10244; VI-NEXT: s_mov_b32 s7, s11245; VI-NEXT: buffer_load_dwordx2 v[0:1], off, s[12:15], 0246; VI-NEXT: buffer_load_dwordx2 v[2:3], off, s[16:19], 0247; VI-NEXT: buffer_load_dwordx2 v[4:5], off, s[4:7], 0248; VI-NEXT: s_mov_b32 s8, s0249; VI-NEXT: s_mov_b32 s9, s1250; VI-NEXT: s_waitcnt vmcnt(0)251; VI-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[4:5]252; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0253; VI-NEXT: s_endpgm254 %r0 = load double, ptr addrspace(1) %in1255 %r1 = load double, ptr addrspace(1) %in2256 %r2 = load double, ptr addrspace(1) %in3257 %tmp = fmul contract double %r0, %r1258 %r3 = fadd contract double %tmp, %r2259 store double %r3, ptr addrspace(1) %out260 ret void261}262 263define amdgpu_kernel void @fadd_a_a_b_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1, ptr addrspace(1) %in2) #0 {264; SI-STRICT-LABEL: fadd_a_a_b_f64:265; SI-STRICT: ; %bb.0:266; SI-STRICT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9267; SI-STRICT-NEXT: s_mov_b32 s3, 0xf000268; SI-STRICT-NEXT: s_mov_b32 s2, 0269; SI-STRICT-NEXT: v_lshlrev_b32_e32 v0, 3, v0270; SI-STRICT-NEXT: v_mov_b32_e32 v1, 0271; SI-STRICT-NEXT: s_waitcnt lgkmcnt(0)272; SI-STRICT-NEXT: buffer_load_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64 glc273; SI-STRICT-NEXT: s_waitcnt vmcnt(0)274; SI-STRICT-NEXT: buffer_load_dwordx2 v[4:5], v[0:1], s[0:3], 0 addr64 offset:8 glc275; SI-STRICT-NEXT: s_waitcnt vmcnt(0)276; SI-STRICT-NEXT: v_add_f64 v[2:3], v[2:3], v[2:3]277; SI-STRICT-NEXT: v_add_f64 v[2:3], v[2:3], v[4:5]278; SI-STRICT-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64279; SI-STRICT-NEXT: s_endpgm280;281; SI-CONTRACT-LABEL: fadd_a_a_b_f64:282; SI-CONTRACT: ; %bb.0:283; SI-CONTRACT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9284; SI-CONTRACT-NEXT: s_mov_b32 s3, 0xf000285; SI-CONTRACT-NEXT: s_mov_b32 s2, 0286; SI-CONTRACT-NEXT: v_lshlrev_b32_e32 v0, 3, v0287; SI-CONTRACT-NEXT: v_mov_b32_e32 v1, 0288; SI-CONTRACT-NEXT: s_waitcnt lgkmcnt(0)289; SI-CONTRACT-NEXT: buffer_load_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64 glc290; SI-CONTRACT-NEXT: s_waitcnt vmcnt(0)291; SI-CONTRACT-NEXT: buffer_load_dwordx2 v[4:5], v[0:1], s[0:3], 0 addr64 offset:8 glc292; SI-CONTRACT-NEXT: s_waitcnt vmcnt(0)293; SI-CONTRACT-NEXT: v_fma_f64 v[2:3], v[2:3], 2.0, v[4:5]294; SI-CONTRACT-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64295; SI-CONTRACT-NEXT: s_endpgm296;297; VI-STRICT-LABEL: fadd_a_a_b_f64:298; VI-STRICT: ; %bb.0:299; VI-STRICT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24300; VI-STRICT-NEXT: v_lshlrev_b32_e32 v0, 3, v0301; VI-STRICT-NEXT: s_waitcnt lgkmcnt(0)302; VI-STRICT-NEXT: v_mov_b32_e32 v1, s1303; VI-STRICT-NEXT: v_add_u32_e32 v0, vcc, s0, v0304; VI-STRICT-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc305; VI-STRICT-NEXT: flat_load_dwordx2 v[2:3], v[0:1] glc306; VI-STRICT-NEXT: s_waitcnt vmcnt(0)307; VI-STRICT-NEXT: v_add_u32_e32 v4, vcc, 8, v0308; VI-STRICT-NEXT: v_addc_u32_e32 v5, vcc, 0, v1, vcc309; VI-STRICT-NEXT: flat_load_dwordx2 v[4:5], v[4:5] glc310; VI-STRICT-NEXT: s_waitcnt vmcnt(0)311; VI-STRICT-NEXT: v_add_f64 v[2:3], v[2:3], v[2:3]312; VI-STRICT-NEXT: v_add_f64 v[2:3], v[2:3], v[4:5]313; VI-STRICT-NEXT: flat_store_dwordx2 v[0:1], v[2:3]314; VI-STRICT-NEXT: s_endpgm315;316; VI-CONTRACT-LABEL: fadd_a_a_b_f64:317; VI-CONTRACT: ; %bb.0:318; VI-CONTRACT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24319; VI-CONTRACT-NEXT: v_lshlrev_b32_e32 v0, 3, v0320; VI-CONTRACT-NEXT: s_waitcnt lgkmcnt(0)321; VI-CONTRACT-NEXT: v_mov_b32_e32 v1, s1322; VI-CONTRACT-NEXT: v_add_u32_e32 v0, vcc, s0, v0323; VI-CONTRACT-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc324; VI-CONTRACT-NEXT: v_add_u32_e32 v2, vcc, 8, v0325; VI-CONTRACT-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc326; VI-CONTRACT-NEXT: flat_load_dwordx2 v[4:5], v[0:1] glc327; VI-CONTRACT-NEXT: s_waitcnt vmcnt(0)328; VI-CONTRACT-NEXT: flat_load_dwordx2 v[2:3], v[2:3] glc329; VI-CONTRACT-NEXT: s_waitcnt vmcnt(0)330; VI-CONTRACT-NEXT: v_fma_f64 v[2:3], v[4:5], 2.0, v[2:3]331; VI-CONTRACT-NEXT: flat_store_dwordx2 v[0:1], v[2:3]332; VI-CONTRACT-NEXT: s_endpgm333 %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone334 %gep.0 = getelementptr double, ptr addrspace(1) %out, i32 %tid335 %gep.1 = getelementptr double, ptr addrspace(1) %gep.0, i32 1336 %gep.out = getelementptr double, ptr addrspace(1) %out, i32 %tid337 338 %r0 = load volatile double, ptr addrspace(1) %gep.0339 %r1 = load volatile double, ptr addrspace(1) %gep.1340 341 %add.0 = fadd double %r0, %r0342 %add.1 = fadd double %add.0, %r1343 store double %add.1, ptr addrspace(1) %gep.out344 ret void345}346 347define amdgpu_kernel void @fadd_b_a_a_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1, ptr addrspace(1) %in2) #0 {348; SI-STRICT-LABEL: fadd_b_a_a_f64:349; SI-STRICT: ; %bb.0:350; SI-STRICT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9351; SI-STRICT-NEXT: s_mov_b32 s3, 0xf000352; SI-STRICT-NEXT: s_mov_b32 s2, 0353; SI-STRICT-NEXT: v_lshlrev_b32_e32 v0, 3, v0354; SI-STRICT-NEXT: v_mov_b32_e32 v1, 0355; SI-STRICT-NEXT: s_waitcnt lgkmcnt(0)356; SI-STRICT-NEXT: buffer_load_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64 glc357; SI-STRICT-NEXT: s_waitcnt vmcnt(0)358; SI-STRICT-NEXT: buffer_load_dwordx2 v[4:5], v[0:1], s[0:3], 0 addr64 offset:8 glc359; SI-STRICT-NEXT: s_waitcnt vmcnt(0)360; SI-STRICT-NEXT: v_add_f64 v[2:3], v[2:3], v[2:3]361; SI-STRICT-NEXT: v_add_f64 v[2:3], v[4:5], v[2:3]362; SI-STRICT-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64363; SI-STRICT-NEXT: s_endpgm364;365; SI-CONTRACT-LABEL: fadd_b_a_a_f64:366; SI-CONTRACT: ; %bb.0:367; SI-CONTRACT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9368; SI-CONTRACT-NEXT: s_mov_b32 s3, 0xf000369; SI-CONTRACT-NEXT: s_mov_b32 s2, 0370; SI-CONTRACT-NEXT: v_lshlrev_b32_e32 v0, 3, v0371; SI-CONTRACT-NEXT: v_mov_b32_e32 v1, 0372; SI-CONTRACT-NEXT: s_waitcnt lgkmcnt(0)373; SI-CONTRACT-NEXT: buffer_load_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64 glc374; SI-CONTRACT-NEXT: s_waitcnt vmcnt(0)375; SI-CONTRACT-NEXT: buffer_load_dwordx2 v[4:5], v[0:1], s[0:3], 0 addr64 offset:8 glc376; SI-CONTRACT-NEXT: s_waitcnt vmcnt(0)377; SI-CONTRACT-NEXT: v_fma_f64 v[2:3], v[2:3], 2.0, v[4:5]378; SI-CONTRACT-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64379; SI-CONTRACT-NEXT: s_endpgm380;381; VI-STRICT-LABEL: fadd_b_a_a_f64:382; VI-STRICT: ; %bb.0:383; VI-STRICT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24384; VI-STRICT-NEXT: v_lshlrev_b32_e32 v0, 3, v0385; VI-STRICT-NEXT: s_waitcnt lgkmcnt(0)386; VI-STRICT-NEXT: v_mov_b32_e32 v1, s1387; VI-STRICT-NEXT: v_add_u32_e32 v0, vcc, s0, v0388; VI-STRICT-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc389; VI-STRICT-NEXT: flat_load_dwordx2 v[2:3], v[0:1] glc390; VI-STRICT-NEXT: s_waitcnt vmcnt(0)391; VI-STRICT-NEXT: v_add_u32_e32 v4, vcc, 8, v0392; VI-STRICT-NEXT: v_addc_u32_e32 v5, vcc, 0, v1, vcc393; VI-STRICT-NEXT: flat_load_dwordx2 v[4:5], v[4:5] glc394; VI-STRICT-NEXT: s_waitcnt vmcnt(0)395; VI-STRICT-NEXT: v_add_f64 v[2:3], v[2:3], v[2:3]396; VI-STRICT-NEXT: v_add_f64 v[2:3], v[4:5], v[2:3]397; VI-STRICT-NEXT: flat_store_dwordx2 v[0:1], v[2:3]398; VI-STRICT-NEXT: s_endpgm399;400; VI-CONTRACT-LABEL: fadd_b_a_a_f64:401; VI-CONTRACT: ; %bb.0:402; VI-CONTRACT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24403; VI-CONTRACT-NEXT: v_lshlrev_b32_e32 v0, 3, v0404; VI-CONTRACT-NEXT: s_waitcnt lgkmcnt(0)405; VI-CONTRACT-NEXT: v_mov_b32_e32 v1, s1406; VI-CONTRACT-NEXT: v_add_u32_e32 v0, vcc, s0, v0407; VI-CONTRACT-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc408; VI-CONTRACT-NEXT: v_add_u32_e32 v2, vcc, 8, v0409; VI-CONTRACT-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc410; VI-CONTRACT-NEXT: flat_load_dwordx2 v[4:5], v[0:1] glc411; VI-CONTRACT-NEXT: s_waitcnt vmcnt(0)412; VI-CONTRACT-NEXT: flat_load_dwordx2 v[2:3], v[2:3] glc413; VI-CONTRACT-NEXT: s_waitcnt vmcnt(0)414; VI-CONTRACT-NEXT: v_fma_f64 v[2:3], v[4:5], 2.0, v[2:3]415; VI-CONTRACT-NEXT: flat_store_dwordx2 v[0:1], v[2:3]416; VI-CONTRACT-NEXT: s_endpgm417 %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone418 %gep.0 = getelementptr double, ptr addrspace(1) %out, i32 %tid419 %gep.1 = getelementptr double, ptr addrspace(1) %gep.0, i32 1420 %gep.out = getelementptr double, ptr addrspace(1) %out, i32 %tid421 422 %r0 = load volatile double, ptr addrspace(1) %gep.0423 %r1 = load volatile double, ptr addrspace(1) %gep.1424 425 %add.0 = fadd double %r0, %r0426 %add.1 = fadd double %r1, %add.0427 store double %add.1, ptr addrspace(1) %gep.out428 ret void429}430 431define amdgpu_kernel void @mad_sub_f64(ptr addrspace(1) noalias nocapture %out, ptr addrspace(1) noalias nocapture readonly %ptr) #1 {432; SI-STRICT-LABEL: mad_sub_f64:433; SI-STRICT: ; %bb.0:434; SI-STRICT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9435; SI-STRICT-NEXT: s_mov_b32 s7, 0xf000436; SI-STRICT-NEXT: s_mov_b32 s6, 0437; SI-STRICT-NEXT: v_lshlrev_b32_e32 v0, 3, v0438; SI-STRICT-NEXT: v_mov_b32_e32 v1, 0439; SI-STRICT-NEXT: s_waitcnt lgkmcnt(0)440; SI-STRICT-NEXT: s_mov_b64 s[4:5], s[2:3]441; SI-STRICT-NEXT: buffer_load_dwordx2 v[2:3], v[0:1], s[4:7], 0 addr64 glc442; SI-STRICT-NEXT: s_waitcnt vmcnt(0)443; SI-STRICT-NEXT: buffer_load_dwordx2 v[4:5], v[0:1], s[4:7], 0 addr64 offset:8 glc444; SI-STRICT-NEXT: s_waitcnt vmcnt(0)445; SI-STRICT-NEXT: buffer_load_dwordx2 v[6:7], v[0:1], s[4:7], 0 addr64 offset:16 glc446; SI-STRICT-NEXT: s_waitcnt vmcnt(0)447; SI-STRICT-NEXT: s_mov_b64 s[2:3], s[6:7]448; SI-STRICT-NEXT: v_mul_f64 v[2:3], v[2:3], v[4:5]449; SI-STRICT-NEXT: v_add_f64 v[2:3], v[2:3], -v[6:7]450; SI-STRICT-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64451; SI-STRICT-NEXT: s_endpgm452;453; SI-CONTRACT-LABEL: mad_sub_f64:454; SI-CONTRACT: ; %bb.0:455; SI-CONTRACT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9456; SI-CONTRACT-NEXT: s_mov_b32 s7, 0xf000457; SI-CONTRACT-NEXT: s_mov_b32 s6, 0458; SI-CONTRACT-NEXT: v_lshlrev_b32_e32 v0, 3, v0459; SI-CONTRACT-NEXT: v_mov_b32_e32 v1, 0460; SI-CONTRACT-NEXT: s_waitcnt lgkmcnt(0)461; SI-CONTRACT-NEXT: s_mov_b64 s[4:5], s[2:3]462; SI-CONTRACT-NEXT: buffer_load_dwordx2 v[2:3], v[0:1], s[4:7], 0 addr64 glc463; SI-CONTRACT-NEXT: s_waitcnt vmcnt(0)464; SI-CONTRACT-NEXT: buffer_load_dwordx2 v[4:5], v[0:1], s[4:7], 0 addr64 offset:8 glc465; SI-CONTRACT-NEXT: s_waitcnt vmcnt(0)466; SI-CONTRACT-NEXT: buffer_load_dwordx2 v[6:7], v[0:1], s[4:7], 0 addr64 offset:16 glc467; SI-CONTRACT-NEXT: s_waitcnt vmcnt(0)468; SI-CONTRACT-NEXT: s_mov_b64 s[2:3], s[6:7]469; SI-CONTRACT-NEXT: v_fma_f64 v[2:3], v[2:3], v[4:5], -v[6:7]470; SI-CONTRACT-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64471; SI-CONTRACT-NEXT: s_endpgm472;473; VI-STRICT-LABEL: mad_sub_f64:474; VI-STRICT: ; %bb.0:475; VI-STRICT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24476; VI-STRICT-NEXT: v_lshlrev_b32_e32 v6, 3, v0477; VI-STRICT-NEXT: s_waitcnt lgkmcnt(0)478; VI-STRICT-NEXT: v_mov_b32_e32 v1, s3479; VI-STRICT-NEXT: v_add_u32_e32 v0, vcc, s2, v6480; VI-STRICT-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc481; VI-STRICT-NEXT: v_add_u32_e32 v2, vcc, 8, v0482; VI-STRICT-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc483; VI-STRICT-NEXT: flat_load_dwordx2 v[4:5], v[0:1] glc484; VI-STRICT-NEXT: s_waitcnt vmcnt(0)485; VI-STRICT-NEXT: flat_load_dwordx2 v[2:3], v[2:3] glc486; VI-STRICT-NEXT: s_waitcnt vmcnt(0)487; VI-STRICT-NEXT: v_add_u32_e32 v0, vcc, 16, v0488; VI-STRICT-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc489; VI-STRICT-NEXT: flat_load_dwordx2 v[0:1], v[0:1] glc490; VI-STRICT-NEXT: s_waitcnt vmcnt(0)491; VI-STRICT-NEXT: v_mul_f64 v[2:3], v[4:5], v[2:3]492; VI-STRICT-NEXT: v_add_f64 v[0:1], v[2:3], -v[0:1]493; VI-STRICT-NEXT: v_mov_b32_e32 v3, s1494; VI-STRICT-NEXT: v_add_u32_e32 v2, vcc, s0, v6495; VI-STRICT-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc496; VI-STRICT-NEXT: flat_store_dwordx2 v[2:3], v[0:1]497; VI-STRICT-NEXT: s_endpgm498;499; VI-CONTRACT-LABEL: mad_sub_f64:500; VI-CONTRACT: ; %bb.0:501; VI-CONTRACT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24502; VI-CONTRACT-NEXT: v_lshlrev_b32_e32 v6, 3, v0503; VI-CONTRACT-NEXT: s_waitcnt lgkmcnt(0)504; VI-CONTRACT-NEXT: v_mov_b32_e32 v1, s3505; VI-CONTRACT-NEXT: v_add_u32_e32 v0, vcc, s2, v6506; VI-CONTRACT-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc507; VI-CONTRACT-NEXT: v_add_u32_e32 v2, vcc, 8, v0508; VI-CONTRACT-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc509; VI-CONTRACT-NEXT: v_add_u32_e32 v4, vcc, 16, v0510; VI-CONTRACT-NEXT: v_addc_u32_e32 v5, vcc, 0, v1, vcc511; VI-CONTRACT-NEXT: flat_load_dwordx2 v[0:1], v[0:1] glc512; VI-CONTRACT-NEXT: s_waitcnt vmcnt(0)513; VI-CONTRACT-NEXT: flat_load_dwordx2 v[2:3], v[2:3] glc514; VI-CONTRACT-NEXT: s_waitcnt vmcnt(0)515; VI-CONTRACT-NEXT: flat_load_dwordx2 v[4:5], v[4:5] glc516; VI-CONTRACT-NEXT: s_waitcnt vmcnt(0)517; VI-CONTRACT-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], -v[4:5]518; VI-CONTRACT-NEXT: v_mov_b32_e32 v3, s1519; VI-CONTRACT-NEXT: v_add_u32_e32 v2, vcc, s0, v6520; VI-CONTRACT-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc521; VI-CONTRACT-NEXT: flat_store_dwordx2 v[2:3], v[0:1]522; VI-CONTRACT-NEXT: s_endpgm523 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0524 %tid.ext = sext i32 %tid to i64525 %gep0 = getelementptr double, ptr addrspace(1) %ptr, i64 %tid.ext526 %add1 = add i64 %tid.ext, 1527 %gep1 = getelementptr double, ptr addrspace(1) %ptr, i64 %add1528 %add2 = add i64 %tid.ext, 2529 %gep2 = getelementptr double, ptr addrspace(1) %ptr, i64 %add2530 %outgep = getelementptr double, ptr addrspace(1) %out, i64 %tid.ext531 %a = load volatile double, ptr addrspace(1) %gep0, align 8532 %b = load volatile double, ptr addrspace(1) %gep1, align 8533 %c = load volatile double, ptr addrspace(1) %gep2, align 8534 %mul = fmul double %a, %b535 %sub = fsub double %mul, %c536 store double %sub, ptr addrspace(1) %outgep, align 8537 ret void538}539 540define amdgpu_kernel void @fadd_a_a_b_f64_fast_add0(ptr addrspace(1) %out, ptr addrspace(1) %in1, ptr addrspace(1) %in2) #0 {541; SI-STRICT-LABEL: fadd_a_a_b_f64_fast_add0:542; SI-STRICT: ; %bb.0:543; SI-STRICT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9544; SI-STRICT-NEXT: s_mov_b32 s3, 0xf000545; SI-STRICT-NEXT: s_mov_b32 s2, 0546; SI-STRICT-NEXT: v_lshlrev_b32_e32 v0, 3, v0547; SI-STRICT-NEXT: v_mov_b32_e32 v1, 0548; SI-STRICT-NEXT: s_waitcnt lgkmcnt(0)549; SI-STRICT-NEXT: buffer_load_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64 glc550; SI-STRICT-NEXT: s_waitcnt vmcnt(0)551; SI-STRICT-NEXT: buffer_load_dwordx2 v[4:5], v[0:1], s[0:3], 0 addr64 offset:8 glc552; SI-STRICT-NEXT: s_waitcnt vmcnt(0)553; SI-STRICT-NEXT: v_add_f64 v[2:3], v[2:3], v[2:3]554; SI-STRICT-NEXT: v_add_f64 v[2:3], v[2:3], v[4:5]555; SI-STRICT-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64556; SI-STRICT-NEXT: s_endpgm557;558; SI-CONTRACT-LABEL: fadd_a_a_b_f64_fast_add0:559; SI-CONTRACT: ; %bb.0:560; SI-CONTRACT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9561; SI-CONTRACT-NEXT: s_mov_b32 s3, 0xf000562; SI-CONTRACT-NEXT: s_mov_b32 s2, 0563; SI-CONTRACT-NEXT: v_lshlrev_b32_e32 v0, 3, v0564; SI-CONTRACT-NEXT: v_mov_b32_e32 v1, 0565; SI-CONTRACT-NEXT: s_waitcnt lgkmcnt(0)566; SI-CONTRACT-NEXT: buffer_load_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64 glc567; SI-CONTRACT-NEXT: s_waitcnt vmcnt(0)568; SI-CONTRACT-NEXT: buffer_load_dwordx2 v[4:5], v[0:1], s[0:3], 0 addr64 offset:8 glc569; SI-CONTRACT-NEXT: s_waitcnt vmcnt(0)570; SI-CONTRACT-NEXT: v_fma_f64 v[2:3], v[2:3], 2.0, v[4:5]571; SI-CONTRACT-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64572; SI-CONTRACT-NEXT: s_endpgm573;574; VI-STRICT-LABEL: fadd_a_a_b_f64_fast_add0:575; VI-STRICT: ; %bb.0:576; VI-STRICT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24577; VI-STRICT-NEXT: v_lshlrev_b32_e32 v0, 3, v0578; VI-STRICT-NEXT: s_waitcnt lgkmcnt(0)579; VI-STRICT-NEXT: v_mov_b32_e32 v1, s1580; VI-STRICT-NEXT: v_add_u32_e32 v0, vcc, s0, v0581; VI-STRICT-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc582; VI-STRICT-NEXT: flat_load_dwordx2 v[2:3], v[0:1] glc583; VI-STRICT-NEXT: s_waitcnt vmcnt(0)584; VI-STRICT-NEXT: v_add_u32_e32 v4, vcc, 8, v0585; VI-STRICT-NEXT: v_addc_u32_e32 v5, vcc, 0, v1, vcc586; VI-STRICT-NEXT: flat_load_dwordx2 v[4:5], v[4:5] glc587; VI-STRICT-NEXT: s_waitcnt vmcnt(0)588; VI-STRICT-NEXT: v_add_f64 v[2:3], v[2:3], v[2:3]589; VI-STRICT-NEXT: v_add_f64 v[2:3], v[2:3], v[4:5]590; VI-STRICT-NEXT: flat_store_dwordx2 v[0:1], v[2:3]591; VI-STRICT-NEXT: s_endpgm592;593; VI-CONTRACT-LABEL: fadd_a_a_b_f64_fast_add0:594; VI-CONTRACT: ; %bb.0:595; VI-CONTRACT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24596; VI-CONTRACT-NEXT: v_lshlrev_b32_e32 v0, 3, v0597; VI-CONTRACT-NEXT: s_waitcnt lgkmcnt(0)598; VI-CONTRACT-NEXT: v_mov_b32_e32 v1, s1599; VI-CONTRACT-NEXT: v_add_u32_e32 v0, vcc, s0, v0600; VI-CONTRACT-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc601; VI-CONTRACT-NEXT: v_add_u32_e32 v2, vcc, 8, v0602; VI-CONTRACT-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc603; VI-CONTRACT-NEXT: flat_load_dwordx2 v[4:5], v[0:1] glc604; VI-CONTRACT-NEXT: s_waitcnt vmcnt(0)605; VI-CONTRACT-NEXT: flat_load_dwordx2 v[2:3], v[2:3] glc606; VI-CONTRACT-NEXT: s_waitcnt vmcnt(0)607; VI-CONTRACT-NEXT: v_fma_f64 v[2:3], v[4:5], 2.0, v[2:3]608; VI-CONTRACT-NEXT: flat_store_dwordx2 v[0:1], v[2:3]609; VI-CONTRACT-NEXT: s_endpgm610 %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone611 %gep.0 = getelementptr double, ptr addrspace(1) %out, i32 %tid612 %gep.1 = getelementptr double, ptr addrspace(1) %gep.0, i32 1613 %gep.out = getelementptr double, ptr addrspace(1) %out, i32 %tid614 615 %r0 = load volatile double, ptr addrspace(1) %gep.0616 %r1 = load volatile double, ptr addrspace(1) %gep.1617 618 %add.0 = fadd fast double %r0, %r0619 %add.1 = fadd double %add.0, %r1620 store double %add.1, ptr addrspace(1) %gep.out621 ret void622}623 624define amdgpu_kernel void @fadd_a_a_b_f64_fast_add1(ptr addrspace(1) %out, ptr addrspace(1) %in1, ptr addrspace(1) %in2) #0 {625; SI-STRICT-LABEL: fadd_a_a_b_f64_fast_add1:626; SI-STRICT: ; %bb.0:627; SI-STRICT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9628; SI-STRICT-NEXT: s_mov_b32 s3, 0xf000629; SI-STRICT-NEXT: s_mov_b32 s2, 0630; SI-STRICT-NEXT: v_lshlrev_b32_e32 v0, 3, v0631; SI-STRICT-NEXT: v_mov_b32_e32 v1, 0632; SI-STRICT-NEXT: s_waitcnt lgkmcnt(0)633; SI-STRICT-NEXT: buffer_load_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64 glc634; SI-STRICT-NEXT: s_waitcnt vmcnt(0)635; SI-STRICT-NEXT: buffer_load_dwordx2 v[4:5], v[0:1], s[0:3], 0 addr64 offset:8 glc636; SI-STRICT-NEXT: s_waitcnt vmcnt(0)637; SI-STRICT-NEXT: v_add_f64 v[2:3], v[2:3], v[2:3]638; SI-STRICT-NEXT: v_add_f64 v[2:3], v[2:3], v[4:5]639; SI-STRICT-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64640; SI-STRICT-NEXT: s_endpgm641;642; SI-CONTRACT-LABEL: fadd_a_a_b_f64_fast_add1:643; SI-CONTRACT: ; %bb.0:644; SI-CONTRACT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9645; SI-CONTRACT-NEXT: s_mov_b32 s3, 0xf000646; SI-CONTRACT-NEXT: s_mov_b32 s2, 0647; SI-CONTRACT-NEXT: v_lshlrev_b32_e32 v0, 3, v0648; SI-CONTRACT-NEXT: v_mov_b32_e32 v1, 0649; SI-CONTRACT-NEXT: s_waitcnt lgkmcnt(0)650; SI-CONTRACT-NEXT: buffer_load_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64 glc651; SI-CONTRACT-NEXT: s_waitcnt vmcnt(0)652; SI-CONTRACT-NEXT: buffer_load_dwordx2 v[4:5], v[0:1], s[0:3], 0 addr64 offset:8 glc653; SI-CONTRACT-NEXT: s_waitcnt vmcnt(0)654; SI-CONTRACT-NEXT: v_fma_f64 v[2:3], v[2:3], 2.0, v[4:5]655; SI-CONTRACT-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64656; SI-CONTRACT-NEXT: s_endpgm657;658; VI-STRICT-LABEL: fadd_a_a_b_f64_fast_add1:659; VI-STRICT: ; %bb.0:660; VI-STRICT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24661; VI-STRICT-NEXT: v_lshlrev_b32_e32 v0, 3, v0662; VI-STRICT-NEXT: s_waitcnt lgkmcnt(0)663; VI-STRICT-NEXT: v_mov_b32_e32 v1, s1664; VI-STRICT-NEXT: v_add_u32_e32 v0, vcc, s0, v0665; VI-STRICT-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc666; VI-STRICT-NEXT: flat_load_dwordx2 v[2:3], v[0:1] glc667; VI-STRICT-NEXT: s_waitcnt vmcnt(0)668; VI-STRICT-NEXT: v_add_u32_e32 v4, vcc, 8, v0669; VI-STRICT-NEXT: v_addc_u32_e32 v5, vcc, 0, v1, vcc670; VI-STRICT-NEXT: flat_load_dwordx2 v[4:5], v[4:5] glc671; VI-STRICT-NEXT: s_waitcnt vmcnt(0)672; VI-STRICT-NEXT: v_add_f64 v[2:3], v[2:3], v[2:3]673; VI-STRICT-NEXT: v_add_f64 v[2:3], v[2:3], v[4:5]674; VI-STRICT-NEXT: flat_store_dwordx2 v[0:1], v[2:3]675; VI-STRICT-NEXT: s_endpgm676;677; VI-CONTRACT-LABEL: fadd_a_a_b_f64_fast_add1:678; VI-CONTRACT: ; %bb.0:679; VI-CONTRACT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24680; VI-CONTRACT-NEXT: v_lshlrev_b32_e32 v0, 3, v0681; VI-CONTRACT-NEXT: s_waitcnt lgkmcnt(0)682; VI-CONTRACT-NEXT: v_mov_b32_e32 v1, s1683; VI-CONTRACT-NEXT: v_add_u32_e32 v0, vcc, s0, v0684; VI-CONTRACT-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc685; VI-CONTRACT-NEXT: v_add_u32_e32 v2, vcc, 8, v0686; VI-CONTRACT-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc687; VI-CONTRACT-NEXT: flat_load_dwordx2 v[4:5], v[0:1] glc688; VI-CONTRACT-NEXT: s_waitcnt vmcnt(0)689; VI-CONTRACT-NEXT: flat_load_dwordx2 v[2:3], v[2:3] glc690; VI-CONTRACT-NEXT: s_waitcnt vmcnt(0)691; VI-CONTRACT-NEXT: v_fma_f64 v[2:3], v[4:5], 2.0, v[2:3]692; VI-CONTRACT-NEXT: flat_store_dwordx2 v[0:1], v[2:3]693; VI-CONTRACT-NEXT: s_endpgm694 %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone695 %gep.0 = getelementptr double, ptr addrspace(1) %out, i32 %tid696 %gep.1 = getelementptr double, ptr addrspace(1) %gep.0, i32 1697 %gep.out = getelementptr double, ptr addrspace(1) %out, i32 %tid698 699 %r0 = load volatile double, ptr addrspace(1) %gep.0700 %r1 = load volatile double, ptr addrspace(1) %gep.1701 702 %add.0 = fadd double %r0, %r0703 %add.1 = fadd fast double %add.0, %r1704 store double %add.1, ptr addrspace(1) %gep.out705 ret void706}707 708define amdgpu_kernel void @fadd_a_a_b_f64_fast(ptr addrspace(1) %out, ptr addrspace(1) %in1, ptr addrspace(1) %in2) #0 {709; SI-LABEL: fadd_a_a_b_f64_fast:710; SI: ; %bb.0:711; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9712; SI-NEXT: s_mov_b32 s3, 0xf000713; SI-NEXT: s_mov_b32 s2, 0714; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v0715; SI-NEXT: v_mov_b32_e32 v1, 0716; SI-NEXT: s_waitcnt lgkmcnt(0)717; SI-NEXT: buffer_load_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64 glc718; SI-NEXT: s_waitcnt vmcnt(0)719; SI-NEXT: buffer_load_dwordx2 v[4:5], v[0:1], s[0:3], 0 addr64 offset:8 glc720; SI-NEXT: s_waitcnt vmcnt(0)721; SI-NEXT: v_fma_f64 v[2:3], v[2:3], 2.0, v[4:5]722; SI-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64723; SI-NEXT: s_endpgm724;725; VI-LABEL: fadd_a_a_b_f64_fast:726; VI: ; %bb.0:727; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24728; VI-NEXT: v_lshlrev_b32_e32 v0, 3, v0729; VI-NEXT: s_waitcnt lgkmcnt(0)730; VI-NEXT: v_mov_b32_e32 v1, s1731; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v0732; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc733; VI-NEXT: v_add_u32_e32 v2, vcc, 8, v0734; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc735; VI-NEXT: flat_load_dwordx2 v[4:5], v[0:1] glc736; VI-NEXT: s_waitcnt vmcnt(0)737; VI-NEXT: flat_load_dwordx2 v[2:3], v[2:3] glc738; VI-NEXT: s_waitcnt vmcnt(0)739; VI-NEXT: v_fma_f64 v[2:3], v[4:5], 2.0, v[2:3]740; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]741; VI-NEXT: s_endpgm742 %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone743 %gep.0 = getelementptr double, ptr addrspace(1) %out, i32 %tid744 %gep.1 = getelementptr double, ptr addrspace(1) %gep.0, i32 1745 %gep.out = getelementptr double, ptr addrspace(1) %out, i32 %tid746 747 %r0 = load volatile double, ptr addrspace(1) %gep.0748 %r1 = load volatile double, ptr addrspace(1) %gep.1749 750 %add.0 = fadd fast double %r0, %r0751 %add.1 = fadd fast double %add.0, %r1752 store double %add.1, ptr addrspace(1) %gep.out753 ret void754}755 756declare i32 @llvm.amdgcn.workitem.id.x() #1757declare double @llvm.fmuladd.f64(double, double, double) #1758 759attributes #0 = { nounwind }760attributes #1 = { nounwind readnone }761