brintos / llvm-project-archived public Read only

1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn -mcpu=hawaii -mattr=+flat-for-global < %s | FileCheck -enable-var-scope --check-prefixes=SI,SI-SAFE %s3; RUN: llc -enable-no-signed-zeros-fp-math -mtriple=amdgcn -mcpu=hawaii -mattr=+flat-for-global < %s | FileCheck -enable-var-scope --check-prefixes=SI,SI-NSZ %s4 5; RUN: llc -mtriple=amdgcn -mcpu=fiji < %s | FileCheck -enable-var-scope --check-prefixes=VI,VI-SAFE %s6; RUN: llc -enable-no-signed-zeros-fp-math -mtriple=amdgcn -mcpu=fiji < %s | FileCheck -enable-var-scope --check-prefixes=VI,VI-NSZ %s7 8; FIXME-TRUE16. fix true16 test9; XUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -enable-var-scope --check-prefixes=GFX11,GFX11-SAFE,GFX11-SAFE-TRUE16 %s10; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -enable-var-scope --check-prefixes=GFX11,GFX11-SAFE,GFX11-SAFE-FAKE16 %s11; XUN: llc -enable-no-signed-zeros-fp-math -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -enable-var-scope --check-prefixes=GFX11,GFX11-NSZ,GFX11-NSZ-TRUE16 %s12; RUN: llc -enable-no-signed-zeros-fp-math -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -enable-var-scope --check-prefixes=GFX11,GFX11-NSZ,GFX11-NSZ-FAKE16 %s13 14; --------------------------------------------------------------------------------15; fadd tests16; --------------------------------------------------------------------------------17 18define half @v_fneg_add_f16(half %a, half %b) #0 {19; SI-SAFE-LABEL: v_fneg_add_f16:20; SI-SAFE:       ; %bb.0:21; SI-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)22; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v1, v123; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v0, v024; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v1, v125; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v0, v026; SI-SAFE-NEXT:    v_add_f32_e32 v0, v0, v127; SI-SAFE-NEXT:    v_xor_b32_e32 v0, 0x80000000, v028; SI-SAFE-NEXT:    s_setpc_b64 s[30:31]29;30; SI-NSZ-LABEL: v_fneg_add_f16:31; SI-NSZ:       ; %bb.0:32; SI-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)33; SI-NSZ-NEXT:    v_cvt_f16_f32_e32 v1, v134; SI-NSZ-NEXT:    v_cvt_f16_f32_e64 v0, -v035; SI-NSZ-NEXT:    v_cvt_f32_f16_e32 v1, v136; SI-NSZ-NEXT:    v_cvt_f32_f16_e32 v0, v037; SI-NSZ-NEXT:    v_sub_f32_e32 v0, v0, v138; SI-NSZ-NEXT:    s_setpc_b64 s[30:31]39;40; VI-SAFE-LABEL: v_fneg_add_f16:41; VI-SAFE:       ; %bb.0:42; VI-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)43; VI-SAFE-NEXT:    v_add_f16_e32 v0, v0, v144; VI-SAFE-NEXT:    v_xor_b32_e32 v0, 0x8000, v045; VI-SAFE-NEXT:    s_setpc_b64 s[30:31]46;47; VI-NSZ-LABEL: v_fneg_add_f16:48; VI-NSZ:       ; %bb.0:49; VI-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)50; VI-NSZ-NEXT:    v_sub_f16_e64 v0, -v0, v151; VI-NSZ-NEXT:    s_setpc_b64 s[30:31]52;53; GFX11-SAFE-LABEL: v_fneg_add_f16:54; GFX11-SAFE:       ; %bb.0:55; GFX11-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)56; GFX11-SAFE-NEXT:    v_add_f16_e32 v0, v0, v157; GFX11-SAFE-NEXT:    s_delay_alu instid0(VALU_DEP_1)58; GFX11-SAFE-NEXT:    v_xor_b32_e32 v0, 0x8000, v059; GFX11-SAFE-NEXT:    s_setpc_b64 s[30:31]60;61; GFX11-NSZ-LABEL: v_fneg_add_f16:62; GFX11-NSZ:       ; %bb.0:63; GFX11-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)64; GFX11-NSZ-NEXT:    v_sub_f16_e64 v0, -v0, v165; GFX11-NSZ-NEXT:    s_setpc_b64 s[30:31]66; GFX11-SAFE-TRUE16-LABEL: v_fneg_add_f16:67; GFX11-SAFE-TRUE16:       ; %bb.0:68; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)69; GFX11-SAFE-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v1.l70; GFX11-SAFE-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)71; GFX11-SAFE-TRUE16-NEXT:    v_xor_b16 v0.l, 0x8000, v0.l72; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]73; GFX11-NSZ-TRUE16-LABEL: v_fneg_add_f16:74; GFX11-NSZ-TRUE16:       ; %bb.0:75; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)76; GFX11-NSZ-TRUE16-NEXT:    v_sub_f16_e64 v0.l, -v0.l, v1.l77; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]78  %add = fadd half %a, %b79  %fneg = fneg half %add80  ret half %fneg81}82 83define { half, half } @v_fneg_add_store_use_add_f16(half %a, half %b) #0 {84; SI-LABEL: v_fneg_add_store_use_add_f16:85; SI:       ; %bb.0:86; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)87; SI-NEXT:    v_cvt_f16_f32_e32 v1, v188; SI-NEXT:    v_cvt_f16_f32_e32 v0, v089; SI-NEXT:    v_cvt_f32_f16_e32 v1, v190; SI-NEXT:    v_cvt_f32_f16_e32 v0, v091; SI-NEXT:    v_add_f32_e32 v1, v0, v192; SI-NEXT:    v_xor_b32_e32 v0, 0x80000000, v193; SI-NEXT:    s_setpc_b64 s[30:31]94;95; VI-LABEL: v_fneg_add_store_use_add_f16:96; VI:       ; %bb.0:97; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)98; VI-NEXT:    v_add_f16_e32 v1, v0, v199; VI-NEXT:    v_xor_b32_e32 v0, 0x8000, v1100; VI-NEXT:    s_setpc_b64 s[30:31]101;102; GFX11-LABEL: v_fneg_add_store_use_add_f16:103; GFX11:       ; %bb.0:104; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)105; GFX11-NEXT:    v_add_f16_e32 v1, v0, v1106; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)107; GFX11-NEXT:    v_xor_b32_e32 v0, 0x8000, v1108; GFX11-NEXT:    s_setpc_b64 s[30:31]109; GFX11-SAFE-TRUE16-LABEL: v_fneg_add_store_use_add_f16:110; GFX11-SAFE-TRUE16:       ; %bb.0:111; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)112; GFX11-SAFE-TRUE16-NEXT:    v_add_f16_e32 v1.l, v0.l, v1.l113; GFX11-SAFE-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)114; GFX11-SAFE-TRUE16-NEXT:    v_xor_b16 v0.l, 0x8000, v1.l115; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]116; GFX11-NSZ-TRUE16-LABEL: v_fneg_add_store_use_add_f16:117; GFX11-NSZ-TRUE16:       ; %bb.0:118; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)119; GFX11-NSZ-TRUE16-NEXT:    v_add_f16_e32 v1.l, v0.l, v1.l120; GFX11-NSZ-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)121; GFX11-NSZ-TRUE16-NEXT:    v_xor_b16 v0.l, 0x8000, v1.l122; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]123  %add = fadd half %a, %b124  %fneg = fneg half %add125  %insert.0 = insertvalue { half, half } poison, half %fneg, 0126  %insert.1 = insertvalue { half, half } %insert.0, half %add, 1127  ret { half, half } %insert.1128}129 130define { half, half } @v_fneg_add_multi_use_add_f16(half %a, half %b) #0 {131; SI-SAFE-LABEL: v_fneg_add_multi_use_add_f16:132; SI-SAFE:       ; %bb.0:133; SI-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)134; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v1, v1135; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v0, v0136; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v1, v1137; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v0, v0138; SI-SAFE-NEXT:    v_add_f32_e32 v1, v0, v1139; SI-SAFE-NEXT:    v_xor_b32_e32 v0, 0x80000000, v1140; SI-SAFE-NEXT:    v_mul_f32_e32 v1, 4.0, v1141; SI-SAFE-NEXT:    s_setpc_b64 s[30:31]142;143; SI-NSZ-LABEL: v_fneg_add_multi_use_add_f16:144; SI-NSZ:       ; %bb.0:145; SI-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)146; SI-NSZ-NEXT:    v_cvt_f16_f32_e32 v1, v1147; SI-NSZ-NEXT:    v_cvt_f16_f32_e32 v0, v0148; SI-NSZ-NEXT:    v_cvt_f32_f16_e32 v1, v1149; SI-NSZ-NEXT:    v_cvt_f32_f16_e64 v0, -v0150; SI-NSZ-NEXT:    v_sub_f32_e32 v0, v0, v1151; SI-NSZ-NEXT:    v_mul_f32_e32 v1, -4.0, v0152; SI-NSZ-NEXT:    s_setpc_b64 s[30:31]153;154; VI-SAFE-LABEL: v_fneg_add_multi_use_add_f16:155; VI-SAFE:       ; %bb.0:156; VI-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)157; VI-SAFE-NEXT:    v_add_f16_e32 v1, v0, v1158; VI-SAFE-NEXT:    v_xor_b32_e32 v0, 0x8000, v1159; VI-SAFE-NEXT:    v_mul_f16_e32 v1, 4.0, v1160; VI-SAFE-NEXT:    s_setpc_b64 s[30:31]161;162; VI-NSZ-LABEL: v_fneg_add_multi_use_add_f16:163; VI-NSZ:       ; %bb.0:164; VI-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)165; VI-NSZ-NEXT:    v_sub_f16_e64 v0, -v0, v1166; VI-NSZ-NEXT:    v_mul_f16_e32 v1, -4.0, v0167; VI-NSZ-NEXT:    s_setpc_b64 s[30:31]168;169; GFX11-SAFE-LABEL: v_fneg_add_multi_use_add_f16:170; GFX11-SAFE:       ; %bb.0:171; GFX11-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)172; GFX11-SAFE-NEXT:    v_add_f16_e32 v1, v0, v1173; GFX11-SAFE-NEXT:    s_delay_alu instid0(VALU_DEP_1)174; GFX11-SAFE-NEXT:    v_xor_b32_e32 v0, 0x8000, v1175; GFX11-SAFE-NEXT:    v_mul_f16_e32 v1, 4.0, v1176; GFX11-SAFE-NEXT:    s_setpc_b64 s[30:31]177;178; GFX11-NSZ-LABEL: v_fneg_add_multi_use_add_f16:179; GFX11-NSZ:       ; %bb.0:180; GFX11-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)181; GFX11-NSZ-NEXT:    v_sub_f16_e64 v0, -v0, v1182; GFX11-NSZ-NEXT:    s_delay_alu instid0(VALU_DEP_1)183; GFX11-NSZ-NEXT:    v_mul_f16_e32 v1, -4.0, v0184; GFX11-NSZ-NEXT:    s_setpc_b64 s[30:31]185; GFX11-SAFE-TRUE16-LABEL: v_fneg_add_multi_use_add_f16:186; GFX11-SAFE-TRUE16:       ; %bb.0:187; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)188; GFX11-SAFE-TRUE16-NEXT:    v_add_f16_e32 v0.h, v0.l, v1.l189; GFX11-SAFE-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)190; GFX11-SAFE-TRUE16-NEXT:    v_xor_b16 v0.l, 0x8000, v0.h191; GFX11-SAFE-TRUE16-NEXT:    v_mul_f16_e32 v1.l, 4.0, v0.h192; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]193; GFX11-NSZ-TRUE16-LABEL: v_fneg_add_multi_use_add_f16:194; GFX11-NSZ-TRUE16:       ; %bb.0:195; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)196; GFX11-NSZ-TRUE16-NEXT:    v_sub_f16_e64 v0.l, -v0.l, v1.l197; GFX11-NSZ-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)198; GFX11-NSZ-TRUE16-NEXT:    v_mul_f16_e32 v1.l, -4.0, v0.l199; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]200  %add = fadd half %a, %b201  %fneg = fneg half %add202  %use1 = fmul half %add, 4.0203 204  %insert.0 = insertvalue { half, half } poison, half %fneg, 0205  %insert.1 = insertvalue { half, half } %insert.0, half %use1, 1206  ret { half, half } %insert.1207}208 209define half @v_fneg_add_fneg_x_f16(half %a, half %b) #0 {210; SI-SAFE-LABEL: v_fneg_add_fneg_x_f16:211; SI-SAFE:       ; %bb.0:212; SI-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)213; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v0, v0214; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v1, v1215; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v0, v0216; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v1, v1217; SI-SAFE-NEXT:    v_sub_f32_e32 v0, v1, v0218; SI-SAFE-NEXT:    v_xor_b32_e32 v0, 0x80000000, v0219; SI-SAFE-NEXT:    s_setpc_b64 s[30:31]220;221; SI-NSZ-LABEL: v_fneg_add_fneg_x_f16:222; SI-NSZ:       ; %bb.0:223; SI-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)224; SI-NSZ-NEXT:    v_cvt_f16_f32_e32 v1, v1225; SI-NSZ-NEXT:    v_cvt_f16_f32_e32 v0, v0226; SI-NSZ-NEXT:    v_cvt_f32_f16_e32 v1, v1227; SI-NSZ-NEXT:    v_cvt_f32_f16_e32 v0, v0228; SI-NSZ-NEXT:    v_sub_f32_e32 v0, v0, v1229; SI-NSZ-NEXT:    s_setpc_b64 s[30:31]230;231; VI-SAFE-LABEL: v_fneg_add_fneg_x_f16:232; VI-SAFE:       ; %bb.0:233; VI-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)234; VI-SAFE-NEXT:    v_sub_f16_e32 v0, v1, v0235; VI-SAFE-NEXT:    v_xor_b32_e32 v0, 0x8000, v0236; VI-SAFE-NEXT:    s_setpc_b64 s[30:31]237;238; VI-NSZ-LABEL: v_fneg_add_fneg_x_f16:239; VI-NSZ:       ; %bb.0:240; VI-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)241; VI-NSZ-NEXT:    v_sub_f16_e32 v0, v0, v1242; VI-NSZ-NEXT:    s_setpc_b64 s[30:31]243;244; GFX11-SAFE-LABEL: v_fneg_add_fneg_x_f16:245; GFX11-SAFE:       ; %bb.0:246; GFX11-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)247; GFX11-SAFE-NEXT:    v_sub_f16_e32 v0, v1, v0248; GFX11-SAFE-NEXT:    s_delay_alu instid0(VALU_DEP_1)249; GFX11-SAFE-NEXT:    v_xor_b32_e32 v0, 0x8000, v0250; GFX11-SAFE-NEXT:    s_setpc_b64 s[30:31]251;252; GFX11-NSZ-LABEL: v_fneg_add_fneg_x_f16:253; GFX11-NSZ:       ; %bb.0:254; GFX11-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)255; GFX11-NSZ-NEXT:    v_sub_f16_e32 v0, v0, v1256; GFX11-NSZ-NEXT:    s_setpc_b64 s[30:31]257; GFX11-SAFE-TRUE16-LABEL: v_fneg_add_fneg_x_f16:258; GFX11-SAFE-TRUE16:       ; %bb.0:259; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)260; GFX11-SAFE-TRUE16-NEXT:    v_sub_f16_e32 v0.l, v1.l, v0.l261; GFX11-SAFE-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)262; GFX11-SAFE-TRUE16-NEXT:    v_xor_b16 v0.l, 0x8000, v0.l263; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]264; GFX11-NSZ-TRUE16-LABEL: v_fneg_add_fneg_x_f16:265; GFX11-NSZ-TRUE16:       ; %bb.0:266; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)267; GFX11-NSZ-TRUE16-NEXT:    v_sub_f16_e32 v0.l, v0.l, v1.l268; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]269  %fneg.a = fneg half %a270  %add = fadd half %fneg.a, %b271  %fneg = fneg half %add272  ret half %fneg273}274 275define half @v_fneg_add_x_fneg_f16(half %a, half %b) #0 {276; SI-SAFE-LABEL: v_fneg_add_x_fneg_f16:277; SI-SAFE:       ; %bb.0:278; SI-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)279; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v1, v1280; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v0, v0281; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v1, v1282; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v0, v0283; SI-SAFE-NEXT:    v_sub_f32_e32 v0, v0, v1284; SI-SAFE-NEXT:    v_xor_b32_e32 v0, 0x80000000, v0285; SI-SAFE-NEXT:    s_setpc_b64 s[30:31]286;287; SI-NSZ-LABEL: v_fneg_add_x_fneg_f16:288; SI-NSZ:       ; %bb.0:289; SI-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)290; SI-NSZ-NEXT:    v_cvt_f16_f32_e32 v0, v0291; SI-NSZ-NEXT:    v_cvt_f16_f32_e32 v1, v1292; SI-NSZ-NEXT:    v_cvt_f32_f16_e32 v0, v0293; SI-NSZ-NEXT:    v_cvt_f32_f16_e32 v1, v1294; SI-NSZ-NEXT:    v_sub_f32_e32 v0, v1, v0295; SI-NSZ-NEXT:    s_setpc_b64 s[30:31]296;297; VI-SAFE-LABEL: v_fneg_add_x_fneg_f16:298; VI-SAFE:       ; %bb.0:299; VI-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)300; VI-SAFE-NEXT:    v_sub_f16_e32 v0, v0, v1301; VI-SAFE-NEXT:    v_xor_b32_e32 v0, 0x8000, v0302; VI-SAFE-NEXT:    s_setpc_b64 s[30:31]303;304; VI-NSZ-LABEL: v_fneg_add_x_fneg_f16:305; VI-NSZ:       ; %bb.0:306; VI-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)307; VI-NSZ-NEXT:    v_sub_f16_e32 v0, v1, v0308; VI-NSZ-NEXT:    s_setpc_b64 s[30:31]309;310; GFX11-SAFE-LABEL: v_fneg_add_x_fneg_f16:311; GFX11-SAFE:       ; %bb.0:312; GFX11-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)313; GFX11-SAFE-NEXT:    v_sub_f16_e32 v0, v0, v1314; GFX11-SAFE-NEXT:    s_delay_alu instid0(VALU_DEP_1)315; GFX11-SAFE-NEXT:    v_xor_b32_e32 v0, 0x8000, v0316; GFX11-SAFE-NEXT:    s_setpc_b64 s[30:31]317;318; GFX11-NSZ-LABEL: v_fneg_add_x_fneg_f16:319; GFX11-NSZ:       ; %bb.0:320; GFX11-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)321; GFX11-NSZ-NEXT:    v_sub_f16_e32 v0, v1, v0322; GFX11-NSZ-NEXT:    s_setpc_b64 s[30:31]323; GFX11-SAFE-TRUE16-LABEL: v_fneg_add_x_fneg_f16:324; GFX11-SAFE-TRUE16:       ; %bb.0:325; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)326; GFX11-SAFE-TRUE16-NEXT:    v_sub_f16_e32 v0.l, v0.l, v1.l327; GFX11-SAFE-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)328; GFX11-SAFE-TRUE16-NEXT:    v_xor_b16 v0.l, 0x8000, v0.l329; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]330; GFX11-NSZ-TRUE16-LABEL: v_fneg_add_x_fneg_f16:331; GFX11-NSZ-TRUE16:       ; %bb.0:332; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)333; GFX11-NSZ-TRUE16-NEXT:    v_sub_f16_e32 v0.l, v1.l, v0.l334; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]335  %fneg.b = fneg half %b336  %add = fadd half %a, %fneg.b337  %fneg = fneg half %add338  ret half %fneg339}340 341define half @v_fneg_add_fneg_fneg_f16(half %a, half %b) #0 {342; SI-SAFE-LABEL: v_fneg_add_fneg_fneg_f16:343; SI-SAFE:       ; %bb.0:344; SI-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)345; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v1, v1346; SI-SAFE-NEXT:    v_cvt_f16_f32_e64 v0, -v0347; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v1, v1348; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v0, v0349; SI-SAFE-NEXT:    v_sub_f32_e32 v0, v0, v1350; SI-SAFE-NEXT:    v_xor_b32_e32 v0, 0x80000000, v0351; SI-SAFE-NEXT:    s_setpc_b64 s[30:31]352;353; SI-NSZ-LABEL: v_fneg_add_fneg_fneg_f16:354; SI-NSZ:       ; %bb.0:355; SI-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)356; SI-NSZ-NEXT:    v_cvt_f16_f32_e32 v1, v1357; SI-NSZ-NEXT:    v_cvt_f16_f32_e32 v0, v0358; SI-NSZ-NEXT:    v_cvt_f32_f16_e32 v1, v1359; SI-NSZ-NEXT:    v_cvt_f32_f16_e32 v0, v0360; SI-NSZ-NEXT:    v_add_f32_e32 v0, v0, v1361; SI-NSZ-NEXT:    s_setpc_b64 s[30:31]362;363; VI-SAFE-LABEL: v_fneg_add_fneg_fneg_f16:364; VI-SAFE:       ; %bb.0:365; VI-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)366; VI-SAFE-NEXT:    v_sub_f16_e64 v0, -v0, v1367; VI-SAFE-NEXT:    v_xor_b32_e32 v0, 0x8000, v0368; VI-SAFE-NEXT:    s_setpc_b64 s[30:31]369;370; VI-NSZ-LABEL: v_fneg_add_fneg_fneg_f16:371; VI-NSZ:       ; %bb.0:372; VI-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)373; VI-NSZ-NEXT:    v_add_f16_e32 v0, v0, v1374; VI-NSZ-NEXT:    s_setpc_b64 s[30:31]375;376; GFX11-SAFE-LABEL: v_fneg_add_fneg_fneg_f16:377; GFX11-SAFE:       ; %bb.0:378; GFX11-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)379; GFX11-SAFE-NEXT:    v_sub_f16_e64 v0, -v0, v1380; GFX11-SAFE-NEXT:    s_delay_alu instid0(VALU_DEP_1)381; GFX11-SAFE-NEXT:    v_xor_b32_e32 v0, 0x8000, v0382; GFX11-SAFE-NEXT:    s_setpc_b64 s[30:31]383;384; GFX11-NSZ-LABEL: v_fneg_add_fneg_fneg_f16:385; GFX11-NSZ:       ; %bb.0:386; GFX11-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)387; GFX11-NSZ-NEXT:    v_add_f16_e32 v0, v0, v1388; GFX11-NSZ-NEXT:    s_setpc_b64 s[30:31]389; GFX11-SAFE-TRUE16-LABEL: v_fneg_add_fneg_fneg_f16:390; GFX11-SAFE-TRUE16:       ; %bb.0:391; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)392; GFX11-SAFE-TRUE16-NEXT:    v_sub_f16_e64 v0.l, -v0.l, v1.l393; GFX11-SAFE-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)394; GFX11-SAFE-TRUE16-NEXT:    v_xor_b16 v0.l, 0x8000, v0.l395; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]396; GFX11-NSZ-TRUE16-LABEL: v_fneg_add_fneg_fneg_f16:397; GFX11-NSZ-TRUE16:       ; %bb.0:398; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)399; GFX11-NSZ-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v1.l400; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]401  %fneg.a = fneg half %a402  %fneg.b = fneg half %b403  %add = fadd half %fneg.a, %fneg.b404  %fneg = fneg half %add405  ret half %fneg406}407 408define { half, half } @v_fneg_add_store_use_fneg_x_f16(half %a, half %b) #0 {409; SI-SAFE-LABEL: v_fneg_add_store_use_fneg_x_f16:410; SI-SAFE:       ; %bb.0:411; SI-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)412; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v0, v0413; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v1, v1414; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v2, v0415; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v3, v1416; SI-SAFE-NEXT:    v_cvt_f32_f16_e64 v1, -v0417; SI-SAFE-NEXT:    v_sub_f32_e32 v0, v3, v2418; SI-SAFE-NEXT:    v_xor_b32_e32 v0, 0x80000000, v0419; SI-SAFE-NEXT:    s_setpc_b64 s[30:31]420;421; SI-NSZ-LABEL: v_fneg_add_store_use_fneg_x_f16:422; SI-NSZ:       ; %bb.0:423; SI-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)424; SI-NSZ-NEXT:    v_cvt_f16_f32_e32 v1, v1425; SI-NSZ-NEXT:    v_cvt_f16_f32_e32 v0, v0426; SI-NSZ-NEXT:    v_cvt_f32_f16_e32 v2, v1427; SI-NSZ-NEXT:    v_cvt_f32_f16_e32 v3, v0428; SI-NSZ-NEXT:    v_cvt_f32_f16_e64 v1, -v0429; SI-NSZ-NEXT:    v_sub_f32_e32 v0, v3, v2430; SI-NSZ-NEXT:    s_setpc_b64 s[30:31]431;432; VI-SAFE-LABEL: v_fneg_add_store_use_fneg_x_f16:433; VI-SAFE:       ; %bb.0:434; VI-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)435; VI-SAFE-NEXT:    v_xor_b32_e32 v2, 0x8000, v0436; VI-SAFE-NEXT:    v_sub_f16_e32 v0, v1, v0437; VI-SAFE-NEXT:    v_xor_b32_e32 v0, 0x8000, v0438; VI-SAFE-NEXT:    v_mov_b32_e32 v1, v2439; VI-SAFE-NEXT:    s_setpc_b64 s[30:31]440;441; VI-NSZ-LABEL: v_fneg_add_store_use_fneg_x_f16:442; VI-NSZ:       ; %bb.0:443; VI-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)444; VI-NSZ-NEXT:    v_xor_b32_e32 v2, 0x8000, v0445; VI-NSZ-NEXT:    v_sub_f16_e32 v0, v0, v1446; VI-NSZ-NEXT:    v_mov_b32_e32 v1, v2447; VI-NSZ-NEXT:    s_setpc_b64 s[30:31]448;449; GFX11-SAFE-LABEL: v_fneg_add_store_use_fneg_x_f16:450; GFX11-SAFE:       ; %bb.0:451; GFX11-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)452; GFX11-SAFE-NEXT:    v_sub_f16_e32 v1, v1, v0453; GFX11-SAFE-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)454; GFX11-SAFE-NEXT:    v_xor_b32_e32 v2, 0x8000, v1455; GFX11-SAFE-NEXT:    v_xor_b32_e32 v1, 0x8000, v0456; GFX11-SAFE-NEXT:    v_mov_b32_e32 v0, v2457; GFX11-SAFE-NEXT:    s_setpc_b64 s[30:31]458;459; GFX11-NSZ-LABEL: v_fneg_add_store_use_fneg_x_f16:460; GFX11-NSZ:       ; %bb.0:461; GFX11-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)462; GFX11-NSZ-NEXT:    v_sub_f16_e32 v2, v0, v1463; GFX11-NSZ-NEXT:    v_xor_b32_e32 v1, 0x8000, v0464; GFX11-NSZ-NEXT:    s_delay_alu instid0(VALU_DEP_2)465; GFX11-NSZ-NEXT:    v_mov_b32_e32 v0, v2466; GFX11-NSZ-NEXT:    s_setpc_b64 s[30:31]467; GFX11-SAFE-TRUE16-LABEL: v_fneg_add_store_use_fneg_x_f16:468; GFX11-SAFE-TRUE16:       ; %bb.0:469; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)470; GFX11-SAFE-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v0.l471; GFX11-SAFE-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)472; GFX11-SAFE-TRUE16-NEXT:    v_sub_f16_e32 v0.l, v1.l, v0.h473; GFX11-SAFE-TRUE16-NEXT:    v_xor_b16 v1.l, 0x8000, v0.h474; GFX11-SAFE-TRUE16-NEXT:    v_xor_b16 v0.l, 0x8000, v0.l475; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]476; GFX11-NSZ-TRUE16-LABEL: v_fneg_add_store_use_fneg_x_f16:477; GFX11-NSZ-TRUE16:       ; %bb.0:478; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)479; GFX11-NSZ-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v0.l480; GFX11-NSZ-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)481; GFX11-NSZ-TRUE16-NEXT:    v_sub_f16_e32 v0.l, v0.h, v1.l482; GFX11-NSZ-TRUE16-NEXT:    v_xor_b16 v1.l, 0x8000, v0.h483; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]484  %fneg.a = fneg half %a485  %add = fadd half %fneg.a, %b486  %fneg = fneg half %add487  %insert.0 = insertvalue { half, half } poison, half %fneg, 0488  %insert.1 = insertvalue { half, half } %insert.0, half %fneg.a, 1489  ret { half, half } %insert.1490}491 492define { half, half } @v_fneg_add_multi_use_fneg_x_f16(half %a, half %b, half %c) #0 {493; SI-SAFE-LABEL: v_fneg_add_multi_use_fneg_x_f16:494; SI-SAFE:       ; %bb.0:495; SI-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)496; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v0, v0497; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v1, v1498; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v2, v2499; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v3, v0500; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v1, v1501; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v2, v2502; SI-SAFE-NEXT:    v_cvt_f32_f16_e64 v4, -v0503; SI-SAFE-NEXT:    v_sub_f32_e32 v0, v1, v3504; SI-SAFE-NEXT:    v_xor_b32_e32 v0, 0x80000000, v0505; SI-SAFE-NEXT:    v_mul_f32_e32 v1, v4, v2506; SI-SAFE-NEXT:    s_setpc_b64 s[30:31]507;508; SI-NSZ-LABEL: v_fneg_add_multi_use_fneg_x_f16:509; SI-NSZ:       ; %bb.0:510; SI-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)511; SI-NSZ-NEXT:    v_cvt_f16_f32_e32 v2, v2512; SI-NSZ-NEXT:    v_cvt_f16_f32_e32 v1, v1513; SI-NSZ-NEXT:    v_cvt_f16_f32_e32 v0, v0514; SI-NSZ-NEXT:    v_cvt_f32_f16_e32 v2, v2515; SI-NSZ-NEXT:    v_cvt_f32_f16_e32 v1, v1516; SI-NSZ-NEXT:    v_cvt_f32_f16_e32 v3, v0517; SI-NSZ-NEXT:    v_cvt_f32_f16_e64 v4, -v0518; SI-NSZ-NEXT:    v_sub_f32_e32 v0, v3, v1519; SI-NSZ-NEXT:    v_mul_f32_e32 v1, v4, v2520; SI-NSZ-NEXT:    s_setpc_b64 s[30:31]521;522; VI-SAFE-LABEL: v_fneg_add_multi_use_fneg_x_f16:523; VI-SAFE:       ; %bb.0:524; VI-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)525; VI-SAFE-NEXT:    v_sub_f16_e32 v1, v1, v0526; VI-SAFE-NEXT:    v_xor_b32_e32 v3, 0x8000, v1527; VI-SAFE-NEXT:    v_mul_f16_e64 v1, -v0, v2528; VI-SAFE-NEXT:    v_mov_b32_e32 v0, v3529; VI-SAFE-NEXT:    s_setpc_b64 s[30:31]530;531; VI-NSZ-LABEL: v_fneg_add_multi_use_fneg_x_f16:532; VI-NSZ:       ; %bb.0:533; VI-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)534; VI-NSZ-NEXT:    v_sub_f16_e32 v3, v0, v1535; VI-NSZ-NEXT:    v_mul_f16_e64 v1, -v0, v2536; VI-NSZ-NEXT:    v_mov_b32_e32 v0, v3537; VI-NSZ-NEXT:    s_setpc_b64 s[30:31]538;539; GFX11-SAFE-LABEL: v_fneg_add_multi_use_fneg_x_f16:540; GFX11-SAFE:       ; %bb.0:541; GFX11-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)542; GFX11-SAFE-NEXT:    v_sub_f16_e32 v1, v1, v0543; GFX11-SAFE-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)544; GFX11-SAFE-NEXT:    v_xor_b32_e32 v3, 0x8000, v1545; GFX11-SAFE-NEXT:    v_mul_f16_e64 v1, -v0, v2546; GFX11-SAFE-NEXT:    v_mov_b32_e32 v0, v3547; GFX11-SAFE-NEXT:    s_setpc_b64 s[30:31]548;549; GFX11-NSZ-LABEL: v_fneg_add_multi_use_fneg_x_f16:550; GFX11-NSZ:       ; %bb.0:551; GFX11-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)552; GFX11-NSZ-NEXT:    v_sub_f16_e32 v3, v0, v1553; GFX11-NSZ-NEXT:    v_mul_f16_e64 v1, -v0, v2554; GFX11-NSZ-NEXT:    s_delay_alu instid0(VALU_DEP_2)555; GFX11-NSZ-NEXT:    v_mov_b32_e32 v0, v3556; GFX11-NSZ-NEXT:    s_setpc_b64 s[30:31]557; GFX11-SAFE-TRUE16-LABEL: v_fneg_add_multi_use_fneg_x_f16:558; GFX11-SAFE-TRUE16:       ; %bb.0:559; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)560; GFX11-SAFE-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v0.l561; GFX11-SAFE-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)562; GFX11-SAFE-TRUE16-NEXT:    v_sub_f16_e32 v0.l, v1.l, v0.h563; GFX11-SAFE-TRUE16-NEXT:    v_mul_f16_e64 v1.l, -v0.h, v2.l564; GFX11-SAFE-TRUE16-NEXT:    v_xor_b16 v0.l, 0x8000, v0.l565; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]566; GFX11-NSZ-TRUE16-LABEL: v_fneg_add_multi_use_fneg_x_f16:567; GFX11-NSZ-TRUE16:       ; %bb.0:568; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)569; GFX11-NSZ-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v0.l570; GFX11-NSZ-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)571; GFX11-NSZ-TRUE16-NEXT:    v_sub_f16_e32 v0.l, v0.h, v1.l572; GFX11-NSZ-TRUE16-NEXT:    v_mul_f16_e64 v1.l, -v0.h, v2.l573; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]574  %fneg.a = fneg half %a575  %add = fadd half %fneg.a, %b576  %fneg = fneg half %add577  %use1 = fmul half %fneg.a, %c578 579  %insert.0 = insertvalue { half, half } poison, half %fneg, 0580  %insert.1 = insertvalue { half, half } %insert.0, half %use1, 1581  ret { half, half } %insert.1582}583 584define amdgpu_ps half @fneg_fadd_0_safe_f16(half inreg %tmp2, half inreg %tmp6, <4 x i32> %arg) #0 {585; SI-LABEL: fneg_fadd_0_safe_f16:586; SI:       ; %bb.0: ; %.entry587; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0588; SI-NEXT:    v_cvt_f16_f32_e32 v0, s1589; SI-NEXT:    v_cvt_f16_f32_e32 v1, s0590; SI-NEXT:    v_cvt_f32_f16_e32 v0, v0591; SI-NEXT:    v_cvt_f32_f16_e32 v1, v1592; SI-NEXT:    v_div_scale_f32 v2, s[0:1], v0, v0, 1.0593; SI-NEXT:    v_rcp_f32_e32 v3, v2594; SI-NEXT:    v_div_scale_f32 v4, vcc, 1.0, v0, 1.0595; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3596; SI-NEXT:    v_fma_f32 v5, -v2, v3, 1.0597; SI-NEXT:    v_fma_f32 v3, v5, v3, v3598; SI-NEXT:    v_mul_f32_e32 v5, v4, v3599; SI-NEXT:    v_fma_f32 v6, -v2, v5, v4600; SI-NEXT:    v_fma_f32 v5, v6, v3, v5601; SI-NEXT:    v_fma_f32 v2, -v2, v5, v4602; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0603; SI-NEXT:    v_div_fmas_f32 v2, v2, v3, v5604; SI-NEXT:    v_div_fixup_f32 v0, v2, v0, 1.0605; SI-NEXT:    v_mad_f32 v0, v0, 0, 0606; SI-NEXT:    v_cmp_nlt_f32_e32 vcc, v0, v1607; SI-NEXT:    v_cndmask_b32_e64 v0, -v0, v1, vcc608; SI-NEXT:    v_mov_b32_e32 v1, 0x7fc00000609; SI-NEXT:    v_cmp_nlt_f32_e32 vcc, 0, v0610; SI-NEXT:    v_cndmask_b32_e64 v0, v1, 0, vcc611; SI-NEXT:    ; return to shader part epilog612;613; VI-LABEL: fneg_fadd_0_safe_f16:614; VI:       ; %bb.0: ; %.entry615; VI-NEXT:    v_rcp_f16_e32 v0, s1616; VI-NEXT:    v_mov_b32_e32 v1, s0617; VI-NEXT:    v_mul_f16_e32 v0, 0, v0618; VI-NEXT:    v_add_f16_e32 v0, 0, v0619; VI-NEXT:    v_xor_b32_e32 v2, 0x8000, v0620; VI-NEXT:    v_cmp_ngt_f16_e32 vcc, s0, v0621; VI-NEXT:    v_cndmask_b32_e32 v0, v2, v1, vcc622; VI-NEXT:    v_mov_b32_e32 v1, 0x7e00623; VI-NEXT:    v_cmp_nlt_f16_e32 vcc, 0, v0624; VI-NEXT:    v_cndmask_b32_e64 v0, v1, 0, vcc625; VI-NEXT:    ; return to shader part epilog626;627; GFX11-LABEL: fneg_fadd_0_safe_f16:628; GFX11:       ; %bb.0: ; %.entry629; GFX11-NEXT:    v_rcp_f16_e32 v0, s1630; GFX11-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)631; GFX11-NEXT:    v_mul_f16_e32 v0, 0, v0632; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)633; GFX11-NEXT:    v_add_f16_e32 v0, 0, v0634; GFX11-NEXT:    v_xor_b32_e32 v1, 0x8000, v0635; GFX11-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, s0, v0636; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)637; GFX11-NEXT:    v_cndmask_b32_e64 v0, v1, s0, vcc_lo638; GFX11-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, 0, v0639; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0x7e00, 0, vcc_lo640; GFX11-NEXT:    ; return to shader part epilog641.entry:642  %tmp7 = fdiv half 1.000000e+00, %tmp6643  %tmp8 = fmul half 0.000000e+00, %tmp7644  %tmp9 = fmul reassoc nnan arcp contract half 0.000000e+00, %tmp8645  %.i188 = fadd half %tmp9, 0.000000e+00646  %tmp10 = fcmp uge half %.i188, %tmp2647  %tmp11 = fneg half %.i188648  %.i092 = select i1 %tmp10, half %tmp2, half %tmp11649  %tmp12 = fcmp ule half %.i092, 0.000000e+00650  %.i198 = select i1 %tmp12, half 0.000000e+00, half 0x7FF8000000000000651  ret half %.i198652}653 654define amdgpu_ps half @fneg_fadd_0_nsz_f16(half inreg %tmp2, half inreg %tmp6, <4 x i32> %arg) #2 {655; SI-LABEL: fneg_fadd_0_nsz_f16:656; SI:       ; %bb.0: ; %.entry657; SI-NEXT:    v_cvt_f16_f32_e32 v0, s1658; SI-NEXT:    v_cvt_f16_f32_e32 v1, s0659; SI-NEXT:    v_mov_b32_e32 v2, 0x7fc00000660; SI-NEXT:    v_cvt_f32_f16_e32 v0, v0661; SI-NEXT:    v_cvt_f32_f16_e32 v1, v1662; SI-NEXT:    v_rcp_f32_e32 v0, v0663; SI-NEXT:    v_mul_f32_e32 v0, 0x80000000, v0664; SI-NEXT:    v_cmp_nlt_f32_e64 vcc, -v0, v1665; SI-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc666; SI-NEXT:    v_cmp_nlt_f32_e32 vcc, 0, v0667; SI-NEXT:    v_cndmask_b32_e64 v0, v2, 0, vcc668; SI-NEXT:    ; return to shader part epilog669;670; VI-LABEL: fneg_fadd_0_nsz_f16:671; VI:       ; %bb.0: ; %.entry672; VI-NEXT:    v_rcp_f16_e32 v0, s1673; VI-NEXT:    v_mov_b32_e32 v1, s0674; VI-NEXT:    v_mul_f16_e32 v0, 0x8000, v0675; VI-NEXT:    v_cmp_nlt_f16_e64 vcc, -v0, s0676; VI-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc677; VI-NEXT:    v_mov_b32_e32 v1, 0x7e00678; VI-NEXT:    v_cmp_nlt_f16_e32 vcc, 0, v0679; VI-NEXT:    v_cndmask_b32_e64 v0, v1, 0, vcc680; VI-NEXT:    ; return to shader part epilog681;682; GFX11-LABEL: fneg_fadd_0_nsz_f16:683; GFX11:       ; %bb.0: ; %.entry684; GFX11-NEXT:    v_rcp_f16_e32 v0, s1685; GFX11-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)686; GFX11-NEXT:    v_mul_f16_e32 v0, 0x8000, v0687; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)688; GFX11-NEXT:    v_cmp_nlt_f16_e64 s1, -v0, s0689; GFX11-NEXT:    v_cndmask_b32_e64 v0, v0, s0, s1690; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)691; GFX11-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, 0, v0692; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0x7e00, 0, vcc_lo693; GFX11-NEXT:    ; return to shader part epilog694.entry:695  %tmp7 = fdiv afn half 1.000000e+00, %tmp6696  %tmp8 = fmul contract half 0.000000e+00, %tmp7697  %tmp9 = fmul reassoc nnan arcp contract half 0.000000e+00, %tmp8698  %.i188 = fadd nsz half %tmp9, 0.000000e+00699  %tmp10 = fcmp uge half %.i188, %tmp2700  %tmp11 = fneg half %.i188701  %.i092 = select i1 %tmp10, half %tmp2, half %tmp11702  %tmp12 = fcmp ule half %.i092, 0.000000e+00703  %.i198 = select i1 %tmp12, half 0.000000e+00, half 0x7FF8000000000000704  ret half %.i198705}706 707; --------------------------------------------------------------------------------708; fmul tests709; --------------------------------------------------------------------------------710 711define half @v_fneg_mul_f16(half %a, half %b) #0 {712; SI-LABEL: v_fneg_mul_f16:713; SI:       ; %bb.0:714; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)715; SI-NEXT:    v_cvt_f16_f32_e32 v0, v0716; SI-NEXT:    v_cvt_f16_f32_e64 v1, -v1717; SI-NEXT:    v_cvt_f32_f16_e32 v0, v0718; SI-NEXT:    v_cvt_f32_f16_e32 v1, v1719; SI-NEXT:    v_mul_f32_e32 v0, v0, v1720; SI-NEXT:    s_setpc_b64 s[30:31]721;722; VI-LABEL: v_fneg_mul_f16:723; VI:       ; %bb.0:724; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)725; VI-NEXT:    v_mul_f16_e64 v0, v0, -v1726; VI-NEXT:    s_setpc_b64 s[30:31]727;728; GFX11-LABEL: v_fneg_mul_f16:729; GFX11:       ; %bb.0:730; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)731; GFX11-NEXT:    v_mul_f16_e64 v0, v0, -v1732; GFX11-NEXT:    s_setpc_b64 s[30:31]733; GFX11-SAFE-TRUE16-LABEL: v_fneg_mul_f16:734; GFX11-SAFE-TRUE16:       ; %bb.0:735; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)736; GFX11-SAFE-TRUE16-NEXT:    v_mul_f16_e64 v0.l, v0.l, -v1.l737; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]738; GFX11-NSZ-TRUE16-LABEL: v_fneg_mul_f16:739; GFX11-NSZ-TRUE16:       ; %bb.0:740; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)741; GFX11-NSZ-TRUE16-NEXT:    v_mul_f16_e64 v0.l, v0.l, -v1.l742; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]743  %mul = fmul half %a, %b744  %fneg = fneg half %mul745  ret half %fneg746}747 748define { half, half } @v_fneg_mul_store_use_mul_f16(half %a, half %b) #0 {749; SI-LABEL: v_fneg_mul_store_use_mul_f16:750; SI:       ; %bb.0:751; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)752; SI-NEXT:    v_cvt_f16_f32_e32 v1, v1753; SI-NEXT:    v_cvt_f16_f32_e32 v0, v0754; SI-NEXT:    v_cvt_f32_f16_e32 v1, v1755; SI-NEXT:    v_cvt_f32_f16_e32 v0, v0756; SI-NEXT:    v_mul_f32_e32 v1, v0, v1757; SI-NEXT:    v_xor_b32_e32 v0, 0x80000000, v1758; SI-NEXT:    s_setpc_b64 s[30:31]759;760; VI-LABEL: v_fneg_mul_store_use_mul_f16:761; VI:       ; %bb.0:762; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)763; VI-NEXT:    v_mul_f16_e32 v1, v0, v1764; VI-NEXT:    v_xor_b32_e32 v0, 0x8000, v1765; VI-NEXT:    s_setpc_b64 s[30:31]766;767; GFX11-LABEL: v_fneg_mul_store_use_mul_f16:768; GFX11:       ; %bb.0:769; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)770; GFX11-NEXT:    v_mul_f16_e32 v1, v0, v1771; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)772; GFX11-NEXT:    v_xor_b32_e32 v0, 0x8000, v1773; GFX11-NEXT:    s_setpc_b64 s[30:31]774; GFX11-SAFE-TRUE16-LABEL: v_fneg_mul_store_use_mul_f16:775; GFX11-SAFE-TRUE16:       ; %bb.0:776; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)777; GFX11-SAFE-TRUE16-NEXT:    v_mul_f16_e32 v1.l, v0.l, v1.l778; GFX11-SAFE-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)779; GFX11-SAFE-TRUE16-NEXT:    v_xor_b16 v0.l, 0x8000, v1.l780; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]781; GFX11-NSZ-TRUE16-LABEL: v_fneg_mul_store_use_mul_f16:782; GFX11-NSZ-TRUE16:       ; %bb.0:783; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)784; GFX11-NSZ-TRUE16-NEXT:    v_mul_f16_e32 v1.l, v0.l, v1.l785; GFX11-NSZ-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)786; GFX11-NSZ-TRUE16-NEXT:    v_xor_b16 v0.l, 0x8000, v1.l787; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]788  %mul = fmul half %a, %b789  %fneg = fneg half %mul790  %insert.0 = insertvalue { half, half } poison, half %fneg, 0791  %insert.1 = insertvalue { half, half } %insert.0, half %mul, 1792  ret { half, half } %insert.1793}794 795define { half, half } @v_fneg_mul_multi_use_mul_f16(half %a, half %b) #0 {796; SI-LABEL: v_fneg_mul_multi_use_mul_f16:797; SI:       ; %bb.0:798; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)799; SI-NEXT:    v_cvt_f16_f32_e32 v0, v0800; SI-NEXT:    v_cvt_f16_f32_e32 v1, v1801; SI-NEXT:    v_cvt_f32_f16_e32 v0, v0802; SI-NEXT:    v_cvt_f32_f16_e64 v1, -v1803; SI-NEXT:    v_mul_f32_e32 v0, v0, v1804; SI-NEXT:    v_mul_f32_e32 v1, -4.0, v0805; SI-NEXT:    s_setpc_b64 s[30:31]806;807; VI-LABEL: v_fneg_mul_multi_use_mul_f16:808; VI:       ; %bb.0:809; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)810; VI-NEXT:    v_mul_f16_e64 v0, v0, -v1811; VI-NEXT:    v_mul_f16_e32 v1, -4.0, v0812; VI-NEXT:    s_setpc_b64 s[30:31]813;814; GFX11-LABEL: v_fneg_mul_multi_use_mul_f16:815; GFX11:       ; %bb.0:816; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)817; GFX11-NEXT:    v_mul_f16_e64 v0, v0, -v1818; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)819; GFX11-NEXT:    v_mul_f16_e32 v1, -4.0, v0820; GFX11-NEXT:    s_setpc_b64 s[30:31]821; GFX11-SAFE-TRUE16-LABEL: v_fneg_mul_multi_use_mul_f16:822; GFX11-SAFE-TRUE16:       ; %bb.0:823; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)824; GFX11-SAFE-TRUE16-NEXT:    v_mul_f16_e64 v0.l, v0.l, -v1.l825; GFX11-SAFE-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)826; GFX11-SAFE-TRUE16-NEXT:    v_mul_f16_e32 v1.l, -4.0, v0.l827; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]828; GFX11-NSZ-TRUE16-LABEL: v_fneg_mul_multi_use_mul_f16:829; GFX11-NSZ-TRUE16:       ; %bb.0:830; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)831; GFX11-NSZ-TRUE16-NEXT:    v_mul_f16_e64 v0.l, v0.l, -v1.l832; GFX11-NSZ-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)833; GFX11-NSZ-TRUE16-NEXT:    v_mul_f16_e32 v1.l, -4.0, v0.l834; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]835  %mul = fmul half %a, %b836  %fneg = fneg half %mul837  %use1 = fmul half %mul, 4.0838  %insert.0 = insertvalue { half, half } poison, half %fneg, 0839  %insert.1 = insertvalue { half, half } %insert.0, half %use1, 1840  ret { half, half } %insert.1841}842 843define half @v_fneg_mul_fneg_x_f16(half %a, half %b) #0 {844; SI-LABEL: v_fneg_mul_fneg_x_f16:845; SI:       ; %bb.0:846; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)847; SI-NEXT:    v_cvt_f16_f32_e32 v1, v1848; SI-NEXT:    v_cvt_f16_f32_e32 v0, v0849; SI-NEXT:    v_cvt_f32_f16_e32 v1, v1850; SI-NEXT:    v_cvt_f32_f16_e32 v0, v0851; SI-NEXT:    v_mul_f32_e32 v0, v0, v1852; SI-NEXT:    s_setpc_b64 s[30:31]853;854; VI-LABEL: v_fneg_mul_fneg_x_f16:855; VI:       ; %bb.0:856; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)857; VI-NEXT:    v_mul_f16_e32 v0, v0, v1858; VI-NEXT:    s_setpc_b64 s[30:31]859;860; GFX11-LABEL: v_fneg_mul_fneg_x_f16:861; GFX11:       ; %bb.0:862; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)863; GFX11-NEXT:    v_mul_f16_e32 v0, v0, v1864; GFX11-NEXT:    s_setpc_b64 s[30:31]865; GFX11-SAFE-TRUE16-LABEL: v_fneg_mul_fneg_x_f16:866; GFX11-SAFE-TRUE16:       ; %bb.0:867; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)868; GFX11-SAFE-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v1.l869; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]870; GFX11-NSZ-TRUE16-LABEL: v_fneg_mul_fneg_x_f16:871; GFX11-NSZ-TRUE16:       ; %bb.0:872; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)873; GFX11-NSZ-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v1.l874; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]875  %fneg.a = fneg half %a876  %mul = fmul half %fneg.a, %b877  %fneg = fneg half %mul878  ret half %fneg879}880 881define half @v_fneg_mul_x_fneg_f16(half %a, half %b) #0 {882; SI-LABEL: v_fneg_mul_x_fneg_f16:883; SI:       ; %bb.0:884; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)885; SI-NEXT:    v_cvt_f16_f32_e32 v1, v1886; SI-NEXT:    v_cvt_f16_f32_e32 v0, v0887; SI-NEXT:    v_cvt_f32_f16_e32 v1, v1888; SI-NEXT:    v_cvt_f32_f16_e32 v0, v0889; SI-NEXT:    v_mul_f32_e32 v0, v0, v1890; SI-NEXT:    s_setpc_b64 s[30:31]891;892; VI-LABEL: v_fneg_mul_x_fneg_f16:893; VI:       ; %bb.0:894; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)895; VI-NEXT:    v_mul_f16_e32 v0, v0, v1896; VI-NEXT:    s_setpc_b64 s[30:31]897;898; GFX11-LABEL: v_fneg_mul_x_fneg_f16:899; GFX11:       ; %bb.0:900; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)901; GFX11-NEXT:    v_mul_f16_e32 v0, v0, v1902; GFX11-NEXT:    s_setpc_b64 s[30:31]903; GFX11-SAFE-TRUE16-LABEL: v_fneg_mul_x_fneg_f16:904; GFX11-SAFE-TRUE16:       ; %bb.0:905; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)906; GFX11-SAFE-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v1.l907; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]908; GFX11-NSZ-TRUE16-LABEL: v_fneg_mul_x_fneg_f16:909; GFX11-NSZ-TRUE16:       ; %bb.0:910; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)911; GFX11-NSZ-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v1.l912; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]913  %fneg.b = fneg half %b914  %mul = fmul half %a, %fneg.b915  %fneg = fneg half %mul916  ret half %fneg917}918 919define half @v_fneg_mul_fneg_fneg_f16(half %a, half %b) #0 {920; SI-LABEL: v_fneg_mul_fneg_fneg_f16:921; SI:       ; %bb.0:922; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)923; SI-NEXT:    v_cvt_f16_f32_e32 v0, v0924; SI-NEXT:    v_cvt_f16_f32_e64 v1, -v1925; SI-NEXT:    v_cvt_f32_f16_e32 v0, v0926; SI-NEXT:    v_cvt_f32_f16_e32 v1, v1927; SI-NEXT:    v_mul_f32_e32 v0, v0, v1928; SI-NEXT:    s_setpc_b64 s[30:31]929;930; VI-LABEL: v_fneg_mul_fneg_fneg_f16:931; VI:       ; %bb.0:932; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)933; VI-NEXT:    v_mul_f16_e64 v0, v0, -v1934; VI-NEXT:    s_setpc_b64 s[30:31]935;936; GFX11-LABEL: v_fneg_mul_fneg_fneg_f16:937; GFX11:       ; %bb.0:938; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)939; GFX11-NEXT:    v_mul_f16_e64 v0, v0, -v1940; GFX11-NEXT:    s_setpc_b64 s[30:31]941; GFX11-SAFE-TRUE16-LABEL: v_fneg_mul_fneg_fneg_f16:942; GFX11-SAFE-TRUE16:       ; %bb.0:943; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)944; GFX11-SAFE-TRUE16-NEXT:    v_mul_f16_e64 v0.l, v0.l, -v1.l945; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]946; GFX11-NSZ-TRUE16-LABEL: v_fneg_mul_fneg_fneg_f16:947; GFX11-NSZ-TRUE16:       ; %bb.0:948; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)949; GFX11-NSZ-TRUE16-NEXT:    v_mul_f16_e64 v0.l, v0.l, -v1.l950; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]951  %fneg.a = fneg half %a952  %fneg.b = fneg half %b953  %mul = fmul half %fneg.a, %fneg.b954  %fneg = fneg half %mul955  ret half %fneg956}957 958define { half, half } @v_fneg_mul_store_use_fneg_x_f16(half %a, half %b) #0 {959; SI-LABEL: v_fneg_mul_store_use_fneg_x_f16:960; SI:       ; %bb.0:961; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)962; SI-NEXT:    v_cvt_f16_f32_e32 v1, v1963; SI-NEXT:    v_cvt_f16_f32_e32 v0, v0964; SI-NEXT:    v_cvt_f32_f16_e32 v2, v1965; SI-NEXT:    v_cvt_f32_f16_e32 v3, v0966; SI-NEXT:    v_cvt_f32_f16_e64 v1, -v0967; SI-NEXT:    v_mul_f32_e32 v0, v3, v2968; SI-NEXT:    s_setpc_b64 s[30:31]969;970; VI-LABEL: v_fneg_mul_store_use_fneg_x_f16:971; VI:       ; %bb.0:972; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)973; VI-NEXT:    v_xor_b32_e32 v2, 0x8000, v0974; VI-NEXT:    v_mul_f16_e32 v0, v0, v1975; VI-NEXT:    v_mov_b32_e32 v1, v2976; VI-NEXT:    s_setpc_b64 s[30:31]977;978; GFX11-LABEL: v_fneg_mul_store_use_fneg_x_f16:979; GFX11:       ; %bb.0:980; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)981; GFX11-NEXT:    v_mul_f16_e32 v2, v0, v1982; GFX11-NEXT:    v_xor_b32_e32 v1, 0x8000, v0983; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)984; GFX11-NEXT:    v_mov_b32_e32 v0, v2985; GFX11-NEXT:    s_setpc_b64 s[30:31]986; GFX11-SAFE-TRUE16-LABEL: v_fneg_mul_store_use_fneg_x_f16:987; GFX11-SAFE-TRUE16:       ; %bb.0:988; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)989; GFX11-SAFE-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v0.l990; GFX11-SAFE-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)991; GFX11-SAFE-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.h, v1.l992; GFX11-SAFE-TRUE16-NEXT:    v_xor_b16 v1.l, 0x8000, v0.h993; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]994; GFX11-NSZ-TRUE16-LABEL: v_fneg_mul_store_use_fneg_x_f16:995; GFX11-NSZ-TRUE16:       ; %bb.0:996; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)997; GFX11-NSZ-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v0.l998; GFX11-NSZ-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)999; GFX11-NSZ-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.h, v1.l1000; GFX11-NSZ-TRUE16-NEXT:    v_xor_b16 v1.l, 0x8000, v0.h1001; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]1002  %fneg.a = fneg half %a1003  %mul = fmul half %fneg.a, %b1004  %fneg = fneg half %mul1005  %insert.0 = insertvalue { half, half } poison, half %fneg, 01006  %insert.1 = insertvalue { half, half } %insert.0, half %fneg.a, 11007  ret { half, half } %insert.11008}1009 1010define { half, half } @v_fneg_mul_multi_use_fneg_x_f16(half %a, half %b, half %c) #0 {1011; SI-LABEL: v_fneg_mul_multi_use_fneg_x_f16:1012; SI:       ; %bb.0:1013; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1014; SI-NEXT:    v_cvt_f16_f32_e32 v2, v21015; SI-NEXT:    v_cvt_f16_f32_e32 v1, v11016; SI-NEXT:    v_cvt_f16_f32_e32 v0, v01017; SI-NEXT:    v_cvt_f32_f16_e32 v2, v21018; SI-NEXT:    v_cvt_f32_f16_e32 v1, v11019; SI-NEXT:    v_cvt_f32_f16_e32 v3, v01020; SI-NEXT:    v_cvt_f32_f16_e64 v4, -v01021; SI-NEXT:    v_mul_f32_e32 v0, v3, v11022; SI-NEXT:    v_mul_f32_e32 v1, v4, v21023; SI-NEXT:    s_setpc_b64 s[30:31]1024;1025; VI-LABEL: v_fneg_mul_multi_use_fneg_x_f16:1026; VI:       ; %bb.0:1027; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1028; VI-NEXT:    v_mul_f16_e32 v3, v0, v11029; VI-NEXT:    v_mul_f16_e64 v1, -v0, v21030; VI-NEXT:    v_mov_b32_e32 v0, v31031; VI-NEXT:    s_setpc_b64 s[30:31]1032;1033; GFX11-LABEL: v_fneg_mul_multi_use_fneg_x_f16:1034; GFX11:       ; %bb.0:1035; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1036; GFX11-NEXT:    v_mul_f16_e32 v3, v0, v11037; GFX11-NEXT:    v_mul_f16_e64 v1, -v0, v21038; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)1039; GFX11-NEXT:    v_mov_b32_e32 v0, v31040; GFX11-NEXT:    s_setpc_b64 s[30:31]1041; GFX11-SAFE-TRUE16-LABEL: v_fneg_mul_multi_use_fneg_x_f16:1042; GFX11-SAFE-TRUE16:       ; %bb.0:1043; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1044; GFX11-SAFE-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v0.l1045; GFX11-SAFE-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)1046; GFX11-SAFE-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.h, v1.l1047; GFX11-SAFE-TRUE16-NEXT:    v_mul_f16_e64 v1.l, -v0.h, v2.l1048; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]1049; GFX11-NSZ-TRUE16-LABEL: v_fneg_mul_multi_use_fneg_x_f16:1050; GFX11-NSZ-TRUE16:       ; %bb.0:1051; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1052; GFX11-NSZ-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v0.l1053; GFX11-NSZ-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)1054; GFX11-NSZ-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.h, v1.l1055; GFX11-NSZ-TRUE16-NEXT:    v_mul_f16_e64 v1.l, -v0.h, v2.l1056; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]1057  %fneg.a = fneg half %a1058  %mul = fmul half %fneg.a, %b1059  %fneg = fneg half %mul1060  %use1 = fmul half %fneg.a, %c1061  %insert.0 = insertvalue { half, half } poison, half %fneg, 01062  %insert.1 = insertvalue { half, half } %insert.0, half %use1, 11063  ret { half, half } %insert.11064}1065 1066; --------------------------------------------------------------------------------1067; fminnum tests1068; --------------------------------------------------------------------------------1069 1070define half @v_fneg_minnum_f16_ieee(half %a, half %b) #0 {1071; SI-LABEL: v_fneg_minnum_f16_ieee:1072; SI:       ; %bb.0:1073; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1074; SI-NEXT:    v_cvt_f16_f32_e64 v1, -v11075; SI-NEXT:    v_cvt_f16_f32_e64 v0, -v01076; SI-NEXT:    v_cvt_f32_f16_e32 v1, v11077; SI-NEXT:    v_cvt_f32_f16_e32 v0, v01078; SI-NEXT:    v_max_f32_e32 v0, v0, v11079; SI-NEXT:    s_setpc_b64 s[30:31]1080;1081; VI-LABEL: v_fneg_minnum_f16_ieee:1082; VI:       ; %bb.0:1083; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1084; VI-NEXT:    v_max_f16_e64 v1, -v1, -v11085; VI-NEXT:    v_max_f16_e64 v0, -v0, -v01086; VI-NEXT:    v_max_f16_e32 v0, v0, v11087; VI-NEXT:    s_setpc_b64 s[30:31]1088;1089; GFX11-LABEL: v_fneg_minnum_f16_ieee:1090; GFX11:       ; %bb.0:1091; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1092; GFX11-NEXT:    v_max_f16_e64 v1, -v1, -v11093; GFX11-NEXT:    v_max_f16_e64 v0, -v0, -v01094; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)1095; GFX11-NEXT:    v_max_f16_e32 v0, v0, v11096; GFX11-NEXT:    s_setpc_b64 s[30:31]1097; GFX11-SAFE-TRUE16-LABEL: v_fneg_minnum_f16_ieee:1098; GFX11-SAFE-TRUE16:       ; %bb.0:1099; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1100; GFX11-SAFE-TRUE16-NEXT:    v_max_f16_e64 v0.h, -v1.l, -v1.l1101; GFX11-SAFE-TRUE16-NEXT:    v_max_f16_e64 v0.l, -v0.l, -v0.l1102; GFX11-SAFE-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)1103; GFX11-SAFE-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v0.h1104; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]1105; GFX11-NSZ-TRUE16-LABEL: v_fneg_minnum_f16_ieee:1106; GFX11-NSZ-TRUE16:       ; %bb.0:1107; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1108; GFX11-NSZ-TRUE16-NEXT:    v_max_f16_e64 v0.h, -v1.l, -v1.l1109; GFX11-NSZ-TRUE16-NEXT:    v_max_f16_e64 v0.l, -v0.l, -v0.l1110; GFX11-NSZ-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)1111; GFX11-NSZ-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v0.h1112; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]1113  %min = call half @llvm.minnum.f16(half %a, half %b)1114  %fneg = fneg half %min1115  ret half %fneg1116}1117 1118define half @v_fneg_minnum_f16_no_ieee(half %a, half %b) #4 {1119; SI-LABEL: v_fneg_minnum_f16_no_ieee:1120; SI:       ; %bb.0:1121; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1122; SI-NEXT:    v_cvt_f16_f32_e64 v1, -v11123; SI-NEXT:    v_cvt_f16_f32_e64 v0, -v01124; SI-NEXT:    v_cvt_f32_f16_e32 v1, v11125; SI-NEXT:    v_cvt_f32_f16_e32 v0, v01126; SI-NEXT:    v_max_f32_e32 v0, v0, v11127; SI-NEXT:    s_setpc_b64 s[30:31]1128;1129; VI-LABEL: v_fneg_minnum_f16_no_ieee:1130; VI:       ; %bb.0:1131; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1132; VI-NEXT:    v_max_f16_e64 v0, -v0, -v11133; VI-NEXT:    s_setpc_b64 s[30:31]1134;1135; GFX11-LABEL: v_fneg_minnum_f16_no_ieee:1136; GFX11:       ; %bb.0:1137; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1138; GFX11-NEXT:    v_max_f16_e64 v0, -v0, -v11139; GFX11-NEXT:    s_setpc_b64 s[30:31]1140; GFX11-SAFE-TRUE16-LABEL: v_fneg_minnum_f16_no_ieee:1141; GFX11-SAFE-TRUE16:       ; %bb.0:1142; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1143; GFX11-SAFE-TRUE16-NEXT:    v_max_f16_e64 v0.l, -v0.l, -v1.l1144; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]1145; GFX11-NSZ-TRUE16-LABEL: v_fneg_minnum_f16_no_ieee:1146; GFX11-NSZ-TRUE16:       ; %bb.0:1147; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1148; GFX11-NSZ-TRUE16-NEXT:    v_max_f16_e64 v0.l, -v0.l, -v1.l1149; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]1150  %min = call half @llvm.minnum.f16(half %a, half %b)1151  %fneg = fneg half %min1152  ret half %fneg1153}1154 1155define half @v_fneg_self_minnum_f16_ieee(half %a) #0 {1156; SI-LABEL: v_fneg_self_minnum_f16_ieee:1157; SI:       ; %bb.0:1158; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1159; SI-NEXT:    v_xor_b32_e32 v0, 0x80000000, v01160; SI-NEXT:    s_setpc_b64 s[30:31]1161;1162; VI-LABEL: v_fneg_self_minnum_f16_ieee:1163; VI:       ; %bb.0:1164; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1165; VI-NEXT:    v_xor_b32_e32 v0, 0x8000, v01166; VI-NEXT:    s_setpc_b64 s[30:31]1167;1168; GFX11-LABEL: v_fneg_self_minnum_f16_ieee:1169; GFX11:       ; %bb.0:1170; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1171; GFX11-NEXT:    v_xor_b32_e32 v0, 0x8000, v01172; GFX11-NEXT:    s_setpc_b64 s[30:31]1173; GFX11-SAFE-TRUE16-LABEL: v_fneg_self_minnum_f16_ieee:1174; GFX11-SAFE-TRUE16:       ; %bb.0:1175; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1176; GFX11-SAFE-TRUE16-NEXT:    v_xor_b16 v0.l, 0x8000, v0.l1177; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]1178; GFX11-NSZ-TRUE16-LABEL: v_fneg_self_minnum_f16_ieee:1179; GFX11-NSZ-TRUE16:       ; %bb.0:1180; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1181; GFX11-NSZ-TRUE16-NEXT:    v_xor_b16 v0.l, 0x8000, v0.l1182; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]1183  %min = call half @llvm.minnum.f16(half %a, half %a)1184  %min.fneg = fneg half %min1185  ret half %min.fneg1186}1187 1188define half @v_fneg_self_minnum_f16_no_ieee(half %a) #4 {1189; SI-LABEL: v_fneg_self_minnum_f16_no_ieee:1190; SI:       ; %bb.0:1191; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1192; SI-NEXT:    v_xor_b32_e32 v0, 0x80000000, v01193; SI-NEXT:    s_setpc_b64 s[30:31]1194;1195; VI-LABEL: v_fneg_self_minnum_f16_no_ieee:1196; VI:       ; %bb.0:1197; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1198; VI-NEXT:    v_xor_b32_e32 v0, 0x8000, v01199; VI-NEXT:    s_setpc_b64 s[30:31]1200;1201; GFX11-LABEL: v_fneg_self_minnum_f16_no_ieee:1202; GFX11:       ; %bb.0:1203; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1204; GFX11-NEXT:    v_xor_b32_e32 v0, 0x8000, v01205; GFX11-NEXT:    s_setpc_b64 s[30:31]1206; GFX11-SAFE-TRUE16-LABEL: v_fneg_self_minnum_f16_no_ieee:1207; GFX11-SAFE-TRUE16:       ; %bb.0:1208; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1209; GFX11-SAFE-TRUE16-NEXT:    v_xor_b16 v0.l, 0x8000, v0.l1210; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]1211; GFX11-NSZ-TRUE16-LABEL: v_fneg_self_minnum_f16_no_ieee:1212; GFX11-NSZ-TRUE16:       ; %bb.0:1213; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1214; GFX11-NSZ-TRUE16-NEXT:    v_xor_b16 v0.l, 0x8000, v0.l1215; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]1216  %min = call half @llvm.minnum.f16(half %a, half %a)1217  %min.fneg = fneg half %min1218  ret half %min.fneg1219}1220 1221define half @v_fneg_posk_minnum_f16_ieee(half %a) #0 {1222; SI-LABEL: v_fneg_posk_minnum_f16_ieee:1223; SI:       ; %bb.0:1224; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1225; SI-NEXT:    v_cvt_f16_f32_e64 v0, -v01226; SI-NEXT:    v_cvt_f32_f16_e32 v0, v01227; SI-NEXT:    v_max_f32_e32 v0, -4.0, v01228; SI-NEXT:    s_setpc_b64 s[30:31]1229;1230; VI-LABEL: v_fneg_posk_minnum_f16_ieee:1231; VI:       ; %bb.0:1232; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1233; VI-NEXT:    v_max_f16_e64 v0, -v0, -v01234; VI-NEXT:    v_max_f16_e32 v0, -4.0, v01235; VI-NEXT:    s_setpc_b64 s[30:31]1236;1237; GFX11-LABEL: v_fneg_posk_minnum_f16_ieee:1238; GFX11:       ; %bb.0:1239; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1240; GFX11-NEXT:    v_max_f16_e64 v0, -v0, -v01241; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)1242; GFX11-NEXT:    v_max_f16_e32 v0, -4.0, v01243; GFX11-NEXT:    s_setpc_b64 s[30:31]1244; GFX11-SAFE-TRUE16-LABEL: v_fneg_posk_minnum_f16_ieee:1245; GFX11-SAFE-TRUE16:       ; %bb.0:1246; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1247; GFX11-SAFE-TRUE16-NEXT:    v_max_f16_e64 v0.l, -v0.l, -v0.l1248; GFX11-SAFE-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)1249; GFX11-SAFE-TRUE16-NEXT:    v_max_f16_e32 v0.l, -4.0, v0.l1250; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]1251; GFX11-NSZ-TRUE16-LABEL: v_fneg_posk_minnum_f16_ieee:1252; GFX11-NSZ-TRUE16:       ; %bb.0:1253; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1254; GFX11-NSZ-TRUE16-NEXT:    v_max_f16_e64 v0.l, -v0.l, -v0.l1255; GFX11-NSZ-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)1256; GFX11-NSZ-TRUE16-NEXT:    v_max_f16_e32 v0.l, -4.0, v0.l1257; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]1258  %min = call half @llvm.minnum.f16(half 4.0, half %a)1259  %fneg = fneg half %min1260  ret half %fneg1261}1262 1263define half @v_fneg_posk_minnum_f16_no_ieee(half %a) #4 {1264; SI-LABEL: v_fneg_posk_minnum_f16_no_ieee:1265; SI:       ; %bb.0:1266; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1267; SI-NEXT:    v_cvt_f16_f32_e64 v0, -v01268; SI-NEXT:    v_cvt_f32_f16_e32 v0, v01269; SI-NEXT:    v_max_f32_e32 v0, -4.0, v01270; SI-NEXT:    s_setpc_b64 s[30:31]1271;1272; VI-LABEL: v_fneg_posk_minnum_f16_no_ieee:1273; VI:       ; %bb.0:1274; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1275; VI-NEXT:    v_max_f16_e64 v0, -v0, -4.01276; VI-NEXT:    s_setpc_b64 s[30:31]1277;1278; GFX11-LABEL: v_fneg_posk_minnum_f16_no_ieee:1279; GFX11:       ; %bb.0:1280; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1281; GFX11-NEXT:    v_max_f16_e64 v0, -v0, -4.01282; GFX11-NEXT:    s_setpc_b64 s[30:31]1283; GFX11-SAFE-TRUE16-LABEL: v_fneg_posk_minnum_f16_no_ieee:1284; GFX11-SAFE-TRUE16:       ; %bb.0:1285; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1286; GFX11-SAFE-TRUE16-NEXT:    v_max_f16_e64 v0.l, -v0.l, -4.01287; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]1288; GFX11-NSZ-TRUE16-LABEL: v_fneg_posk_minnum_f16_no_ieee:1289; GFX11-NSZ-TRUE16:       ; %bb.0:1290; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1291; GFX11-NSZ-TRUE16-NEXT:    v_max_f16_e64 v0.l, -v0.l, -4.01292; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]1293  %min = call half @llvm.minnum.f16(half 4.0, half %a)1294  %fneg = fneg half %min1295  ret half %fneg1296}1297 1298define half @v_fneg_negk_minnum_f16_ieee(half %a) #0 {1299; SI-LABEL: v_fneg_negk_minnum_f16_ieee:1300; SI:       ; %bb.0:1301; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1302; SI-NEXT:    v_cvt_f16_f32_e64 v0, -v01303; SI-NEXT:    v_cvt_f32_f16_e32 v0, v01304; SI-NEXT:    v_max_f32_e32 v0, 4.0, v01305; SI-NEXT:    s_setpc_b64 s[30:31]1306;1307; VI-LABEL: v_fneg_negk_minnum_f16_ieee:1308; VI:       ; %bb.0:1309; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1310; VI-NEXT:    v_max_f16_e64 v0, -v0, -v01311; VI-NEXT:    v_max_f16_e32 v0, 4.0, v01312; VI-NEXT:    s_setpc_b64 s[30:31]1313;1314; GFX11-LABEL: v_fneg_negk_minnum_f16_ieee:1315; GFX11:       ; %bb.0:1316; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1317; GFX11-NEXT:    v_max_f16_e64 v0, -v0, -v01318; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)1319; GFX11-NEXT:    v_max_f16_e32 v0, 4.0, v01320; GFX11-NEXT:    s_setpc_b64 s[30:31]1321; GFX11-SAFE-TRUE16-LABEL: v_fneg_negk_minnum_f16_ieee:1322; GFX11-SAFE-TRUE16:       ; %bb.0:1323; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1324; GFX11-SAFE-TRUE16-NEXT:    v_max_f16_e64 v0.l, -v0.l, -v0.l1325; GFX11-SAFE-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)1326; GFX11-SAFE-TRUE16-NEXT:    v_max_f16_e32 v0.l, 4.0, v0.l1327; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]1328; GFX11-NSZ-TRUE16-LABEL: v_fneg_negk_minnum_f16_ieee:1329; GFX11-NSZ-TRUE16:       ; %bb.0:1330; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1331; GFX11-NSZ-TRUE16-NEXT:    v_max_f16_e64 v0.l, -v0.l, -v0.l1332; GFX11-NSZ-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)1333; GFX11-NSZ-TRUE16-NEXT:    v_max_f16_e32 v0.l, 4.0, v0.l1334; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]1335  %min = call half @llvm.minnum.f16(half -4.0, half %a)1336  %fneg = fneg half %min1337  ret half %fneg1338}1339 1340define half @v_fneg_negk_minnum_f16_no_ieee(half %a) #4 {1341; SI-LABEL: v_fneg_negk_minnum_f16_no_ieee:1342; SI:       ; %bb.0:1343; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1344; SI-NEXT:    v_cvt_f16_f32_e64 v0, -v01345; SI-NEXT:    v_cvt_f32_f16_e32 v0, v01346; SI-NEXT:    v_max_f32_e32 v0, 4.0, v01347; SI-NEXT:    s_setpc_b64 s[30:31]1348;1349; VI-LABEL: v_fneg_negk_minnum_f16_no_ieee:1350; VI:       ; %bb.0:1351; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1352; VI-NEXT:    v_max_f16_e64 v0, -v0, 4.01353; VI-NEXT:    s_setpc_b64 s[30:31]1354;1355; GFX11-LABEL: v_fneg_negk_minnum_f16_no_ieee:1356; GFX11:       ; %bb.0:1357; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1358; GFX11-NEXT:    v_max_f16_e64 v0, -v0, 4.01359; GFX11-NEXT:    s_setpc_b64 s[30:31]1360; GFX11-SAFE-TRUE16-LABEL: v_fneg_negk_minnum_f16_no_ieee:1361; GFX11-SAFE-TRUE16:       ; %bb.0:1362; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1363; GFX11-SAFE-TRUE16-NEXT:    v_max_f16_e64 v0.l, -v0.l, 4.01364; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]1365; GFX11-NSZ-TRUE16-LABEL: v_fneg_negk_minnum_f16_no_ieee:1366; GFX11-NSZ-TRUE16:       ; %bb.0:1367; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1368; GFX11-NSZ-TRUE16-NEXT:    v_max_f16_e64 v0.l, -v0.l, 4.01369; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]1370  %min = call half @llvm.minnum.f16(half -4.0, half %a)1371  %fneg = fneg half %min1372  ret half %fneg1373}1374 1375define half @v_fneg_0_minnum_f16(half %a) #0 {1376; SI-LABEL: v_fneg_0_minnum_f16:1377; SI:       ; %bb.0:1378; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1379; SI-NEXT:    v_cvt_f16_f32_e32 v0, v01380; SI-NEXT:    v_cvt_f32_f16_e32 v0, v01381; SI-NEXT:    v_min_f32_e32 v0, 0, v01382; SI-NEXT:    v_xor_b32_e32 v0, 0x80000000, v01383; SI-NEXT:    s_setpc_b64 s[30:31]1384;1385; VI-LABEL: v_fneg_0_minnum_f16:1386; VI:       ; %bb.0:1387; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1388; VI-NEXT:    v_min_f16_e32 v0, 0, v01389; VI-NEXT:    v_xor_b32_e32 v0, 0x8000, v01390; VI-NEXT:    s_setpc_b64 s[30:31]1391;1392; GFX11-LABEL: v_fneg_0_minnum_f16:1393; GFX11:       ; %bb.0:1394; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1395; GFX11-NEXT:    v_min_f16_e32 v0, 0, v01396; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)1397; GFX11-NEXT:    v_xor_b32_e32 v0, 0x8000, v01398; GFX11-NEXT:    s_setpc_b64 s[30:31]1399; GFX11-SAFE-TRUE16-LABEL: v_fneg_0_minnum_f16:1400; GFX11-SAFE-TRUE16:       ; %bb.0:1401; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1402; GFX11-SAFE-TRUE16-NEXT:    v_min_f16_e32 v0.l, 0, v0.l1403; GFX11-SAFE-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)1404; GFX11-SAFE-TRUE16-NEXT:    v_xor_b16 v0.l, 0x8000, v0.l1405; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]1406; GFX11-NSZ-TRUE16-LABEL: v_fneg_0_minnum_f16:1407; GFX11-NSZ-TRUE16:       ; %bb.0:1408; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1409; GFX11-NSZ-TRUE16-NEXT:    v_min_f16_e32 v0.l, 0, v0.l1410; GFX11-NSZ-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)1411; GFX11-NSZ-TRUE16-NEXT:    v_xor_b16 v0.l, 0x8000, v0.l1412; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]1413  %min = call nnan half @llvm.minnum.f16(half 0.0, half %a)1414  %fneg = fneg half %min1415  ret half %fneg1416}1417 1418define half @v_fneg_neg0_minnum_f16_ieee(half %a) #0 {1419; SI-LABEL: v_fneg_neg0_minnum_f16_ieee:1420; SI:       ; %bb.0:1421; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1422; SI-NEXT:    v_cvt_f16_f32_e64 v0, -v01423; SI-NEXT:    v_cvt_f32_f16_e32 v0, v01424; SI-NEXT:    v_max_f32_e32 v0, 0, v01425; SI-NEXT:    s_setpc_b64 s[30:31]1426;1427; VI-LABEL: v_fneg_neg0_minnum_f16_ieee:1428; VI:       ; %bb.0:1429; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1430; VI-NEXT:    v_max_f16_e64 v0, -v0, -v01431; VI-NEXT:    v_max_f16_e32 v0, 0, v01432; VI-NEXT:    s_setpc_b64 s[30:31]1433;1434; GFX11-LABEL: v_fneg_neg0_minnum_f16_ieee:1435; GFX11:       ; %bb.0:1436; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1437; GFX11-NEXT:    v_max_f16_e64 v0, -v0, -v01438; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)1439; GFX11-NEXT:    v_max_f16_e32 v0, 0, v01440; GFX11-NEXT:    s_setpc_b64 s[30:31]1441; GFX11-SAFE-TRUE16-LABEL: v_fneg_neg0_minnum_f16_ieee:1442; GFX11-SAFE-TRUE16:       ; %bb.0:1443; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1444; GFX11-SAFE-TRUE16-NEXT:    v_max_f16_e64 v0.l, -v0.l, -v0.l1445; GFX11-SAFE-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)1446; GFX11-SAFE-TRUE16-NEXT:    v_max_f16_e32 v0.l, 0, v0.l1447; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]1448; GFX11-NSZ-TRUE16-LABEL: v_fneg_neg0_minnum_f16_ieee:1449; GFX11-NSZ-TRUE16:       ; %bb.0:1450; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1451; GFX11-NSZ-TRUE16-NEXT:    v_max_f16_e64 v0.l, -v0.l, -v0.l1452; GFX11-NSZ-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)1453; GFX11-NSZ-TRUE16-NEXT:    v_max_f16_e32 v0.l, 0, v0.l1454; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]1455  %min = call half @llvm.minnum.f16(half -0.0, half %a)1456  %fneg = fneg half %min1457  ret half %fneg1458}1459 1460define half @v_fneg_inv2pi_minnum_f16(half %a) #0 {1461; SI-LABEL: v_fneg_inv2pi_minnum_f16:1462; SI:       ; %bb.0:1463; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1464; SI-NEXT:    v_cvt_f16_f32_e64 v0, -v01465; SI-NEXT:    v_cvt_f32_f16_e32 v0, v01466; SI-NEXT:    v_max_f32_e32 v0, 0xbe230000, v01467; SI-NEXT:    s_setpc_b64 s[30:31]1468;1469; VI-LABEL: v_fneg_inv2pi_minnum_f16:1470; VI:       ; %bb.0:1471; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1472; VI-NEXT:    v_max_f16_e32 v0, v0, v01473; VI-NEXT:    v_min_f16_e32 v0, 0.15915494, v01474; VI-NEXT:    v_xor_b32_e32 v0, 0x8000, v01475; VI-NEXT:    s_setpc_b64 s[30:31]1476;1477; GFX11-LABEL: v_fneg_inv2pi_minnum_f16:1478; GFX11:       ; %bb.0:1479; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1480; GFX11-NEXT:    v_max_f16_e32 v0, v0, v01481; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1482; GFX11-NEXT:    v_min_f16_e32 v0, 0.15915494, v01483; GFX11-NEXT:    v_xor_b32_e32 v0, 0x8000, v01484; GFX11-NEXT:    s_setpc_b64 s[30:31]1485; GFX11-SAFE-TRUE16-LABEL: v_fneg_inv2pi_minnum_f16:1486; GFX11-SAFE-TRUE16:       ; %bb.0:1487; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1488; GFX11-SAFE-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v0.l1489; GFX11-SAFE-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1490; GFX11-SAFE-TRUE16-NEXT:    v_min_f16_e32 v0.l, 0.15915494, v0.l1491; GFX11-SAFE-TRUE16-NEXT:    v_xor_b16 v0.l, 0x8000, v0.l1492; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]1493; GFX11-NSZ-TRUE16-LABEL: v_fneg_inv2pi_minnum_f16:1494; GFX11-NSZ-TRUE16:       ; %bb.0:1495; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1496; GFX11-NSZ-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v0.l1497; GFX11-NSZ-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1498; GFX11-NSZ-TRUE16-NEXT:    v_min_f16_e32 v0.l, 0.15915494, v0.l1499; GFX11-NSZ-TRUE16-NEXT:    v_xor_b16 v0.l, 0x8000, v0.l1500; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]1501  %min = call half @llvm.minnum.f16(half 0xH3118, half %a)1502  %fneg = fneg half %min1503  ret half %fneg1504}1505 1506define half @v_fneg_neg_inv2pi_minnum_f16(half %a) #0 {1507; SI-LABEL: v_fneg_neg_inv2pi_minnum_f16:1508; SI:       ; %bb.0:1509; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1510; SI-NEXT:    v_cvt_f16_f32_e64 v0, -v01511; SI-NEXT:    v_cvt_f32_f16_e32 v0, v01512; SI-NEXT:    v_max_f32_e32 v0, 0xbe230000, v01513; SI-NEXT:    s_setpc_b64 s[30:31]1514;1515; VI-LABEL: v_fneg_neg_inv2pi_minnum_f16:1516; VI:       ; %bb.0:1517; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1518; VI-NEXT:    v_max_f16_e32 v0, v0, v01519; VI-NEXT:    v_min_f16_e32 v0, 0.15915494, v01520; VI-NEXT:    v_xor_b32_e32 v0, 0x8000, v01521; VI-NEXT:    s_setpc_b64 s[30:31]1522;1523; GFX11-LABEL: v_fneg_neg_inv2pi_minnum_f16:1524; GFX11:       ; %bb.0:1525; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1526; GFX11-NEXT:    v_max_f16_e32 v0, v0, v01527; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1528; GFX11-NEXT:    v_min_f16_e32 v0, 0.15915494, v01529; GFX11-NEXT:    v_xor_b32_e32 v0, 0x8000, v01530; GFX11-NEXT:    s_setpc_b64 s[30:31]1531; GFX11-SAFE-TRUE16-LABEL: v_fneg_neg_inv2pi_minnum_f16:1532; GFX11-SAFE-TRUE16:       ; %bb.0:1533; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1534; GFX11-SAFE-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v0.l1535; GFX11-SAFE-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1536; GFX11-SAFE-TRUE16-NEXT:    v_min_f16_e32 v0.l, 0.15915494, v0.l1537; GFX11-SAFE-TRUE16-NEXT:    v_xor_b16 v0.l, 0x8000, v0.l1538; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]1539; GFX11-NSZ-TRUE16-LABEL: v_fneg_neg_inv2pi_minnum_f16:1540; GFX11-NSZ-TRUE16:       ; %bb.0:1541; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1542; GFX11-NSZ-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v0.l1543; GFX11-NSZ-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1544; GFX11-NSZ-TRUE16-NEXT:    v_min_f16_e32 v0.l, 0.15915494, v0.l1545; GFX11-NSZ-TRUE16-NEXT:    v_xor_b16 v0.l, 0x8000, v0.l1546; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]1547  %min = call half @llvm.minnum.f16(half 0xH3118, half %a)1548  %fneg = fneg half %min1549  ret half %fneg1550}1551 1552define half @v_fneg_neg0_minnum_f16_no_ieee(half %a) #4 {1553; SI-LABEL: v_fneg_neg0_minnum_f16_no_ieee:1554; SI:       ; %bb.0:1555; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1556; SI-NEXT:    v_cvt_f16_f32_e64 v0, -v01557; SI-NEXT:    v_cvt_f32_f16_e32 v0, v01558; SI-NEXT:    v_max_f32_e32 v0, 0, v01559; SI-NEXT:    s_setpc_b64 s[30:31]1560;1561; VI-LABEL: v_fneg_neg0_minnum_f16_no_ieee:1562; VI:       ; %bb.0:1563; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1564; VI-NEXT:    v_max_f16_e64 v0, -v0, 01565; VI-NEXT:    s_setpc_b64 s[30:31]1566;1567; GFX11-LABEL: v_fneg_neg0_minnum_f16_no_ieee:1568; GFX11:       ; %bb.0:1569; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1570; GFX11-NEXT:    v_max_f16_e64 v0, -v0, 01571; GFX11-NEXT:    s_setpc_b64 s[30:31]1572; GFX11-SAFE-TRUE16-LABEL: v_fneg_neg0_minnum_f16_no_ieee:1573; GFX11-SAFE-TRUE16:       ; %bb.0:1574; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1575; GFX11-SAFE-TRUE16-NEXT:    v_max_f16_e64 v0.l, -v0.l, 01576; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]1577; GFX11-NSZ-TRUE16-LABEL: v_fneg_neg0_minnum_f16_no_ieee:1578; GFX11-NSZ-TRUE16:       ; %bb.0:1579; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1580; GFX11-NSZ-TRUE16-NEXT:    v_max_f16_e64 v0.l, -v0.l, 01581; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]1582  %min = call half @llvm.minnum.f16(half -0.0, half %a)1583  %fneg = fneg half %min1584  ret half %fneg1585}1586 1587define half @v_fneg_0_minnum_foldable_use_f16_ieee(half %a, half %b) #0 {1588; SI-LABEL: v_fneg_0_minnum_foldable_use_f16_ieee:1589; SI:       ; %bb.0:1590; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1591; SI-NEXT:    v_cvt_f16_f32_e32 v0, v01592; SI-NEXT:    v_cvt_f16_f32_e32 v1, v11593; SI-NEXT:    v_cvt_f32_f16_e32 v0, v01594; SI-NEXT:    v_cvt_f32_f16_e32 v1, v11595; SI-NEXT:    v_min_f32_e32 v0, 0, v01596; SI-NEXT:    v_mul_f32_e64 v0, -v0, v11597; SI-NEXT:    s_setpc_b64 s[30:31]1598;1599; VI-LABEL: v_fneg_0_minnum_foldable_use_f16_ieee:1600; VI:       ; %bb.0:1601; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1602; VI-NEXT:    v_max_f16_e32 v0, v0, v01603; VI-NEXT:    v_min_f16_e32 v0, 0, v01604; VI-NEXT:    v_mul_f16_e64 v0, -v0, v11605; VI-NEXT:    s_setpc_b64 s[30:31]1606;1607; GFX11-LABEL: v_fneg_0_minnum_foldable_use_f16_ieee:1608; GFX11:       ; %bb.0:1609; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1610; GFX11-NEXT:    v_max_f16_e32 v0, v0, v01611; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1612; GFX11-NEXT:    v_min_f16_e32 v0, 0, v01613; GFX11-NEXT:    v_mul_f16_e64 v0, -v0, v11614; GFX11-NEXT:    s_setpc_b64 s[30:31]1615; GFX11-SAFE-TRUE16-LABEL: v_fneg_0_minnum_foldable_use_f16_ieee:1616; GFX11-SAFE-TRUE16:       ; %bb.0:1617; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1618; GFX11-SAFE-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v0.l1619; GFX11-SAFE-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1620; GFX11-SAFE-TRUE16-NEXT:    v_min_f16_e32 v0.l, 0, v0.l1621; GFX11-SAFE-TRUE16-NEXT:    v_mul_f16_e64 v0.l, -v0.l, v1.l1622; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]1623; GFX11-NSZ-TRUE16-LABEL: v_fneg_0_minnum_foldable_use_f16_ieee:1624; GFX11-NSZ-TRUE16:       ; %bb.0:1625; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1626; GFX11-NSZ-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v0.l1627; GFX11-NSZ-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1628; GFX11-NSZ-TRUE16-NEXT:    v_min_f16_e32 v0.l, 0, v0.l1629; GFX11-NSZ-TRUE16-NEXT:    v_mul_f16_e64 v0.l, -v0.l, v1.l1630; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]1631  %min = call half @llvm.minnum.f16(half 0.0, half %a)1632  %fneg = fneg half %min1633  %mul = fmul half %fneg, %b1634  ret half %mul1635}1636 1637define half @v_fneg_inv2pi_minnum_foldable_use_f16(half %a, half %b) #0 {1638; SI-LABEL: v_fneg_inv2pi_minnum_foldable_use_f16:1639; SI:       ; %bb.0:1640; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1641; SI-NEXT:    v_cvt_f16_f32_e64 v0, -v01642; SI-NEXT:    v_cvt_f16_f32_e32 v1, v11643; SI-NEXT:    v_cvt_f32_f16_e32 v0, v01644; SI-NEXT:    v_cvt_f32_f16_e32 v1, v11645; SI-NEXT:    v_max_f32_e32 v0, 0xbe230000, v01646; SI-NEXT:    v_mul_f32_e32 v0, v0, v11647; SI-NEXT:    s_setpc_b64 s[30:31]1648;1649; VI-LABEL: v_fneg_inv2pi_minnum_foldable_use_f16:1650; VI:       ; %bb.0:1651; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1652; VI-NEXT:    v_max_f16_e32 v0, v0, v01653; VI-NEXT:    v_min_f16_e32 v0, 0.15915494, v01654; VI-NEXT:    v_mul_f16_e64 v0, -v0, v11655; VI-NEXT:    s_setpc_b64 s[30:31]1656;1657; GFX11-LABEL: v_fneg_inv2pi_minnum_foldable_use_f16:1658; GFX11:       ; %bb.0:1659; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1660; GFX11-NEXT:    v_max_f16_e32 v0, v0, v01661; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1662; GFX11-NEXT:    v_min_f16_e32 v0, 0.15915494, v01663; GFX11-NEXT:    v_mul_f16_e64 v0, -v0, v11664; GFX11-NEXT:    s_setpc_b64 s[30:31]1665; GFX11-SAFE-TRUE16-LABEL: v_fneg_inv2pi_minnum_foldable_use_f16:1666; GFX11-SAFE-TRUE16:       ; %bb.0:1667; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1668; GFX11-SAFE-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v0.l1669; GFX11-SAFE-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1670; GFX11-SAFE-TRUE16-NEXT:    v_min_f16_e32 v0.l, 0.15915494, v0.l1671; GFX11-SAFE-TRUE16-NEXT:    v_mul_f16_e64 v0.l, -v0.l, v1.l1672; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]1673; GFX11-NSZ-TRUE16-LABEL: v_fneg_inv2pi_minnum_foldable_use_f16:1674; GFX11-NSZ-TRUE16:       ; %bb.0:1675; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1676; GFX11-NSZ-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v0.l1677; GFX11-NSZ-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1678; GFX11-NSZ-TRUE16-NEXT:    v_min_f16_e32 v0.l, 0.15915494, v0.l1679; GFX11-NSZ-TRUE16-NEXT:    v_mul_f16_e64 v0.l, -v0.l, v1.l1680; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]1681  %min = call half @llvm.minnum.f16(half 0xH3118, half %a)1682  %fneg = fneg half %min1683  %mul = fmul half %fneg, %b1684  ret half %mul1685}1686 1687define half @v_fneg_0_minnum_foldable_use_f16_no_ieee(half %a, half %b) #4 {1688; SI-LABEL: v_fneg_0_minnum_foldable_use_f16_no_ieee:1689; SI:       ; %bb.0:1690; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1691; SI-NEXT:    v_cvt_f16_f32_e32 v0, v01692; SI-NEXT:    v_cvt_f16_f32_e32 v1, v11693; SI-NEXT:    v_cvt_f32_f16_e32 v0, v01694; SI-NEXT:    v_cvt_f32_f16_e32 v1, v11695; SI-NEXT:    v_min_f32_e32 v0, 0, v01696; SI-NEXT:    v_mul_f32_e64 v0, -v0, v11697; SI-NEXT:    s_setpc_b64 s[30:31]1698;1699; VI-LABEL: v_fneg_0_minnum_foldable_use_f16_no_ieee:1700; VI:       ; %bb.0:1701; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1702; VI-NEXT:    v_min_f16_e32 v0, 0, v01703; VI-NEXT:    v_mul_f16_e64 v0, -v0, v11704; VI-NEXT:    s_setpc_b64 s[30:31]1705;1706; GFX11-LABEL: v_fneg_0_minnum_foldable_use_f16_no_ieee:1707; GFX11:       ; %bb.0:1708; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1709; GFX11-NEXT:    v_min_f16_e32 v0, 0, v01710; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)1711; GFX11-NEXT:    v_mul_f16_e64 v0, -v0, v11712; GFX11-NEXT:    s_setpc_b64 s[30:31]1713; GFX11-SAFE-TRUE16-LABEL: v_fneg_0_minnum_foldable_use_f16_no_ieee:1714; GFX11-SAFE-TRUE16:       ; %bb.0:1715; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1716; GFX11-SAFE-TRUE16-NEXT:    v_min_f16_e32 v0.l, 0, v0.l1717; GFX11-SAFE-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)1718; GFX11-SAFE-TRUE16-NEXT:    v_mul_f16_e64 v0.l, -v0.l, v1.l1719; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]1720; GFX11-NSZ-TRUE16-LABEL: v_fneg_0_minnum_foldable_use_f16_no_ieee:1721; GFX11-NSZ-TRUE16:       ; %bb.0:1722; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1723; GFX11-NSZ-TRUE16-NEXT:    v_min_f16_e32 v0.l, 0, v0.l1724; GFX11-NSZ-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)1725; GFX11-NSZ-TRUE16-NEXT:    v_mul_f16_e64 v0.l, -v0.l, v1.l1726; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]1727  %min = call half @llvm.minnum.f16(half 0.0, half %a)1728  %fneg = fneg half %min1729  %mul = fmul half %fneg, %b1730  ret half %mul1731}1732 1733define { half, half } @v_fneg_minnum_multi_use_minnum_f16_ieee(half %a, half %b) #0 {1734; SI-LABEL: v_fneg_minnum_multi_use_minnum_f16_ieee:1735; SI:       ; %bb.0:1736; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1737; SI-NEXT:    v_cvt_f16_f32_e32 v1, v11738; SI-NEXT:    v_cvt_f16_f32_e32 v0, v01739; SI-NEXT:    v_cvt_f32_f16_e64 v1, -v11740; SI-NEXT:    v_cvt_f32_f16_e64 v0, -v01741; SI-NEXT:    v_max_f32_e32 v0, v0, v11742; SI-NEXT:    v_mul_f32_e32 v1, -4.0, v01743; SI-NEXT:    s_setpc_b64 s[30:31]1744;1745; VI-LABEL: v_fneg_minnum_multi_use_minnum_f16_ieee:1746; VI:       ; %bb.0:1747; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1748; VI-NEXT:    v_max_f16_e64 v1, -v1, -v11749; VI-NEXT:    v_max_f16_e64 v0, -v0, -v01750; VI-NEXT:    v_max_f16_e32 v0, v0, v11751; VI-NEXT:    v_mul_f16_e32 v1, -4.0, v01752; VI-NEXT:    s_setpc_b64 s[30:31]1753;1754; GFX11-LABEL: v_fneg_minnum_multi_use_minnum_f16_ieee:1755; GFX11:       ; %bb.0:1756; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1757; GFX11-NEXT:    v_max_f16_e64 v1, -v1, -v11758; GFX11-NEXT:    v_max_f16_e64 v0, -v0, -v01759; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1760; GFX11-NEXT:    v_max_f16_e32 v0, v0, v11761; GFX11-NEXT:    v_mul_f16_e32 v1, -4.0, v01762; GFX11-NEXT:    s_setpc_b64 s[30:31]1763; GFX11-SAFE-TRUE16-LABEL: v_fneg_minnum_multi_use_minnum_f16_ieee:1764; GFX11-SAFE-TRUE16:       ; %bb.0:1765; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1766; GFX11-SAFE-TRUE16-NEXT:    v_max_f16_e64 v0.h, -v1.l, -v1.l1767; GFX11-SAFE-TRUE16-NEXT:    v_max_f16_e64 v0.l, -v0.l, -v0.l1768; GFX11-SAFE-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1769; GFX11-SAFE-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v0.h1770; GFX11-SAFE-TRUE16-NEXT:    v_mul_f16_e32 v1.l, -4.0, v0.l1771; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]1772; GFX11-NSZ-TRUE16-LABEL: v_fneg_minnum_multi_use_minnum_f16_ieee:1773; GFX11-NSZ-TRUE16:       ; %bb.0:1774; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1775; GFX11-NSZ-TRUE16-NEXT:    v_max_f16_e64 v0.h, -v1.l, -v1.l1776; GFX11-NSZ-TRUE16-NEXT:    v_max_f16_e64 v0.l, -v0.l, -v0.l1777; GFX11-NSZ-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1778; GFX11-NSZ-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v0.h1779; GFX11-NSZ-TRUE16-NEXT:    v_mul_f16_e32 v1.l, -4.0, v0.l1780; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]1781  %min = call half @llvm.minnum.f16(half %a, half %b)1782  %fneg = fneg half %min1783  %use1 = fmul half %min, 4.01784  %insert.0 = insertvalue { half, half } poison, half %fneg, 01785  %insert.1 = insertvalue { half, half } %insert.0, half %use1, 11786  ret { half, half } %insert.11787}1788 1789define <2 x half> @v_fneg_minnum_multi_use_minnum_f16_no_ieee(half %a, half %b) #4 {1790; SI-LABEL: v_fneg_minnum_multi_use_minnum_f16_no_ieee:1791; SI:       ; %bb.0:1792; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1793; SI-NEXT:    v_cvt_f16_f32_e32 v1, v11794; SI-NEXT:    v_cvt_f16_f32_e32 v0, v01795; SI-NEXT:    v_cvt_f32_f16_e64 v1, -v11796; SI-NEXT:    v_cvt_f32_f16_e64 v0, -v01797; SI-NEXT:    v_max_f32_e32 v0, v0, v11798; SI-NEXT:    v_mul_f32_e32 v1, -4.0, v01799; SI-NEXT:    s_setpc_b64 s[30:31]1800;1801; VI-LABEL: v_fneg_minnum_multi_use_minnum_f16_no_ieee:1802; VI:       ; %bb.0:1803; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1804; VI-NEXT:    v_max_f16_e64 v0, -v0, -v11805; VI-NEXT:    v_mov_b32_e32 v1, 0xc4001806; VI-NEXT:    v_mul_f16_sdwa v1, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD1807; VI-NEXT:    v_or_b32_e32 v0, v0, v11808; VI-NEXT:    s_setpc_b64 s[30:31]1809;1810; GFX11-LABEL: v_fneg_minnum_multi_use_minnum_f16_no_ieee:1811; GFX11:       ; %bb.0:1812; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1813; GFX11-NEXT:    v_min_f16_e32 v0, v0, v11814; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1815; GFX11-NEXT:    v_mul_f16_e32 v1, 4.0, v01816; GFX11-NEXT:    v_pack_b32_f16 v0, -v0, v11817; GFX11-NEXT:    s_setpc_b64 s[30:31]1818; GFX11-SAFE-TRUE16-LABEL: v_fneg_minnum_multi_use_minnum_f16_no_ieee:1819; GFX11-SAFE-TRUE16:       ; %bb.0:1820; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1821; GFX11-SAFE-TRUE16-NEXT:    v_min_f16_e32 v0.l, v0.l, v1.l1822; GFX11-SAFE-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1823; GFX11-SAFE-TRUE16-NEXT:    v_mul_f16_e32 v0.h, 4.0, v0.l1824; GFX11-SAFE-TRUE16-NEXT:    v_pack_b32_f16 v0, -v0.l, v0.h1825; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]1826; GFX11-NSZ-TRUE16-LABEL: v_fneg_minnum_multi_use_minnum_f16_no_ieee:1827; GFX11-NSZ-TRUE16:       ; %bb.0:1828; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1829; GFX11-NSZ-TRUE16-NEXT:    v_min_f16_e32 v0.l, v0.l, v1.l1830; GFX11-NSZ-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1831; GFX11-NSZ-TRUE16-NEXT:    v_mul_f16_e32 v0.h, 4.0, v0.l1832; GFX11-NSZ-TRUE16-NEXT:    v_pack_b32_f16 v0, -v0.l, v0.h1833; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]1834  %min = call half @llvm.minnum.f16(half %a, half %b)1835  %fneg = fneg half %min1836  %use1 = fmul half %min, 4.01837  %ins0 = insertelement <2 x half> poison, half %fneg, i32 01838  %ins1 = insertelement <2 x half> %ins0, half %use1, i32 11839  ret <2 x half> %ins11840}1841 1842; --------------------------------------------------------------------------------1843; fmaxnum tests1844; --------------------------------------------------------------------------------1845 1846define half @v_fneg_maxnum_f16_ieee(half %a, half %b) #0 {1847; SI-LABEL: v_fneg_maxnum_f16_ieee:1848; SI:       ; %bb.0:1849; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1850; SI-NEXT:    v_cvt_f16_f32_e64 v1, -v11851; SI-NEXT:    v_cvt_f16_f32_e64 v0, -v01852; SI-NEXT:    v_cvt_f32_f16_e32 v1, v11853; SI-NEXT:    v_cvt_f32_f16_e32 v0, v01854; SI-NEXT:    v_min_f32_e32 v0, v0, v11855; SI-NEXT:    s_setpc_b64 s[30:31]1856;1857; VI-LABEL: v_fneg_maxnum_f16_ieee:1858; VI:       ; %bb.0:1859; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1860; VI-NEXT:    v_max_f16_e64 v1, -v1, -v11861; VI-NEXT:    v_max_f16_e64 v0, -v0, -v01862; VI-NEXT:    v_min_f16_e32 v0, v0, v11863; VI-NEXT:    s_setpc_b64 s[30:31]1864;1865; GFX11-LABEL: v_fneg_maxnum_f16_ieee:1866; GFX11:       ; %bb.0:1867; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1868; GFX11-NEXT:    v_max_f16_e64 v1, -v1, -v11869; GFX11-NEXT:    v_max_f16_e64 v0, -v0, -v01870; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)1871; GFX11-NEXT:    v_min_f16_e32 v0, v0, v11872; GFX11-NEXT:    s_setpc_b64 s[30:31]1873; GFX11-SAFE-TRUE16-LABEL: v_fneg_maxnum_f16_ieee:1874; GFX11-SAFE-TRUE16:       ; %bb.0:1875; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1876; GFX11-SAFE-TRUE16-NEXT:    v_max_f16_e64 v0.h, -v1.l, -v1.l1877; GFX11-SAFE-TRUE16-NEXT:    v_max_f16_e64 v0.l, -v0.l, -v0.l1878; GFX11-SAFE-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)1879; GFX11-SAFE-TRUE16-NEXT:    v_min_f16_e32 v0.l, v0.l, v0.h1880; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]1881; GFX11-NSZ-TRUE16-LABEL: v_fneg_maxnum_f16_ieee:1882; GFX11-NSZ-TRUE16:       ; %bb.0:1883; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1884; GFX11-NSZ-TRUE16-NEXT:    v_max_f16_e64 v0.h, -v1.l, -v1.l1885; GFX11-NSZ-TRUE16-NEXT:    v_max_f16_e64 v0.l, -v0.l, -v0.l1886; GFX11-NSZ-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)1887; GFX11-NSZ-TRUE16-NEXT:    v_min_f16_e32 v0.l, v0.l, v0.h1888; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]1889  %max = call half @llvm.maxnum.f16(half %a, half %b)1890  %fneg = fneg half %max1891  ret half %fneg1892}1893 1894define half @v_fneg_maxnum_f16_no_ieee(half %a, half %b) #4 {1895; SI-LABEL: v_fneg_maxnum_f16_no_ieee:1896; SI:       ; %bb.0:1897; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1898; SI-NEXT:    v_cvt_f16_f32_e64 v1, -v11899; SI-NEXT:    v_cvt_f16_f32_e64 v0, -v01900; SI-NEXT:    v_cvt_f32_f16_e32 v1, v11901; SI-NEXT:    v_cvt_f32_f16_e32 v0, v01902; SI-NEXT:    v_min_f32_e32 v0, v0, v11903; SI-NEXT:    s_setpc_b64 s[30:31]1904;1905; VI-LABEL: v_fneg_maxnum_f16_no_ieee:1906; VI:       ; %bb.0:1907; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1908; VI-NEXT:    v_min_f16_e64 v0, -v0, -v11909; VI-NEXT:    s_setpc_b64 s[30:31]1910;1911; GFX11-LABEL: v_fneg_maxnum_f16_no_ieee:1912; GFX11:       ; %bb.0:1913; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1914; GFX11-NEXT:    v_min_f16_e64 v0, -v0, -v11915; GFX11-NEXT:    s_setpc_b64 s[30:31]1916; GFX11-SAFE-TRUE16-LABEL: v_fneg_maxnum_f16_no_ieee:1917; GFX11-SAFE-TRUE16:       ; %bb.0:1918; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1919; GFX11-SAFE-TRUE16-NEXT:    v_min_f16_e64 v0.l, -v0.l, -v1.l1920; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]1921; GFX11-NSZ-TRUE16-LABEL: v_fneg_maxnum_f16_no_ieee:1922; GFX11-NSZ-TRUE16:       ; %bb.0:1923; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1924; GFX11-NSZ-TRUE16-NEXT:    v_min_f16_e64 v0.l, -v0.l, -v1.l1925; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]1926  %max = call half @llvm.maxnum.f16(half %a, half %b)1927  %fneg = fneg half %max1928  ret half %fneg1929}1930 1931define half @v_fneg_self_maxnum_f16_ieee(half %a) #0 {1932; SI-LABEL: v_fneg_self_maxnum_f16_ieee:1933; SI:       ; %bb.0:1934; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1935; SI-NEXT:    v_xor_b32_e32 v0, 0x80000000, v01936; SI-NEXT:    s_setpc_b64 s[30:31]1937;1938; VI-LABEL: v_fneg_self_maxnum_f16_ieee:1939; VI:       ; %bb.0:1940; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1941; VI-NEXT:    v_xor_b32_e32 v0, 0x8000, v01942; VI-NEXT:    s_setpc_b64 s[30:31]1943;1944; GFX11-LABEL: v_fneg_self_maxnum_f16_ieee:1945; GFX11:       ; %bb.0:1946; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1947; GFX11-NEXT:    v_xor_b32_e32 v0, 0x8000, v01948; GFX11-NEXT:    s_setpc_b64 s[30:31]1949; GFX11-SAFE-TRUE16-LABEL: v_fneg_self_maxnum_f16_ieee:1950; GFX11-SAFE-TRUE16:       ; %bb.0:1951; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1952; GFX11-SAFE-TRUE16-NEXT:    v_xor_b16 v0.l, 0x8000, v0.l1953; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]1954; GFX11-NSZ-TRUE16-LABEL: v_fneg_self_maxnum_f16_ieee:1955; GFX11-NSZ-TRUE16:       ; %bb.0:1956; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1957; GFX11-NSZ-TRUE16-NEXT:    v_xor_b16 v0.l, 0x8000, v0.l1958; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]1959  %max = call half @llvm.maxnum.f16(half %a, half %a)1960  %max.fneg = fneg half %max1961  ret half %max.fneg1962}1963 1964define half @v_fneg_self_maxnum_f16_no_ieee(half %a) #4 {1965; SI-LABEL: v_fneg_self_maxnum_f16_no_ieee:1966; SI:       ; %bb.0:1967; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1968; SI-NEXT:    v_xor_b32_e32 v0, 0x80000000, v01969; SI-NEXT:    s_setpc_b64 s[30:31]1970;1971; VI-LABEL: v_fneg_self_maxnum_f16_no_ieee:1972; VI:       ; %bb.0:1973; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1974; VI-NEXT:    v_xor_b32_e32 v0, 0x8000, v01975; VI-NEXT:    s_setpc_b64 s[30:31]1976;1977; GFX11-LABEL: v_fneg_self_maxnum_f16_no_ieee:1978; GFX11:       ; %bb.0:1979; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1980; GFX11-NEXT:    v_xor_b32_e32 v0, 0x8000, v01981; GFX11-NEXT:    s_setpc_b64 s[30:31]1982; GFX11-SAFE-TRUE16-LABEL: v_fneg_self_maxnum_f16_no_ieee:1983; GFX11-SAFE-TRUE16:       ; %bb.0:1984; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1985; GFX11-SAFE-TRUE16-NEXT:    v_xor_b16 v0.l, 0x8000, v0.l1986; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]1987; GFX11-NSZ-TRUE16-LABEL: v_fneg_self_maxnum_f16_no_ieee:1988; GFX11-NSZ-TRUE16:       ; %bb.0:1989; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1990; GFX11-NSZ-TRUE16-NEXT:    v_xor_b16 v0.l, 0x8000, v0.l1991; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]1992  %max = call half @llvm.maxnum.f16(half %a, half %a)1993  %max.fneg = fneg half %max1994  ret half %max.fneg1995}1996 1997define half @v_fneg_posk_maxnum_f16_ieee(half %a) #0 {1998; SI-LABEL: v_fneg_posk_maxnum_f16_ieee:1999; SI:       ; %bb.0:2000; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2001; SI-NEXT:    v_cvt_f16_f32_e64 v0, -v02002; SI-NEXT:    v_cvt_f32_f16_e32 v0, v02003; SI-NEXT:    v_min_f32_e32 v0, -4.0, v02004; SI-NEXT:    s_setpc_b64 s[30:31]2005;2006; VI-LABEL: v_fneg_posk_maxnum_f16_ieee:2007; VI:       ; %bb.0:2008; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2009; VI-NEXT:    v_max_f16_e64 v0, -v0, -v02010; VI-NEXT:    v_min_f16_e32 v0, -4.0, v02011; VI-NEXT:    s_setpc_b64 s[30:31]2012;2013; GFX11-LABEL: v_fneg_posk_maxnum_f16_ieee:2014; GFX11:       ; %bb.0:2015; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2016; GFX11-NEXT:    v_max_f16_e64 v0, -v0, -v02017; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)2018; GFX11-NEXT:    v_min_f16_e32 v0, -4.0, v02019; GFX11-NEXT:    s_setpc_b64 s[30:31]2020; GFX11-SAFE-TRUE16-LABEL: v_fneg_posk_maxnum_f16_ieee:2021; GFX11-SAFE-TRUE16:       ; %bb.0:2022; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2023; GFX11-SAFE-TRUE16-NEXT:    v_max_f16_e64 v0.l, -v0.l, -v0.l2024; GFX11-SAFE-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)2025; GFX11-SAFE-TRUE16-NEXT:    v_min_f16_e32 v0.l, -4.0, v0.l2026; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]2027; GFX11-NSZ-TRUE16-LABEL: v_fneg_posk_maxnum_f16_ieee:2028; GFX11-NSZ-TRUE16:       ; %bb.0:2029; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2030; GFX11-NSZ-TRUE16-NEXT:    v_max_f16_e64 v0.l, -v0.l, -v0.l2031; GFX11-NSZ-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)2032; GFX11-NSZ-TRUE16-NEXT:    v_min_f16_e32 v0.l, -4.0, v0.l2033; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]2034  %max = call half @llvm.maxnum.f16(half 4.0, half %a)2035  %fneg = fneg half %max2036  ret half %fneg2037}2038 2039define half @v_fneg_posk_maxnum_f16_no_ieee(half %a) #4 {2040; SI-LABEL: v_fneg_posk_maxnum_f16_no_ieee:2041; SI:       ; %bb.0:2042; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2043; SI-NEXT:    v_cvt_f16_f32_e64 v0, -v02044; SI-NEXT:    v_cvt_f32_f16_e32 v0, v02045; SI-NEXT:    v_min_f32_e32 v0, -4.0, v02046; SI-NEXT:    s_setpc_b64 s[30:31]2047;2048; VI-LABEL: v_fneg_posk_maxnum_f16_no_ieee:2049; VI:       ; %bb.0:2050; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2051; VI-NEXT:    v_min_f16_e64 v0, -v0, -4.02052; VI-NEXT:    s_setpc_b64 s[30:31]2053;2054; GFX11-LABEL: v_fneg_posk_maxnum_f16_no_ieee:2055; GFX11:       ; %bb.0:2056; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2057; GFX11-NEXT:    v_min_f16_e64 v0, -v0, -4.02058; GFX11-NEXT:    s_setpc_b64 s[30:31]2059; GFX11-SAFE-TRUE16-LABEL: v_fneg_posk_maxnum_f16_no_ieee:2060; GFX11-SAFE-TRUE16:       ; %bb.0:2061; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2062; GFX11-SAFE-TRUE16-NEXT:    v_min_f16_e64 v0.l, -v0.l, -4.02063; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]2064; GFX11-NSZ-TRUE16-LABEL: v_fneg_posk_maxnum_f16_no_ieee:2065; GFX11-NSZ-TRUE16:       ; %bb.0:2066; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2067; GFX11-NSZ-TRUE16-NEXT:    v_min_f16_e64 v0.l, -v0.l, -4.02068; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]2069  %max = call half @llvm.maxnum.f16(half 4.0, half %a)2070  %fneg = fneg half %max2071  ret half %fneg2072}2073 2074define half @v_fneg_negk_maxnum_f16_ieee(half %a) #0 {2075; SI-LABEL: v_fneg_negk_maxnum_f16_ieee:2076; SI:       ; %bb.0:2077; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2078; SI-NEXT:    v_cvt_f16_f32_e64 v0, -v02079; SI-NEXT:    v_cvt_f32_f16_e32 v0, v02080; SI-NEXT:    v_min_f32_e32 v0, 4.0, v02081; SI-NEXT:    s_setpc_b64 s[30:31]2082;2083; VI-LABEL: v_fneg_negk_maxnum_f16_ieee:2084; VI:       ; %bb.0:2085; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2086; VI-NEXT:    v_max_f16_e64 v0, -v0, -v02087; VI-NEXT:    v_min_f16_e32 v0, 4.0, v02088; VI-NEXT:    s_setpc_b64 s[30:31]2089;2090; GFX11-LABEL: v_fneg_negk_maxnum_f16_ieee:2091; GFX11:       ; %bb.0:2092; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2093; GFX11-NEXT:    v_max_f16_e64 v0, -v0, -v02094; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)2095; GFX11-NEXT:    v_min_f16_e32 v0, 4.0, v02096; GFX11-NEXT:    s_setpc_b64 s[30:31]2097; GFX11-SAFE-TRUE16-LABEL: v_fneg_negk_maxnum_f16_ieee:2098; GFX11-SAFE-TRUE16:       ; %bb.0:2099; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2100; GFX11-SAFE-TRUE16-NEXT:    v_max_f16_e64 v0.l, -v0.l, -v0.l2101; GFX11-SAFE-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)2102; GFX11-SAFE-TRUE16-NEXT:    v_min_f16_e32 v0.l, 4.0, v0.l2103; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]2104; GFX11-NSZ-TRUE16-LABEL: v_fneg_negk_maxnum_f16_ieee:2105; GFX11-NSZ-TRUE16:       ; %bb.0:2106; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2107; GFX11-NSZ-TRUE16-NEXT:    v_max_f16_e64 v0.l, -v0.l, -v0.l2108; GFX11-NSZ-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)2109; GFX11-NSZ-TRUE16-NEXT:    v_min_f16_e32 v0.l, 4.0, v0.l2110; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]2111  %max = call half @llvm.maxnum.f16(half -4.0, half %a)2112  %fneg = fneg half %max2113  ret half %fneg2114}2115 2116define half @v_fneg_negk_maxnum_f16_no_ieee(half %a) #4 {2117; SI-LABEL: v_fneg_negk_maxnum_f16_no_ieee:2118; SI:       ; %bb.0:2119; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2120; SI-NEXT:    v_cvt_f16_f32_e64 v0, -v02121; SI-NEXT:    v_cvt_f32_f16_e32 v0, v02122; SI-NEXT:    v_min_f32_e32 v0, 4.0, v02123; SI-NEXT:    s_setpc_b64 s[30:31]2124;2125; VI-LABEL: v_fneg_negk_maxnum_f16_no_ieee:2126; VI:       ; %bb.0:2127; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2128; VI-NEXT:    v_min_f16_e64 v0, -v0, 4.02129; VI-NEXT:    s_setpc_b64 s[30:31]2130;2131; GFX11-LABEL: v_fneg_negk_maxnum_f16_no_ieee:2132; GFX11:       ; %bb.0:2133; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2134; GFX11-NEXT:    v_min_f16_e64 v0, -v0, 4.02135; GFX11-NEXT:    s_setpc_b64 s[30:31]2136; GFX11-SAFE-TRUE16-LABEL: v_fneg_negk_maxnum_f16_no_ieee:2137; GFX11-SAFE-TRUE16:       ; %bb.0:2138; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2139; GFX11-SAFE-TRUE16-NEXT:    v_min_f16_e64 v0.l, -v0.l, 4.02140; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]2141; GFX11-NSZ-TRUE16-LABEL: v_fneg_negk_maxnum_f16_no_ieee:2142; GFX11-NSZ-TRUE16:       ; %bb.0:2143; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2144; GFX11-NSZ-TRUE16-NEXT:    v_min_f16_e64 v0.l, -v0.l, 4.02145; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]2146  %max = call half @llvm.maxnum.f16(half -4.0, half %a)2147  %fneg = fneg half %max2148  ret half %fneg2149}2150 2151define half @v_fneg_0_maxnum_f16(half %a) #0 {2152; SI-LABEL: v_fneg_0_maxnum_f16:2153; SI:       ; %bb.0:2154; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2155; SI-NEXT:    v_cvt_f16_f32_e32 v0, v02156; SI-NEXT:    v_cvt_f32_f16_e32 v0, v02157; SI-NEXT:    v_max_f32_e32 v0, 0, v02158; SI-NEXT:    v_xor_b32_e32 v0, 0x80000000, v02159; SI-NEXT:    s_setpc_b64 s[30:31]2160;2161; VI-LABEL: v_fneg_0_maxnum_f16:2162; VI:       ; %bb.0:2163; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2164; VI-NEXT:    v_max_f16_e32 v0, 0, v02165; VI-NEXT:    v_xor_b32_e32 v0, 0x8000, v02166; VI-NEXT:    s_setpc_b64 s[30:31]2167;2168; GFX11-LABEL: v_fneg_0_maxnum_f16:2169; GFX11:       ; %bb.0:2170; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2171; GFX11-NEXT:    v_max_f16_e32 v0, 0, v02172; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)2173; GFX11-NEXT:    v_xor_b32_e32 v0, 0x8000, v02174; GFX11-NEXT:    s_setpc_b64 s[30:31]2175; GFX11-SAFE-TRUE16-LABEL: v_fneg_0_maxnum_f16:2176; GFX11-SAFE-TRUE16:       ; %bb.0:2177; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2178; GFX11-SAFE-TRUE16-NEXT:    v_max_f16_e32 v0.l, 0, v0.l2179; GFX11-SAFE-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)2180; GFX11-SAFE-TRUE16-NEXT:    v_xor_b16 v0.l, 0x8000, v0.l2181; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]2182; GFX11-NSZ-TRUE16-LABEL: v_fneg_0_maxnum_f16:2183; GFX11-NSZ-TRUE16:       ; %bb.0:2184; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2185; GFX11-NSZ-TRUE16-NEXT:    v_max_f16_e32 v0.l, 0, v0.l2186; GFX11-NSZ-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)2187; GFX11-NSZ-TRUE16-NEXT:    v_xor_b16 v0.l, 0x8000, v0.l2188; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]2189  %max = call nnan half @llvm.maxnum.f16(half 0.0, half %a)2190  %fneg = fneg half %max2191  ret half %fneg2192}2193 2194define half @v_fneg_neg0_maxnum_f16_ieee(half %a) #0 {2195; SI-LABEL: v_fneg_neg0_maxnum_f16_ieee:2196; SI:       ; %bb.0:2197; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2198; SI-NEXT:    v_cvt_f16_f32_e64 v0, -v02199; SI-NEXT:    v_cvt_f32_f16_e32 v0, v02200; SI-NEXT:    v_min_f32_e32 v0, 0, v02201; SI-NEXT:    s_setpc_b64 s[30:31]2202;2203; VI-LABEL: v_fneg_neg0_maxnum_f16_ieee:2204; VI:       ; %bb.0:2205; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2206; VI-NEXT:    v_max_f16_e64 v0, -v0, -v02207; VI-NEXT:    v_min_f16_e32 v0, 0, v02208; VI-NEXT:    s_setpc_b64 s[30:31]2209;2210; GFX11-LABEL: v_fneg_neg0_maxnum_f16_ieee:2211; GFX11:       ; %bb.0:2212; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2213; GFX11-NEXT:    v_max_f16_e64 v0, -v0, -v02214; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)2215; GFX11-NEXT:    v_min_f16_e32 v0, 0, v02216; GFX11-NEXT:    s_setpc_b64 s[30:31]2217; GFX11-SAFE-TRUE16-LABEL: v_fneg_neg0_maxnum_f16_ieee:2218; GFX11-SAFE-TRUE16:       ; %bb.0:2219; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2220; GFX11-SAFE-TRUE16-NEXT:    v_max_f16_e64 v0.l, -v0.l, -v0.l2221; GFX11-SAFE-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)2222; GFX11-SAFE-TRUE16-NEXT:    v_min_f16_e32 v0.l, 0, v0.l2223; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]2224; GFX11-NSZ-TRUE16-LABEL: v_fneg_neg0_maxnum_f16_ieee:2225; GFX11-NSZ-TRUE16:       ; %bb.0:2226; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2227; GFX11-NSZ-TRUE16-NEXT:    v_max_f16_e64 v0.l, -v0.l, -v0.l2228; GFX11-NSZ-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)2229; GFX11-NSZ-TRUE16-NEXT:    v_min_f16_e32 v0.l, 0, v0.l2230; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]2231  %max = call half @llvm.maxnum.f16(half -0.0, half %a)2232  %fneg = fneg half %max2233  ret half %fneg2234}2235 2236define half @v_fneg_neg0_maxnum_f16_no_ieee(half %a) #4 {2237; SI-LABEL: v_fneg_neg0_maxnum_f16_no_ieee:2238; SI:       ; %bb.0:2239; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2240; SI-NEXT:    v_cvt_f16_f32_e64 v0, -v02241; SI-NEXT:    v_cvt_f32_f16_e32 v0, v02242; SI-NEXT:    v_min_f32_e32 v0, 0, v02243; SI-NEXT:    s_setpc_b64 s[30:31]2244;2245; VI-LABEL: v_fneg_neg0_maxnum_f16_no_ieee:2246; VI:       ; %bb.0:2247; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2248; VI-NEXT:    v_min_f16_e64 v0, -v0, 02249; VI-NEXT:    s_setpc_b64 s[30:31]2250;2251; GFX11-LABEL: v_fneg_neg0_maxnum_f16_no_ieee:2252; GFX11:       ; %bb.0:2253; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2254; GFX11-NEXT:    v_min_f16_e64 v0, -v0, 02255; GFX11-NEXT:    s_setpc_b64 s[30:31]2256; GFX11-SAFE-TRUE16-LABEL: v_fneg_neg0_maxnum_f16_no_ieee:2257; GFX11-SAFE-TRUE16:       ; %bb.0:2258; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2259; GFX11-SAFE-TRUE16-NEXT:    v_min_f16_e64 v0.l, -v0.l, 02260; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]2261; GFX11-NSZ-TRUE16-LABEL: v_fneg_neg0_maxnum_f16_no_ieee:2262; GFX11-NSZ-TRUE16:       ; %bb.0:2263; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2264; GFX11-NSZ-TRUE16-NEXT:    v_min_f16_e64 v0.l, -v0.l, 02265; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]2266  %max = call half @llvm.maxnum.f16(half -0.0, half %a)2267  %fneg = fneg half %max2268  ret half %fneg2269}2270 2271define half @v_fneg_0_maxnum_foldable_use_f16_ieee(half %a, half %b) #0 {2272; SI-LABEL: v_fneg_0_maxnum_foldable_use_f16_ieee:2273; SI:       ; %bb.0:2274; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2275; SI-NEXT:    v_cvt_f16_f32_e32 v0, v02276; SI-NEXT:    v_cvt_f16_f32_e32 v1, v12277; SI-NEXT:    v_cvt_f32_f16_e32 v0, v02278; SI-NEXT:    v_cvt_f32_f16_e32 v1, v12279; SI-NEXT:    v_max_f32_e32 v0, 0, v02280; SI-NEXT:    v_mul_f32_e64 v0, -v0, v12281; SI-NEXT:    s_setpc_b64 s[30:31]2282;2283; VI-LABEL: v_fneg_0_maxnum_foldable_use_f16_ieee:2284; VI:       ; %bb.0:2285; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2286; VI-NEXT:    v_max_f16_e32 v0, v0, v02287; VI-NEXT:    v_max_f16_e32 v0, 0, v02288; VI-NEXT:    v_mul_f16_e64 v0, -v0, v12289; VI-NEXT:    s_setpc_b64 s[30:31]2290;2291; GFX11-LABEL: v_fneg_0_maxnum_foldable_use_f16_ieee:2292; GFX11:       ; %bb.0:2293; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2294; GFX11-NEXT:    v_max_f16_e32 v0, v0, v02295; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)2296; GFX11-NEXT:    v_max_f16_e32 v0, 0, v02297; GFX11-NEXT:    v_mul_f16_e64 v0, -v0, v12298; GFX11-NEXT:    s_setpc_b64 s[30:31]2299; GFX11-SAFE-TRUE16-LABEL: v_fneg_0_maxnum_foldable_use_f16_ieee:2300; GFX11-SAFE-TRUE16:       ; %bb.0:2301; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2302; GFX11-SAFE-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v0.l2303; GFX11-SAFE-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)2304; GFX11-SAFE-TRUE16-NEXT:    v_max_f16_e32 v0.l, 0, v0.l2305; GFX11-SAFE-TRUE16-NEXT:    v_mul_f16_e64 v0.l, -v0.l, v1.l2306; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]2307; GFX11-NSZ-TRUE16-LABEL: v_fneg_0_maxnum_foldable_use_f16_ieee:2308; GFX11-NSZ-TRUE16:       ; %bb.0:2309; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2310; GFX11-NSZ-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v0.l2311; GFX11-NSZ-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)2312; GFX11-NSZ-TRUE16-NEXT:    v_max_f16_e32 v0.l, 0, v0.l2313; GFX11-NSZ-TRUE16-NEXT:    v_mul_f16_e64 v0.l, -v0.l, v1.l2314; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]2315  %max = call half @llvm.maxnum.f16(half 0.0, half %a)2316  %fneg = fneg half %max2317  %mul = fmul half %fneg, %b2318  ret half %mul2319}2320 2321define half @v_fneg_0_maxnum_foldable_use_f16_no_ieee(half %a, half %b) #4 {2322; SI-LABEL: v_fneg_0_maxnum_foldable_use_f16_no_ieee:2323; SI:       ; %bb.0:2324; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2325; SI-NEXT:    v_cvt_f16_f32_e32 v0, v02326; SI-NEXT:    v_cvt_f16_f32_e32 v1, v12327; SI-NEXT:    v_cvt_f32_f16_e32 v0, v02328; SI-NEXT:    v_cvt_f32_f16_e32 v1, v12329; SI-NEXT:    v_max_f32_e32 v0, 0, v02330; SI-NEXT:    v_mul_f32_e64 v0, -v0, v12331; SI-NEXT:    s_setpc_b64 s[30:31]2332;2333; VI-LABEL: v_fneg_0_maxnum_foldable_use_f16_no_ieee:2334; VI:       ; %bb.0:2335; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2336; VI-NEXT:    v_max_f16_e32 v0, 0, v02337; VI-NEXT:    v_mul_f16_e64 v0, -v0, v12338; VI-NEXT:    s_setpc_b64 s[30:31]2339;2340; GFX11-LABEL: v_fneg_0_maxnum_foldable_use_f16_no_ieee:2341; GFX11:       ; %bb.0:2342; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2343; GFX11-NEXT:    v_max_f16_e32 v0, 0, v02344; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)2345; GFX11-NEXT:    v_mul_f16_e64 v0, -v0, v12346; GFX11-NEXT:    s_setpc_b64 s[30:31]2347; GFX11-SAFE-TRUE16-LABEL: v_fneg_0_maxnum_foldable_use_f16_no_ieee:2348; GFX11-SAFE-TRUE16:       ; %bb.0:2349; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2350; GFX11-SAFE-TRUE16-NEXT:    v_max_f16_e32 v0.l, 0, v0.l2351; GFX11-SAFE-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)2352; GFX11-SAFE-TRUE16-NEXT:    v_mul_f16_e64 v0.l, -v0.l, v1.l2353; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]2354; GFX11-NSZ-TRUE16-LABEL: v_fneg_0_maxnum_foldable_use_f16_no_ieee:2355; GFX11-NSZ-TRUE16:       ; %bb.0:2356; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2357; GFX11-NSZ-TRUE16-NEXT:    v_max_f16_e32 v0.l, 0, v0.l2358; GFX11-NSZ-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)2359; GFX11-NSZ-TRUE16-NEXT:    v_mul_f16_e64 v0.l, -v0.l, v1.l2360; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]2361  %max = call half @llvm.maxnum.f16(half 0.0, half %a)2362  %fneg = fneg half %max2363  %mul = fmul half %fneg, %b2364  ret half %mul2365}2366 2367define { half, half } @v_fneg_maxnum_multi_use_maxnum_f16_ieee(half %a, half %b) #0 {2368; SI-LABEL: v_fneg_maxnum_multi_use_maxnum_f16_ieee:2369; SI:       ; %bb.0:2370; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2371; SI-NEXT:    v_cvt_f16_f32_e32 v1, v12372; SI-NEXT:    v_cvt_f16_f32_e32 v0, v02373; SI-NEXT:    v_cvt_f32_f16_e64 v1, -v12374; SI-NEXT:    v_cvt_f32_f16_e64 v0, -v02375; SI-NEXT:    v_min_f32_e32 v0, v0, v12376; SI-NEXT:    v_mul_f32_e32 v1, -4.0, v02377; SI-NEXT:    s_setpc_b64 s[30:31]2378;2379; VI-LABEL: v_fneg_maxnum_multi_use_maxnum_f16_ieee:2380; VI:       ; %bb.0:2381; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2382; VI-NEXT:    v_max_f16_e64 v1, -v1, -v12383; VI-NEXT:    v_max_f16_e64 v0, -v0, -v02384; VI-NEXT:    v_min_f16_e32 v0, v0, v12385; VI-NEXT:    v_mul_f16_e32 v1, -4.0, v02386; VI-NEXT:    s_setpc_b64 s[30:31]2387;2388; GFX11-LABEL: v_fneg_maxnum_multi_use_maxnum_f16_ieee:2389; GFX11:       ; %bb.0:2390; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2391; GFX11-NEXT:    v_max_f16_e64 v1, -v1, -v12392; GFX11-NEXT:    v_max_f16_e64 v0, -v0, -v02393; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)2394; GFX11-NEXT:    v_min_f16_e32 v0, v0, v12395; GFX11-NEXT:    v_mul_f16_e32 v1, -4.0, v02396; GFX11-NEXT:    s_setpc_b64 s[30:31]2397; GFX11-SAFE-TRUE16-LABEL: v_fneg_maxnum_multi_use_maxnum_f16_ieee:2398; GFX11-SAFE-TRUE16:       ; %bb.0:2399; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2400; GFX11-SAFE-TRUE16-NEXT:    v_max_f16_e64 v0.h, -v1.l, -v1.l2401; GFX11-SAFE-TRUE16-NEXT:    v_max_f16_e64 v0.l, -v0.l, -v0.l2402; GFX11-SAFE-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)2403; GFX11-SAFE-TRUE16-NEXT:    v_min_f16_e32 v0.l, v0.l, v0.h2404; GFX11-SAFE-TRUE16-NEXT:    v_mul_f16_e32 v1.l, -4.0, v0.l2405; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]2406; GFX11-NSZ-TRUE16-LABEL: v_fneg_maxnum_multi_use_maxnum_f16_ieee:2407; GFX11-NSZ-TRUE16:       ; %bb.0:2408; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2409; GFX11-NSZ-TRUE16-NEXT:    v_max_f16_e64 v0.h, -v1.l, -v1.l2410; GFX11-NSZ-TRUE16-NEXT:    v_max_f16_e64 v0.l, -v0.l, -v0.l2411; GFX11-NSZ-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)2412; GFX11-NSZ-TRUE16-NEXT:    v_min_f16_e32 v0.l, v0.l, v0.h2413; GFX11-NSZ-TRUE16-NEXT:    v_mul_f16_e32 v1.l, -4.0, v0.l2414; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]2415  %max = call half @llvm.maxnum.f16(half %a, half %b)2416  %fneg = fneg half %max2417  %use1 = fmul half %max, 4.02418  %insert.0 = insertvalue { half, half } poison, half %fneg, 02419  %insert.1 = insertvalue { half, half } %insert.0, half %use1, 12420  ret { half, half } %insert.12421}2422 2423define <2 x half> @v_fneg_maxnum_multi_use_maxnum_f16_no_ieee(half %a, half %b) #4 {2424; SI-LABEL: v_fneg_maxnum_multi_use_maxnum_f16_no_ieee:2425; SI:       ; %bb.0:2426; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2427; SI-NEXT:    v_cvt_f16_f32_e32 v1, v12428; SI-NEXT:    v_cvt_f16_f32_e32 v0, v02429; SI-NEXT:    v_cvt_f32_f16_e64 v1, -v12430; SI-NEXT:    v_cvt_f32_f16_e64 v0, -v02431; SI-NEXT:    v_min_f32_e32 v0, v0, v12432; SI-NEXT:    v_mul_f32_e32 v1, -4.0, v02433; SI-NEXT:    s_setpc_b64 s[30:31]2434;2435; VI-LABEL: v_fneg_maxnum_multi_use_maxnum_f16_no_ieee:2436; VI:       ; %bb.0:2437; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2438; VI-NEXT:    v_min_f16_e64 v0, -v0, -v12439; VI-NEXT:    v_mov_b32_e32 v1, 0xc4002440; VI-NEXT:    v_mul_f16_sdwa v1, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD2441; VI-NEXT:    v_or_b32_e32 v0, v0, v12442; VI-NEXT:    s_setpc_b64 s[30:31]2443;2444; GFX11-LABEL: v_fneg_maxnum_multi_use_maxnum_f16_no_ieee:2445; GFX11:       ; %bb.0:2446; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2447; GFX11-NEXT:    v_max_f16_e32 v0, v0, v12448; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)2449; GFX11-NEXT:    v_mul_f16_e32 v1, 4.0, v02450; GFX11-NEXT:    v_pack_b32_f16 v0, -v0, v12451; GFX11-NEXT:    s_setpc_b64 s[30:31]2452; GFX11-SAFE-TRUE16-LABEL: v_fneg_maxnum_multi_use_maxnum_f16_no_ieee:2453; GFX11-SAFE-TRUE16:       ; %bb.0:2454; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2455; GFX11-SAFE-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v1.l2456; GFX11-SAFE-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)2457; GFX11-SAFE-TRUE16-NEXT:    v_mul_f16_e32 v0.h, 4.0, v0.l2458; GFX11-SAFE-TRUE16-NEXT:    v_pack_b32_f16 v0, -v0.l, v0.h2459; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]2460; GFX11-NSZ-TRUE16-LABEL: v_fneg_maxnum_multi_use_maxnum_f16_no_ieee:2461; GFX11-NSZ-TRUE16:       ; %bb.0:2462; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2463; GFX11-NSZ-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v1.l2464; GFX11-NSZ-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)2465; GFX11-NSZ-TRUE16-NEXT:    v_mul_f16_e32 v0.h, 4.0, v0.l2466; GFX11-NSZ-TRUE16-NEXT:    v_pack_b32_f16 v0, -v0.l, v0.h2467; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]2468  %max = call half @llvm.maxnum.f16(half %a, half %b)2469  %fneg = fneg half %max2470  %use1 = fmul half %max, 4.02471  %ins0 = insertelement <2 x half> poison, half %fneg, i32 02472  %ins1 = insertelement <2 x half> %ins0, half %use1, i32 12473  ret <2 x half> %ins12474}2475 2476; --------------------------------------------------------------------------------2477; fma tests2478; --------------------------------------------------------------------------------2479 2480define half @v_fneg_fma_f16(half %a, half %b, half %c) #0 {2481; SI-SAFE-LABEL: v_fneg_fma_f16:2482; SI-SAFE:       ; %bb.0:2483; SI-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2484; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v2, v22485; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v1, v12486; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v0, v02487; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v2, v22488; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v1, v12489; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v0, v02490; SI-SAFE-NEXT:    v_fma_f32 v0, v0, v1, v22491; SI-SAFE-NEXT:    v_xor_b32_e32 v0, 0x80000000, v02492; SI-SAFE-NEXT:    s_setpc_b64 s[30:31]2493;2494; SI-NSZ-LABEL: v_fneg_fma_f16:2495; SI-NSZ:       ; %bb.0:2496; SI-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2497; SI-NSZ-NEXT:    v_cvt_f16_f32_e32 v2, v22498; SI-NSZ-NEXT:    v_cvt_f16_f32_e32 v1, v12499; SI-NSZ-NEXT:    v_cvt_f16_f32_e32 v0, v02500; SI-NSZ-NEXT:    v_cvt_f32_f16_e32 v2, v22501; SI-NSZ-NEXT:    v_cvt_f32_f16_e32 v1, v12502; SI-NSZ-NEXT:    v_cvt_f32_f16_e32 v0, v02503; SI-NSZ-NEXT:    v_fma_f32 v0, v0, -v1, -v22504; SI-NSZ-NEXT:    s_setpc_b64 s[30:31]2505;2506; VI-SAFE-LABEL: v_fneg_fma_f16:2507; VI-SAFE:       ; %bb.0:2508; VI-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2509; VI-SAFE-NEXT:    v_fma_f16 v0, v0, v1, v22510; VI-SAFE-NEXT:    v_xor_b32_e32 v0, 0x8000, v02511; VI-SAFE-NEXT:    s_setpc_b64 s[30:31]2512;2513; VI-NSZ-LABEL: v_fneg_fma_f16:2514; VI-NSZ:       ; %bb.0:2515; VI-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2516; VI-NSZ-NEXT:    v_fma_f16 v0, v0, -v1, -v22517; VI-NSZ-NEXT:    s_setpc_b64 s[30:31]2518;2519; GFX11-SAFE-LABEL: v_fneg_fma_f16:2520; GFX11-SAFE:       ; %bb.0:2521; GFX11-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2522; GFX11-SAFE-NEXT:    v_fmac_f16_e32 v2, v0, v12523; GFX11-SAFE-NEXT:    s_delay_alu instid0(VALU_DEP_1)2524; GFX11-SAFE-NEXT:    v_xor_b32_e32 v0, 0x8000, v22525; GFX11-SAFE-NEXT:    s_setpc_b64 s[30:31]2526;2527; GFX11-NSZ-LABEL: v_fneg_fma_f16:2528; GFX11-NSZ:       ; %bb.0:2529; GFX11-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2530; GFX11-NSZ-NEXT:    v_fma_f16 v0, v0, -v1, -v22531; GFX11-NSZ-NEXT:    s_setpc_b64 s[30:31]2532; GFX11-SAFE-TRUE16-LABEL: v_fneg_fma_f16:2533; GFX11-SAFE-TRUE16:       ; %bb.0:2534; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2535; GFX11-SAFE-TRUE16-NEXT:    v_fmac_f16_e32 v2.l, v0.l, v1.l2536; GFX11-SAFE-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)2537; GFX11-SAFE-TRUE16-NEXT:    v_xor_b16 v0.l, 0x8000, v2.l2538; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]2539; GFX11-NSZ-TRUE16-LABEL: v_fneg_fma_f16:2540; GFX11-NSZ-TRUE16:       ; %bb.0:2541; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2542; GFX11-NSZ-TRUE16-NEXT:    v_fma_f16 v0.l, v0.l, -v1.l, -v2.l2543; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]2544  %fma = call half @llvm.fma.f16(half %a, half %b, half %c)2545  %fneg = fneg half %fma2546  ret half %fneg2547}2548 2549define { half, half } @v_fneg_fma_store_use_fma_f16(half %a, half %b, half %c) #0 {2550; SI-LABEL: v_fneg_fma_store_use_fma_f16:2551; SI:       ; %bb.0:2552; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2553; SI-NEXT:    v_cvt_f16_f32_e32 v2, v22554; SI-NEXT:    v_cvt_f16_f32_e32 v1, v12555; SI-NEXT:    v_cvt_f16_f32_e32 v0, v02556; SI-NEXT:    v_cvt_f32_f16_e32 v2, v22557; SI-NEXT:    v_cvt_f32_f16_e32 v1, v12558; SI-NEXT:    v_cvt_f32_f16_e32 v0, v02559; SI-NEXT:    v_fma_f32 v1, v0, v1, v22560; SI-NEXT:    v_xor_b32_e32 v0, 0x80000000, v12561; SI-NEXT:    s_setpc_b64 s[30:31]2562;2563; VI-LABEL: v_fneg_fma_store_use_fma_f16:2564; VI:       ; %bb.0:2565; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2566; VI-NEXT:    v_fma_f16 v1, v0, v1, v22567; VI-NEXT:    v_xor_b32_e32 v0, 0x8000, v12568; VI-NEXT:    s_setpc_b64 s[30:31]2569;2570; GFX11-LABEL: v_fneg_fma_store_use_fma_f16:2571; GFX11:       ; %bb.0:2572; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2573; GFX11-NEXT:    v_fma_f16 v1, v0, v1, v22574; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)2575; GFX11-NEXT:    v_xor_b32_e32 v0, 0x8000, v12576; GFX11-NEXT:    s_setpc_b64 s[30:31]2577; GFX11-SAFE-TRUE16-LABEL: v_fneg_fma_store_use_fma_f16:2578; GFX11-SAFE-TRUE16:       ; %bb.0:2579; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2580; GFX11-SAFE-TRUE16-NEXT:    v_fma_f16 v1.l, v0.l, v1.l, v2.l2581; GFX11-SAFE-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)2582; GFX11-SAFE-TRUE16-NEXT:    v_xor_b16 v0.l, 0x8000, v1.l2583; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]2584; GFX11-NSZ-TRUE16-LABEL: v_fneg_fma_store_use_fma_f16:2585; GFX11-NSZ-TRUE16:       ; %bb.0:2586; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2587; GFX11-NSZ-TRUE16-NEXT:    v_fma_f16 v1.l, v0.l, v1.l, v2.l2588; GFX11-NSZ-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)2589; GFX11-NSZ-TRUE16-NEXT:    v_xor_b16 v0.l, 0x8000, v1.l2590; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]2591  %fma = call half @llvm.fma.f16(half %a, half %b, half %c)2592  %fneg = fneg half %fma2593  %insert.0 = insertvalue { half, half } poison, half %fneg, 02594  %insert.1 = insertvalue { half, half } %insert.0, half %fma, 12595  ret { half, half } %insert.12596}2597 2598define { half, half } @v_fneg_fma_multi_use_fma_f16(half %a, half %b, half %c) #0 {2599; SI-SAFE-LABEL: v_fneg_fma_multi_use_fma_f16:2600; SI-SAFE:       ; %bb.0:2601; SI-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2602; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v2, v22603; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v1, v12604; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v0, v02605; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v2, v22606; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v1, v12607; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v0, v02608; SI-SAFE-NEXT:    v_fma_f32 v1, v0, v1, v22609; SI-SAFE-NEXT:    v_xor_b32_e32 v0, 0x80000000, v12610; SI-SAFE-NEXT:    v_mul_f32_e32 v1, 4.0, v12611; SI-SAFE-NEXT:    s_setpc_b64 s[30:31]2612;2613; SI-NSZ-LABEL: v_fneg_fma_multi_use_fma_f16:2614; SI-NSZ:       ; %bb.0:2615; SI-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2616; SI-NSZ-NEXT:    v_cvt_f16_f32_e32 v2, v22617; SI-NSZ-NEXT:    v_cvt_f16_f32_e32 v1, v12618; SI-NSZ-NEXT:    v_cvt_f16_f32_e32 v0, v02619; SI-NSZ-NEXT:    v_cvt_f32_f16_e32 v2, v22620; SI-NSZ-NEXT:    v_cvt_f32_f16_e32 v1, v12621; SI-NSZ-NEXT:    v_cvt_f32_f16_e32 v0, v02622; SI-NSZ-NEXT:    v_fma_f32 v0, v0, -v1, -v22623; SI-NSZ-NEXT:    v_mul_f32_e32 v1, -4.0, v02624; SI-NSZ-NEXT:    s_setpc_b64 s[30:31]2625;2626; VI-SAFE-LABEL: v_fneg_fma_multi_use_fma_f16:2627; VI-SAFE:       ; %bb.0:2628; VI-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2629; VI-SAFE-NEXT:    v_fma_f16 v1, v0, v1, v22630; VI-SAFE-NEXT:    v_xor_b32_e32 v0, 0x8000, v12631; VI-SAFE-NEXT:    v_mul_f16_e32 v1, 4.0, v12632; VI-SAFE-NEXT:    s_setpc_b64 s[30:31]2633;2634; VI-NSZ-LABEL: v_fneg_fma_multi_use_fma_f16:2635; VI-NSZ:       ; %bb.0:2636; VI-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2637; VI-NSZ-NEXT:    v_fma_f16 v0, v0, -v1, -v22638; VI-NSZ-NEXT:    v_mul_f16_e32 v1, -4.0, v02639; VI-NSZ-NEXT:    s_setpc_b64 s[30:31]2640;2641; GFX11-SAFE-LABEL: v_fneg_fma_multi_use_fma_f16:2642; GFX11-SAFE:       ; %bb.0:2643; GFX11-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2644; GFX11-SAFE-NEXT:    v_fmac_f16_e32 v2, v0, v12645; GFX11-SAFE-NEXT:    s_delay_alu instid0(VALU_DEP_1)2646; GFX11-SAFE-NEXT:    v_xor_b32_e32 v0, 0x8000, v22647; GFX11-SAFE-NEXT:    v_mul_f16_e32 v1, 4.0, v22648; GFX11-SAFE-NEXT:    s_setpc_b64 s[30:31]2649;2650; GFX11-NSZ-LABEL: v_fneg_fma_multi_use_fma_f16:2651; GFX11-NSZ:       ; %bb.0:2652; GFX11-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2653; GFX11-NSZ-NEXT:    v_fma_f16 v0, v0, -v1, -v22654; GFX11-NSZ-NEXT:    s_delay_alu instid0(VALU_DEP_1)2655; GFX11-NSZ-NEXT:    v_mul_f16_e32 v1, -4.0, v02656; GFX11-NSZ-NEXT:    s_setpc_b64 s[30:31]2657; GFX11-SAFE-TRUE16-LABEL: v_fneg_fma_multi_use_fma_f16:2658; GFX11-SAFE-TRUE16:       ; %bb.0:2659; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2660; GFX11-SAFE-TRUE16-NEXT:    v_fmac_f16_e32 v2.l, v0.l, v1.l2661; GFX11-SAFE-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)2662; GFX11-SAFE-TRUE16-NEXT:    v_xor_b16 v0.l, 0x8000, v2.l2663; GFX11-SAFE-TRUE16-NEXT:    v_mul_f16_e32 v1.l, 4.0, v2.l2664; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]2665; GFX11-NSZ-TRUE16-LABEL: v_fneg_fma_multi_use_fma_f16:2666; GFX11-NSZ-TRUE16:       ; %bb.0:2667; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2668; GFX11-NSZ-TRUE16-NEXT:    v_fma_f16 v0.l, v0.l, -v1.l, -v2.l2669; GFX11-NSZ-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)2670; GFX11-NSZ-TRUE16-NEXT:    v_mul_f16_e32 v1.l, -4.0, v0.l2671; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]2672  %fma = call half @llvm.fma.f16(half %a, half %b, half %c)2673  %fneg = fneg half %fma2674  %use1 = fmul half %fma, 4.02675  %insert.0 = insertvalue { half, half } poison, half %fneg, 02676  %insert.1 = insertvalue { half, half } %insert.0, half %use1, 12677  ret { half, half } %insert.12678}2679 2680define half @v_fneg_fma_fneg_x_y_f16(half %a, half %b, half %c) #0 {2681; SI-SAFE-LABEL: v_fneg_fma_fneg_x_y_f16:2682; SI-SAFE:       ; %bb.0:2683; SI-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2684; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v2, v22685; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v1, v12686; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v0, v02687; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v2, v22688; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v1, v12689; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v0, v02690; SI-SAFE-NEXT:    v_fma_f32 v0, -v0, v1, v22691; SI-SAFE-NEXT:    v_xor_b32_e32 v0, 0x80000000, v02692; SI-SAFE-NEXT:    s_setpc_b64 s[30:31]2693;2694; SI-NSZ-LABEL: v_fneg_fma_fneg_x_y_f16:2695; SI-NSZ:       ; %bb.0:2696; SI-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2697; SI-NSZ-NEXT:    v_cvt_f16_f32_e32 v2, v22698; SI-NSZ-NEXT:    v_cvt_f16_f32_e32 v1, v12699; SI-NSZ-NEXT:    v_cvt_f16_f32_e32 v0, v02700; SI-NSZ-NEXT:    v_cvt_f32_f16_e32 v2, v22701; SI-NSZ-NEXT:    v_cvt_f32_f16_e32 v1, v12702; SI-NSZ-NEXT:    v_cvt_f32_f16_e32 v0, v02703; SI-NSZ-NEXT:    v_fma_f32 v0, v0, v1, -v22704; SI-NSZ-NEXT:    s_setpc_b64 s[30:31]2705;2706; VI-SAFE-LABEL: v_fneg_fma_fneg_x_y_f16:2707; VI-SAFE:       ; %bb.0:2708; VI-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2709; VI-SAFE-NEXT:    v_fma_f16 v0, -v0, v1, v22710; VI-SAFE-NEXT:    v_xor_b32_e32 v0, 0x8000, v02711; VI-SAFE-NEXT:    s_setpc_b64 s[30:31]2712;2713; VI-NSZ-LABEL: v_fneg_fma_fneg_x_y_f16:2714; VI-NSZ:       ; %bb.0:2715; VI-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2716; VI-NSZ-NEXT:    v_fma_f16 v0, v0, v1, -v22717; VI-NSZ-NEXT:    s_setpc_b64 s[30:31]2718;2719; GFX11-SAFE-LABEL: v_fneg_fma_fneg_x_y_f16:2720; GFX11-SAFE:       ; %bb.0:2721; GFX11-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2722; GFX11-SAFE-NEXT:    v_fma_f16 v0, -v0, v1, v22723; GFX11-SAFE-NEXT:    s_delay_alu instid0(VALU_DEP_1)2724; GFX11-SAFE-NEXT:    v_xor_b32_e32 v0, 0x8000, v02725; GFX11-SAFE-NEXT:    s_setpc_b64 s[30:31]2726;2727; GFX11-NSZ-LABEL: v_fneg_fma_fneg_x_y_f16:2728; GFX11-NSZ:       ; %bb.0:2729; GFX11-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2730; GFX11-NSZ-NEXT:    v_fma_f16 v0, v0, v1, -v22731; GFX11-NSZ-NEXT:    s_setpc_b64 s[30:31]2732; GFX11-SAFE-TRUE16-LABEL: v_fneg_fma_fneg_x_y_f16:2733; GFX11-SAFE-TRUE16:       ; %bb.0:2734; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2735; GFX11-SAFE-TRUE16-NEXT:    v_fma_f16 v0.l, -v0.l, v1.l, v2.l2736; GFX11-SAFE-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)2737; GFX11-SAFE-TRUE16-NEXT:    v_xor_b16 v0.l, 0x8000, v0.l2738; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]2739; GFX11-NSZ-TRUE16-LABEL: v_fneg_fma_fneg_x_y_f16:2740; GFX11-NSZ-TRUE16:       ; %bb.0:2741; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2742; GFX11-NSZ-TRUE16-NEXT:    v_fma_f16 v0.l, v0.l, v1.l, -v2.l2743; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]2744  %fneg.a = fneg half %a2745  %fma = call half @llvm.fma.f16(half %fneg.a, half %b, half %c)2746  %fneg = fneg half %fma2747  ret half %fneg2748}2749 2750define half @v_fneg_fma_x_fneg_y_f16(half %a, half %b, half %c) #0 {2751; SI-SAFE-LABEL: v_fneg_fma_x_fneg_y_f16:2752; SI-SAFE:       ; %bb.0:2753; SI-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2754; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v2, v22755; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v1, v12756; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v0, v02757; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v2, v22758; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v1, v12759; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v0, v02760; SI-SAFE-NEXT:    v_fma_f32 v0, v0, -v1, v22761; SI-SAFE-NEXT:    v_xor_b32_e32 v0, 0x80000000, v02762; SI-SAFE-NEXT:    s_setpc_b64 s[30:31]2763;2764; SI-NSZ-LABEL: v_fneg_fma_x_fneg_y_f16:2765; SI-NSZ:       ; %bb.0:2766; SI-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2767; SI-NSZ-NEXT:    v_cvt_f16_f32_e32 v2, v22768; SI-NSZ-NEXT:    v_cvt_f16_f32_e32 v1, v12769; SI-NSZ-NEXT:    v_cvt_f16_f32_e32 v0, v02770; SI-NSZ-NEXT:    v_cvt_f32_f16_e32 v2, v22771; SI-NSZ-NEXT:    v_cvt_f32_f16_e32 v1, v12772; SI-NSZ-NEXT:    v_cvt_f32_f16_e32 v0, v02773; SI-NSZ-NEXT:    v_fma_f32 v0, v0, v1, -v22774; SI-NSZ-NEXT:    s_setpc_b64 s[30:31]2775;2776; VI-SAFE-LABEL: v_fneg_fma_x_fneg_y_f16:2777; VI-SAFE:       ; %bb.0:2778; VI-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2779; VI-SAFE-NEXT:    v_fma_f16 v0, v0, -v1, v22780; VI-SAFE-NEXT:    v_xor_b32_e32 v0, 0x8000, v02781; VI-SAFE-NEXT:    s_setpc_b64 s[30:31]2782;2783; VI-NSZ-LABEL: v_fneg_fma_x_fneg_y_f16:2784; VI-NSZ:       ; %bb.0:2785; VI-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2786; VI-NSZ-NEXT:    v_fma_f16 v0, v0, v1, -v22787; VI-NSZ-NEXT:    s_setpc_b64 s[30:31]2788;2789; GFX11-SAFE-LABEL: v_fneg_fma_x_fneg_y_f16:2790; GFX11-SAFE:       ; %bb.0:2791; GFX11-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2792; GFX11-SAFE-NEXT:    v_fma_f16 v0, v0, -v1, v22793; GFX11-SAFE-NEXT:    s_delay_alu instid0(VALU_DEP_1)2794; GFX11-SAFE-NEXT:    v_xor_b32_e32 v0, 0x8000, v02795; GFX11-SAFE-NEXT:    s_setpc_b64 s[30:31]2796;2797; GFX11-NSZ-LABEL: v_fneg_fma_x_fneg_y_f16:2798; GFX11-NSZ:       ; %bb.0:2799; GFX11-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2800; GFX11-NSZ-NEXT:    v_fma_f16 v0, v0, v1, -v22801; GFX11-NSZ-NEXT:    s_setpc_b64 s[30:31]2802; GFX11-SAFE-TRUE16-LABEL: v_fneg_fma_x_fneg_y_f16:2803; GFX11-SAFE-TRUE16:       ; %bb.0:2804; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2805; GFX11-SAFE-TRUE16-NEXT:    v_fma_f16 v0.l, v0.l, -v1.l, v2.l2806; GFX11-SAFE-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)2807; GFX11-SAFE-TRUE16-NEXT:    v_xor_b16 v0.l, 0x8000, v0.l2808; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]2809; GFX11-NSZ-TRUE16-LABEL: v_fneg_fma_x_fneg_y_f16:2810; GFX11-NSZ-TRUE16:       ; %bb.0:2811; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2812; GFX11-NSZ-TRUE16-NEXT:    v_fma_f16 v0.l, v0.l, v1.l, -v2.l2813; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]2814  %fneg.b = fneg half %b2815  %fma = call half @llvm.fma.f16(half %a, half %fneg.b, half %c)2816  %fneg = fneg half %fma2817  ret half %fneg2818}2819 2820define half @v_fneg_fma_fneg_fneg_y_f16(half %a, half %b, half %c) #0 {2821; SI-SAFE-LABEL: v_fneg_fma_fneg_fneg_y_f16:2822; SI-SAFE:       ; %bb.0:2823; SI-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2824; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v2, v22825; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v1, v12826; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v0, v02827; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v2, v22828; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v1, v12829; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v0, v02830; SI-SAFE-NEXT:    v_fma_f32 v0, v0, v1, v22831; SI-SAFE-NEXT:    v_xor_b32_e32 v0, 0x80000000, v02832; SI-SAFE-NEXT:    s_setpc_b64 s[30:31]2833;2834; SI-NSZ-LABEL: v_fneg_fma_fneg_fneg_y_f16:2835; SI-NSZ:       ; %bb.0:2836; SI-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2837; SI-NSZ-NEXT:    v_cvt_f16_f32_e32 v2, v22838; SI-NSZ-NEXT:    v_cvt_f16_f32_e32 v1, v12839; SI-NSZ-NEXT:    v_cvt_f16_f32_e32 v0, v02840; SI-NSZ-NEXT:    v_cvt_f32_f16_e32 v2, v22841; SI-NSZ-NEXT:    v_cvt_f32_f16_e32 v1, v12842; SI-NSZ-NEXT:    v_cvt_f32_f16_e32 v0, v02843; SI-NSZ-NEXT:    v_fma_f32 v0, v0, -v1, -v22844; SI-NSZ-NEXT:    s_setpc_b64 s[30:31]2845;2846; VI-SAFE-LABEL: v_fneg_fma_fneg_fneg_y_f16:2847; VI-SAFE:       ; %bb.0:2848; VI-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2849; VI-SAFE-NEXT:    v_fma_f16 v0, v0, v1, v22850; VI-SAFE-NEXT:    v_xor_b32_e32 v0, 0x8000, v02851; VI-SAFE-NEXT:    s_setpc_b64 s[30:31]2852;2853; VI-NSZ-LABEL: v_fneg_fma_fneg_fneg_y_f16:2854; VI-NSZ:       ; %bb.0:2855; VI-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2856; VI-NSZ-NEXT:    v_fma_f16 v0, v0, -v1, -v22857; VI-NSZ-NEXT:    s_setpc_b64 s[30:31]2858;2859; GFX11-SAFE-LABEL: v_fneg_fma_fneg_fneg_y_f16:2860; GFX11-SAFE:       ; %bb.0:2861; GFX11-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2862; GFX11-SAFE-NEXT:    v_fmac_f16_e32 v2, v0, v12863; GFX11-SAFE-NEXT:    s_delay_alu instid0(VALU_DEP_1)2864; GFX11-SAFE-NEXT:    v_xor_b32_e32 v0, 0x8000, v22865; GFX11-SAFE-NEXT:    s_setpc_b64 s[30:31]2866;2867; GFX11-NSZ-LABEL: v_fneg_fma_fneg_fneg_y_f16:2868; GFX11-NSZ:       ; %bb.0:2869; GFX11-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2870; GFX11-NSZ-NEXT:    v_fma_f16 v0, v0, -v1, -v22871; GFX11-NSZ-NEXT:    s_setpc_b64 s[30:31]2872; GFX11-SAFE-TRUE16-LABEL: v_fneg_fma_fneg_fneg_y_f16:2873; GFX11-SAFE-TRUE16:       ; %bb.0:2874; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2875; GFX11-SAFE-TRUE16-NEXT:    v_fmac_f16_e32 v2.l, v0.l, v1.l2876; GFX11-SAFE-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)2877; GFX11-SAFE-TRUE16-NEXT:    v_xor_b16 v0.l, 0x8000, v2.l2878; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]2879; GFX11-NSZ-TRUE16-LABEL: v_fneg_fma_fneg_fneg_y_f16:2880; GFX11-NSZ-TRUE16:       ; %bb.0:2881; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2882; GFX11-NSZ-TRUE16-NEXT:    v_fma_f16 v0.l, v0.l, -v1.l, -v2.l2883; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]2884  %fneg.a = fneg half %a2885  %fneg.b = fneg half %b2886  %fma = call half @llvm.fma.f16(half %fneg.a, half %fneg.b, half %c)2887  %fneg = fneg half %fma2888  ret half %fneg2889}2890 2891define half @v_fneg_fma_fneg_x_fneg_f16(half %a, half %b, half %c) #0 {2892; SI-SAFE-LABEL: v_fneg_fma_fneg_x_fneg_f16:2893; SI-SAFE:       ; %bb.0:2894; SI-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2895; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v2, v22896; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v1, v12897; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v0, v02898; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v2, v22899; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v1, v12900; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v0, v02901; SI-SAFE-NEXT:    v_fma_f32 v0, -v0, v1, -v22902; SI-SAFE-NEXT:    v_xor_b32_e32 v0, 0x80000000, v02903; SI-SAFE-NEXT:    s_setpc_b64 s[30:31]2904;2905; SI-NSZ-LABEL: v_fneg_fma_fneg_x_fneg_f16:2906; SI-NSZ:       ; %bb.0:2907; SI-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2908; SI-NSZ-NEXT:    v_cvt_f16_f32_e32 v2, v22909; SI-NSZ-NEXT:    v_cvt_f16_f32_e32 v1, v12910; SI-NSZ-NEXT:    v_cvt_f16_f32_e32 v0, v02911; SI-NSZ-NEXT:    v_cvt_f32_f16_e32 v2, v22912; SI-NSZ-NEXT:    v_cvt_f32_f16_e32 v1, v12913; SI-NSZ-NEXT:    v_cvt_f32_f16_e32 v0, v02914; SI-NSZ-NEXT:    v_fma_f32 v0, v0, v1, v22915; SI-NSZ-NEXT:    s_setpc_b64 s[30:31]2916;2917; VI-SAFE-LABEL: v_fneg_fma_fneg_x_fneg_f16:2918; VI-SAFE:       ; %bb.0:2919; VI-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2920; VI-SAFE-NEXT:    v_fma_f16 v0, -v0, v1, -v22921; VI-SAFE-NEXT:    v_xor_b32_e32 v0, 0x8000, v02922; VI-SAFE-NEXT:    s_setpc_b64 s[30:31]2923;2924; VI-NSZ-LABEL: v_fneg_fma_fneg_x_fneg_f16:2925; VI-NSZ:       ; %bb.0:2926; VI-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2927; VI-NSZ-NEXT:    v_fma_f16 v0, v0, v1, v22928; VI-NSZ-NEXT:    s_setpc_b64 s[30:31]2929;2930; GFX11-SAFE-LABEL: v_fneg_fma_fneg_x_fneg_f16:2931; GFX11-SAFE:       ; %bb.0:2932; GFX11-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2933; GFX11-SAFE-NEXT:    v_fma_f16 v0, -v0, v1, -v22934; GFX11-SAFE-NEXT:    s_delay_alu instid0(VALU_DEP_1)2935; GFX11-SAFE-NEXT:    v_xor_b32_e32 v0, 0x8000, v02936; GFX11-SAFE-NEXT:    s_setpc_b64 s[30:31]2937;2938; GFX11-NSZ-LABEL: v_fneg_fma_fneg_x_fneg_f16:2939; GFX11-NSZ:       ; %bb.0:2940; GFX11-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2941; GFX11-NSZ-NEXT:    v_fma_f16 v0, v0, v1, v22942; GFX11-NSZ-NEXT:    s_setpc_b64 s[30:31]2943; GFX11-SAFE-TRUE16-LABEL: v_fneg_fma_fneg_x_fneg_f16:2944; GFX11-SAFE-TRUE16:       ; %bb.0:2945; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2946; GFX11-SAFE-TRUE16-NEXT:    v_fma_f16 v0.l, -v0.l, v1.l, -v2.l2947; GFX11-SAFE-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)2948; GFX11-SAFE-TRUE16-NEXT:    v_xor_b16 v0.l, 0x8000, v0.l2949; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]2950; GFX11-NSZ-TRUE16-LABEL: v_fneg_fma_fneg_x_fneg_f16:2951; GFX11-NSZ-TRUE16:       ; %bb.0:2952; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2953; GFX11-NSZ-TRUE16-NEXT:    v_fma_f16 v0.l, v0.l, v1.l, v2.l2954; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]2955  %fneg.a = fneg half %a2956  %fneg.c = fneg half %c2957  %fma = call half @llvm.fma.f16(half %fneg.a, half %b, half %fneg.c)2958  %fneg = fneg half %fma2959  ret half %fneg2960}2961 2962define half @v_fneg_fma_x_y_fneg_f16(half %a, half %b, half %c) #0 {2963; SI-SAFE-LABEL: v_fneg_fma_x_y_fneg_f16:2964; SI-SAFE:       ; %bb.0:2965; SI-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2966; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v2, v22967; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v1, v12968; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v0, v02969; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v2, v22970; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v1, v12971; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v0, v02972; SI-SAFE-NEXT:    v_fma_f32 v0, v0, v1, -v22973; SI-SAFE-NEXT:    v_xor_b32_e32 v0, 0x80000000, v02974; SI-SAFE-NEXT:    s_setpc_b64 s[30:31]2975;2976; SI-NSZ-LABEL: v_fneg_fma_x_y_fneg_f16:2977; SI-NSZ:       ; %bb.0:2978; SI-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2979; SI-NSZ-NEXT:    v_cvt_f16_f32_e32 v2, v22980; SI-NSZ-NEXT:    v_cvt_f16_f32_e32 v1, v12981; SI-NSZ-NEXT:    v_cvt_f16_f32_e32 v0, v02982; SI-NSZ-NEXT:    v_cvt_f32_f16_e32 v2, v22983; SI-NSZ-NEXT:    v_cvt_f32_f16_e32 v1, v12984; SI-NSZ-NEXT:    v_cvt_f32_f16_e32 v0, v02985; SI-NSZ-NEXT:    v_fma_f32 v0, v0, -v1, v22986; SI-NSZ-NEXT:    s_setpc_b64 s[30:31]2987;2988; VI-SAFE-LABEL: v_fneg_fma_x_y_fneg_f16:2989; VI-SAFE:       ; %bb.0:2990; VI-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2991; VI-SAFE-NEXT:    v_fma_f16 v0, v0, v1, -v22992; VI-SAFE-NEXT:    v_xor_b32_e32 v0, 0x8000, v02993; VI-SAFE-NEXT:    s_setpc_b64 s[30:31]2994;2995; VI-NSZ-LABEL: v_fneg_fma_x_y_fneg_f16:2996; VI-NSZ:       ; %bb.0:2997; VI-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2998; VI-NSZ-NEXT:    v_fma_f16 v0, v0, -v1, v22999; VI-NSZ-NEXT:    s_setpc_b64 s[30:31]3000;3001; GFX11-SAFE-LABEL: v_fneg_fma_x_y_fneg_f16:3002; GFX11-SAFE:       ; %bb.0:3003; GFX11-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3004; GFX11-SAFE-NEXT:    v_fma_f16 v0, v0, v1, -v23005; GFX11-SAFE-NEXT:    s_delay_alu instid0(VALU_DEP_1)3006; GFX11-SAFE-NEXT:    v_xor_b32_e32 v0, 0x8000, v03007; GFX11-SAFE-NEXT:    s_setpc_b64 s[30:31]3008;3009; GFX11-NSZ-LABEL: v_fneg_fma_x_y_fneg_f16:3010; GFX11-NSZ:       ; %bb.0:3011; GFX11-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3012; GFX11-NSZ-NEXT:    v_fma_f16 v0, v0, -v1, v23013; GFX11-NSZ-NEXT:    s_setpc_b64 s[30:31]3014; GFX11-SAFE-TRUE16-LABEL: v_fneg_fma_x_y_fneg_f16:3015; GFX11-SAFE-TRUE16:       ; %bb.0:3016; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3017; GFX11-SAFE-TRUE16-NEXT:    v_fma_f16 v0.l, v0.l, v1.l, -v2.l3018; GFX11-SAFE-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)3019; GFX11-SAFE-TRUE16-NEXT:    v_xor_b16 v0.l, 0x8000, v0.l3020; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]3021; GFX11-NSZ-TRUE16-LABEL: v_fneg_fma_x_y_fneg_f16:3022; GFX11-NSZ-TRUE16:       ; %bb.0:3023; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3024; GFX11-NSZ-TRUE16-NEXT:    v_fma_f16 v0.l, v0.l, -v1.l, v2.l3025; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]3026  %fneg.c = fneg half %c3027  %fma = call half @llvm.fma.f16(half %a, half %b, half %fneg.c)3028  %fneg = fneg half %fma3029  ret half %fneg3030}3031 3032define { half, half } @v_fneg_fma_store_use_fneg_x_y_f16(half %a, half %b, half %c) #0 {3033; SI-SAFE-LABEL: v_fneg_fma_store_use_fneg_x_y_f16:3034; SI-SAFE:       ; %bb.0:3035; SI-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3036; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v2, v23037; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v1, v13038; SI-SAFE-NEXT:    v_cvt_f16_f32_e64 v3, -v03039; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v2, v23040; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v4, v13041; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v3, v33042; SI-SAFE-NEXT:    v_xor_b32_e32 v1, 0x80000000, v03043; SI-SAFE-NEXT:    v_fma_f32 v0, v3, v4, v23044; SI-SAFE-NEXT:    v_xor_b32_e32 v0, 0x80000000, v03045; SI-SAFE-NEXT:    s_setpc_b64 s[30:31]3046;3047; SI-NSZ-LABEL: v_fneg_fma_store_use_fneg_x_y_f16:3048; SI-NSZ:       ; %bb.0:3049; SI-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3050; SI-NSZ-NEXT:    v_cvt_f16_f32_e32 v2, v23051; SI-NSZ-NEXT:    v_cvt_f16_f32_e32 v1, v13052; SI-NSZ-NEXT:    v_cvt_f16_f32_e32 v0, v03053; SI-NSZ-NEXT:    v_cvt_f32_f16_e32 v2, v23054; SI-NSZ-NEXT:    v_cvt_f32_f16_e32 v3, v13055; SI-NSZ-NEXT:    v_cvt_f32_f16_e32 v4, v03056; SI-NSZ-NEXT:    v_cvt_f32_f16_e64 v1, -v03057; SI-NSZ-NEXT:    v_fma_f32 v0, v4, v3, -v23058; SI-NSZ-NEXT:    s_setpc_b64 s[30:31]3059;3060; VI-SAFE-LABEL: v_fneg_fma_store_use_fneg_x_y_f16:3061; VI-SAFE:       ; %bb.0:3062; VI-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3063; VI-SAFE-NEXT:    v_xor_b32_e32 v3, 0x8000, v03064; VI-SAFE-NEXT:    v_fma_f16 v0, -v0, v1, v23065; VI-SAFE-NEXT:    v_xor_b32_e32 v0, 0x8000, v03066; VI-SAFE-NEXT:    v_mov_b32_e32 v1, v33067; VI-SAFE-NEXT:    s_setpc_b64 s[30:31]3068;3069; VI-NSZ-LABEL: v_fneg_fma_store_use_fneg_x_y_f16:3070; VI-NSZ:       ; %bb.0:3071; VI-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3072; VI-NSZ-NEXT:    v_xor_b32_e32 v3, 0x8000, v03073; VI-NSZ-NEXT:    v_fma_f16 v0, v0, v1, -v23074; VI-NSZ-NEXT:    v_mov_b32_e32 v1, v33075; VI-NSZ-NEXT:    s_setpc_b64 s[30:31]3076;3077; GFX11-SAFE-LABEL: v_fneg_fma_store_use_fneg_x_y_f16:3078; GFX11-SAFE:       ; %bb.0:3079; GFX11-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3080; GFX11-SAFE-NEXT:    v_fma_f16 v1, -v0, v1, v23081; GFX11-SAFE-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)3082; GFX11-SAFE-NEXT:    v_xor_b32_e32 v2, 0x8000, v13083; GFX11-SAFE-NEXT:    v_xor_b32_e32 v1, 0x8000, v03084; GFX11-SAFE-NEXT:    v_mov_b32_e32 v0, v23085; GFX11-SAFE-NEXT:    s_setpc_b64 s[30:31]3086;3087; GFX11-NSZ-LABEL: v_fneg_fma_store_use_fneg_x_y_f16:3088; GFX11-NSZ:       ; %bb.0:3089; GFX11-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3090; GFX11-NSZ-NEXT:    v_fma_f16 v2, v0, v1, -v23091; GFX11-NSZ-NEXT:    v_xor_b32_e32 v1, 0x8000, v03092; GFX11-NSZ-NEXT:    s_delay_alu instid0(VALU_DEP_2)3093; GFX11-NSZ-NEXT:    v_mov_b32_e32 v0, v23094; GFX11-NSZ-NEXT:    s_setpc_b64 s[30:31]3095; GFX11-SAFE-TRUE16-LABEL: v_fneg_fma_store_use_fneg_x_y_f16:3096; GFX11-SAFE-TRUE16:       ; %bb.0:3097; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3098; GFX11-SAFE-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v0.l3099; GFX11-SAFE-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)3100; GFX11-SAFE-TRUE16-NEXT:    v_fma_f16 v0.l, -v0.h, v1.l, v2.l3101; GFX11-SAFE-TRUE16-NEXT:    v_xor_b16 v1.l, 0x8000, v0.h3102; GFX11-SAFE-TRUE16-NEXT:    v_xor_b16 v0.l, 0x8000, v0.l3103; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]3104; GFX11-NSZ-TRUE16-LABEL: v_fneg_fma_store_use_fneg_x_y_f16:3105; GFX11-NSZ-TRUE16:       ; %bb.0:3106; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3107; GFX11-NSZ-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v0.l3108; GFX11-NSZ-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)3109; GFX11-NSZ-TRUE16-NEXT:    v_fma_f16 v0.l, v0.h, v1.l, -v2.l3110; GFX11-NSZ-TRUE16-NEXT:    v_xor_b16 v1.l, 0x8000, v0.h3111; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]3112  %fneg.a = fneg half %a3113  %fma = call half @llvm.fma.f16(half %fneg.a, half %b, half %c)3114  %fneg = fneg half %fma3115  %insert.0 = insertvalue { half, half } poison, half %fneg, 03116  %insert.1 = insertvalue { half, half } %insert.0, half %fneg.a, 13117  ret { half, half } %insert.13118}3119 3120define { half, half } @v_fneg_fma_multi_use_fneg_x_y_f16(half %a, half %b, half %c, half %d) #0 {3121; SI-SAFE-LABEL: v_fneg_fma_multi_use_fneg_x_y_f16:3122; SI-SAFE:       ; %bb.0:3123; SI-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3124; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v2, v23125; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v1, v13126; SI-SAFE-NEXT:    v_cvt_f16_f32_e64 v0, -v03127; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v3, v33128; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v2, v23129; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v1, v13130; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v4, v03131; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v3, v33132; SI-SAFE-NEXT:    v_fma_f32 v0, v4, v1, v23133; SI-SAFE-NEXT:    v_xor_b32_e32 v0, 0x80000000, v03134; SI-SAFE-NEXT:    v_mul_f32_e32 v1, v4, v33135; SI-SAFE-NEXT:    s_setpc_b64 s[30:31]3136;3137; SI-NSZ-LABEL: v_fneg_fma_multi_use_fneg_x_y_f16:3138; SI-NSZ:       ; %bb.0:3139; SI-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3140; SI-NSZ-NEXT:    v_cvt_f16_f32_e32 v3, v33141; SI-NSZ-NEXT:    v_cvt_f16_f32_e32 v2, v23142; SI-NSZ-NEXT:    v_cvt_f16_f32_e32 v1, v13143; SI-NSZ-NEXT:    v_cvt_f16_f32_e32 v0, v03144; SI-NSZ-NEXT:    v_cvt_f32_f16_e32 v3, v33145; SI-NSZ-NEXT:    v_cvt_f32_f16_e32 v2, v23146; SI-NSZ-NEXT:    v_cvt_f32_f16_e32 v1, v13147; SI-NSZ-NEXT:    v_cvt_f32_f16_e32 v4, v03148; SI-NSZ-NEXT:    v_cvt_f32_f16_e64 v5, -v03149; SI-NSZ-NEXT:    v_fma_f32 v0, v4, v1, -v23150; SI-NSZ-NEXT:    v_mul_f32_e32 v1, v5, v33151; SI-NSZ-NEXT:    s_setpc_b64 s[30:31]3152;3153; VI-SAFE-LABEL: v_fneg_fma_multi_use_fneg_x_y_f16:3154; VI-SAFE:       ; %bb.0:3155; VI-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3156; VI-SAFE-NEXT:    v_fma_f16 v1, -v0, v1, v23157; VI-SAFE-NEXT:    v_xor_b32_e32 v2, 0x8000, v13158; VI-SAFE-NEXT:    v_mul_f16_e64 v1, -v0, v33159; VI-SAFE-NEXT:    v_mov_b32_e32 v0, v23160; VI-SAFE-NEXT:    s_setpc_b64 s[30:31]3161;3162; VI-NSZ-LABEL: v_fneg_fma_multi_use_fneg_x_y_f16:3163; VI-NSZ:       ; %bb.0:3164; VI-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3165; VI-NSZ-NEXT:    v_fma_f16 v2, v0, v1, -v23166; VI-NSZ-NEXT:    v_mul_f16_e64 v1, -v0, v33167; VI-NSZ-NEXT:    v_mov_b32_e32 v0, v23168; VI-NSZ-NEXT:    s_setpc_b64 s[30:31]3169;3170; GFX11-SAFE-LABEL: v_fneg_fma_multi_use_fneg_x_y_f16:3171; GFX11-SAFE:       ; %bb.0:3172; GFX11-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3173; GFX11-SAFE-NEXT:    v_fma_f16 v1, -v0, v1, v23174; GFX11-SAFE-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)3175; GFX11-SAFE-NEXT:    v_xor_b32_e32 v2, 0x8000, v13176; GFX11-SAFE-NEXT:    v_mul_f16_e64 v1, -v0, v33177; GFX11-SAFE-NEXT:    v_mov_b32_e32 v0, v23178; GFX11-SAFE-NEXT:    s_setpc_b64 s[30:31]3179;3180; GFX11-NSZ-LABEL: v_fneg_fma_multi_use_fneg_x_y_f16:3181; GFX11-NSZ:       ; %bb.0:3182; GFX11-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3183; GFX11-NSZ-NEXT:    v_fma_f16 v2, v0, v1, -v23184; GFX11-NSZ-NEXT:    v_mul_f16_e64 v1, -v0, v33185; GFX11-NSZ-NEXT:    s_delay_alu instid0(VALU_DEP_2)3186; GFX11-NSZ-NEXT:    v_mov_b32_e32 v0, v23187; GFX11-NSZ-NEXT:    s_setpc_b64 s[30:31]3188; GFX11-SAFE-TRUE16-LABEL: v_fneg_fma_multi_use_fneg_x_y_f16:3189; GFX11-SAFE-TRUE16:       ; %bb.0:3190; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3191; GFX11-SAFE-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v0.l3192; GFX11-SAFE-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)3193; GFX11-SAFE-TRUE16-NEXT:    v_fma_f16 v0.l, -v0.h, v1.l, v2.l3194; GFX11-SAFE-TRUE16-NEXT:    v_mul_f16_e64 v1.l, -v0.h, v3.l3195; GFX11-SAFE-TRUE16-NEXT:    v_xor_b16 v0.l, 0x8000, v0.l3196; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]3197; GFX11-NSZ-TRUE16-LABEL: v_fneg_fma_multi_use_fneg_x_y_f16:3198; GFX11-NSZ-TRUE16:       ; %bb.0:3199; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3200; GFX11-NSZ-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v0.l3201; GFX11-NSZ-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)3202; GFX11-NSZ-TRUE16-NEXT:    v_fma_f16 v0.l, v0.h, v1.l, -v2.l3203; GFX11-NSZ-TRUE16-NEXT:    v_mul_f16_e64 v1.l, -v0.h, v3.l3204; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]3205  %fneg.a = fneg half %a3206  %fma = call half @llvm.fma.f16(half %fneg.a, half %b, half %c)3207  %fneg = fneg half %fma3208  %use1 = fmul half %fneg.a, %d3209  %insert.0 = insertvalue { half, half } poison, half %fneg, 03210  %insert.1 = insertvalue { half, half } %insert.0, half %use1, 13211  ret { half, half } %insert.13212}3213 3214; --------------------------------------------------------------------------------3215; fmad tests3216; --------------------------------------------------------------------------------3217 3218define half @v_fneg_fmad_f16(half %a, half %b, half %c) #0 {3219; SI-SAFE-LABEL: v_fneg_fmad_f16:3220; SI-SAFE:       ; %bb.0:3221; SI-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3222; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v2, v23223; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v1, v13224; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v0, v03225; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v2, v23226; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v1, v13227; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v0, v03228; SI-SAFE-NEXT:    v_mac_f32_e32 v2, v0, v13229; SI-SAFE-NEXT:    v_xor_b32_e32 v0, 0x80000000, v23230; SI-SAFE-NEXT:    s_setpc_b64 s[30:31]3231;3232; SI-NSZ-LABEL: v_fneg_fmad_f16:3233; SI-NSZ:       ; %bb.0:3234; SI-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3235; SI-NSZ-NEXT:    v_cvt_f16_f32_e32 v2, v23236; SI-NSZ-NEXT:    v_cvt_f16_f32_e32 v0, v03237; SI-NSZ-NEXT:    v_cvt_f16_f32_e64 v1, -v13238; SI-NSZ-NEXT:    v_cvt_f32_f16_e32 v2, v23239; SI-NSZ-NEXT:    v_cvt_f32_f16_e32 v0, v03240; SI-NSZ-NEXT:    v_cvt_f32_f16_e32 v1, v13241; SI-NSZ-NEXT:    v_mad_f32 v0, v0, v1, -v23242; SI-NSZ-NEXT:    s_setpc_b64 s[30:31]3243;3244; VI-SAFE-LABEL: v_fneg_fmad_f16:3245; VI-SAFE:       ; %bb.0:3246; VI-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3247; VI-SAFE-NEXT:    v_fma_f16 v0, v0, v1, v23248; VI-SAFE-NEXT:    v_xor_b32_e32 v0, 0x8000, v03249; VI-SAFE-NEXT:    s_setpc_b64 s[30:31]3250;3251; VI-NSZ-LABEL: v_fneg_fmad_f16:3252; VI-NSZ:       ; %bb.0:3253; VI-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3254; VI-NSZ-NEXT:    v_fma_f16 v0, v0, -v1, -v23255; VI-NSZ-NEXT:    s_setpc_b64 s[30:31]3256;3257; GFX11-SAFE-LABEL: v_fneg_fmad_f16:3258; GFX11-SAFE:       ; %bb.0:3259; GFX11-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3260; GFX11-SAFE-NEXT:    v_fmac_f16_e32 v2, v0, v13261; GFX11-SAFE-NEXT:    s_delay_alu instid0(VALU_DEP_1)3262; GFX11-SAFE-NEXT:    v_xor_b32_e32 v0, 0x8000, v23263; GFX11-SAFE-NEXT:    s_setpc_b64 s[30:31]3264;3265; GFX11-NSZ-LABEL: v_fneg_fmad_f16:3266; GFX11-NSZ:       ; %bb.0:3267; GFX11-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3268; GFX11-NSZ-NEXT:    v_fma_f16 v0, v0, -v1, -v23269; GFX11-NSZ-NEXT:    s_setpc_b64 s[30:31]3270; GFX11-SAFE-TRUE16-LABEL: v_fneg_fmad_f16:3271; GFX11-SAFE-TRUE16:       ; %bb.0:3272; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3273; GFX11-SAFE-TRUE16-NEXT:    v_fmac_f16_e32 v2.l, v0.l, v1.l3274; GFX11-SAFE-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)3275; GFX11-SAFE-TRUE16-NEXT:    v_xor_b16 v0.l, 0x8000, v2.l3276; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]3277; GFX11-NSZ-TRUE16-LABEL: v_fneg_fmad_f16:3278; GFX11-NSZ-TRUE16:       ; %bb.0:3279; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3280; GFX11-NSZ-TRUE16-NEXT:    v_fma_f16 v0.l, v0.l, -v1.l, -v2.l3281; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]3282  %fma = call half @llvm.fmuladd.f16(half %a, half %b, half %c)3283  %fneg = fneg half %fma3284  ret half %fneg3285}3286 3287define <4 x half> @v_fneg_fmad_v4f32(<4 x half> %a, <4 x half> %b, <4 x half> %c) #0 {3288; SI-SAFE-LABEL: v_fneg_fmad_v4f32:3289; SI-SAFE:       ; %bb.0:3290; SI-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3291; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v8, v83292; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v4, v43293; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v9, v93294; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v0, v03295; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v5, v53296; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v10, v103297; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v6, v63298; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v1, v13299; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v11, v113300; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v7, v73301; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v3, v33302; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v2, v23303; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v8, v83304; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v4, v43305; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v9, v93306; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v5, v53307; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v10, v103308; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v6, v63309; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v11, v113310; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v7, v73311; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v3, v33312; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v2, v23313; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v1, v13314; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v0, v03315; SI-SAFE-NEXT:    v_mac_f32_e32 v11, v3, v73316; SI-SAFE-NEXT:    v_mac_f32_e32 v10, v2, v63317; SI-SAFE-NEXT:    v_mac_f32_e32 v9, v1, v53318; SI-SAFE-NEXT:    v_mac_f32_e32 v8, v0, v43319; SI-SAFE-NEXT:    v_xor_b32_e32 v0, 0x80000000, v83320; SI-SAFE-NEXT:    v_xor_b32_e32 v1, 0x80000000, v93321; SI-SAFE-NEXT:    v_xor_b32_e32 v2, 0x80000000, v103322; SI-SAFE-NEXT:    v_xor_b32_e32 v3, 0x80000000, v113323; SI-SAFE-NEXT:    s_setpc_b64 s[30:31]3324;3325; SI-NSZ-LABEL: v_fneg_fmad_v4f32:3326; SI-NSZ:       ; %bb.0:3327; SI-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3328; SI-NSZ-NEXT:    v_cvt_f16_f32_e32 v11, v113329; SI-NSZ-NEXT:    v_cvt_f16_f32_e32 v3, v33330; SI-NSZ-NEXT:    v_cvt_f16_f32_e32 v10, v103331; SI-NSZ-NEXT:    v_cvt_f16_f32_e32 v7, v73332; SI-NSZ-NEXT:    v_cvt_f16_f32_e32 v2, v23333; SI-NSZ-NEXT:    v_cvt_f16_f32_e32 v9, v93334; SI-NSZ-NEXT:    v_cvt_f16_f32_e32 v1, v13335; SI-NSZ-NEXT:    v_cvt_f16_f32_e32 v6, v63336; SI-NSZ-NEXT:    v_cvt_f16_f32_e32 v8, v83337; SI-NSZ-NEXT:    v_cvt_f16_f32_e32 v0, v03338; SI-NSZ-NEXT:    v_cvt_f16_f32_e32 v4, v43339; SI-NSZ-NEXT:    v_cvt_f16_f32_e32 v5, v53340; SI-NSZ-NEXT:    v_cvt_f32_f16_e32 v11, v113341; SI-NSZ-NEXT:    v_cvt_f32_f16_e32 v3, v33342; SI-NSZ-NEXT:    v_cvt_f32_f16_e32 v10, v103343; SI-NSZ-NEXT:    v_cvt_f32_f16_e32 v2, v23344; SI-NSZ-NEXT:    v_cvt_f32_f16_e32 v9, v93345; SI-NSZ-NEXT:    v_cvt_f32_f16_e32 v1, v13346; SI-NSZ-NEXT:    v_cvt_f32_f16_e32 v8, v83347; SI-NSZ-NEXT:    v_cvt_f32_f16_e32 v0, v03348; SI-NSZ-NEXT:    v_cvt_f32_f16_e64 v4, -v43349; SI-NSZ-NEXT:    v_cvt_f32_f16_e64 v5, -v53350; SI-NSZ-NEXT:    v_cvt_f32_f16_e64 v6, -v63351; SI-NSZ-NEXT:    v_cvt_f32_f16_e64 v7, -v73352; SI-NSZ-NEXT:    v_mad_f32 v0, v0, v4, -v83353; SI-NSZ-NEXT:    v_mad_f32 v1, v1, v5, -v93354; SI-NSZ-NEXT:    v_mad_f32 v2, v2, v6, -v103355; SI-NSZ-NEXT:    v_mad_f32 v3, v3, v7, -v113356; SI-NSZ-NEXT:    s_setpc_b64 s[30:31]3357;3358; VI-SAFE-LABEL: v_fneg_fmad_v4f32:3359; VI-SAFE:       ; %bb.0:3360; VI-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3361; VI-SAFE-NEXT:    v_lshrrev_b32_e32 v6, 16, v53362; VI-SAFE-NEXT:    v_lshrrev_b32_e32 v7, 16, v33363; VI-SAFE-NEXT:    v_lshrrev_b32_e32 v8, 16, v13364; VI-SAFE-NEXT:    v_fma_f16 v6, v8, v7, v63365; VI-SAFE-NEXT:    v_lshrrev_b32_e32 v7, 16, v43366; VI-SAFE-NEXT:    v_lshrrev_b32_e32 v8, 16, v23367; VI-SAFE-NEXT:    v_lshrrev_b32_e32 v9, 16, v03368; VI-SAFE-NEXT:    v_fma_f16 v7, v9, v8, v73369; VI-SAFE-NEXT:    v_fma_f16 v0, v0, v2, v43370; VI-SAFE-NEXT:    v_lshlrev_b32_e32 v2, 16, v73371; VI-SAFE-NEXT:    v_fma_f16 v1, v1, v3, v53372; VI-SAFE-NEXT:    v_or_b32_e32 v0, v0, v23373; VI-SAFE-NEXT:    v_lshlrev_b32_e32 v2, 16, v63374; VI-SAFE-NEXT:    v_or_b32_e32 v1, v1, v23375; VI-SAFE-NEXT:    v_xor_b32_e32 v0, 0x80008000, v03376; VI-SAFE-NEXT:    v_xor_b32_e32 v1, 0x80008000, v13377; VI-SAFE-NEXT:    s_setpc_b64 s[30:31]3378;3379; VI-NSZ-LABEL: v_fneg_fmad_v4f32:3380; VI-NSZ:       ; %bb.0:3381; VI-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3382; VI-NSZ-NEXT:    v_lshrrev_b32_e32 v6, 16, v53383; VI-NSZ-NEXT:    v_lshrrev_b32_e32 v7, 16, v33384; VI-NSZ-NEXT:    v_lshrrev_b32_e32 v8, 16, v13385; VI-NSZ-NEXT:    v_fma_f16 v6, v8, -v7, -v63386; VI-NSZ-NEXT:    v_lshrrev_b32_e32 v7, 16, v43387; VI-NSZ-NEXT:    v_lshrrev_b32_e32 v8, 16, v23388; VI-NSZ-NEXT:    v_lshrrev_b32_e32 v9, 16, v03389; VI-NSZ-NEXT:    v_fma_f16 v7, v9, -v8, -v73390; VI-NSZ-NEXT:    v_fma_f16 v0, v0, -v2, -v43391; VI-NSZ-NEXT:    v_lshlrev_b32_e32 v2, 16, v73392; VI-NSZ-NEXT:    v_fma_f16 v1, v1, -v3, -v53393; VI-NSZ-NEXT:    v_or_b32_e32 v0, v0, v23394; VI-NSZ-NEXT:    v_lshlrev_b32_e32 v2, 16, v63395; VI-NSZ-NEXT:    v_or_b32_e32 v1, v1, v23396; VI-NSZ-NEXT:    s_setpc_b64 s[30:31]3397;3398; GFX11-SAFE-LABEL: v_fneg_fmad_v4f32:3399; GFX11-SAFE:       ; %bb.0:3400; GFX11-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3401; GFX11-SAFE-NEXT:    v_pk_fma_f16 v0, v0, v2, v43402; GFX11-SAFE-NEXT:    v_pk_fma_f16 v1, v1, v3, v53403; GFX11-SAFE-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)3404; GFX11-SAFE-NEXT:    v_xor_b32_e32 v0, 0x80008000, v03405; GFX11-SAFE-NEXT:    v_xor_b32_e32 v1, 0x80008000, v13406; GFX11-SAFE-NEXT:    s_setpc_b64 s[30:31]3407;3408; GFX11-NSZ-LABEL: v_fneg_fmad_v4f32:3409; GFX11-NSZ:       ; %bb.0:3410; GFX11-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3411; GFX11-NSZ-NEXT:    v_pk_fma_f16 v0, v0, v2, v4 neg_lo:[0,1,1] neg_hi:[0,1,1]3412; GFX11-NSZ-NEXT:    v_pk_fma_f16 v1, v1, v3, v5 neg_lo:[0,1,1] neg_hi:[0,1,1]3413; GFX11-NSZ-NEXT:    s_setpc_b64 s[30:31]3414  %fma = call <4 x half> @llvm.fmuladd.v4f16(<4 x half> %a, <4 x half> %b, <4 x half> %c)3415  %fneg = fneg <4 x half> %fma3416  ret <4 x half> %fneg3417}3418 3419define { half, half } @v_fneg_fmad_multi_use_fmad_f16(half %a, half %b, half %c) #0 {3420; SI-SAFE-LABEL: v_fneg_fmad_multi_use_fmad_f16:3421; SI-SAFE:       ; %bb.0:3422; SI-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3423; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v2, v23424; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v1, v13425; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v0, v03426; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v2, v23427; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v1, v13428; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v0, v03429; SI-SAFE-NEXT:    v_mac_f32_e32 v2, v0, v13430; SI-SAFE-NEXT:    v_xor_b32_e32 v0, 0x80000000, v23431; SI-SAFE-NEXT:    v_mul_f32_e32 v1, 4.0, v23432; SI-SAFE-NEXT:    s_setpc_b64 s[30:31]3433;3434; SI-NSZ-LABEL: v_fneg_fmad_multi_use_fmad_f16:3435; SI-NSZ:       ; %bb.0:3436; SI-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3437; SI-NSZ-NEXT:    v_cvt_f16_f32_e32 v2, v23438; SI-NSZ-NEXT:    v_cvt_f16_f32_e32 v0, v03439; SI-NSZ-NEXT:    v_cvt_f16_f32_e32 v1, v13440; SI-NSZ-NEXT:    v_cvt_f32_f16_e32 v2, v23441; SI-NSZ-NEXT:    v_cvt_f32_f16_e32 v0, v03442; SI-NSZ-NEXT:    v_cvt_f32_f16_e64 v1, -v13443; SI-NSZ-NEXT:    v_mad_f32 v0, v0, v1, -v23444; SI-NSZ-NEXT:    v_mul_f32_e32 v1, -4.0, v03445; SI-NSZ-NEXT:    s_setpc_b64 s[30:31]3446;3447; VI-SAFE-LABEL: v_fneg_fmad_multi_use_fmad_f16:3448; VI-SAFE:       ; %bb.0:3449; VI-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3450; VI-SAFE-NEXT:    v_fma_f16 v1, v0, v1, v23451; VI-SAFE-NEXT:    v_xor_b32_e32 v0, 0x8000, v13452; VI-SAFE-NEXT:    v_mul_f16_e32 v1, 4.0, v13453; VI-SAFE-NEXT:    s_setpc_b64 s[30:31]3454;3455; VI-NSZ-LABEL: v_fneg_fmad_multi_use_fmad_f16:3456; VI-NSZ:       ; %bb.0:3457; VI-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3458; VI-NSZ-NEXT:    v_fma_f16 v0, v0, -v1, -v23459; VI-NSZ-NEXT:    v_mul_f16_e32 v1, -4.0, v03460; VI-NSZ-NEXT:    s_setpc_b64 s[30:31]3461;3462; GFX11-SAFE-LABEL: v_fneg_fmad_multi_use_fmad_f16:3463; GFX11-SAFE:       ; %bb.0:3464; GFX11-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3465; GFX11-SAFE-NEXT:    v_fmac_f16_e32 v2, v0, v13466; GFX11-SAFE-NEXT:    s_delay_alu instid0(VALU_DEP_1)3467; GFX11-SAFE-NEXT:    v_xor_b32_e32 v0, 0x8000, v23468; GFX11-SAFE-NEXT:    v_mul_f16_e32 v1, 4.0, v23469; GFX11-SAFE-NEXT:    s_setpc_b64 s[30:31]3470;3471; GFX11-NSZ-LABEL: v_fneg_fmad_multi_use_fmad_f16:3472; GFX11-NSZ:       ; %bb.0:3473; GFX11-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3474; GFX11-NSZ-NEXT:    v_fma_f16 v0, v0, -v1, -v23475; GFX11-NSZ-NEXT:    s_delay_alu instid0(VALU_DEP_1)3476; GFX11-NSZ-NEXT:    v_mul_f16_e32 v1, -4.0, v03477; GFX11-NSZ-NEXT:    s_setpc_b64 s[30:31]3478; GFX11-SAFE-TRUE16-LABEL: v_fneg_fmad_multi_use_fmad_f16:3479; GFX11-SAFE-TRUE16:       ; %bb.0:3480; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3481; GFX11-SAFE-TRUE16-NEXT:    v_fmac_f16_e32 v2.l, v0.l, v1.l3482; GFX11-SAFE-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)3483; GFX11-SAFE-TRUE16-NEXT:    v_xor_b16 v0.l, 0x8000, v2.l3484; GFX11-SAFE-TRUE16-NEXT:    v_mul_f16_e32 v1.l, 4.0, v2.l3485; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]3486; GFX11-NSZ-TRUE16-LABEL: v_fneg_fmad_multi_use_fmad_f16:3487; GFX11-NSZ-TRUE16:       ; %bb.0:3488; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3489; GFX11-NSZ-TRUE16-NEXT:    v_fma_f16 v0.l, v0.l, -v1.l, -v2.l3490; GFX11-NSZ-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)3491; GFX11-NSZ-TRUE16-NEXT:    v_mul_f16_e32 v1.l, -4.0, v0.l3492; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]3493  %fma = call half @llvm.fmuladd.f16(half %a, half %b, half %c)3494  %fneg = fneg half %fma3495  %use1 = fmul half %fma, 4.03496  %insert.0 = insertvalue { half, half } poison, half %fneg, 03497  %insert.1 = insertvalue { half, half } %insert.0, half %use1, 13498  ret { half, half } %insert.13499}3500 3501; --------------------------------------------------------------------------------3502; fp_extend tests3503; --------------------------------------------------------------------------------3504 3505define double @v_fneg_fp_extend_f16_to_f64(half %a) #0 {3506; SI-LABEL: v_fneg_fp_extend_f16_to_f64:3507; SI:       ; %bb.0:3508; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3509; SI-NEXT:    v_cvt_f64_f32_e64 v[0:1], -v03510; SI-NEXT:    s_setpc_b64 s[30:31]3511;3512; VI-LABEL: v_fneg_fp_extend_f16_to_f64:3513; VI:       ; %bb.0:3514; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3515; VI-NEXT:    v_xor_b32_e32 v0, 0x8000, v03516; VI-NEXT:    v_cvt_f32_f16_e32 v0, v03517; VI-NEXT:    v_cvt_f64_f32_e32 v[0:1], v03518; VI-NEXT:    s_setpc_b64 s[30:31]3519;3520; GFX11-LABEL: v_fneg_fp_extend_f16_to_f64:3521; GFX11:       ; %bb.0:3522; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3523; GFX11-NEXT:    v_xor_b32_e32 v0, 0x8000, v03524; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)3525; GFX11-NEXT:    v_cvt_f32_f16_e32 v0, v03526; GFX11-NEXT:    v_cvt_f64_f32_e32 v[0:1], v03527; GFX11-NEXT:    s_setpc_b64 s[30:31]3528; GFX11-SAFE-TRUE16-LABEL: v_fneg_fp_extend_f16_to_f64:3529; GFX11-SAFE-TRUE16:       ; %bb.0:3530; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3531; GFX11-SAFE-TRUE16-NEXT:    v_xor_b16 v0.l, 0x8000, v0.l3532; GFX11-SAFE-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)3533; GFX11-SAFE-TRUE16-NEXT:    v_cvt_f32_f16_e32 v0, v0.l3534; GFX11-SAFE-TRUE16-NEXT:    v_cvt_f64_f32_e32 v[0:1], v03535; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]3536; GFX11-NSZ-TRUE16-LABEL: v_fneg_fp_extend_f16_to_f64:3537; GFX11-NSZ-TRUE16:       ; %bb.0:3538; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3539; GFX11-NSZ-TRUE16-NEXT:    v_xor_b16 v0.l, 0x8000, v0.l3540; GFX11-NSZ-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)3541; GFX11-NSZ-TRUE16-NEXT:    v_cvt_f32_f16_e32 v0, v0.l3542; GFX11-NSZ-TRUE16-NEXT:    v_cvt_f64_f32_e32 v[0:1], v03543; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]3544  %fpext = fpext half %a to double3545  %fneg = fneg double %fpext3546  ret double %fneg3547}3548 3549define double @v_fneg_fp_extend_fneg_f16_to_f64(half %a) #0 {3550; SI-LABEL: v_fneg_fp_extend_fneg_f16_to_f64:3551; SI:       ; %bb.0:3552; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3553; SI-NEXT:    v_cvt_f64_f32_e32 v[0:1], v03554; SI-NEXT:    s_setpc_b64 s[30:31]3555;3556; VI-LABEL: v_fneg_fp_extend_fneg_f16_to_f64:3557; VI:       ; %bb.0:3558; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3559; VI-NEXT:    v_cvt_f32_f16_e32 v0, v03560; VI-NEXT:    v_cvt_f64_f32_e32 v[0:1], v03561; VI-NEXT:    s_setpc_b64 s[30:31]3562;3563; GFX11-LABEL: v_fneg_fp_extend_fneg_f16_to_f64:3564; GFX11:       ; %bb.0:3565; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3566; GFX11-NEXT:    v_cvt_f32_f16_e32 v0, v03567; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)3568; GFX11-NEXT:    v_cvt_f64_f32_e32 v[0:1], v03569; GFX11-NEXT:    s_setpc_b64 s[30:31]3570; GFX11-SAFE-TRUE16-LABEL: v_fneg_fp_extend_fneg_f16_to_f64:3571; GFX11-SAFE-TRUE16:       ; %bb.0:3572; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3573; GFX11-SAFE-TRUE16-NEXT:    v_cvt_f32_f16_e32 v0, v0.l3574; GFX11-SAFE-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)3575; GFX11-SAFE-TRUE16-NEXT:    v_cvt_f64_f32_e32 v[0:1], v03576; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]3577; GFX11-NSZ-TRUE16-LABEL: v_fneg_fp_extend_fneg_f16_to_f64:3578; GFX11-NSZ-TRUE16:       ; %bb.0:3579; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3580; GFX11-NSZ-TRUE16-NEXT:    v_cvt_f32_f16_e32 v0, v0.l3581; GFX11-NSZ-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)3582; GFX11-NSZ-TRUE16-NEXT:    v_cvt_f64_f32_e32 v[0:1], v03583; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]3584  %fneg.a = fneg half %a3585  %fpext = fpext half %fneg.a to double3586  %fneg = fneg double %fpext3587  ret double %fneg3588}3589 3590define { double, half } @v_fneg_fp_extend_store_use_fneg_f16_to_f64(half %a) #0 {3591; SI-LABEL: v_fneg_fp_extend_store_use_fneg_f16_to_f64:3592; SI:       ; %bb.0:3593; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3594; SI-NEXT:    v_mov_b32_e32 v2, v03595; SI-NEXT:    v_cvt_f64_f32_e32 v[0:1], v23596; SI-NEXT:    v_xor_b32_e32 v2, 0x80000000, v23597; SI-NEXT:    s_setpc_b64 s[30:31]3598;3599; VI-LABEL: v_fneg_fp_extend_store_use_fneg_f16_to_f64:3600; VI:       ; %bb.0:3601; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3602; VI-NEXT:    v_mov_b32_e32 v2, v03603; VI-NEXT:    v_cvt_f32_f16_e32 v0, v23604; VI-NEXT:    v_xor_b32_e32 v2, 0x8000, v23605; VI-NEXT:    v_cvt_f64_f32_e32 v[0:1], v03606; VI-NEXT:    s_setpc_b64 s[30:31]3607;3608; GFX11-LABEL: v_fneg_fp_extend_store_use_fneg_f16_to_f64:3609; GFX11:       ; %bb.0:3610; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3611; GFX11-NEXT:    v_mov_b32_e32 v2, v03612; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)3613; GFX11-NEXT:    v_cvt_f32_f16_e32 v0, v23614; GFX11-NEXT:    v_xor_b32_e32 v2, 0x8000, v23615; GFX11-NEXT:    v_cvt_f64_f32_e32 v[0:1], v03616; GFX11-NEXT:    s_setpc_b64 s[30:31]3617; GFX11-SAFE-TRUE16-LABEL: v_fneg_fp_extend_store_use_fneg_f16_to_f64:3618; GFX11-SAFE-TRUE16:       ; %bb.0:3619; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3620; GFX11-SAFE-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v0.l3621; GFX11-SAFE-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)3622; GFX11-SAFE-TRUE16-NEXT:    v_cvt_f32_f16_e32 v0, v2.l3623; GFX11-SAFE-TRUE16-NEXT:    v_xor_b16 v2.l, 0x8000, v2.l3624; GFX11-SAFE-TRUE16-NEXT:    v_cvt_f64_f32_e32 v[0:1], v03625; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]3626; GFX11-NSZ-TRUE16-LABEL: v_fneg_fp_extend_store_use_fneg_f16_to_f64:3627; GFX11-NSZ-TRUE16:       ; %bb.0:3628; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3629; GFX11-NSZ-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v0.l3630; GFX11-NSZ-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)3631; GFX11-NSZ-TRUE16-NEXT:    v_cvt_f32_f16_e32 v0, v2.l3632; GFX11-NSZ-TRUE16-NEXT:    v_xor_b16 v2.l, 0x8000, v2.l3633; GFX11-NSZ-TRUE16-NEXT:    v_cvt_f64_f32_e32 v[0:1], v03634; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]3635  %fneg.a = fneg half %a3636  %fpext = fpext half %fneg.a to double3637  %fneg = fneg double %fpext3638  %insert.0 = insertvalue { double, half } poison, double %fneg, 03639  %insert.1 = insertvalue { double, half } %insert.0, half %fneg.a, 13640  ret { double, half } %insert.13641}3642 3643define { double, double } @v_fneg_multi_use_fp_extend_fneg_f16_to_f64(half %a) #0 {3644; SI-LABEL: v_fneg_multi_use_fp_extend_fneg_f16_to_f64:3645; SI:       ; %bb.0:3646; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3647; SI-NEXT:    v_cvt_f64_f32_e32 v[2:3], v03648; SI-NEXT:    v_xor_b32_e32 v1, 0x80000000, v33649; SI-NEXT:    v_mov_b32_e32 v0, v23650; SI-NEXT:    s_setpc_b64 s[30:31]3651;3652; VI-LABEL: v_fneg_multi_use_fp_extend_fneg_f16_to_f64:3653; VI:       ; %bb.0:3654; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3655; VI-NEXT:    v_cvt_f32_f16_e32 v0, v03656; VI-NEXT:    v_cvt_f64_f32_e32 v[2:3], v03657; VI-NEXT:    v_xor_b32_e32 v1, 0x80000000, v33658; VI-NEXT:    v_mov_b32_e32 v0, v23659; VI-NEXT:    s_setpc_b64 s[30:31]3660;3661; GFX11-LABEL: v_fneg_multi_use_fp_extend_fneg_f16_to_f64:3662; GFX11:       ; %bb.0:3663; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3664; GFX11-NEXT:    v_cvt_f32_f16_e32 v0, v03665; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)3666; GFX11-NEXT:    v_cvt_f64_f32_e32 v[2:3], v03667; GFX11-NEXT:    v_xor_b32_e32 v1, 0x80000000, v33668; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)3669; GFX11-NEXT:    v_mov_b32_e32 v0, v23670; GFX11-NEXT:    s_setpc_b64 s[30:31]3671; GFX11-SAFE-TRUE16-LABEL: v_fneg_multi_use_fp_extend_fneg_f16_to_f64:3672; GFX11-SAFE-TRUE16:       ; %bb.0:3673; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3674; GFX11-SAFE-TRUE16-NEXT:    v_cvt_f32_f16_e32 v0, v0.l3675; GFX11-SAFE-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)3676; GFX11-SAFE-TRUE16-NEXT:    v_cvt_f64_f32_e32 v[2:3], v03677; GFX11-SAFE-TRUE16-NEXT:    v_xor_b32_e32 v1, 0x80000000, v33678; GFX11-SAFE-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)3679; GFX11-SAFE-TRUE16-NEXT:    v_mov_b32_e32 v0, v23680; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]3681; GFX11-NSZ-TRUE16-LABEL: v_fneg_multi_use_fp_extend_fneg_f16_to_f64:3682; GFX11-NSZ-TRUE16:       ; %bb.0:3683; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3684; GFX11-NSZ-TRUE16-NEXT:    v_cvt_f32_f16_e32 v0, v0.l3685; GFX11-NSZ-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)3686; GFX11-NSZ-TRUE16-NEXT:    v_cvt_f64_f32_e32 v[2:3], v03687; GFX11-NSZ-TRUE16-NEXT:    v_xor_b32_e32 v1, 0x80000000, v33688; GFX11-NSZ-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)3689; GFX11-NSZ-TRUE16-NEXT:    v_mov_b32_e32 v0, v23690; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]3691  %fpext = fpext half %a to double3692  %fneg = fneg double %fpext3693  %insert.0 = insertvalue { double, double } poison, double %fneg, 03694  %insert.1 = insertvalue { double, double } %insert.0, double %fpext, 13695  ret { double, double } %insert.13696}3697 3698define { double, double } @v_fneg_multi_foldable_use_fp_extend_fneg_f16_to_f64(half %a) #0 {3699; SI-LABEL: v_fneg_multi_foldable_use_fp_extend_fneg_f16_to_f64:3700; SI:       ; %bb.0:3701; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3702; SI-NEXT:    v_cvt_f64_f32_e32 v[0:1], v03703; SI-NEXT:    v_xor_b32_e32 v4, 0x80000000, v13704; SI-NEXT:    v_mul_f64 v[2:3], v[0:1], 4.03705; SI-NEXT:    v_mov_b32_e32 v1, v43706; SI-NEXT:    s_setpc_b64 s[30:31]3707;3708; VI-LABEL: v_fneg_multi_foldable_use_fp_extend_fneg_f16_to_f64:3709; VI:       ; %bb.0:3710; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3711; VI-NEXT:    v_cvt_f32_f16_e32 v0, v03712; VI-NEXT:    v_cvt_f64_f32_e32 v[0:1], v03713; VI-NEXT:    v_mul_f64 v[2:3], v[0:1], 4.03714; VI-NEXT:    v_xor_b32_e32 v1, 0x80000000, v13715; VI-NEXT:    s_setpc_b64 s[30:31]3716;3717; GFX11-LABEL: v_fneg_multi_foldable_use_fp_extend_fneg_f16_to_f64:3718; GFX11:       ; %bb.0:3719; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3720; GFX11-NEXT:    v_cvt_f32_f16_e32 v0, v03721; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)3722; GFX11-NEXT:    v_cvt_f64_f32_e32 v[0:1], v03723; GFX11-NEXT:    v_mul_f64 v[2:3], v[0:1], 4.03724; GFX11-NEXT:    v_xor_b32_e32 v1, 0x80000000, v13725; GFX11-NEXT:    s_setpc_b64 s[30:31]3726; GFX11-SAFE-TRUE16-LABEL: v_fneg_multi_foldable_use_fp_extend_fneg_f16_to_f64:3727; GFX11-SAFE-TRUE16:       ; %bb.0:3728; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3729; GFX11-SAFE-TRUE16-NEXT:    v_cvt_f32_f16_e32 v0, v0.l3730; GFX11-SAFE-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)3731; GFX11-SAFE-TRUE16-NEXT:    v_cvt_f64_f32_e32 v[0:1], v03732; GFX11-SAFE-TRUE16-NEXT:    v_mul_f64 v[2:3], v[0:1], 4.03733; GFX11-SAFE-TRUE16-NEXT:    v_xor_b32_e32 v1, 0x80000000, v13734; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]3735; GFX11-NSZ-TRUE16-LABEL: v_fneg_multi_foldable_use_fp_extend_fneg_f16_to_f64:3736; GFX11-NSZ-TRUE16:       ; %bb.0:3737; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3738; GFX11-NSZ-TRUE16-NEXT:    v_cvt_f32_f16_e32 v0, v0.l3739; GFX11-NSZ-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)3740; GFX11-NSZ-TRUE16-NEXT:    v_cvt_f64_f32_e32 v[0:1], v03741; GFX11-NSZ-TRUE16-NEXT:    v_mul_f64 v[2:3], v[0:1], 4.03742; GFX11-NSZ-TRUE16-NEXT:    v_xor_b32_e32 v1, 0x80000000, v13743; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]3744  %fpext = fpext half %a to double3745  %fneg = fneg double %fpext3746  %mul = fmul double %fpext, 4.03747  %insert.0 = insertvalue { double, double } poison, double %fneg, 03748  %insert.1 = insertvalue { double, double } %insert.0, double %mul, 13749  ret { double, double } %insert.13750}3751 3752define { float, float } @v_fneg_multi_use_fp_extend_fneg_f16_to_f32(half %a) #0 {3753; SI-LABEL: v_fneg_multi_use_fp_extend_fneg_f16_to_f32:3754; SI:       ; %bb.0:3755; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3756; SI-NEXT:    v_mov_b32_e32 v1, v03757; SI-NEXT:    v_xor_b32_e32 v0, 0x80000000, v13758; SI-NEXT:    s_setpc_b64 s[30:31]3759;3760; VI-LABEL: v_fneg_multi_use_fp_extend_fneg_f16_to_f32:3761; VI:       ; %bb.0:3762; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3763; VI-NEXT:    v_cvt_f32_f16_e32 v1, v03764; VI-NEXT:    v_xor_b32_e32 v0, 0x80000000, v13765; VI-NEXT:    s_setpc_b64 s[30:31]3766;3767; GFX11-LABEL: v_fneg_multi_use_fp_extend_fneg_f16_to_f32:3768; GFX11:       ; %bb.0:3769; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3770; GFX11-NEXT:    v_cvt_f32_f16_e32 v1, v03771; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)3772; GFX11-NEXT:    v_xor_b32_e32 v0, 0x80000000, v13773; GFX11-NEXT:    s_setpc_b64 s[30:31]3774; GFX11-SAFE-TRUE16-LABEL: v_fneg_multi_use_fp_extend_fneg_f16_to_f32:3775; GFX11-SAFE-TRUE16:       ; %bb.0:3776; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3777; GFX11-SAFE-TRUE16-NEXT:    v_cvt_f32_f16_e32 v1, v0.l3778; GFX11-SAFE-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)3779; GFX11-SAFE-TRUE16-NEXT:    v_xor_b32_e32 v0, 0x80000000, v13780; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]3781; GFX11-NSZ-TRUE16-LABEL: v_fneg_multi_use_fp_extend_fneg_f16_to_f32:3782; GFX11-NSZ-TRUE16:       ; %bb.0:3783; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3784; GFX11-NSZ-TRUE16-NEXT:    v_cvt_f32_f16_e32 v1, v0.l3785; GFX11-NSZ-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)3786; GFX11-NSZ-TRUE16-NEXT:    v_xor_b32_e32 v0, 0x80000000, v13787; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]3788  %fpext = fpext half %a to float3789  %fneg = fneg float %fpext3790  %insert.0 = insertvalue { float, float } poison, float %fneg, 03791  %insert.1 = insertvalue { float, float } %insert.0, float %fpext, 13792  ret { float, float } %insert.13793}3794 3795; --------------------------------------------------------------------------------3796; fp_round tests3797; --------------------------------------------------------------------------------3798 3799define half @v_fneg_fp_round_f64_to_f16(double %a) #0 {3800; SI-LABEL: v_fneg_fp_round_f64_to_f16:3801; SI:       ; %bb.0:3802; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3803; SI-NEXT:    v_xor_b32_e32 v1, 0x80000000, v13804; SI-NEXT:    v_and_b32_e32 v2, 0x1ff, v13805; SI-NEXT:    v_or_b32_e32 v0, v2, v03806; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v03807; SI-NEXT:    v_lshrrev_b32_e32 v2, 8, v13808; SI-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc3809; SI-NEXT:    v_and_b32_e32 v2, 0xffe, v23810; SI-NEXT:    v_bfe_u32 v3, v1, 20, 113811; SI-NEXT:    s_movk_i32 s4, 0x3f13812; SI-NEXT:    v_or_b32_e32 v0, v2, v03813; SI-NEXT:    v_sub_i32_e32 v4, vcc, s4, v33814; SI-NEXT:    v_or_b32_e32 v2, 0x1000, v03815; SI-NEXT:    v_med3_i32 v4, v4, 0, 133816; SI-NEXT:    v_lshrrev_b32_e32 v5, v4, v23817; SI-NEXT:    v_lshlrev_b32_e32 v4, v4, v53818; SI-NEXT:    v_cmp_ne_u32_e32 vcc, v4, v23819; SI-NEXT:    s_movk_i32 s4, 0xfc103820; SI-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc3821; SI-NEXT:    v_add_i32_e32 v3, vcc, s4, v33822; SI-NEXT:    v_lshlrev_b32_e32 v4, 12, v33823; SI-NEXT:    v_or_b32_e32 v2, v5, v23824; SI-NEXT:    v_or_b32_e32 v4, v0, v43825; SI-NEXT:    v_cmp_gt_i32_e32 vcc, 1, v33826; SI-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc3827; SI-NEXT:    v_and_b32_e32 v4, 7, v23828; SI-NEXT:    v_cmp_lt_i32_e32 vcc, 5, v43829; SI-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc3830; SI-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v43831; SI-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc3832; SI-NEXT:    v_or_b32_e32 v4, v4, v53833; SI-NEXT:    v_lshrrev_b32_e32 v2, 2, v23834; SI-NEXT:    v_add_i32_e32 v2, vcc, v2, v43835; SI-NEXT:    v_mov_b32_e32 v4, 0x7c003836; SI-NEXT:    v_cmp_gt_i32_e32 vcc, 31, v33837; SI-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc3838; SI-NEXT:    v_mov_b32_e32 v5, 0x7e003839; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v03840; SI-NEXT:    s_movk_i32 s4, 0x40f3841; SI-NEXT:    v_cndmask_b32_e32 v0, v4, v5, vcc3842; SI-NEXT:    v_cmp_eq_u32_e32 vcc, s4, v33843; SI-NEXT:    v_lshrrev_b32_e32 v1, 16, v13844; SI-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc3845; SI-NEXT:    v_and_b32_e32 v1, 0x8000, v13846; SI-NEXT:    v_or_b32_e32 v0, v1, v03847; SI-NEXT:    v_cvt_f32_f16_e32 v0, v03848; SI-NEXT:    s_setpc_b64 s[30:31]3849;3850; VI-LABEL: v_fneg_fp_round_f64_to_f16:3851; VI:       ; %bb.0:3852; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3853; VI-NEXT:    v_xor_b32_e32 v1, 0x80000000, v13854; VI-NEXT:    v_and_b32_e32 v2, 0x1ff, v13855; VI-NEXT:    v_or_b32_e32 v0, v2, v03856; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v03857; VI-NEXT:    v_lshrrev_b32_e32 v2, 8, v13858; VI-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc3859; VI-NEXT:    v_and_b32_e32 v2, 0xffe, v23860; VI-NEXT:    v_bfe_u32 v3, v1, 20, 113861; VI-NEXT:    s_movk_i32 s4, 0x3f13862; VI-NEXT:    v_or_b32_e32 v0, v2, v03863; VI-NEXT:    v_sub_u32_e32 v4, vcc, s4, v33864; VI-NEXT:    v_or_b32_e32 v2, 0x1000, v03865; VI-NEXT:    v_med3_i32 v4, v4, 0, 133866; VI-NEXT:    v_lshrrev_b32_e32 v5, v4, v23867; VI-NEXT:    v_lshlrev_b32_e32 v4, v4, v53868; VI-NEXT:    v_cmp_ne_u32_e32 vcc, v4, v23869; VI-NEXT:    s_movk_i32 s4, 0xfc103870; VI-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc3871; VI-NEXT:    v_add_u32_e32 v3, vcc, s4, v33872; VI-NEXT:    v_lshlrev_b32_e32 v4, 12, v33873; VI-NEXT:    v_or_b32_e32 v2, v5, v23874; VI-NEXT:    v_or_b32_e32 v4, v0, v43875; VI-NEXT:    v_cmp_gt_i32_e32 vcc, 1, v33876; VI-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc3877; VI-NEXT:    v_and_b32_e32 v4, 7, v23878; VI-NEXT:    v_cmp_lt_i32_e32 vcc, 5, v43879; VI-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc3880; VI-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v43881; VI-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc3882; VI-NEXT:    v_or_b32_e32 v4, v4, v53883; VI-NEXT:    v_lshrrev_b32_e32 v2, 2, v23884; VI-NEXT:    v_add_u32_e32 v2, vcc, v2, v43885; VI-NEXT:    v_mov_b32_e32 v4, 0x7c003886; VI-NEXT:    v_cmp_gt_i32_e32 vcc, 31, v33887; VI-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc3888; VI-NEXT:    v_mov_b32_e32 v5, 0x7e003889; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v03890; VI-NEXT:    s_movk_i32 s4, 0x40f3891; VI-NEXT:    v_cndmask_b32_e32 v0, v4, v5, vcc3892; VI-NEXT:    v_cmp_eq_u32_e32 vcc, s4, v33893; VI-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc3894; VI-NEXT:    v_mov_b32_e32 v2, 0x80003895; VI-NEXT:    v_and_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3896; VI-NEXT:    v_or_b32_e32 v0, v1, v03897; VI-NEXT:    s_setpc_b64 s[30:31]3898;3899; GFX11-LABEL: v_fneg_fp_round_f64_to_f16:3900; GFX11:       ; %bb.0:3901; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3902; GFX11-NEXT:    v_xor_b32_e32 v1, 0x80000000, v13903; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)3904; GFX11-NEXT:    v_and_or_b32 v0, 0x1ff, v1, v03905; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 8, v13906; GFX11-NEXT:    v_bfe_u32 v3, v1, 20, 113907; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 16, v13908; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v03909; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)3910; GFX11-NEXT:    v_sub_nc_u32_e32 v4, 0x3f1, v33911; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo3912; GFX11-NEXT:    v_and_or_b32 v0, 0xffe, v2, v03913; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)3914; GFX11-NEXT:    v_med3_i32 v2, v4, 0, 133915; GFX11-NEXT:    v_or_b32_e32 v4, 0x1000, v03916; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)3917; GFX11-NEXT:    v_lshrrev_b32_e32 v5, v2, v43918; GFX11-NEXT:    v_lshlrev_b32_e32 v2, v2, v53919; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)3920; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, v2, v43921; GFX11-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc_lo3922; GFX11-NEXT:    v_or_b32_e32 v2, v5, v23923; GFX11-NEXT:    v_add_nc_u32_e32 v3, 0xfffffc10, v33924; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)3925; GFX11-NEXT:    v_lshl_or_b32 v4, v3, 12, v03926; GFX11-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 1, v33927; GFX11-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc_lo3928; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)3929; GFX11-NEXT:    v_and_b32_e32 v4, 7, v23930; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 2, v23931; GFX11-NEXT:    v_cmp_lt_i32_e32 vcc_lo, 5, v43932; GFX11-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc_lo3933; GFX11-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 3, v43934; GFX11-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc_lo3935; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v03936; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)3937; GFX11-NEXT:    v_or_b32_e32 v4, v4, v53938; GFX11-NEXT:    v_dual_mov_b32 v5, 0x7e00 :: v_dual_add_nc_u32 v2, v2, v43939; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)3940; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7c00, v5, vcc_lo3941; GFX11-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 31, v33942; GFX11-NEXT:    v_cndmask_b32_e32 v2, 0x7c00, v2, vcc_lo3943; GFX11-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0x40f, v33944; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)3945; GFX11-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo3946; GFX11-NEXT:    v_and_or_b32 v0, 0x8000, v1, v03947; GFX11-NEXT:    s_setpc_b64 s[30:31]3948  %fpround = fptrunc double %a to half3949  %fneg = fneg half %fpround3950  ret half %fneg3951}3952 3953define half @v_fneg_fp_round_fneg_f64_to_f16(double %a) #0 {3954; SI-LABEL: v_fneg_fp_round_fneg_f64_to_f16:3955; SI:       ; %bb.0:3956; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3957; SI-NEXT:    v_and_b32_e32 v2, 0x1ff, v13958; SI-NEXT:    v_or_b32_e32 v0, v2, v03959; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v03960; SI-NEXT:    v_lshrrev_b32_e32 v2, 8, v13961; SI-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc3962; SI-NEXT:    v_and_b32_e32 v2, 0xffe, v23963; SI-NEXT:    v_bfe_u32 v3, v1, 20, 113964; SI-NEXT:    v_or_b32_e32 v0, v2, v03965; SI-NEXT:    v_sub_i32_e32 v4, vcc, 0x3f1, v33966; SI-NEXT:    v_or_b32_e32 v2, 0x1000, v03967; SI-NEXT:    v_med3_i32 v4, v4, 0, 133968; SI-NEXT:    v_lshrrev_b32_e32 v5, v4, v23969; SI-NEXT:    v_lshlrev_b32_e32 v4, v4, v53970; SI-NEXT:    v_cmp_ne_u32_e32 vcc, v4, v23971; SI-NEXT:    s_movk_i32 s4, 0xfc103972; SI-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc3973; SI-NEXT:    v_add_i32_e32 v3, vcc, s4, v33974; SI-NEXT:    v_lshlrev_b32_e32 v4, 12, v33975; SI-NEXT:    v_or_b32_e32 v2, v5, v23976; SI-NEXT:    v_or_b32_e32 v4, v0, v43977; SI-NEXT:    v_cmp_gt_i32_e32 vcc, 1, v33978; SI-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc3979; SI-NEXT:    v_and_b32_e32 v4, 7, v23980; SI-NEXT:    v_cmp_lt_i32_e32 vcc, 5, v43981; SI-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc3982; SI-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v43983; SI-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc3984; SI-NEXT:    v_or_b32_e32 v4, v4, v53985; SI-NEXT:    v_lshrrev_b32_e32 v2, 2, v23986; SI-NEXT:    v_add_i32_e32 v2, vcc, v2, v43987; SI-NEXT:    v_mov_b32_e32 v4, 0x7c003988; SI-NEXT:    v_cmp_gt_i32_e32 vcc, 31, v33989; SI-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc3990; SI-NEXT:    v_mov_b32_e32 v5, 0x7e003991; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v03992; SI-NEXT:    s_movk_i32 s4, 0x40f3993; SI-NEXT:    v_cndmask_b32_e32 v0, v4, v5, vcc3994; SI-NEXT:    v_cmp_eq_u32_e32 vcc, s4, v33995; SI-NEXT:    v_lshrrev_b32_e32 v1, 16, v13996; SI-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc3997; SI-NEXT:    v_and_b32_e32 v1, 0x8000, v13998; SI-NEXT:    v_or_b32_e32 v0, v1, v03999; SI-NEXT:    v_cvt_f32_f16_e32 v0, v04000; SI-NEXT:    s_setpc_b64 s[30:31]4001;4002; VI-LABEL: v_fneg_fp_round_fneg_f64_to_f16:4003; VI:       ; %bb.0:4004; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4005; VI-NEXT:    v_and_b32_e32 v2, 0x1ff, v14006; VI-NEXT:    v_or_b32_e32 v0, v2, v04007; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v04008; VI-NEXT:    v_lshrrev_b32_e32 v2, 8, v14009; VI-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc4010; VI-NEXT:    v_and_b32_e32 v2, 0xffe, v24011; VI-NEXT:    v_bfe_u32 v3, v1, 20, 114012; VI-NEXT:    v_or_b32_e32 v0, v2, v04013; VI-NEXT:    v_sub_u32_e32 v4, vcc, 0x3f1, v34014; VI-NEXT:    v_or_b32_e32 v2, 0x1000, v04015; VI-NEXT:    v_med3_i32 v4, v4, 0, 134016; VI-NEXT:    v_lshrrev_b32_e32 v5, v4, v24017; VI-NEXT:    v_lshlrev_b32_e32 v4, v4, v54018; VI-NEXT:    v_cmp_ne_u32_e32 vcc, v4, v24019; VI-NEXT:    s_movk_i32 s4, 0xfc104020; VI-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc4021; VI-NEXT:    v_add_u32_e32 v3, vcc, s4, v34022; VI-NEXT:    v_lshlrev_b32_e32 v4, 12, v34023; VI-NEXT:    v_or_b32_e32 v2, v5, v24024; VI-NEXT:    v_or_b32_e32 v4, v0, v44025; VI-NEXT:    v_cmp_gt_i32_e32 vcc, 1, v34026; VI-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc4027; VI-NEXT:    v_and_b32_e32 v4, 7, v24028; VI-NEXT:    v_cmp_lt_i32_e32 vcc, 5, v44029; VI-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc4030; VI-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v44031; VI-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc4032; VI-NEXT:    v_or_b32_e32 v4, v4, v54033; VI-NEXT:    v_lshrrev_b32_e32 v2, 2, v24034; VI-NEXT:    v_add_u32_e32 v2, vcc, v2, v44035; VI-NEXT:    v_mov_b32_e32 v4, 0x7c004036; VI-NEXT:    v_cmp_gt_i32_e32 vcc, 31, v34037; VI-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc4038; VI-NEXT:    v_mov_b32_e32 v5, 0x7e004039; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v04040; VI-NEXT:    s_movk_i32 s4, 0x40f4041; VI-NEXT:    v_cndmask_b32_e32 v0, v4, v5, vcc4042; VI-NEXT:    v_cmp_eq_u32_e32 vcc, s4, v34043; VI-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc4044; VI-NEXT:    v_mov_b32_e32 v2, 0x80004045; VI-NEXT:    v_and_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD4046; VI-NEXT:    v_or_b32_e32 v0, v1, v04047; VI-NEXT:    s_setpc_b64 s[30:31]4048;4049; GFX11-LABEL: v_fneg_fp_round_fneg_f64_to_f16:4050; GFX11:       ; %bb.0:4051; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4052; GFX11-NEXT:    v_and_or_b32 v0, 0x1ff, v1, v04053; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 8, v14054; GFX11-NEXT:    v_bfe_u32 v3, v1, 20, 114055; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 16, v14056; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)4057; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v04058; GFX11-NEXT:    v_sub_nc_u32_e32 v4, 0x3f1, v34059; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo4060; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)4061; GFX11-NEXT:    v_and_or_b32 v0, 0xffe, v2, v04062; GFX11-NEXT:    v_med3_i32 v2, v4, 0, 134063; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)4064; GFX11-NEXT:    v_or_b32_e32 v4, 0x1000, v04065; GFX11-NEXT:    v_lshrrev_b32_e32 v5, v2, v44066; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)4067; GFX11-NEXT:    v_lshlrev_b32_e32 v2, v2, v54068; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, v2, v44069; GFX11-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc_lo4070; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)4071; GFX11-NEXT:    v_or_b32_e32 v2, v5, v24072; GFX11-NEXT:    v_add_nc_u32_e32 v3, 0xfffffc10, v34073; GFX11-NEXT:    v_lshl_or_b32 v4, v3, 12, v04074; GFX11-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 1, v34075; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)4076; GFX11-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc_lo4077; GFX11-NEXT:    v_and_b32_e32 v4, 7, v24078; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 2, v24079; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)4080; GFX11-NEXT:    v_cmp_lt_i32_e32 vcc_lo, 5, v44081; GFX11-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc_lo4082; GFX11-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 3, v44083; GFX11-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc_lo4084; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v04085; GFX11-NEXT:    v_or_b32_e32 v4, v4, v54086; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)4087; GFX11-NEXT:    v_dual_mov_b32 v5, 0x7e00 :: v_dual_add_nc_u32 v2, v2, v44088; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7c00, v5, vcc_lo4089; GFX11-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 31, v34090; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)4091; GFX11-NEXT:    v_cndmask_b32_e32 v2, 0x7c00, v2, vcc_lo4092; GFX11-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0x40f, v34093; GFX11-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo4094; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)4095; GFX11-NEXT:    v_and_or_b32 v0, 0x8000, v1, v04096; GFX11-NEXT:    s_setpc_b64 s[30:31]4097  %fneg.a = fneg double %a4098  %fpround = fptrunc double %fneg.a to half4099  %fneg = fneg half %fpround4100  ret half %fneg4101}4102 4103define { half, double } @v_fneg_fp_round_store_use_fneg_f64_to_f16(double %a) #0 {4104; SI-LABEL: v_fneg_fp_round_store_use_fneg_f64_to_f16:4105; SI:       ; %bb.0:4106; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4107; SI-NEXT:    v_mov_b32_e32 v3, v04108; SI-NEXT:    v_and_b32_e32 v0, 0x1ff, v14109; SI-NEXT:    v_or_b32_e32 v0, v0, v34110; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v04111; SI-NEXT:    v_lshrrev_b32_e32 v2, 8, v14112; SI-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc4113; SI-NEXT:    v_and_b32_e32 v2, 0xffe, v24114; SI-NEXT:    v_bfe_u32 v4, v1, 20, 114115; SI-NEXT:    s_movk_i32 s4, 0x3f14116; SI-NEXT:    v_or_b32_e32 v0, v2, v04117; SI-NEXT:    v_sub_i32_e32 v5, vcc, s4, v44118; SI-NEXT:    v_or_b32_e32 v2, 0x1000, v04119; SI-NEXT:    v_med3_i32 v5, v5, 0, 134120; SI-NEXT:    v_lshrrev_b32_e32 v6, v5, v24121; SI-NEXT:    v_lshlrev_b32_e32 v5, v5, v64122; SI-NEXT:    v_cmp_ne_u32_e32 vcc, v5, v24123; SI-NEXT:    s_movk_i32 s4, 0xfc104124; SI-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc4125; SI-NEXT:    v_add_i32_e32 v4, vcc, s4, v44126; SI-NEXT:    v_lshlrev_b32_e32 v5, 12, v44127; SI-NEXT:    v_or_b32_e32 v2, v6, v24128; SI-NEXT:    v_or_b32_e32 v5, v0, v54129; SI-NEXT:    v_cmp_gt_i32_e32 vcc, 1, v44130; SI-NEXT:    v_cndmask_b32_e32 v2, v5, v2, vcc4131; SI-NEXT:    v_and_b32_e32 v5, 7, v24132; SI-NEXT:    v_cmp_lt_i32_e32 vcc, 5, v54133; SI-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc4134; SI-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v54135; SI-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc4136; SI-NEXT:    v_or_b32_e32 v5, v5, v64137; SI-NEXT:    v_lshrrev_b32_e32 v2, 2, v24138; SI-NEXT:    v_add_i32_e32 v2, vcc, v2, v54139; SI-NEXT:    v_mov_b32_e32 v5, 0x7c004140; SI-NEXT:    v_cmp_gt_i32_e32 vcc, 31, v44141; SI-NEXT:    v_cndmask_b32_e32 v2, v5, v2, vcc4142; SI-NEXT:    v_mov_b32_e32 v6, 0x7e004143; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v04144; SI-NEXT:    s_movk_i32 s4, 0x40f4145; SI-NEXT:    v_cndmask_b32_e32 v0, v5, v6, vcc4146; SI-NEXT:    v_cmp_eq_u32_e32 vcc, s4, v44147; SI-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc4148; SI-NEXT:    v_lshrrev_b32_e32 v2, 16, v14149; SI-NEXT:    v_and_b32_e32 v2, 0x8000, v24150; SI-NEXT:    v_or_b32_e32 v0, v2, v04151; SI-NEXT:    v_cvt_f32_f16_e32 v0, v04152; SI-NEXT:    v_xor_b32_e32 v2, 0x80000000, v14153; SI-NEXT:    v_mov_b32_e32 v1, v34154; SI-NEXT:    s_setpc_b64 s[30:31]4155;4156; VI-LABEL: v_fneg_fp_round_store_use_fneg_f64_to_f16:4157; VI:       ; %bb.0:4158; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4159; VI-NEXT:    v_mov_b32_e32 v3, v04160; VI-NEXT:    v_and_b32_e32 v0, 0x1ff, v14161; VI-NEXT:    v_or_b32_e32 v0, v0, v34162; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v04163; VI-NEXT:    v_lshrrev_b32_e32 v4, 8, v14164; VI-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc4165; VI-NEXT:    v_and_b32_e32 v4, 0xffe, v44166; VI-NEXT:    v_bfe_u32 v5, v1, 20, 114167; VI-NEXT:    s_movk_i32 s4, 0x3f14168; VI-NEXT:    v_or_b32_e32 v0, v4, v04169; VI-NEXT:    v_sub_u32_e32 v6, vcc, s4, v54170; VI-NEXT:    v_or_b32_e32 v4, 0x1000, v04171; VI-NEXT:    v_med3_i32 v6, v6, 0, 134172; VI-NEXT:    v_lshrrev_b32_e32 v7, v6, v44173; VI-NEXT:    v_lshlrev_b32_e32 v6, v6, v74174; VI-NEXT:    v_cmp_ne_u32_e32 vcc, v6, v44175; VI-NEXT:    s_movk_i32 s4, 0xfc104176; VI-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc4177; VI-NEXT:    v_add_u32_e32 v5, vcc, s4, v54178; VI-NEXT:    v_lshlrev_b32_e32 v6, 12, v54179; VI-NEXT:    v_or_b32_e32 v4, v7, v44180; VI-NEXT:    v_or_b32_e32 v6, v0, v64181; VI-NEXT:    v_cmp_gt_i32_e32 vcc, 1, v54182; VI-NEXT:    v_cndmask_b32_e32 v4, v6, v4, vcc4183; VI-NEXT:    v_and_b32_e32 v6, 7, v44184; VI-NEXT:    v_cmp_lt_i32_e32 vcc, 5, v64185; VI-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc4186; VI-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v64187; VI-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc4188; VI-NEXT:    v_or_b32_e32 v6, v6, v74189; VI-NEXT:    v_lshrrev_b32_e32 v4, 2, v44190; VI-NEXT:    v_add_u32_e32 v4, vcc, v4, v64191; VI-NEXT:    v_mov_b32_e32 v6, 0x7c004192; VI-NEXT:    v_cmp_gt_i32_e32 vcc, 31, v54193; VI-NEXT:    v_cndmask_b32_e32 v4, v6, v4, vcc4194; VI-NEXT:    v_mov_b32_e32 v7, 0x7e004195; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v04196; VI-NEXT:    s_movk_i32 s4, 0x40f4197; VI-NEXT:    v_cndmask_b32_e32 v0, v6, v7, vcc4198; VI-NEXT:    v_cmp_eq_u32_e32 vcc, s4, v54199; VI-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc4200; VI-NEXT:    v_mov_b32_e32 v4, 0x80004201; VI-NEXT:    v_xor_b32_e32 v2, 0x80000000, v14202; VI-NEXT:    v_and_b32_sdwa v1, v1, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD4203; VI-NEXT:    v_or_b32_e32 v0, v1, v04204; VI-NEXT:    v_mov_b32_e32 v1, v34205; VI-NEXT:    s_setpc_b64 s[30:31]4206;4207; GFX11-LABEL: v_fneg_fp_round_store_use_fneg_f64_to_f16:4208; GFX11:       ; %bb.0:4209; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4210; GFX11-NEXT:    v_and_or_b32 v2, 0x1ff, v1, v04211; GFX11-NEXT:    v_lshrrev_b32_e32 v3, 8, v14212; GFX11-NEXT:    v_bfe_u32 v4, v1, 20, 114213; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)4214; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v24215; GFX11-NEXT:    v_sub_nc_u32_e32 v5, 0x3f1, v44216; GFX11-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc_lo4217; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)4218; GFX11-NEXT:    v_and_or_b32 v2, 0xffe, v3, v24219; GFX11-NEXT:    v_med3_i32 v3, v5, 0, 134220; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)4221; GFX11-NEXT:    v_or_b32_e32 v5, 0x1000, v24222; GFX11-NEXT:    v_lshrrev_b32_e32 v6, v3, v54223; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)4224; GFX11-NEXT:    v_lshlrev_b32_e32 v3, v3, v64225; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, v3, v54226; GFX11-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc_lo4227; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)4228; GFX11-NEXT:    v_or_b32_e32 v3, v6, v34229; GFX11-NEXT:    v_add_nc_u32_e32 v4, 0xfffffc10, v44230; GFX11-NEXT:    v_lshl_or_b32 v5, v4, 12, v24231; GFX11-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 1, v44232; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)4233; GFX11-NEXT:    v_cndmask_b32_e32 v3, v5, v3, vcc_lo4234; GFX11-NEXT:    v_and_b32_e32 v5, 7, v34235; GFX11-NEXT:    v_lshrrev_b32_e32 v3, 2, v34236; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)4237; GFX11-NEXT:    v_cmp_lt_i32_e32 vcc_lo, 5, v54238; GFX11-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc_lo4239; GFX11-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 3, v54240; GFX11-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc_lo4241; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v24242; GFX11-NEXT:    v_or_b32_e32 v5, v5, v64243; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)4244; GFX11-NEXT:    v_dual_mov_b32 v6, 0x7e00 :: v_dual_add_nc_u32 v3, v3, v54245; GFX11-NEXT:    v_cndmask_b32_e32 v2, 0x7c00, v6, vcc_lo4246; GFX11-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 31, v44247; GFX11-NEXT:    v_lshrrev_b32_e32 v5, 16, v14248; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)4249; GFX11-NEXT:    v_cndmask_b32_e32 v3, 0x7c00, v3, vcc_lo4250; GFX11-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0x40f, v44251; GFX11-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc_lo4252; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)4253; GFX11-NEXT:    v_and_or_b32 v3, 0x8000, v5, v24254; GFX11-NEXT:    v_xor_b32_e32 v2, 0x80000000, v14255; GFX11-NEXT:    v_dual_mov_b32 v1, v0 :: v_dual_mov_b32 v0, v34256; GFX11-NEXT:    s_setpc_b64 s[30:31]4257; GFX11-SAFE-TRUE16-LABEL: v_fneg_fp_round_store_use_fneg_f64_to_f16:4258; GFX11-SAFE-TRUE16:       ; %bb.0:4259; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4260; GFX11-SAFE-TRUE16-NEXT:    v_and_or_b32 v2, 0x1ff, v1, v04261; GFX11-SAFE-TRUE16-NEXT:    v_lshrrev_b32_e32 v3, 8, v14262; GFX11-SAFE-TRUE16-NEXT:    v_bfe_u32 v4, v1, 20, 114263; GFX11-SAFE-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)4264; GFX11-SAFE-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v24265; GFX11-SAFE-TRUE16-NEXT:    v_sub_nc_u32_e32 v5, 0x3f1, v44266; GFX11-SAFE-TRUE16-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc_lo4267; GFX11-SAFE-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)4268; GFX11-SAFE-TRUE16-NEXT:    v_and_or_b32 v2, 0xffe, v3, v24269; GFX11-SAFE-TRUE16-NEXT:    v_med3_i32 v3, v5, 0, 134270; GFX11-SAFE-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)4271; GFX11-SAFE-TRUE16-NEXT:    v_or_b32_e32 v5, 0x1000, v24272; GFX11-SAFE-TRUE16-NEXT:    v_lshrrev_b32_e32 v6, v3, v54273; GFX11-SAFE-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)4274; GFX11-SAFE-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, v3, v64275; GFX11-SAFE-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, v3, v54276; GFX11-SAFE-TRUE16-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc_lo4277; GFX11-SAFE-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)4278; GFX11-SAFE-TRUE16-NEXT:    v_or_b32_e32 v3, v6, v34279; GFX11-SAFE-TRUE16-NEXT:    v_add_nc_u32_e32 v4, 0xfffffc10, v44280; GFX11-SAFE-TRUE16-NEXT:    v_lshl_or_b32 v5, v4, 12, v24281; GFX11-SAFE-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 1, v44282; GFX11-SAFE-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)4283; GFX11-SAFE-TRUE16-NEXT:    v_cndmask_b32_e32 v3, v5, v3, vcc_lo4284; GFX11-SAFE-TRUE16-NEXT:    v_and_b32_e32 v5, 7, v34285; GFX11-SAFE-TRUE16-NEXT:    v_lshrrev_b32_e32 v3, 2, v34286; GFX11-SAFE-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)4287; GFX11-SAFE-TRUE16-NEXT:    v_cmp_lt_i32_e32 vcc_lo, 5, v54288; GFX11-SAFE-TRUE16-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc_lo4289; GFX11-SAFE-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 3, v54290; GFX11-SAFE-TRUE16-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc_lo4291; GFX11-SAFE-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v24292; GFX11-SAFE-TRUE16-NEXT:    v_or_b32_e32 v5, v5, v64293; GFX11-SAFE-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)4294; GFX11-SAFE-TRUE16-NEXT:    v_dual_mov_b32 v6, 0x7e00 :: v_dual_add_nc_u32 v3, v3, v54295; GFX11-SAFE-TRUE16-NEXT:    v_cndmask_b32_e32 v2, 0x7c00, v6, vcc_lo4296; GFX11-SAFE-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 31, v44297; GFX11-SAFE-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 16, v14298; GFX11-SAFE-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)4299; GFX11-SAFE-TRUE16-NEXT:    v_cndmask_b32_e32 v3, 0x7c00, v3, vcc_lo4300; GFX11-SAFE-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0x40f, v44301; GFX11-SAFE-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc_lo4302; GFX11-SAFE-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)4303; GFX11-SAFE-TRUE16-NEXT:    v_and_or_b32 v3, 0x8000, v5, v24304; GFX11-SAFE-TRUE16-NEXT:    v_xor_b32_e32 v2, 0x80000000, v14305; GFX11-SAFE-TRUE16-NEXT:    v_mov_b32_e32 v1, v04306; GFX11-SAFE-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v3.l4307; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]4308; GFX11-NSZ-TRUE16-LABEL: v_fneg_fp_round_store_use_fneg_f64_to_f16:4309; GFX11-NSZ-TRUE16:       ; %bb.0:4310; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4311; GFX11-NSZ-TRUE16-NEXT:    v_and_or_b32 v2, 0x1ff, v1, v04312; GFX11-NSZ-TRUE16-NEXT:    v_lshrrev_b32_e32 v3, 8, v14313; GFX11-NSZ-TRUE16-NEXT:    v_bfe_u32 v4, v1, 20, 114314; GFX11-NSZ-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)4315; GFX11-NSZ-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v24316; GFX11-NSZ-TRUE16-NEXT:    v_sub_nc_u32_e32 v5, 0x3f1, v44317; GFX11-NSZ-TRUE16-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc_lo4318; GFX11-NSZ-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)4319; GFX11-NSZ-TRUE16-NEXT:    v_and_or_b32 v2, 0xffe, v3, v24320; GFX11-NSZ-TRUE16-NEXT:    v_med3_i32 v3, v5, 0, 134321; GFX11-NSZ-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)4322; GFX11-NSZ-TRUE16-NEXT:    v_or_b32_e32 v5, 0x1000, v24323; GFX11-NSZ-TRUE16-NEXT:    v_lshrrev_b32_e32 v6, v3, v54324; GFX11-NSZ-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)4325; GFX11-NSZ-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, v3, v64326; GFX11-NSZ-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, v3, v54327; GFX11-NSZ-TRUE16-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc_lo4328; GFX11-NSZ-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)4329; GFX11-NSZ-TRUE16-NEXT:    v_or_b32_e32 v3, v6, v34330; GFX11-NSZ-TRUE16-NEXT:    v_add_nc_u32_e32 v4, 0xfffffc10, v44331; GFX11-NSZ-TRUE16-NEXT:    v_lshl_or_b32 v5, v4, 12, v24332; GFX11-NSZ-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 1, v44333; GFX11-NSZ-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)4334; GFX11-NSZ-TRUE16-NEXT:    v_cndmask_b32_e32 v3, v5, v3, vcc_lo4335; GFX11-NSZ-TRUE16-NEXT:    v_and_b32_e32 v5, 7, v34336; GFX11-NSZ-TRUE16-NEXT:    v_lshrrev_b32_e32 v3, 2, v34337; GFX11-NSZ-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)4338; GFX11-NSZ-TRUE16-NEXT:    v_cmp_lt_i32_e32 vcc_lo, 5, v54339; GFX11-NSZ-TRUE16-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc_lo4340; GFX11-NSZ-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 3, v54341; GFX11-NSZ-TRUE16-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc_lo4342; GFX11-NSZ-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v24343; GFX11-NSZ-TRUE16-NEXT:    v_or_b32_e32 v5, v5, v64344; GFX11-NSZ-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)4345; GFX11-NSZ-TRUE16-NEXT:    v_dual_mov_b32 v6, 0x7e00 :: v_dual_add_nc_u32 v3, v3, v54346; GFX11-NSZ-TRUE16-NEXT:    v_cndmask_b32_e32 v2, 0x7c00, v6, vcc_lo4347; GFX11-NSZ-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 31, v44348; GFX11-NSZ-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 16, v14349; GFX11-NSZ-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)4350; GFX11-NSZ-TRUE16-NEXT:    v_cndmask_b32_e32 v3, 0x7c00, v3, vcc_lo4351; GFX11-NSZ-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0x40f, v44352; GFX11-NSZ-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc_lo4353; GFX11-NSZ-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)4354; GFX11-NSZ-TRUE16-NEXT:    v_and_or_b32 v3, 0x8000, v5, v24355; GFX11-NSZ-TRUE16-NEXT:    v_xor_b32_e32 v2, 0x80000000, v14356; GFX11-NSZ-TRUE16-NEXT:    v_mov_b32_e32 v1, v04357; GFX11-NSZ-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v3.l4358; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]4359  %fneg.a = fneg double %a4360  %fpround = fptrunc double %fneg.a to half4361  %fneg = fneg half %fpround4362  %insert.0 = insertvalue { half, double } poison, half %fneg, 04363  %insert.1 = insertvalue { half, double } %insert.0, double %fneg.a, 14364  ret { half, double } %insert.14365}4366 4367define { half, double } @v_fneg_fp_round_multi_use_fneg_f64_to_f16(double %a, double %c) #0 {4368; SI-LABEL: v_fneg_fp_round_multi_use_fneg_f64_to_f16:4369; SI:       ; %bb.0:4370; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4371; SI-NEXT:    v_and_b32_e32 v4, 0x1ff, v14372; SI-NEXT:    v_or_b32_e32 v4, v4, v04373; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v44374; SI-NEXT:    v_lshrrev_b32_e32 v5, 8, v14375; SI-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc4376; SI-NEXT:    v_and_b32_e32 v5, 0xffe, v54377; SI-NEXT:    v_bfe_u32 v6, v1, 20, 114378; SI-NEXT:    s_movk_i32 s4, 0x3f14379; SI-NEXT:    v_or_b32_e32 v4, v5, v44380; SI-NEXT:    v_sub_i32_e32 v7, vcc, s4, v64381; SI-NEXT:    v_or_b32_e32 v5, 0x1000, v44382; SI-NEXT:    v_med3_i32 v7, v7, 0, 134383; SI-NEXT:    v_lshrrev_b32_e32 v8, v7, v54384; SI-NEXT:    v_lshlrev_b32_e32 v7, v7, v84385; SI-NEXT:    v_cmp_ne_u32_e32 vcc, v7, v54386; SI-NEXT:    s_movk_i32 s4, 0xfc104387; SI-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc4388; SI-NEXT:    v_add_i32_e32 v6, vcc, s4, v64389; SI-NEXT:    v_lshlrev_b32_e32 v7, 12, v64390; SI-NEXT:    v_or_b32_e32 v5, v8, v54391; SI-NEXT:    v_or_b32_e32 v7, v4, v74392; SI-NEXT:    v_cmp_gt_i32_e32 vcc, 1, v64393; SI-NEXT:    v_cndmask_b32_e32 v5, v7, v5, vcc4394; SI-NEXT:    v_and_b32_e32 v7, 7, v54395; SI-NEXT:    v_cmp_lt_i32_e32 vcc, 5, v74396; SI-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc4397; SI-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v74398; SI-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc4399; SI-NEXT:    v_or_b32_e32 v7, v7, v84400; SI-NEXT:    v_lshrrev_b32_e32 v5, 2, v54401; SI-NEXT:    v_add_i32_e32 v5, vcc, v5, v74402; SI-NEXT:    v_mov_b32_e32 v7, 0x7c004403; SI-NEXT:    v_cmp_gt_i32_e32 vcc, 31, v64404; SI-NEXT:    v_cndmask_b32_e32 v5, v7, v5, vcc4405; SI-NEXT:    v_mov_b32_e32 v8, 0x7e004406; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v44407; SI-NEXT:    s_movk_i32 s4, 0x40f4408; SI-NEXT:    v_cndmask_b32_e32 v4, v7, v8, vcc4409; SI-NEXT:    v_cmp_eq_u32_e32 vcc, s4, v64410; SI-NEXT:    v_cndmask_b32_e32 v4, v5, v4, vcc4411; SI-NEXT:    v_lshrrev_b32_e32 v5, 16, v14412; SI-NEXT:    v_and_b32_e32 v5, 0x8000, v54413; SI-NEXT:    v_or_b32_e32 v4, v5, v44414; SI-NEXT:    v_cvt_f32_f16_e32 v4, v44415; SI-NEXT:    v_mul_f64 v[1:2], -v[0:1], v[2:3]4416; SI-NEXT:    v_mov_b32_e32 v0, v44417; SI-NEXT:    s_setpc_b64 s[30:31]4418;4419; VI-LABEL: v_fneg_fp_round_multi_use_fneg_f64_to_f16:4420; VI:       ; %bb.0:4421; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4422; VI-NEXT:    v_and_b32_e32 v4, 0x1ff, v14423; VI-NEXT:    v_or_b32_e32 v4, v4, v04424; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v44425; VI-NEXT:    v_lshrrev_b32_e32 v5, 8, v14426; VI-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc4427; VI-NEXT:    v_and_b32_e32 v5, 0xffe, v54428; VI-NEXT:    v_bfe_u32 v6, v1, 20, 114429; VI-NEXT:    s_movk_i32 s4, 0x3f14430; VI-NEXT:    v_or_b32_e32 v4, v5, v44431; VI-NEXT:    v_sub_u32_e32 v7, vcc, s4, v64432; VI-NEXT:    v_or_b32_e32 v5, 0x1000, v44433; VI-NEXT:    v_med3_i32 v7, v7, 0, 134434; VI-NEXT:    v_lshrrev_b32_e32 v8, v7, v54435; VI-NEXT:    v_lshlrev_b32_e32 v7, v7, v84436; VI-NEXT:    v_cmp_ne_u32_e32 vcc, v7, v54437; VI-NEXT:    s_movk_i32 s4, 0xfc104438; VI-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc4439; VI-NEXT:    v_add_u32_e32 v6, vcc, s4, v64440; VI-NEXT:    v_lshlrev_b32_e32 v7, 12, v64441; VI-NEXT:    v_or_b32_e32 v5, v8, v54442; VI-NEXT:    v_or_b32_e32 v7, v4, v74443; VI-NEXT:    v_cmp_gt_i32_e32 vcc, 1, v64444; VI-NEXT:    v_cndmask_b32_e32 v5, v7, v5, vcc4445; VI-NEXT:    v_and_b32_e32 v7, 7, v54446; VI-NEXT:    v_cmp_lt_i32_e32 vcc, 5, v74447; VI-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc4448; VI-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v74449; VI-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc4450; VI-NEXT:    v_mul_f64 v[2:3], -v[0:1], v[2:3]4451; VI-NEXT:    v_or_b32_e32 v7, v7, v84452; VI-NEXT:    v_lshrrev_b32_e32 v5, 2, v54453; VI-NEXT:    v_add_u32_e32 v5, vcc, v5, v74454; VI-NEXT:    v_mov_b32_e32 v7, 0x7c004455; VI-NEXT:    v_cmp_gt_i32_e32 vcc, 31, v64456; VI-NEXT:    v_cndmask_b32_e32 v5, v7, v5, vcc4457; VI-NEXT:    v_mov_b32_e32 v8, 0x7e004458; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v44459; VI-NEXT:    s_movk_i32 s4, 0x40f4460; VI-NEXT:    v_cndmask_b32_e32 v4, v7, v8, vcc4461; VI-NEXT:    v_cmp_eq_u32_e32 vcc, s4, v64462; VI-NEXT:    v_cndmask_b32_e32 v0, v5, v4, vcc4463; VI-NEXT:    v_mov_b32_e32 v4, 0x80004464; VI-NEXT:    v_and_b32_sdwa v1, v1, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD4465; VI-NEXT:    v_or_b32_e32 v0, v1, v04466; VI-NEXT:    v_mov_b32_e32 v1, v24467; VI-NEXT:    v_mov_b32_e32 v2, v34468; VI-NEXT:    s_setpc_b64 s[30:31]4469;4470; GFX11-LABEL: v_fneg_fp_round_multi_use_fneg_f64_to_f16:4471; GFX11:       ; %bb.0:4472; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4473; GFX11-NEXT:    v_and_or_b32 v4, 0x1ff, v1, v04474; GFX11-NEXT:    v_lshrrev_b32_e32 v5, 8, v14475; GFX11-NEXT:    v_bfe_u32 v6, v1, 20, 114476; GFX11-NEXT:    v_mul_f64 v[2:3], -v[0:1], v[2:3]4477; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 16, v14478; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v44479; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)4480; GFX11-NEXT:    v_sub_nc_u32_e32 v7, 0x3f1, v64481; GFX11-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc_lo4482; GFX11-NEXT:    v_and_or_b32 v4, 0xffe, v5, v44483; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)4484; GFX11-NEXT:    v_med3_i32 v5, v7, 0, 134485; GFX11-NEXT:    v_or_b32_e32 v7, 0x1000, v44486; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)4487; GFX11-NEXT:    v_lshrrev_b32_e32 v8, v5, v74488; GFX11-NEXT:    v_lshlrev_b32_e32 v5, v5, v84489; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)4490; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, v5, v74491; GFX11-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc_lo4492; GFX11-NEXT:    v_or_b32_e32 v5, v8, v54493; GFX11-NEXT:    v_add_nc_u32_e32 v6, 0xfffffc10, v64494; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)4495; GFX11-NEXT:    v_lshl_or_b32 v7, v6, 12, v44496; GFX11-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 1, v64497; GFX11-NEXT:    v_cndmask_b32_e32 v5, v7, v5, vcc_lo4498; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)4499; GFX11-NEXT:    v_and_b32_e32 v0, 7, v54500; GFX11-NEXT:    v_lshrrev_b32_e32 v5, 2, v54501; GFX11-NEXT:    v_cmp_lt_i32_e32 vcc_lo, 5, v04502; GFX11-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc_lo4503; GFX11-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 3, v04504; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo4505; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v44506; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)4507; GFX11-NEXT:    v_or_b32_e32 v0, v0, v74508; GFX11-NEXT:    v_dual_mov_b32 v7, 0x7e00 :: v_dual_add_nc_u32 v0, v5, v04509; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)4510; GFX11-NEXT:    v_cndmask_b32_e32 v4, 0x7c00, v7, vcc_lo4511; GFX11-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 31, v64512; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7c00, v0, vcc_lo4513; GFX11-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0x40f, v64514; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)4515; GFX11-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc_lo4516; GFX11-NEXT:    v_and_or_b32 v0, 0x8000, v1, v04517; GFX11-NEXT:    v_dual_mov_b32 v1, v2 :: v_dual_mov_b32 v2, v34518; GFX11-NEXT:    s_setpc_b64 s[30:31]4519  %fneg.a = fneg double %a4520  %fpround = fptrunc double %fneg.a to half4521  %fneg = fneg half %fpround4522  %use1 = fmul double %fneg.a, %c4523  %insert.0 = insertvalue { half, double } poison, half %fneg, 04524  %insert.1 = insertvalue { half, double } %insert.0, double %use1, 14525  ret { half, double } %insert.14526}4527 4528define { half, half } @v_fneg_multi_use_fp_round_fneg_f64_to_f16(double %a) #0 {4529; SI-LABEL: v_fneg_multi_use_fp_round_fneg_f64_to_f16:4530; SI:       ; %bb.0:4531; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4532; SI-NEXT:    v_and_b32_e32 v2, 0x1ff, v14533; SI-NEXT:    v_or_b32_e32 v0, v2, v04534; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v04535; SI-NEXT:    v_lshrrev_b32_e32 v2, 8, v14536; SI-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc4537; SI-NEXT:    v_and_b32_e32 v2, 0xffe, v24538; SI-NEXT:    v_bfe_u32 v3, v1, 20, 114539; SI-NEXT:    v_or_b32_e32 v0, v2, v04540; SI-NEXT:    v_sub_i32_e32 v4, vcc, 0x3f1, v34541; SI-NEXT:    v_or_b32_e32 v2, 0x1000, v04542; SI-NEXT:    v_med3_i32 v4, v4, 0, 134543; SI-NEXT:    v_lshrrev_b32_e32 v5, v4, v24544; SI-NEXT:    v_lshlrev_b32_e32 v4, v4, v54545; SI-NEXT:    v_cmp_ne_u32_e32 vcc, v4, v24546; SI-NEXT:    s_movk_i32 s4, 0xfc104547; SI-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc4548; SI-NEXT:    v_add_i32_e32 v3, vcc, s4, v34549; SI-NEXT:    v_lshlrev_b32_e32 v4, 12, v34550; SI-NEXT:    v_or_b32_e32 v2, v5, v24551; SI-NEXT:    v_or_b32_e32 v4, v0, v44552; SI-NEXT:    v_cmp_gt_i32_e32 vcc, 1, v34553; SI-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc4554; SI-NEXT:    v_and_b32_e32 v4, 7, v24555; SI-NEXT:    v_cmp_lt_i32_e32 vcc, 5, v44556; SI-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc4557; SI-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v44558; SI-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc4559; SI-NEXT:    v_or_b32_e32 v4, v4, v54560; SI-NEXT:    v_lshrrev_b32_e32 v2, 2, v24561; SI-NEXT:    v_add_i32_e32 v2, vcc, v2, v44562; SI-NEXT:    v_mov_b32_e32 v4, 0x7c004563; SI-NEXT:    v_cmp_gt_i32_e32 vcc, 31, v34564; SI-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc4565; SI-NEXT:    v_mov_b32_e32 v5, 0x7e004566; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v04567; SI-NEXT:    s_movk_i32 s4, 0x40f4568; SI-NEXT:    v_cndmask_b32_e32 v0, v4, v5, vcc4569; SI-NEXT:    v_cmp_eq_u32_e32 vcc, s4, v34570; SI-NEXT:    v_lshrrev_b32_e32 v1, 16, v14571; SI-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc4572; SI-NEXT:    v_and_b32_e32 v1, 0x8000, v14573; SI-NEXT:    v_or_b32_e32 v1, v1, v04574; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v14575; SI-NEXT:    v_cvt_f32_f16_e64 v0, -v04576; SI-NEXT:    v_cvt_f32_f16_e32 v1, v14577; SI-NEXT:    s_setpc_b64 s[30:31]4578;4579; VI-LABEL: v_fneg_multi_use_fp_round_fneg_f64_to_f16:4580; VI:       ; %bb.0:4581; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4582; VI-NEXT:    v_and_b32_e32 v2, 0x1ff, v14583; VI-NEXT:    v_or_b32_e32 v0, v2, v04584; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v04585; VI-NEXT:    v_lshrrev_b32_e32 v2, 8, v14586; VI-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc4587; VI-NEXT:    v_and_b32_e32 v2, 0xffe, v24588; VI-NEXT:    v_bfe_u32 v3, v1, 20, 114589; VI-NEXT:    v_or_b32_e32 v0, v2, v04590; VI-NEXT:    v_sub_u32_e32 v4, vcc, 0x3f1, v34591; VI-NEXT:    v_or_b32_e32 v2, 0x1000, v04592; VI-NEXT:    v_med3_i32 v4, v4, 0, 134593; VI-NEXT:    v_lshrrev_b32_e32 v5, v4, v24594; VI-NEXT:    v_lshlrev_b32_e32 v4, v4, v54595; VI-NEXT:    v_cmp_ne_u32_e32 vcc, v4, v24596; VI-NEXT:    s_movk_i32 s4, 0xfc104597; VI-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc4598; VI-NEXT:    v_add_u32_e32 v3, vcc, s4, v34599; VI-NEXT:    v_lshlrev_b32_e32 v4, 12, v34600; VI-NEXT:    v_or_b32_e32 v2, v5, v24601; VI-NEXT:    v_or_b32_e32 v4, v0, v44602; VI-NEXT:    v_cmp_gt_i32_e32 vcc, 1, v34603; VI-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc4604; VI-NEXT:    v_and_b32_e32 v4, 7, v24605; VI-NEXT:    v_cmp_lt_i32_e32 vcc, 5, v44606; VI-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc4607; VI-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v44608; VI-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc4609; VI-NEXT:    v_or_b32_e32 v4, v4, v54610; VI-NEXT:    v_lshrrev_b32_e32 v2, 2, v24611; VI-NEXT:    v_add_u32_e32 v2, vcc, v2, v44612; VI-NEXT:    v_mov_b32_e32 v4, 0x7c004613; VI-NEXT:    v_cmp_gt_i32_e32 vcc, 31, v34614; VI-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc4615; VI-NEXT:    v_mov_b32_e32 v5, 0x7e004616; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v04617; VI-NEXT:    s_movk_i32 s4, 0x40f4618; VI-NEXT:    v_cndmask_b32_e32 v0, v4, v5, vcc4619; VI-NEXT:    v_cmp_eq_u32_e32 vcc, s4, v34620; VI-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc4621; VI-NEXT:    v_mov_b32_e32 v2, 0x80004622; VI-NEXT:    v_and_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD4623; VI-NEXT:    v_or_b32_e32 v1, v1, v04624; VI-NEXT:    v_xor_b32_e32 v0, 0x8000, v14625; VI-NEXT:    s_setpc_b64 s[30:31]4626;4627; GFX11-LABEL: v_fneg_multi_use_fp_round_fneg_f64_to_f16:4628; GFX11:       ; %bb.0:4629; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4630; GFX11-NEXT:    v_and_or_b32 v0, 0x1ff, v1, v04631; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 8, v14632; GFX11-NEXT:    v_bfe_u32 v3, v1, 20, 114633; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 16, v14634; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)4635; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v04636; GFX11-NEXT:    v_sub_nc_u32_e32 v4, 0x3f1, v34637; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo4638; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)4639; GFX11-NEXT:    v_and_or_b32 v0, 0xffe, v2, v04640; GFX11-NEXT:    v_med3_i32 v2, v4, 0, 134641; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)4642; GFX11-NEXT:    v_or_b32_e32 v4, 0x1000, v04643; GFX11-NEXT:    v_lshrrev_b32_e32 v5, v2, v44644; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)4645; GFX11-NEXT:    v_lshlrev_b32_e32 v2, v2, v54646; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, v2, v44647; GFX11-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc_lo4648; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)4649; GFX11-NEXT:    v_or_b32_e32 v2, v5, v24650; GFX11-NEXT:    v_add_nc_u32_e32 v3, 0xfffffc10, v34651; GFX11-NEXT:    v_lshl_or_b32 v4, v3, 12, v04652; GFX11-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 1, v34653; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)4654; GFX11-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc_lo4655; GFX11-NEXT:    v_and_b32_e32 v4, 7, v24656; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 2, v24657; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)4658; GFX11-NEXT:    v_cmp_lt_i32_e32 vcc_lo, 5, v44659; GFX11-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc_lo4660; GFX11-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 3, v44661; GFX11-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc_lo4662; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v04663; GFX11-NEXT:    v_or_b32_e32 v4, v4, v54664; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)4665; GFX11-NEXT:    v_dual_mov_b32 v5, 0x7e00 :: v_dual_add_nc_u32 v2, v2, v44666; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7c00, v5, vcc_lo4667; GFX11-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 31, v34668; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)4669; GFX11-NEXT:    v_cndmask_b32_e32 v2, 0x7c00, v2, vcc_lo4670; GFX11-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0x40f, v34671; GFX11-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo4672; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)4673; GFX11-NEXT:    v_and_or_b32 v1, 0x8000, v1, v04674; GFX11-NEXT:    v_xor_b32_e32 v0, 0x8000, v14675; GFX11-NEXT:    s_setpc_b64 s[30:31]4676; GFX11-SAFE-TRUE16-LABEL: v_fneg_multi_use_fp_round_fneg_f64_to_f16:4677; GFX11-SAFE-TRUE16:       ; %bb.0:4678; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4679; GFX11-SAFE-TRUE16-NEXT:    v_and_or_b32 v0, 0x1ff, v1, v04680; GFX11-SAFE-TRUE16-NEXT:    v_lshrrev_b32_e32 v2, 8, v14681; GFX11-SAFE-TRUE16-NEXT:    v_bfe_u32 v3, v1, 20, 114682; GFX11-SAFE-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v14683; GFX11-SAFE-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)4684; GFX11-SAFE-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v04685; GFX11-SAFE-TRUE16-NEXT:    v_sub_nc_u32_e32 v4, 0x3f1, v34686; GFX11-SAFE-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo4687; GFX11-SAFE-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)4688; GFX11-SAFE-TRUE16-NEXT:    v_and_or_b32 v0, 0xffe, v2, v04689; GFX11-SAFE-TRUE16-NEXT:    v_med3_i32 v2, v4, 0, 134690; GFX11-SAFE-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)4691; GFX11-SAFE-TRUE16-NEXT:    v_or_b32_e32 v4, 0x1000, v04692; GFX11-SAFE-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, v2, v44693; GFX11-SAFE-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)4694; GFX11-SAFE-TRUE16-NEXT:    v_lshlrev_b32_e32 v2, v2, v54695; GFX11-SAFE-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, v2, v44696; GFX11-SAFE-TRUE16-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc_lo4697; GFX11-SAFE-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)4698; GFX11-SAFE-TRUE16-NEXT:    v_or_b32_e32 v2, v5, v24699; GFX11-SAFE-TRUE16-NEXT:    v_add_nc_u32_e32 v3, 0xfffffc10, v34700; GFX11-SAFE-TRUE16-NEXT:    v_lshl_or_b32 v4, v3, 12, v04701; GFX11-SAFE-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 1, v34702; GFX11-SAFE-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)4703; GFX11-SAFE-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc_lo4704; GFX11-SAFE-TRUE16-NEXT:    v_and_b32_e32 v4, 7, v24705; GFX11-SAFE-TRUE16-NEXT:    v_lshrrev_b32_e32 v2, 2, v24706; GFX11-SAFE-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)4707; GFX11-SAFE-TRUE16-NEXT:    v_cmp_lt_i32_e32 vcc_lo, 5, v44708; GFX11-SAFE-TRUE16-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc_lo4709; GFX11-SAFE-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 3, v44710; GFX11-SAFE-TRUE16-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc_lo4711; GFX11-SAFE-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v04712; GFX11-SAFE-TRUE16-NEXT:    v_or_b32_e32 v4, v4, v54713; GFX11-SAFE-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)4714; GFX11-SAFE-TRUE16-NEXT:    v_dual_mov_b32 v5, 0x7e00 :: v_dual_add_nc_u32 v2, v2, v44715; GFX11-SAFE-TRUE16-NEXT:    v_cndmask_b32_e32 v0, 0x7c00, v5, vcc_lo4716; GFX11-SAFE-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 31, v34717; GFX11-SAFE-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)4718; GFX11-SAFE-TRUE16-NEXT:    v_cndmask_b32_e32 v2, 0x7c00, v2, vcc_lo4719; GFX11-SAFE-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0x40f, v34720; GFX11-SAFE-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo4721; GFX11-SAFE-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)4722; GFX11-SAFE-TRUE16-NEXT:    v_and_or_b32 v1, 0x8000, v1, v04723; GFX11-SAFE-TRUE16-NEXT:    v_xor_b16 v0.l, 0x8000, v1.l4724; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]4725; GFX11-NSZ-TRUE16-LABEL: v_fneg_multi_use_fp_round_fneg_f64_to_f16:4726; GFX11-NSZ-TRUE16:       ; %bb.0:4727; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4728; GFX11-NSZ-TRUE16-NEXT:    v_and_or_b32 v0, 0x1ff, v1, v04729; GFX11-NSZ-TRUE16-NEXT:    v_lshrrev_b32_e32 v2, 8, v14730; GFX11-NSZ-TRUE16-NEXT:    v_bfe_u32 v3, v1, 20, 114731; GFX11-NSZ-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v14732; GFX11-NSZ-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)4733; GFX11-NSZ-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v04734; GFX11-NSZ-TRUE16-NEXT:    v_sub_nc_u32_e32 v4, 0x3f1, v34735; GFX11-NSZ-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo4736; GFX11-NSZ-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)4737; GFX11-NSZ-TRUE16-NEXT:    v_and_or_b32 v0, 0xffe, v2, v04738; GFX11-NSZ-TRUE16-NEXT:    v_med3_i32 v2, v4, 0, 134739; GFX11-NSZ-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)4740; GFX11-NSZ-TRUE16-NEXT:    v_or_b32_e32 v4, 0x1000, v04741; GFX11-NSZ-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, v2, v44742; GFX11-NSZ-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)4743; GFX11-NSZ-TRUE16-NEXT:    v_lshlrev_b32_e32 v2, v2, v54744; GFX11-NSZ-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, v2, v44745; GFX11-NSZ-TRUE16-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc_lo4746; GFX11-NSZ-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)4747; GFX11-NSZ-TRUE16-NEXT:    v_or_b32_e32 v2, v5, v24748; GFX11-NSZ-TRUE16-NEXT:    v_add_nc_u32_e32 v3, 0xfffffc10, v34749; GFX11-NSZ-TRUE16-NEXT:    v_lshl_or_b32 v4, v3, 12, v04750; GFX11-NSZ-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 1, v34751; GFX11-NSZ-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)4752; GFX11-NSZ-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc_lo4753; GFX11-NSZ-TRUE16-NEXT:    v_and_b32_e32 v4, 7, v24754; GFX11-NSZ-TRUE16-NEXT:    v_lshrrev_b32_e32 v2, 2, v24755; GFX11-NSZ-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)4756; GFX11-NSZ-TRUE16-NEXT:    v_cmp_lt_i32_e32 vcc_lo, 5, v44757; GFX11-NSZ-TRUE16-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc_lo4758; GFX11-NSZ-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 3, v44759; GFX11-NSZ-TRUE16-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc_lo4760; GFX11-NSZ-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v04761; GFX11-NSZ-TRUE16-NEXT:    v_or_b32_e32 v4, v4, v54762; GFX11-NSZ-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)4763; GFX11-NSZ-TRUE16-NEXT:    v_dual_mov_b32 v5, 0x7e00 :: v_dual_add_nc_u32 v2, v2, v44764; GFX11-NSZ-TRUE16-NEXT:    v_cndmask_b32_e32 v0, 0x7c00, v5, vcc_lo4765; GFX11-NSZ-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 31, v34766; GFX11-NSZ-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)4767; GFX11-NSZ-TRUE16-NEXT:    v_cndmask_b32_e32 v2, 0x7c00, v2, vcc_lo4768; GFX11-NSZ-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0x40f, v34769; GFX11-NSZ-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo4770; GFX11-NSZ-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)4771; GFX11-NSZ-TRUE16-NEXT:    v_and_or_b32 v1, 0x8000, v1, v04772; GFX11-NSZ-TRUE16-NEXT:    v_xor_b16 v0.l, 0x8000, v1.l4773; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]4774  %fpround = fptrunc double %a to half4775  %fneg = fneg half %fpround4776  %insert.0 = insertvalue { half, half } poison, half %fneg, 04777  %insert.1 = insertvalue { half, half } %insert.0, half %fpround, 14778  ret { half, half } %insert.14779}4780 4781; --------------------------------------------------------------------------------4782; ftrunc tests4783; --------------------------------------------------------------------------------4784 4785define half @v_fneg_trunc_f16(half %a) #0 {4786; SI-LABEL: v_fneg_trunc_f16:4787; SI:       ; %bb.0:4788; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4789; SI-NEXT:    v_cvt_f16_f32_e64 v0, -v04790; SI-NEXT:    v_cvt_f32_f16_e32 v0, v04791; SI-NEXT:    v_trunc_f32_e32 v0, v04792; SI-NEXT:    s_setpc_b64 s[30:31]4793;4794; VI-LABEL: v_fneg_trunc_f16:4795; VI:       ; %bb.0:4796; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4797; VI-NEXT:    v_trunc_f16_e64 v0, -v04798; VI-NEXT:    s_setpc_b64 s[30:31]4799;4800; GFX11-LABEL: v_fneg_trunc_f16:4801; GFX11:       ; %bb.0:4802; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4803; GFX11-NEXT:    v_trunc_f16_e64 v0, -v04804; GFX11-NEXT:    s_setpc_b64 s[30:31]4805; GFX11-SAFE-TRUE16-LABEL: v_fneg_trunc_f16:4806; GFX11-SAFE-TRUE16:       ; %bb.0:4807; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4808; GFX11-SAFE-TRUE16-NEXT:    v_trunc_f16_e64 v0.l, -v0.l4809; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]4810; GFX11-NSZ-TRUE16-LABEL: v_fneg_trunc_f16:4811; GFX11-NSZ-TRUE16:       ; %bb.0:4812; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4813; GFX11-NSZ-TRUE16-NEXT:    v_trunc_f16_e64 v0.l, -v0.l4814; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]4815  %trunc = call half @llvm.trunc.f16(half %a)4816  %fneg = fneg half %trunc4817  ret half %fneg4818}4819 4820; --------------------------------------------------------------------------------4821; fround tests4822; --------------------------------------------------------------------------------4823 4824define half @v_fneg_round_f16(half %a) #0 {4825; SI-SAFE-LABEL: v_fneg_round_f16:4826; SI-SAFE:       ; %bb.0:4827; SI-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4828; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v0, v04829; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v0, v04830; SI-SAFE-NEXT:    v_trunc_f32_e32 v1, v04831; SI-SAFE-NEXT:    v_sub_f32_e32 v2, v0, v14832; SI-SAFE-NEXT:    v_cmp_ge_f32_e64 s[4:5], |v2|, 0.54833; SI-SAFE-NEXT:    v_cndmask_b32_e64 v2, 0, 1.0, s[4:5]4834; SI-SAFE-NEXT:    s_brev_b32 s4, -24835; SI-SAFE-NEXT:    v_bfi_b32 v0, s4, v2, v04836; SI-SAFE-NEXT:    v_add_f32_e32 v0, v1, v04837; SI-SAFE-NEXT:    v_xor_b32_e32 v0, 0x80000000, v04838; SI-SAFE-NEXT:    s_setpc_b64 s[30:31]4839;4840; SI-NSZ-LABEL: v_fneg_round_f16:4841; SI-NSZ:       ; %bb.0:4842; SI-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4843; SI-NSZ-NEXT:    v_cvt_f16_f32_e32 v0, v04844; SI-NSZ-NEXT:    v_cvt_f32_f16_e32 v0, v04845; SI-NSZ-NEXT:    v_trunc_f32_e32 v1, v04846; SI-NSZ-NEXT:    v_sub_f32_e32 v2, v0, v14847; SI-NSZ-NEXT:    v_cmp_ge_f32_e64 s[4:5], |v2|, 0.54848; SI-NSZ-NEXT:    v_cndmask_b32_e64 v2, 0, 1.0, s[4:5]4849; SI-NSZ-NEXT:    s_brev_b32 s4, -24850; SI-NSZ-NEXT:    v_bfi_b32 v0, s4, v2, v04851; SI-NSZ-NEXT:    v_sub_f32_e64 v0, -v1, v04852; SI-NSZ-NEXT:    s_setpc_b64 s[30:31]4853;4854; VI-SAFE-LABEL: v_fneg_round_f16:4855; VI-SAFE:       ; %bb.0:4856; VI-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4857; VI-SAFE-NEXT:    v_trunc_f16_e32 v1, v04858; VI-SAFE-NEXT:    v_sub_f16_e32 v2, v0, v14859; VI-SAFE-NEXT:    v_mov_b32_e32 v3, 0x3c004860; VI-SAFE-NEXT:    v_cmp_ge_f16_e64 vcc, |v2|, 0.54861; VI-SAFE-NEXT:    v_cndmask_b32_e32 v2, 0, v3, vcc4862; VI-SAFE-NEXT:    s_movk_i32 s4, 0x7fff4863; VI-SAFE-NEXT:    v_bfi_b32 v0, s4, v2, v04864; VI-SAFE-NEXT:    v_add_f16_e32 v0, v1, v04865; VI-SAFE-NEXT:    v_xor_b32_e32 v0, 0x8000, v04866; VI-SAFE-NEXT:    s_setpc_b64 s[30:31]4867;4868; VI-NSZ-LABEL: v_fneg_round_f16:4869; VI-NSZ:       ; %bb.0:4870; VI-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4871; VI-NSZ-NEXT:    v_trunc_f16_e32 v1, v04872; VI-NSZ-NEXT:    v_sub_f16_e32 v2, v0, v14873; VI-NSZ-NEXT:    v_mov_b32_e32 v3, 0x3c004874; VI-NSZ-NEXT:    v_cmp_ge_f16_e64 vcc, |v2|, 0.54875; VI-NSZ-NEXT:    v_cndmask_b32_e32 v2, 0, v3, vcc4876; VI-NSZ-NEXT:    s_movk_i32 s4, 0x7fff4877; VI-NSZ-NEXT:    v_bfi_b32 v0, s4, v2, v04878; VI-NSZ-NEXT:    v_sub_f16_e64 v0, -v1, v04879; VI-NSZ-NEXT:    s_setpc_b64 s[30:31]4880;4881; GFX11-SAFE-LABEL: v_fneg_round_f16:4882; GFX11-SAFE:       ; %bb.0:4883; GFX11-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4884; GFX11-SAFE-NEXT:    v_trunc_f16_e32 v1, v04885; GFX11-SAFE-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)4886; GFX11-SAFE-NEXT:    v_sub_f16_e32 v2, v0, v14887; GFX11-SAFE-NEXT:    v_cmp_ge_f16_e64 s0, |v2|, 0.54888; GFX11-SAFE-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)4889; GFX11-SAFE-NEXT:    v_cndmask_b32_e64 v2, 0, 0x3c00, s04890; GFX11-SAFE-NEXT:    v_bfi_b32 v0, 0x7fff, v2, v04891; GFX11-SAFE-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)4892; GFX11-SAFE-NEXT:    v_add_f16_e32 v0, v1, v04893; GFX11-SAFE-NEXT:    v_xor_b32_e32 v0, 0x8000, v04894; GFX11-SAFE-NEXT:    s_setpc_b64 s[30:31]4895;4896; GFX11-NSZ-LABEL: v_fneg_round_f16:4897; GFX11-NSZ:       ; %bb.0:4898; GFX11-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4899; GFX11-NSZ-NEXT:    v_trunc_f16_e32 v1, v04900; GFX11-NSZ-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)4901; GFX11-NSZ-NEXT:    v_sub_f16_e32 v2, v0, v14902; GFX11-NSZ-NEXT:    v_cmp_ge_f16_e64 s0, |v2|, 0.54903; GFX11-NSZ-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)4904; GFX11-NSZ-NEXT:    v_cndmask_b32_e64 v2, 0, 0x3c00, s04905; GFX11-NSZ-NEXT:    v_bfi_b32 v0, 0x7fff, v2, v04906; GFX11-NSZ-NEXT:    s_delay_alu instid0(VALU_DEP_1)4907; GFX11-NSZ-NEXT:    v_sub_f16_e64 v0, -v1, v04908; GFX11-NSZ-NEXT:    s_setpc_b64 s[30:31]4909; GFX11-SAFE-TRUE16-LABEL: v_fneg_round_f16:4910; GFX11-SAFE-TRUE16:       ; %bb.0:4911; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4912; GFX11-SAFE-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v0.l4913; GFX11-SAFE-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)4914; GFX11-SAFE-TRUE16-NEXT:    v_trunc_f16_e32 v1.h, v1.l4915; GFX11-SAFE-TRUE16-NEXT:    v_sub_f16_e32 v1.l, v1.l, v1.h4916; GFX11-SAFE-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)4917; GFX11-SAFE-TRUE16-NEXT:    v_cmp_ge_f16_e64 s0, |v1.l|, 0.54918; GFX11-SAFE-TRUE16-NEXT:    v_cndmask_b16 v1.l, 0, 0x3c00, s04919; GFX11-SAFE-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)4920; GFX11-SAFE-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v1.l4921; GFX11-SAFE-TRUE16-NEXT:    v_bfi_b32 v0, 0x7fff, v2, v04922; GFX11-SAFE-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)4923; GFX11-SAFE-TRUE16-NEXT:    v_add_f16_e32 v0.l, v1.h, v0.l4924; GFX11-SAFE-TRUE16-NEXT:    v_xor_b16 v0.l, 0x8000, v0.l4925; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]4926; GFX11-NSZ-TRUE16-LABEL: v_fneg_round_f16:4927; GFX11-NSZ-TRUE16:       ; %bb.0:4928; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4929; GFX11-NSZ-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v0.l4930; GFX11-NSZ-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)4931; GFX11-NSZ-TRUE16-NEXT:    v_trunc_f16_e32 v1.h, v1.l4932; GFX11-NSZ-TRUE16-NEXT:    v_sub_f16_e32 v1.l, v1.l, v1.h4933; GFX11-NSZ-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)4934; GFX11-NSZ-TRUE16-NEXT:    v_cmp_ge_f16_e64 s0, |v1.l|, 0.54935; GFX11-NSZ-TRUE16-NEXT:    v_cndmask_b16 v1.l, 0, 0x3c00, s04936; GFX11-NSZ-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)4937; GFX11-NSZ-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v1.l4938; GFX11-NSZ-TRUE16-NEXT:    v_bfi_b32 v0, 0x7fff, v2, v04939; GFX11-NSZ-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)4940; GFX11-NSZ-TRUE16-NEXT:    v_sub_f16_e64 v0.l, -v1.h, v0.l4941; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]4942  %round = call half @llvm.round.f16(half %a)4943  %fneg = fneg half %round4944  ret half %fneg4945}4946 4947; --------------------------------------------------------------------------------4948; rint tests4949; --------------------------------------------------------------------------------4950 4951define half @v_fneg_rint_f16(half %a) #0 {4952; SI-LABEL: v_fneg_rint_f16:4953; SI:       ; %bb.0:4954; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4955; SI-NEXT:    v_cvt_f16_f32_e64 v0, -v04956; SI-NEXT:    v_cvt_f32_f16_e32 v0, v04957; SI-NEXT:    v_rndne_f32_e32 v0, v04958; SI-NEXT:    s_setpc_b64 s[30:31]4959;4960; VI-LABEL: v_fneg_rint_f16:4961; VI:       ; %bb.0:4962; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4963; VI-NEXT:    v_rndne_f16_e64 v0, -v04964; VI-NEXT:    s_setpc_b64 s[30:31]4965;4966; GFX11-LABEL: v_fneg_rint_f16:4967; GFX11:       ; %bb.0:4968; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4969; GFX11-NEXT:    v_rndne_f16_e64 v0, -v04970; GFX11-NEXT:    s_setpc_b64 s[30:31]4971; GFX11-SAFE-TRUE16-LABEL: v_fneg_rint_f16:4972; GFX11-SAFE-TRUE16:       ; %bb.0:4973; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4974; GFX11-SAFE-TRUE16-NEXT:    v_rndne_f16_e64 v0.l, -v0.l4975; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]4976; GFX11-NSZ-TRUE16-LABEL: v_fneg_rint_f16:4977; GFX11-NSZ-TRUE16:       ; %bb.0:4978; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4979; GFX11-NSZ-TRUE16-NEXT:    v_rndne_f16_e64 v0.l, -v0.l4980; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]4981  %rint = call half @llvm.rint.f16(half %a)4982  %fneg = fneg half %rint4983  ret half %fneg4984}4985 4986; --------------------------------------------------------------------------------4987; nearbyint tests4988; --------------------------------------------------------------------------------4989 4990define half @v_fneg_nearbyint_f16(half %a) #0 {4991; SI-LABEL: v_fneg_nearbyint_f16:4992; SI:       ; %bb.0:4993; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4994; SI-NEXT:    v_cvt_f16_f32_e64 v0, -v04995; SI-NEXT:    v_cvt_f32_f16_e32 v0, v04996; SI-NEXT:    v_rndne_f32_e32 v0, v04997; SI-NEXT:    s_setpc_b64 s[30:31]4998;4999; VI-LABEL: v_fneg_nearbyint_f16:5000; VI:       ; %bb.0:5001; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5002; VI-NEXT:    v_rndne_f16_e64 v0, -v05003; VI-NEXT:    s_setpc_b64 s[30:31]5004;5005; GFX11-LABEL: v_fneg_nearbyint_f16:5006; GFX11:       ; %bb.0:5007; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5008; GFX11-NEXT:    v_rndne_f16_e64 v0, -v05009; GFX11-NEXT:    s_setpc_b64 s[30:31]5010; GFX11-SAFE-TRUE16-LABEL: v_fneg_nearbyint_f16:5011; GFX11-SAFE-TRUE16:       ; %bb.0:5012; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5013; GFX11-SAFE-TRUE16-NEXT:    v_rndne_f16_e64 v0.l, -v0.l5014; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]5015; GFX11-NSZ-TRUE16-LABEL: v_fneg_nearbyint_f16:5016; GFX11-NSZ-TRUE16:       ; %bb.0:5017; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5018; GFX11-NSZ-TRUE16-NEXT:    v_rndne_f16_e64 v0.l, -v0.l5019; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]5020  %nearbyint = call half @llvm.nearbyint.f16(half %a)5021  %fneg = fneg half %nearbyint5022  ret half %fneg5023}5024 5025; --------------------------------------------------------------------------------5026; sin tests5027; --------------------------------------------------------------------------------5028 5029define half @v_fneg_sin_f16(half %a) #0 {5030; SI-LABEL: v_fneg_sin_f16:5031; SI:       ; %bb.0:5032; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5033; SI-NEXT:    v_cvt_f16_f32_e64 v0, -v05034; SI-NEXT:    v_cvt_f32_f16_e32 v0, v05035; SI-NEXT:    v_mul_f32_e32 v0, 0x3e22f983, v05036; SI-NEXT:    v_fract_f32_e32 v0, v05037; SI-NEXT:    v_sin_f32_e32 v0, v05038; SI-NEXT:    s_setpc_b64 s[30:31]5039;5040; VI-LABEL: v_fneg_sin_f16:5041; VI:       ; %bb.0:5042; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5043; VI-NEXT:    v_mul_f16_e32 v0, 0xb118, v05044; VI-NEXT:    v_fract_f16_e32 v0, v05045; VI-NEXT:    v_sin_f16_e32 v0, v05046; VI-NEXT:    s_setpc_b64 s[30:31]5047;5048; GFX11-LABEL: v_fneg_sin_f16:5049; GFX11:       ; %bb.0:5050; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5051; GFX11-NEXT:    v_mul_f16_e32 v0, 0xb118, v05052; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)5053; GFX11-NEXT:    v_sin_f16_e32 v0, v05054; GFX11-NEXT:    s_setpc_b64 s[30:31]5055; GFX11-SAFE-TRUE16-LABEL: v_fneg_sin_f16:5056; GFX11-SAFE-TRUE16:       ; %bb.0:5057; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5058; GFX11-SAFE-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0xb118, v0.l5059; GFX11-SAFE-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)5060; GFX11-SAFE-TRUE16-NEXT:    v_sin_f16_e32 v0.l, v0.l5061; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]5062; GFX11-NSZ-TRUE16-LABEL: v_fneg_sin_f16:5063; GFX11-NSZ-TRUE16:       ; %bb.0:5064; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5065; GFX11-NSZ-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0xb118, v0.l5066; GFX11-NSZ-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)5067; GFX11-NSZ-TRUE16-NEXT:    v_sin_f16_e32 v0.l, v0.l5068; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]5069  %sin = call half @llvm.sin.f16(half %a)5070  %fneg = fneg half %sin5071  ret half %fneg5072}5073 5074; --------------------------------------------------------------------------------5075; fcanonicalize tests5076; --------------------------------------------------------------------------------5077 5078define half @v_fneg_canonicalize_f16(half %a) #0 {5079; SI-LABEL: v_fneg_canonicalize_f16:5080; SI:       ; %bb.0:5081; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5082; SI-NEXT:    v_cvt_f16_f32_e64 v0, -v05083; SI-NEXT:    v_cvt_f32_f16_e32 v0, v05084; SI-NEXT:    s_setpc_b64 s[30:31]5085;5086; VI-LABEL: v_fneg_canonicalize_f16:5087; VI:       ; %bb.0:5088; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5089; VI-NEXT:    v_max_f16_e64 v0, -v0, -v05090; VI-NEXT:    s_setpc_b64 s[30:31]5091;5092; GFX11-LABEL: v_fneg_canonicalize_f16:5093; GFX11:       ; %bb.0:5094; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5095; GFX11-NEXT:    v_max_f16_e64 v0, -v0, -v05096; GFX11-NEXT:    s_setpc_b64 s[30:31]5097; GFX11-SAFE-TRUE16-LABEL: v_fneg_canonicalize_f16:5098; GFX11-SAFE-TRUE16:       ; %bb.0:5099; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5100; GFX11-SAFE-TRUE16-NEXT:    v_max_f16_e64 v0.l, -v0.l, -v0.l5101; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]5102; GFX11-NSZ-TRUE16-LABEL: v_fneg_canonicalize_f16:5103; GFX11-NSZ-TRUE16:       ; %bb.0:5104; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5105; GFX11-NSZ-TRUE16-NEXT:    v_max_f16_e64 v0.l, -v0.l, -v0.l5106; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]5107  %trunc = call half @llvm.canonicalize.f16(half %a)5108  %fneg = fneg half %trunc5109  ret half %fneg5110}5111 5112; --------------------------------------------------------------------------------5113; CopyToReg tests5114; --------------------------------------------------------------------------------5115 5116define void @v_fneg_copytoreg_f16(ptr addrspace(1) %out, half %a, half %b, half %c, i32 %d) #0 {5117; SI-LABEL: v_fneg_copytoreg_f16:5118; SI:       ; %bb.0:5119; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5120; SI-NEXT:    v_cvt_f16_f32_e32 v3, v35121; SI-NEXT:    v_cvt_f16_f32_e32 v2, v25122; SI-NEXT:    v_and_b32_e32 v6, 0x3ff, v315123; SI-NEXT:    v_lshlrev_b32_e32 v6, 1, v65124; SI-NEXT:    v_cvt_f32_f16_e32 v3, v35125; SI-NEXT:    v_cvt_f32_f16_e32 v2, v25126; SI-NEXT:    v_add_i32_e32 v0, vcc, v0, v65127; SI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc5128; SI-NEXT:    v_mul_f32_e32 v2, v2, v35129; SI-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v55130; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc5131; SI-NEXT:    s_cbranch_execz .LBB81_25132; SI-NEXT:  ; %bb.1: ; %if5133; SI-NEXT:    v_cvt_f16_f32_e64 v3, -v25134; SI-NEXT:    v_cvt_f16_f32_e32 v4, v45135; SI-NEXT:    v_cvt_f32_f16_e32 v3, v35136; SI-NEXT:    v_cvt_f32_f16_e32 v4, v45137; SI-NEXT:    v_mul_f32_e32 v3, v3, v45138; SI-NEXT:    v_cvt_f16_f32_e32 v3, v35139; SI-NEXT:    flat_store_short v[0:1], v35140; SI-NEXT:    s_waitcnt vmcnt(0)5141; SI-NEXT:  .LBB81_2: ; %endif5142; SI-NEXT:    s_or_b64 exec, exec, s[4:5]5143; SI-NEXT:    v_cvt_f16_f32_e32 v2, v25144; SI-NEXT:    flat_store_short v[0:1], v25145; SI-NEXT:    s_waitcnt vmcnt(0)5146; SI-NEXT:    s_setpc_b64 s[30:31]5147;5148; VI-LABEL: v_fneg_copytoreg_f16:5149; VI:       ; %bb.0:5150; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5151; VI-NEXT:    v_and_b32_e32 v6, 0x3ff, v315152; VI-NEXT:    v_lshlrev_b32_e32 v6, 1, v65153; VI-NEXT:    v_add_u32_e32 v0, vcc, v0, v65154; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc5155; VI-NEXT:    v_mul_f16_e32 v2, v2, v35156; VI-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v55157; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc5158; VI-NEXT:    s_cbranch_execz .LBB81_25159; VI-NEXT:  ; %bb.1: ; %if5160; VI-NEXT:    v_mul_f16_e64 v3, -v2, v45161; VI-NEXT:    flat_store_short v[0:1], v35162; VI-NEXT:    s_waitcnt vmcnt(0)5163; VI-NEXT:  .LBB81_2: ; %endif5164; VI-NEXT:    s_or_b64 exec, exec, s[4:5]5165; VI-NEXT:    flat_store_short v[0:1], v25166; VI-NEXT:    s_waitcnt vmcnt(0)5167; VI-NEXT:    s_setpc_b64 s[30:31]5168;5169; GFX11-LABEL: v_fneg_copytoreg_f16:5170; GFX11:       ; %bb.0:5171; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5172; GFX11-NEXT:    v_and_b32_e32 v6, 0x3ff, v315173; GFX11-NEXT:    v_mul_f16_e32 v2, v2, v35174; GFX11-NEXT:    s_mov_b32 s0, exec_lo5175; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)5176; GFX11-NEXT:    v_lshlrev_b32_e32 v6, 1, v65177; GFX11-NEXT:    v_add_co_u32 v0, vcc_lo, v0, v65178; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)5179; GFX11-NEXT:    v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo5180; GFX11-NEXT:    v_cmpx_eq_u32_e32 0, v55181; GFX11-NEXT:    s_cbranch_execz .LBB81_25182; GFX11-NEXT:  ; %bb.1: ; %if5183; GFX11-NEXT:    v_mul_f16_e64 v3, -v2, v45184; GFX11-NEXT:    global_store_b16 v[0:1], v3, off dlc5185; GFX11-NEXT:    s_waitcnt_vscnt null, 0x05186; GFX11-NEXT:  .LBB81_2: ; %endif5187; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s05188; GFX11-NEXT:    global_store_b16 v[0:1], v2, off dlc5189; GFX11-NEXT:    s_waitcnt_vscnt null, 0x05190; GFX11-NEXT:    s_setpc_b64 s[30:31]5191; GFX11-SAFE-TRUE16-LABEL: v_fneg_copytoreg_f16:5192; GFX11-SAFE-TRUE16:       ; %bb.0:5193; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5194; GFX11-SAFE-TRUE16-NEXT:    v_and_b32_e32 v6, 0x3ff, v315195; GFX11-SAFE-TRUE16-NEXT:    v_mul_f16_e32 v2.l, v2.l, v3.l5196; GFX11-SAFE-TRUE16-NEXT:    s_mov_b32 s0, exec_lo5197; GFX11-SAFE-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)5198; GFX11-SAFE-TRUE16-NEXT:    v_lshlrev_b32_e32 v6, 1, v65199; GFX11-SAFE-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, v0, v65200; GFX11-SAFE-TRUE16-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo5201; GFX11-SAFE-TRUE16-NEXT:    v_cmpx_eq_u32_e32 0, v55202; GFX11-SAFE-TRUE16-NEXT:    s_cbranch_execz .LBB81_25203; GFX11-SAFE-TRUE16-NEXT:  ; %bb.1: ; %if5204; GFX11-SAFE-TRUE16-NEXT:    v_mul_f16_e64 v2.h, -v2.l, v4.l5205; GFX11-SAFE-TRUE16-NEXT:    global_store_d16_hi_b16 v[0:1], v2, off dlc5206; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt_vscnt null, 0x05207; GFX11-SAFE-TRUE16-NEXT:  .LBB81_2: ; %endif5208; GFX11-SAFE-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s05209; GFX11-SAFE-TRUE16-NEXT:    global_store_b16 v[0:1], v2, off dlc5210; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt_vscnt null, 0x05211; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]5212; GFX11-NSZ-TRUE16-LABEL: v_fneg_copytoreg_f16:5213; GFX11-NSZ-TRUE16:       ; %bb.0:5214; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5215; GFX11-NSZ-TRUE16-NEXT:    v_and_b32_e32 v6, 0x3ff, v315216; GFX11-NSZ-TRUE16-NEXT:    v_mul_f16_e32 v2.l, v2.l, v3.l5217; GFX11-NSZ-TRUE16-NEXT:    s_mov_b32 s0, exec_lo5218; GFX11-NSZ-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)5219; GFX11-NSZ-TRUE16-NEXT:    v_lshlrev_b32_e32 v6, 1, v65220; GFX11-NSZ-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, v0, v65221; GFX11-NSZ-TRUE16-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo5222; GFX11-NSZ-TRUE16-NEXT:    v_cmpx_eq_u32_e32 0, v55223; GFX11-NSZ-TRUE16-NEXT:    s_cbranch_execz .LBB81_25224; GFX11-NSZ-TRUE16-NEXT:  ; %bb.1: ; %if5225; GFX11-NSZ-TRUE16-NEXT:    v_mul_f16_e64 v2.h, -v2.l, v4.l5226; GFX11-NSZ-TRUE16-NEXT:    global_store_d16_hi_b16 v[0:1], v2, off dlc5227; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt_vscnt null, 0x05228; GFX11-NSZ-TRUE16-NEXT:  .LBB81_2: ; %endif5229; GFX11-NSZ-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s05230; GFX11-NSZ-TRUE16-NEXT:    global_store_b16 v[0:1], v2, off dlc5231; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt_vscnt null, 0x05232; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]5233  %tid = call i32 @llvm.amdgcn.workitem.id.x()5234  %tid.ext = sext i32 %tid to i645235  %out.gep = getelementptr inbounds half, ptr addrspace(1) %out, i64 %tid.ext5236  %mul = fmul half %a, %b5237  %fneg = fneg half %mul5238  %cmp0 = icmp eq i32 %d, 05239  br i1 %cmp0, label %if, label %endif5240 5241if:5242  %mul1 = fmul half %fneg, %c5243  store volatile half %mul1, ptr addrspace(1) %out.gep5244  br label %endif5245 5246endif:5247  store volatile half %mul, ptr addrspace(1) %out.gep5248  ret void5249}5250 5251; --------------------------------------------------------------------------------5252; inlineasm tests5253; --------------------------------------------------------------------------------5254 5255; Can't fold into use, so should fold into source5256define half @v_fneg_inlineasm_f16(half %a, half %b, half %c, i32 %d) #0 {5257; SI-LABEL: v_fneg_inlineasm_f16:5258; SI:       ; %bb.0:5259; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5260; SI-NEXT:    v_cvt_f16_f32_e32 v0, v05261; SI-NEXT:    v_cvt_f16_f32_e64 v1, -v15262; SI-NEXT:    v_cvt_f32_f16_e32 v0, v05263; SI-NEXT:    v_cvt_f32_f16_e32 v1, v15264; SI-NEXT:    v_mul_f32_e32 v0, v0, v15265; SI-NEXT:    v_cvt_f16_f32_e32 v1, v05266; SI-NEXT:    ;;#ASMSTART5267; SI-NEXT:    ; use v15268; SI-NEXT:    ;;#ASMEND5269; SI-NEXT:    s_setpc_b64 s[30:31]5270;5271; VI-LABEL: v_fneg_inlineasm_f16:5272; VI:       ; %bb.0:5273; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5274; VI-NEXT:    v_mul_f16_e64 v0, v0, -v15275; VI-NEXT:    ;;#ASMSTART5276; VI-NEXT:    ; use v05277; VI-NEXT:    ;;#ASMEND5278; VI-NEXT:    s_setpc_b64 s[30:31]5279;5280; GFX11-LABEL: v_fneg_inlineasm_f16:5281; GFX11:       ; %bb.0:5282; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5283; GFX11-NEXT:    v_mul_f16_e64 v0, v0, -v15284; GFX11-NEXT:    ;;#ASMSTART5285; GFX11-NEXT:    ; use v05286; GFX11-NEXT:    ;;#ASMEND5287; GFX11-NEXT:    s_setpc_b64 s[30:31]5288; GFX11-SAFE-TRUE16-LABEL: v_fneg_inlineasm_f16:5289; GFX11-SAFE-TRUE16:       ; %bb.0:5290; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5291; GFX11-SAFE-TRUE16-NEXT:    v_mul_f16_e64 v0.l, v0.l, -v1.l5292; GFX11-SAFE-TRUE16-NEXT:    ;;#ASMSTART5293; GFX11-SAFE-TRUE16-NEXT:    ; use v05294; GFX11-SAFE-TRUE16-NEXT:    ;;#ASMEND5295; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]5296; GFX11-NSZ-TRUE16-LABEL: v_fneg_inlineasm_f16:5297; GFX11-NSZ-TRUE16:       ; %bb.0:5298; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5299; GFX11-NSZ-TRUE16-NEXT:    v_mul_f16_e64 v0.l, v0.l, -v1.l5300; GFX11-NSZ-TRUE16-NEXT:    ;;#ASMSTART5301; GFX11-NSZ-TRUE16-NEXT:    ; use v05302; GFX11-NSZ-TRUE16-NEXT:    ;;#ASMEND5303; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]5304  %mul = fmul half %a, %b5305  %fneg = fneg half %mul5306  call void asm sideeffect "; use $0", "v"(half %fneg) #05307  ret half %fneg5308}5309 5310; --------------------------------------------------------------------------------5311; inlineasm tests5312; --------------------------------------------------------------------------------5313 5314; Can't fold into use, so should fold into source5315define half @v_fneg_inlineasm_multi_use_src_f16(ptr addrspace(1) %out, half %a, half %b, half %c, i32 %d) #0 {5316; SI-LABEL: v_fneg_inlineasm_multi_use_src_f16:5317; SI:       ; %bb.0:5318; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5319; SI-NEXT:    v_cvt_f16_f32_e32 v0, v25320; SI-NEXT:    v_cvt_f16_f32_e64 v1, -v35321; SI-NEXT:    v_cvt_f32_f16_e32 v0, v05322; SI-NEXT:    v_cvt_f32_f16_e64 v1, -v15323; SI-NEXT:    v_mul_f32_e32 v0, v0, v15324; SI-NEXT:    v_cvt_f16_f32_e64 v1, -v05325; SI-NEXT:    ;;#ASMSTART5326; SI-NEXT:    ; use v15327; SI-NEXT:    ;;#ASMEND5328; SI-NEXT:    s_setpc_b64 s[30:31]5329;5330; VI-LABEL: v_fneg_inlineasm_multi_use_src_f16:5331; VI:       ; %bb.0:5332; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5333; VI-NEXT:    v_mul_f16_e32 v0, v2, v35334; VI-NEXT:    v_xor_b32_e32 v1, 0x8000, v05335; VI-NEXT:    ;;#ASMSTART5336; VI-NEXT:    ; use v15337; VI-NEXT:    ;;#ASMEND5338; VI-NEXT:    s_setpc_b64 s[30:31]5339;5340; GFX11-LABEL: v_fneg_inlineasm_multi_use_src_f16:5341; GFX11:       ; %bb.0:5342; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5343; GFX11-NEXT:    v_mul_f16_e32 v0, v2, v35344; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)5345; GFX11-NEXT:    v_xor_b32_e32 v1, 0x8000, v05346; GFX11-NEXT:    ;;#ASMSTART5347; GFX11-NEXT:    ; use v15348; GFX11-NEXT:    ;;#ASMEND5349; GFX11-NEXT:    s_setpc_b64 s[30:31]5350; GFX11-SAFE-TRUE16-LABEL: v_fneg_inlineasm_multi_use_src_f16:5351; GFX11-SAFE-TRUE16:       ; %bb.0:5352; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5353; GFX11-SAFE-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v2.l, v3.l5354; GFX11-SAFE-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)5355; GFX11-SAFE-TRUE16-NEXT:    v_xor_b16 v1.l, 0x8000, v0.l5356; GFX11-SAFE-TRUE16-NEXT:    ;;#ASMSTART5357; GFX11-SAFE-TRUE16-NEXT:    ; use v15358; GFX11-SAFE-TRUE16-NEXT:    ;;#ASMEND5359; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]5360; GFX11-NSZ-TRUE16-LABEL: v_fneg_inlineasm_multi_use_src_f16:5361; GFX11-NSZ-TRUE16:       ; %bb.0:5362; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5363; GFX11-NSZ-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v2.l, v3.l5364; GFX11-NSZ-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)5365; GFX11-NSZ-TRUE16-NEXT:    v_xor_b16 v1.l, 0x8000, v0.l5366; GFX11-NSZ-TRUE16-NEXT:    ;;#ASMSTART5367; GFX11-NSZ-TRUE16-NEXT:    ; use v15368; GFX11-NSZ-TRUE16-NEXT:    ;;#ASMEND5369; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]5370  %tid = call i32 @llvm.amdgcn.workitem.id.x()5371  %tid.ext = sext i32 %tid to i645372  %out.gep = getelementptr inbounds half, ptr addrspace(1) %out, i64 %tid.ext5373  %mul = fmul half %a, %b5374  %fneg = fneg half %mul5375  call void asm sideeffect "; use $0", "v"(half %fneg) #05376  ret half %mul5377}5378 5379; --------------------------------------------------------------------------------5380; code size regression tests5381; --------------------------------------------------------------------------------5382 5383; There are multiple users of the fneg that must use a VOP35384; instruction, so there is no penalty5385define { half, half } @multiuse_fneg_2_vop3_users_f16(half %a, half %b, half %c) #0 {5386; SI-LABEL: multiuse_fneg_2_vop3_users_f16:5387; SI:       ; %bb.0:5388; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5389; SI-NEXT:    v_cvt_f16_f32_e32 v2, v25390; SI-NEXT:    v_cvt_f16_f32_e32 v1, v15391; SI-NEXT:    v_cvt_f16_f32_e32 v0, v05392; SI-NEXT:    v_cvt_f32_f16_e32 v2, v25393; SI-NEXT:    v_cvt_f32_f16_e32 v1, v15394; SI-NEXT:    v_cvt_f32_f16_e32 v3, v05395; SI-NEXT:    v_fma_f32 v0, -v3, v1, v25396; SI-NEXT:    v_fma_f32 v1, -v3, v2, 2.05397; SI-NEXT:    s_setpc_b64 s[30:31]5398;5399; VI-LABEL: multiuse_fneg_2_vop3_users_f16:5400; VI:       ; %bb.0:5401; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5402; VI-NEXT:    v_fma_f16 v3, -v0, v1, v25403; VI-NEXT:    v_fma_f16 v1, -v0, v2, 2.05404; VI-NEXT:    v_mov_b32_e32 v0, v35405; VI-NEXT:    s_setpc_b64 s[30:31]5406;5407; GFX11-LABEL: multiuse_fneg_2_vop3_users_f16:5408; GFX11:       ; %bb.0:5409; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5410; GFX11-NEXT:    v_fma_f16 v3, -v0, v1, v25411; GFX11-NEXT:    v_fma_f16 v1, -v0, v2, 2.05412; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)5413; GFX11-NEXT:    v_mov_b32_e32 v0, v35414; GFX11-NEXT:    s_setpc_b64 s[30:31]5415; GFX11-SAFE-TRUE16-LABEL: multiuse_fneg_2_vop3_users_f16:5416; GFX11-SAFE-TRUE16:       ; %bb.0:5417; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5418; GFX11-SAFE-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v0.l5419; GFX11-SAFE-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)5420; GFX11-SAFE-TRUE16-NEXT:    v_fma_f16 v0.l, -v0.h, v1.l, v2.l5421; GFX11-SAFE-TRUE16-NEXT:    v_fma_f16 v1.l, -v0.h, v2.l, 2.05422; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]5423; GFX11-NSZ-TRUE16-LABEL: multiuse_fneg_2_vop3_users_f16:5424; GFX11-NSZ-TRUE16:       ; %bb.0:5425; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5426; GFX11-NSZ-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v0.l5427; GFX11-NSZ-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)5428; GFX11-NSZ-TRUE16-NEXT:    v_fma_f16 v0.l, -v0.h, v1.l, v2.l5429; GFX11-NSZ-TRUE16-NEXT:    v_fma_f16 v1.l, -v0.h, v2.l, 2.05430; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]5431  %fneg.a = fneg half %a5432  %fma0 = call half @llvm.fma.f16(half %fneg.a, half %b, half %c)5433  %fma1 = call half @llvm.fma.f16(half %fneg.a, half %c, half 2.0)5434  %insert.0 = insertvalue { half, half } poison, half %fma0, 05435  %insert.1 = insertvalue { half, half } %insert.0, half %fma1, 15436  ret { half, half } %insert.15437}5438 5439; There are multiple users, but both require using a larger encoding5440; for the modifier.5441define { half, half } @multiuse_fneg_2_vop2_users_f16(half %a, half %b, half %c) #0 {5442; SI-LABEL: multiuse_fneg_2_vop2_users_f16:5443; SI:       ; %bb.0:5444; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5445; SI-NEXT:    v_cvt_f16_f32_e32 v1, v15446; SI-NEXT:    v_cvt_f16_f32_e64 v0, -v05447; SI-NEXT:    v_cvt_f16_f32_e32 v2, v25448; SI-NEXT:    v_cvt_f32_f16_e32 v1, v15449; SI-NEXT:    v_cvt_f32_f16_e32 v3, v05450; SI-NEXT:    v_cvt_f32_f16_e32 v2, v25451; SI-NEXT:    v_mul_f32_e32 v0, v3, v15452; SI-NEXT:    v_mul_f32_e32 v1, v3, v25453; SI-NEXT:    s_setpc_b64 s[30:31]5454;5455; VI-LABEL: multiuse_fneg_2_vop2_users_f16:5456; VI:       ; %bb.0:5457; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5458; VI-NEXT:    v_mul_f16_e64 v3, -v0, v15459; VI-NEXT:    v_mul_f16_e64 v1, -v0, v25460; VI-NEXT:    v_mov_b32_e32 v0, v35461; VI-NEXT:    s_setpc_b64 s[30:31]5462;5463; GFX11-LABEL: multiuse_fneg_2_vop2_users_f16:5464; GFX11:       ; %bb.0:5465; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5466; GFX11-NEXT:    v_mul_f16_e64 v3, -v0, v15467; GFX11-NEXT:    v_mul_f16_e64 v1, -v0, v25468; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)5469; GFX11-NEXT:    v_mov_b32_e32 v0, v35470; GFX11-NEXT:    s_setpc_b64 s[30:31]5471; GFX11-SAFE-TRUE16-LABEL: multiuse_fneg_2_vop2_users_f16:5472; GFX11-SAFE-TRUE16:       ; %bb.0:5473; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5474; GFX11-SAFE-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v0.l5475; GFX11-SAFE-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)5476; GFX11-SAFE-TRUE16-NEXT:    v_mul_f16_e64 v0.l, -v0.h, v1.l5477; GFX11-SAFE-TRUE16-NEXT:    v_mul_f16_e64 v1.l, -v0.h, v2.l5478; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]5479; GFX11-NSZ-TRUE16-LABEL: multiuse_fneg_2_vop2_users_f16:5480; GFX11-NSZ-TRUE16:       ; %bb.0:5481; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5482; GFX11-NSZ-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v0.l5483; GFX11-NSZ-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)5484; GFX11-NSZ-TRUE16-NEXT:    v_mul_f16_e64 v0.l, -v0.h, v1.l5485; GFX11-NSZ-TRUE16-NEXT:    v_mul_f16_e64 v1.l, -v0.h, v2.l5486; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]5487  %fneg.a = fneg half %a5488  %mul0 = fmul half %fneg.a, %b5489  %mul1 = fmul half %fneg.a, %c5490  %insert.0 = insertvalue { half, half } poison, half %mul0, 05491  %insert.1 = insertvalue { half, half } %insert.0, half %mul1, 15492  ret { half, half } %insert.15493}5494 5495; One user is VOP3 so has no cost to folding the modifier, the other does.5496define { half, half } @multiuse_fneg_vop2_vop3_users_f16(ptr addrspace(1) %out, half %a, half %b, half %c) #0 {5497; SI-LABEL: multiuse_fneg_vop2_vop3_users_f16:5498; SI:       ; %bb.0:5499; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5500; SI-NEXT:    v_cvt_f16_f32_e32 v0, v35501; SI-NEXT:    v_cvt_f16_f32_e64 v1, -v25502; SI-NEXT:    v_cvt_f16_f32_e32 v2, v45503; SI-NEXT:    v_cvt_f32_f16_e32 v0, v05504; SI-NEXT:    v_cvt_f32_f16_e32 v1, v15505; SI-NEXT:    v_cvt_f32_f16_e32 v2, v25506; SI-NEXT:    v_fma_f32 v0, v1, v0, 2.05507; SI-NEXT:    v_mul_f32_e32 v1, v1, v25508; SI-NEXT:    s_setpc_b64 s[30:31]5509;5510; VI-LABEL: multiuse_fneg_vop2_vop3_users_f16:5511; VI:       ; %bb.0:5512; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5513; VI-NEXT:    v_fma_f16 v0, -v2, v3, 2.05514; VI-NEXT:    v_mul_f16_e64 v1, -v2, v45515; VI-NEXT:    s_setpc_b64 s[30:31]5516;5517; GFX11-LABEL: multiuse_fneg_vop2_vop3_users_f16:5518; GFX11:       ; %bb.0:5519; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5520; GFX11-NEXT:    v_fma_f16 v0, -v2, v3, 2.05521; GFX11-NEXT:    v_mul_f16_e64 v1, -v2, v45522; GFX11-NEXT:    s_setpc_b64 s[30:31]5523; GFX11-SAFE-TRUE16-LABEL: multiuse_fneg_vop2_vop3_users_f16:5524; GFX11-SAFE-TRUE16:       ; %bb.0:5525; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5526; GFX11-SAFE-TRUE16-NEXT:    v_fma_f16 v0.l, -v2.l, v3.l, 2.05527; GFX11-SAFE-TRUE16-NEXT:    v_mul_f16_e64 v1.l, -v2.l, v4.l5528; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]5529; GFX11-NSZ-TRUE16-LABEL: multiuse_fneg_vop2_vop3_users_f16:5530; GFX11-NSZ-TRUE16:       ; %bb.0:5531; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5532; GFX11-NSZ-TRUE16-NEXT:    v_fma_f16 v0.l, -v2.l, v3.l, 2.05533; GFX11-NSZ-TRUE16-NEXT:    v_mul_f16_e64 v1.l, -v2.l, v4.l5534; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]5535  %tid = call i32 @llvm.amdgcn.workitem.id.x()5536  %tid.ext = sext i32 %tid to i645537  %out.gep = getelementptr inbounds half, ptr addrspace(1) %out, i64 %tid.ext5538 5539  %fneg.a = fneg half %a5540  %fma0 = call half @llvm.fma.f16(half %fneg.a, half %b, half 2.0)5541  %mul1 = fmul half %fneg.a, %c5542 5543  %insert.0 = insertvalue { half, half } poison, half %fma0, 05544  %insert.1 = insertvalue { half, half } %insert.0, half %mul1, 15545  ret { half, half } %insert.15546}5547 5548; The use of the fneg requires a code size increase, but folding into5549; the source does not5550define { half, half } @free_fold_src_code_size_cost_use_f16(ptr addrspace(1) %out, half %a, half %b, half %c, half %d) #0 {5551; SI-SAFE-LABEL: free_fold_src_code_size_cost_use_f16:5552; SI-SAFE:       ; %bb.0:5553; SI-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5554; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v0, v35555; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v1, v25556; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v2, v45557; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v3, v55558; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v0, v05559; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v1, v15560; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v2, v25561; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v3, v35562; SI-SAFE-NEXT:    v_fma_f32 v1, v1, v0, 2.05563; SI-SAFE-NEXT:    v_mul_f32_e64 v0, -v1, v25564; SI-SAFE-NEXT:    v_mul_f32_e64 v1, -v1, v35565; SI-SAFE-NEXT:    s_setpc_b64 s[30:31]5566;5567; SI-NSZ-LABEL: free_fold_src_code_size_cost_use_f16:5568; SI-NSZ:       ; %bb.0:5569; SI-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5570; SI-NSZ-NEXT:    v_cvt_f16_f32_e32 v0, v35571; SI-NSZ-NEXT:    v_cvt_f16_f32_e32 v1, v25572; SI-NSZ-NEXT:    v_cvt_f16_f32_e32 v2, v45573; SI-NSZ-NEXT:    v_cvt_f16_f32_e32 v3, v55574; SI-NSZ-NEXT:    v_cvt_f32_f16_e32 v0, v05575; SI-NSZ-NEXT:    v_cvt_f32_f16_e32 v1, v15576; SI-NSZ-NEXT:    v_cvt_f32_f16_e32 v2, v25577; SI-NSZ-NEXT:    v_cvt_f32_f16_e32 v3, v35578; SI-NSZ-NEXT:    v_fma_f32 v1, v1, -v0, -2.05579; SI-NSZ-NEXT:    v_mul_f32_e32 v0, v1, v25580; SI-NSZ-NEXT:    v_mul_f32_e32 v1, v1, v35581; SI-NSZ-NEXT:    s_setpc_b64 s[30:31]5582;5583; VI-SAFE-LABEL: free_fold_src_code_size_cost_use_f16:5584; VI-SAFE:       ; %bb.0:5585; VI-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5586; VI-SAFE-NEXT:    v_fma_f16 v1, v2, v3, 2.05587; VI-SAFE-NEXT:    v_mul_f16_e64 v0, -v1, v45588; VI-SAFE-NEXT:    v_mul_f16_e64 v1, -v1, v55589; VI-SAFE-NEXT:    s_setpc_b64 s[30:31]5590;5591; VI-NSZ-LABEL: free_fold_src_code_size_cost_use_f16:5592; VI-NSZ:       ; %bb.0:5593; VI-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5594; VI-NSZ-NEXT:    v_fma_f16 v1, v2, -v3, -2.05595; VI-NSZ-NEXT:    v_mul_f16_e32 v0, v1, v45596; VI-NSZ-NEXT:    v_mul_f16_e32 v1, v1, v55597; VI-NSZ-NEXT:    s_setpc_b64 s[30:31]5598;5599; GFX11-SAFE-LABEL: free_fold_src_code_size_cost_use_f16:5600; GFX11-SAFE:       ; %bb.0:5601; GFX11-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5602; GFX11-SAFE-NEXT:    v_fma_f16 v1, v2, v3, 2.05603; GFX11-SAFE-NEXT:    s_delay_alu instid0(VALU_DEP_1)5604; GFX11-SAFE-NEXT:    v_mul_f16_e64 v0, -v1, v45605; GFX11-SAFE-NEXT:    v_mul_f16_e64 v1, -v1, v55606; GFX11-SAFE-NEXT:    s_setpc_b64 s[30:31]5607;5608; GFX11-NSZ-LABEL: free_fold_src_code_size_cost_use_f16:5609; GFX11-NSZ:       ; %bb.0:5610; GFX11-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5611; GFX11-NSZ-NEXT:    v_fma_f16 v1, v2, -v3, -2.05612; GFX11-NSZ-NEXT:    s_delay_alu instid0(VALU_DEP_1)5613; GFX11-NSZ-NEXT:    v_mul_f16_e32 v0, v1, v45614; GFX11-NSZ-NEXT:    v_mul_f16_e32 v1, v1, v55615; GFX11-NSZ-NEXT:    s_setpc_b64 s[30:31]5616; GFX11-SAFE-TRUE16-LABEL: free_fold_src_code_size_cost_use_f16:5617; GFX11-SAFE-TRUE16:       ; %bb.0:5618; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5619; GFX11-SAFE-TRUE16-NEXT:    v_fma_f16 v0.h, v2.l, v3.l, 2.05620; GFX11-SAFE-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)5621; GFX11-SAFE-TRUE16-NEXT:    v_mul_f16_e64 v0.l, -v0.h, v4.l5622; GFX11-SAFE-TRUE16-NEXT:    v_mul_f16_e64 v1.l, -v0.h, v5.l5623; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]5624; GFX11-NSZ-TRUE16-LABEL: free_fold_src_code_size_cost_use_f16:5625; GFX11-NSZ-TRUE16:       ; %bb.0:5626; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5627; GFX11-NSZ-TRUE16-NEXT:    v_fma_f16 v0.h, v2.l, -v3.l, -2.05628; GFX11-NSZ-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)5629; GFX11-NSZ-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.h, v4.l5630; GFX11-NSZ-TRUE16-NEXT:    v_mul_f16_e32 v1.l, v0.h, v5.l5631; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]5632  %tid = call i32 @llvm.amdgcn.workitem.id.x()5633  %tid.ext = sext i32 %tid to i645634  %out.gep = getelementptr inbounds half, ptr addrspace(1) %out, i64 %tid.ext5635 5636  %fma0 = call half @llvm.fma.f16(half %a, half %b, half 2.0)5637  %fneg.fma0 = fneg half %fma05638  %mul1 = fmul half %fneg.fma0, %c5639  %mul2 = fmul half %fneg.fma0, %d5640 5641  %insert.0 = insertvalue { half, half } poison, half %mul1, 05642  %insert.1 = insertvalue { half, half } %insert.0, half %mul2, 15643  ret { half, half } %insert.15644}5645 5646; %trunc.a has one fneg use, but it requires a code size increase and5647; %the fneg can instead be folded for free into the fma.5648define half @one_use_cost_to_fold_into_src_f16(ptr addrspace(1) %out, half %a, half %b, half %c, half %d) #0 {5649; SI-LABEL: one_use_cost_to_fold_into_src_f16:5650; SI:       ; %bb.0:5651; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5652; SI-NEXT:    v_cvt_f16_f32_e32 v1, v25653; SI-NEXT:    v_cvt_f16_f32_e32 v0, v45654; SI-NEXT:    v_cvt_f16_f32_e32 v2, v35655; SI-NEXT:    v_cvt_f32_f16_e32 v1, v15656; SI-NEXT:    v_cvt_f32_f16_e32 v0, v05657; SI-NEXT:    v_cvt_f32_f16_e32 v2, v25658; SI-NEXT:    v_trunc_f32_e32 v1, v15659; SI-NEXT:    v_fma_f32 v0, -v1, v2, v05660; SI-NEXT:    s_setpc_b64 s[30:31]5661;5662; VI-LABEL: one_use_cost_to_fold_into_src_f16:5663; VI:       ; %bb.0:5664; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5665; VI-NEXT:    v_trunc_f16_e32 v0, v25666; VI-NEXT:    v_fma_f16 v0, -v0, v3, v45667; VI-NEXT:    s_setpc_b64 s[30:31]5668;5669; GFX11-LABEL: one_use_cost_to_fold_into_src_f16:5670; GFX11:       ; %bb.0:5671; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5672; GFX11-NEXT:    v_trunc_f16_e32 v0, v25673; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)5674; GFX11-NEXT:    v_fma_f16 v0, -v0, v3, v45675; GFX11-NEXT:    s_setpc_b64 s[30:31]5676; GFX11-SAFE-TRUE16-LABEL: one_use_cost_to_fold_into_src_f16:5677; GFX11-SAFE-TRUE16:       ; %bb.0:5678; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5679; GFX11-SAFE-TRUE16-NEXT:    v_trunc_f16_e32 v0.l, v2.l5680; GFX11-SAFE-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)5681; GFX11-SAFE-TRUE16-NEXT:    v_fma_f16 v0.l, -v0.l, v3.l, v4.l5682; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]5683; GFX11-NSZ-TRUE16-LABEL: one_use_cost_to_fold_into_src_f16:5684; GFX11-NSZ-TRUE16:       ; %bb.0:5685; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5686; GFX11-NSZ-TRUE16-NEXT:    v_trunc_f16_e32 v0.l, v2.l5687; GFX11-NSZ-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)5688; GFX11-NSZ-TRUE16-NEXT:    v_fma_f16 v0.l, -v0.l, v3.l, v4.l5689; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]5690  %tid = call i32 @llvm.amdgcn.workitem.id.x()5691  %tid.ext = sext i32 %tid to i645692  %out.gep = getelementptr inbounds half, ptr addrspace(1) %out, i64 %tid.ext5693 5694  %trunc.a = call half @llvm.trunc.f16(half %a)5695  %trunc.fneg.a = fneg half %trunc.a5696  %fma0 = call half @llvm.fma.f16(half %trunc.fneg.a, half %b, half %c)5697  ret half %fma05698}5699 5700define { half, half } @multi_use_cost_to_fold_into_src(ptr addrspace(1) %out, half %a, half %b, half %c, half %d) #0 {5701; SI-LABEL: multi_use_cost_to_fold_into_src:5702; SI:       ; %bb.0:5703; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5704; SI-NEXT:    v_cvt_f16_f32_e32 v1, v25705; SI-NEXT:    v_cvt_f16_f32_e32 v0, v45706; SI-NEXT:    v_cvt_f16_f32_e32 v2, v35707; SI-NEXT:    v_cvt_f16_f32_e32 v3, v55708; SI-NEXT:    v_cvt_f32_f16_e32 v1, v15709; SI-NEXT:    v_cvt_f32_f16_e32 v0, v05710; SI-NEXT:    v_cvt_f32_f16_e32 v2, v25711; SI-NEXT:    v_cvt_f32_f16_e32 v3, v35712; SI-NEXT:    v_trunc_f32_e32 v1, v15713; SI-NEXT:    v_fma_f32 v0, -v1, v2, v05714; SI-NEXT:    v_mul_f32_e32 v1, v1, v35715; SI-NEXT:    s_setpc_b64 s[30:31]5716;5717; VI-LABEL: multi_use_cost_to_fold_into_src:5718; VI:       ; %bb.0:5719; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5720; VI-NEXT:    v_trunc_f16_e32 v1, v25721; VI-NEXT:    v_fma_f16 v0, -v1, v3, v45722; VI-NEXT:    v_mul_f16_e32 v1, v1, v55723; VI-NEXT:    s_setpc_b64 s[30:31]5724;5725; GFX11-LABEL: multi_use_cost_to_fold_into_src:5726; GFX11:       ; %bb.0:5727; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5728; GFX11-NEXT:    v_trunc_f16_e32 v1, v25729; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)5730; GFX11-NEXT:    v_fma_f16 v0, -v1, v3, v45731; GFX11-NEXT:    v_mul_f16_e32 v1, v1, v55732; GFX11-NEXT:    s_setpc_b64 s[30:31]5733; GFX11-SAFE-TRUE16-LABEL: multi_use_cost_to_fold_into_src:5734; GFX11-SAFE-TRUE16:       ; %bb.0:5735; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5736; GFX11-SAFE-TRUE16-NEXT:    v_trunc_f16_e32 v0.h, v2.l5737; GFX11-SAFE-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)5738; GFX11-SAFE-TRUE16-NEXT:    v_fma_f16 v0.l, -v0.h, v3.l, v4.l5739; GFX11-SAFE-TRUE16-NEXT:    v_mul_f16_e32 v1.l, v0.h, v5.l5740; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]5741; GFX11-NSZ-TRUE16-LABEL: multi_use_cost_to_fold_into_src:5742; GFX11-NSZ-TRUE16:       ; %bb.0:5743; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5744; GFX11-NSZ-TRUE16-NEXT:    v_trunc_f16_e32 v0.h, v2.l5745; GFX11-NSZ-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)5746; GFX11-NSZ-TRUE16-NEXT:    v_fma_f16 v0.l, -v0.h, v3.l, v4.l5747; GFX11-NSZ-TRUE16-NEXT:    v_mul_f16_e32 v1.l, v0.h, v5.l5748; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]5749  %tid = call i32 @llvm.amdgcn.workitem.id.x()5750  %tid.ext = sext i32 %tid to i645751  %out.gep = getelementptr inbounds half, ptr addrspace(1) %out, i64 %tid.ext5752  %trunc.a = call half @llvm.trunc.f16(half %a)5753  %trunc.fneg.a = fneg half %trunc.a5754  %fma0 = call half @llvm.fma.f16(half %trunc.fneg.a, half %b, half %c)5755  %mul1 = fmul half %trunc.a, %d5756  %insert.0 = insertvalue { half, half } poison, half %fma0, 05757  %insert.1 = insertvalue { half, half } %insert.0, half %mul1, 15758  ret { half, half } %insert.15759}5760 5761; The AMDGPU combine to pull fneg into the FMA operands was being5762; undone by the generic combine to pull the fneg out of the fma if5763; !isFNegFree. We were reporting false for v2f32 even though it will5764; be split into f32 where it will be free.5765define <2 x half> @fneg_fma_fneg_dagcombine_loop(<2 x half> %arg, <2 x half> %arg1, <2 x half> %arg2) #0 {5766; SI-LABEL: fneg_fma_fneg_dagcombine_loop:5767; SI:       ; %bb.0: ; %bb5768; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5769; SI-NEXT:    v_cvt_f16_f32_e32 v5, v55770; SI-NEXT:    v_cvt_f16_f32_e32 v4, v45771; SI-NEXT:    v_cvt_f16_f32_e32 v2, v25772; SI-NEXT:    v_cvt_f16_f32_e32 v3, v35773; SI-NEXT:    v_lshlrev_b32_e32 v6, 16, v55774; SI-NEXT:    v_or_b32_e32 v6, v4, v65775; SI-NEXT:    v_cvt_f16_f32_e32 v0, v05776; SI-NEXT:    v_cvt_f16_f32_e32 v1, v15777; SI-NEXT:    v_xor_b32_e32 v6, 0x80008000, v65778; SI-NEXT:    v_lshrrev_b32_e32 v7, 16, v65779; SI-NEXT:    v_cvt_f32_f16_e32 v2, v25780; SI-NEXT:    v_cvt_f32_f16_e32 v3, v35781; SI-NEXT:    v_cvt_f32_f16_e32 v7, v75782; SI-NEXT:    v_cvt_f32_f16_e32 v6, v65783; SI-NEXT:    v_cvt_f32_f16_e32 v0, v05784; SI-NEXT:    v_cvt_f32_f16_e32 v1, v15785; SI-NEXT:    v_cvt_f32_f16_e32 v5, v55786; SI-NEXT:    v_cvt_f32_f16_e32 v4, v45787; SI-NEXT:    s_brev_b32 s4, 15788; SI-NEXT:    v_fma_f32 v3, v3, v7, s45789; SI-NEXT:    v_fma_f32 v2, v2, v6, s45790; SI-NEXT:    v_sub_f32_e32 v1, v3, v15791; SI-NEXT:    v_sub_f32_e32 v0, v2, v05792; SI-NEXT:    v_mul_f32_e32 v0, v0, v45793; SI-NEXT:    v_mul_f32_e32 v1, v1, v55794; SI-NEXT:    s_setpc_b64 s[30:31]5795;5796; VI-LABEL: fneg_fma_fneg_dagcombine_loop:5797; VI:       ; %bb.0: ; %bb5798; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5799; VI-NEXT:    s_mov_b32 s4, 0x80005800; VI-NEXT:    v_fma_f16 v3, v1, -v2, s45801; VI-NEXT:    v_lshrrev_b32_e32 v1, 16, v15802; VI-NEXT:    v_lshrrev_b32_e32 v4, 16, v25803; VI-NEXT:    v_fma_f16 v1, v1, -v4, s45804; VI-NEXT:    v_sub_f16_e32 v3, v3, v05805; VI-NEXT:    v_sub_f16_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_15806; VI-NEXT:    v_mul_f16_sdwa v0, v0, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD5807; VI-NEXT:    v_mul_f16_e32 v1, v3, v25808; VI-NEXT:    v_or_b32_e32 v0, v1, v05809; VI-NEXT:    s_setpc_b64 s[30:31]5810;5811; GFX11-LABEL: fneg_fma_fneg_dagcombine_loop:5812; GFX11:       ; %bb.0: ; %bb5813; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5814; GFX11-NEXT:    v_pk_fma_f16 v1, v1, v2, 0x8000 op_sel_hi:[1,1,0] neg_lo:[0,1,0] neg_hi:[0,1,0]5815; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)5816; GFX11-NEXT:    v_pk_add_f16 v0, v1, v0 neg_lo:[0,1] neg_hi:[0,1]5817; GFX11-NEXT:    v_pk_mul_f16 v0, v0, v25818; GFX11-NEXT:    s_setpc_b64 s[30:31]5819bb:5820  %i3 = call fast <2 x half> @llvm.fma.v2f16(<2 x half> %arg1, <2 x half> %arg2, <2 x half> zeroinitializer)5821  %i4 = fadd fast <2 x half> %i3, %arg5822  %i5 = fneg <2 x half> %i45823  %i6 = fmul fast <2 x half> %i5, %arg25824  ret <2 x half> %i65825}5826 5827; This expects denormal flushing, so can't turn this fmul into fneg5828; TODO: Keeping this as fmul saves encoding size5829define half @nnan_fmul_neg1_to_fneg(half %x, half %y) #0 {5830; SI-LABEL: nnan_fmul_neg1_to_fneg:5831; SI:       ; %bb.0:5832; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5833; SI-NEXT:    v_cvt_f16_f32_e32 v1, v15834; SI-NEXT:    v_cvt_f16_f32_e64 v0, -v05835; SI-NEXT:    v_cvt_f32_f16_e32 v1, v15836; SI-NEXT:    v_cvt_f32_f16_e32 v0, v05837; SI-NEXT:    v_mul_f32_e32 v0, v0, v15838; SI-NEXT:    s_setpc_b64 s[30:31]5839;5840; VI-LABEL: nnan_fmul_neg1_to_fneg:5841; VI:       ; %bb.0:5842; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5843; VI-NEXT:    v_mul_f16_e64 v0, -v0, v15844; VI-NEXT:    s_setpc_b64 s[30:31]5845;5846; GFX11-LABEL: nnan_fmul_neg1_to_fneg:5847; GFX11:       ; %bb.0:5848; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5849; GFX11-NEXT:    v_mul_f16_e64 v0, -v0, v15850; GFX11-NEXT:    s_setpc_b64 s[30:31]5851; GFX11-SAFE-TRUE16-LABEL: nnan_fmul_neg1_to_fneg:5852; GFX11-SAFE-TRUE16:       ; %bb.0:5853; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5854; GFX11-SAFE-TRUE16-NEXT:    v_mul_f16_e64 v0.l, -v0.l, v1.l5855; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]5856; GFX11-NSZ-TRUE16-LABEL: nnan_fmul_neg1_to_fneg:5857; GFX11-NSZ-TRUE16:       ; %bb.0:5858; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5859; GFX11-NSZ-TRUE16-NEXT:    v_mul_f16_e64 v0.l, -v0.l, v1.l5860; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]5861  %mul = fmul half %x, -1.05862  %add = fmul nnan half %mul, %y5863  ret half %add5864}5865 5866; It's legal to turn this fmul into an fneg since denormals are5867; preserved and we know an snan can't happen from the flag.5868define half @denormal_fmul_neg1_to_fneg(half %x, half %y) {5869; SI-LABEL: denormal_fmul_neg1_to_fneg:5870; SI:       ; %bb.0:5871; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5872; SI-NEXT:    v_cvt_f16_f32_e32 v1, v15873; SI-NEXT:    v_cvt_f16_f32_e64 v0, -v05874; SI-NEXT:    v_cvt_f32_f16_e32 v1, v15875; SI-NEXT:    v_cvt_f32_f16_e32 v0, v05876; SI-NEXT:    v_mul_f32_e32 v0, v0, v15877; SI-NEXT:    s_setpc_b64 s[30:31]5878;5879; VI-LABEL: denormal_fmul_neg1_to_fneg:5880; VI:       ; %bb.0:5881; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5882; VI-NEXT:    v_mul_f16_e64 v0, -v0, v15883; VI-NEXT:    s_setpc_b64 s[30:31]5884;5885; GFX11-LABEL: denormal_fmul_neg1_to_fneg:5886; GFX11:       ; %bb.0:5887; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5888; GFX11-NEXT:    v_mul_f16_e64 v0, -v0, v15889; GFX11-NEXT:    s_setpc_b64 s[30:31]5890; GFX11-SAFE-TRUE16-LABEL: denormal_fmul_neg1_to_fneg:5891; GFX11-SAFE-TRUE16:       ; %bb.0:5892; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5893; GFX11-SAFE-TRUE16-NEXT:    v_mul_f16_e64 v0.l, -v0.l, v1.l5894; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]5895; GFX11-NSZ-TRUE16-LABEL: denormal_fmul_neg1_to_fneg:5896; GFX11-NSZ-TRUE16:       ; %bb.0:5897; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5898; GFX11-NSZ-TRUE16-NEXT:    v_mul_f16_e64 v0.l, -v0.l, v1.l5899; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]5900  %mul = fmul nnan half %x, -1.05901  %add = fmul half %mul, %y5902  ret half %add5903}5904 5905; know the source can't be an snan5906define half @denorm_snan_fmul_neg1_to_fneg(half %x, half %y) {5907; SI-LABEL: denorm_snan_fmul_neg1_to_fneg:5908; SI:       ; %bb.0:5909; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5910; SI-NEXT:    v_cvt_f16_f32_e32 v0, v05911; SI-NEXT:    v_cvt_f16_f32_e32 v1, v15912; SI-NEXT:    v_cvt_f32_f16_e32 v2, v05913; SI-NEXT:    v_cvt_f32_f16_e64 v0, -v05914; SI-NEXT:    v_cvt_f32_f16_e32 v1, v15915; SI-NEXT:    v_mul_f32_e32 v0, v2, v05916; SI-NEXT:    v_mul_f32_e32 v0, v0, v15917; SI-NEXT:    s_setpc_b64 s[30:31]5918;5919; VI-LABEL: denorm_snan_fmul_neg1_to_fneg:5920; VI:       ; %bb.0:5921; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5922; VI-NEXT:    v_mul_f16_e64 v0, v0, -v05923; VI-NEXT:    v_mul_f16_e32 v0, v0, v15924; VI-NEXT:    s_setpc_b64 s[30:31]5925;5926; GFX11-LABEL: denorm_snan_fmul_neg1_to_fneg:5927; GFX11:       ; %bb.0:5928; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5929; GFX11-NEXT:    v_mul_f16_e64 v0, v0, -v05930; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)5931; GFX11-NEXT:    v_mul_f16_e32 v0, v0, v15932; GFX11-NEXT:    s_setpc_b64 s[30:31]5933; GFX11-SAFE-TRUE16-LABEL: denorm_snan_fmul_neg1_to_fneg:5934; GFX11-SAFE-TRUE16:       ; %bb.0:5935; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5936; GFX11-SAFE-TRUE16-NEXT:    v_mul_f16_e64 v0.l, v0.l, -v0.l5937; GFX11-SAFE-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)5938; GFX11-SAFE-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v1.l5939; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]5940; GFX11-NSZ-TRUE16-LABEL: denorm_snan_fmul_neg1_to_fneg:5941; GFX11-NSZ-TRUE16:       ; %bb.0:5942; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5943; GFX11-NSZ-TRUE16-NEXT:    v_mul_f16_e64 v0.l, v0.l, -v0.l5944; GFX11-NSZ-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)5945; GFX11-NSZ-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v1.l5946; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]5947  %canonical = fmul half %x, %x5948  %mul = fmul half %canonical, -1.05949  %add = fmul half %mul, %y5950  ret half %add5951}5952 5953define half @flush_snan_fmul_neg1_to_fneg(half %x, half %y) #0 {5954; SI-LABEL: flush_snan_fmul_neg1_to_fneg:5955; SI:       ; %bb.0:5956; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5957; SI-NEXT:    v_cvt_f16_f32_e32 v1, v15958; SI-NEXT:    v_cvt_f16_f32_e64 v0, -v05959; SI-NEXT:    v_cvt_f32_f16_e32 v1, v15960; SI-NEXT:    v_cvt_f32_f16_e32 v0, v05961; SI-NEXT:    v_mul_f32_e32 v0, v0, v15962; SI-NEXT:    s_setpc_b64 s[30:31]5963;5964; VI-LABEL: flush_snan_fmul_neg1_to_fneg:5965; VI:       ; %bb.0:5966; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5967; VI-NEXT:    v_max_f16_e64 v0, -v0, -v05968; VI-NEXT:    v_mul_f16_e32 v0, v0, v15969; VI-NEXT:    s_setpc_b64 s[30:31]5970;5971; GFX11-LABEL: flush_snan_fmul_neg1_to_fneg:5972; GFX11:       ; %bb.0:5973; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5974; GFX11-NEXT:    v_max_f16_e64 v0, -v0, -v05975; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)5976; GFX11-NEXT:    v_mul_f16_e32 v0, v0, v15977; GFX11-NEXT:    s_setpc_b64 s[30:31]5978; GFX11-SAFE-TRUE16-LABEL: flush_snan_fmul_neg1_to_fneg:5979; GFX11-SAFE-TRUE16:       ; %bb.0:5980; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5981; GFX11-SAFE-TRUE16-NEXT:    v_max_f16_e64 v0.l, -v0.l, -v0.l5982; GFX11-SAFE-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)5983; GFX11-SAFE-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v1.l5984; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]5985; GFX11-NSZ-TRUE16-LABEL: flush_snan_fmul_neg1_to_fneg:5986; GFX11-NSZ-TRUE16:       ; %bb.0:5987; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5988; GFX11-NSZ-TRUE16-NEXT:    v_max_f16_e64 v0.l, -v0.l, -v0.l5989; GFX11-NSZ-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)5990; GFX11-NSZ-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v1.l5991; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]5992  %quiet = call half @llvm.canonicalize.f16(half %x)5993  %mul = fmul half %quiet, -1.05994  %add = fmul half %mul, %y5995  ret half %add5996}5997 5998define half @fadd_select_fneg_fneg_f16(i32 %arg0, half %x, half %y, half %z) {5999; SI-LABEL: fadd_select_fneg_fneg_f16:6000; SI:       ; %bb.0:6001; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6002; SI-NEXT:    v_cvt_f16_f32_e32 v1, v16003; SI-NEXT:    v_cvt_f16_f32_e32 v2, v26004; SI-NEXT:    v_cvt_f16_f32_e32 v3, v36005; SI-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v06006; SI-NEXT:    v_cvt_f32_f16_e32 v1, v16007; SI-NEXT:    v_cvt_f32_f16_e32 v2, v26008; SI-NEXT:    v_cvt_f32_f16_e32 v3, v36009; SI-NEXT:    v_cndmask_b32_e32 v0, v2, v1, vcc6010; SI-NEXT:    v_sub_f32_e32 v0, v3, v06011; SI-NEXT:    s_setpc_b64 s[30:31]6012;6013; VI-LABEL: fadd_select_fneg_fneg_f16:6014; VI:       ; %bb.0:6015; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6016; VI-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v06017; VI-NEXT:    v_cndmask_b32_e32 v0, v2, v1, vcc6018; VI-NEXT:    v_sub_f16_e32 v0, v3, v06019; VI-NEXT:    s_setpc_b64 s[30:31]6020;6021; GFX11-LABEL: fadd_select_fneg_fneg_f16:6022; GFX11:       ; %bb.0:6023; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6024; GFX11-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v06025; GFX11-NEXT:    v_cndmask_b32_e32 v0, v2, v1, vcc_lo6026; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)6027; GFX11-NEXT:    v_sub_f16_e32 v0, v3, v06028; GFX11-NEXT:    s_setpc_b64 s[30:31]6029; GFX11-SAFE-TRUE16-LABEL: fadd_select_fneg_fneg_f16:6030; GFX11-SAFE-TRUE16:       ; %bb.0:6031; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6032; GFX11-SAFE-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v06033; GFX11-SAFE-TRUE16-NEXT:    v_cndmask_b16 v0.l, v2.l, v1.l, vcc_lo6034; GFX11-SAFE-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)6035; GFX11-SAFE-TRUE16-NEXT:    v_sub_f16_e32 v0.l, v3.l, v0.l6036; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]6037; GFX11-NSZ-TRUE16-LABEL: fadd_select_fneg_fneg_f16:6038; GFX11-NSZ-TRUE16:       ; %bb.0:6039; GFX11-NSZ-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6040; GFX11-NSZ-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v06041; GFX11-NSZ-TRUE16-NEXT:    v_cndmask_b16 v0.l, v2.l, v1.l, vcc_lo6042; GFX11-NSZ-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)6043; GFX11-NSZ-TRUE16-NEXT:    v_sub_f16_e32 v0.l, v3.l, v0.l6044; GFX11-NSZ-TRUE16-NEXT:    s_setpc_b64 s[30:31]6045  %cmp = icmp eq i32 %arg0, 06046  %neg.x = fneg half %x6047  %neg.y  = fneg half %y6048  %select = select i1 %cmp, half %neg.x, half %neg.y6049  %add = fadd half %select, %z6050  ret half %add6051}6052 6053; FIXME: Terrible code for SI6054define <2 x half> @fadd_select_fneg_fneg_v2f16(i32 %arg0, <2 x half> %x, <2 x half> %y, <2 x half> %z) {6055; SI-LABEL: fadd_select_fneg_fneg_v2f16:6056; SI:       ; %bb.0:6057; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6058; SI-NEXT:    v_cvt_f16_f32_e32 v2, v26059; SI-NEXT:    v_cvt_f16_f32_e32 v1, v16060; SI-NEXT:    v_cvt_f16_f32_e32 v3, v36061; SI-NEXT:    v_cvt_f16_f32_e32 v5, v56062; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v26063; SI-NEXT:    v_or_b32_e32 v1, v1, v26064; SI-NEXT:    v_cvt_f16_f32_e32 v2, v46065; SI-NEXT:    v_cvt_f16_f32_e32 v4, v66066; SI-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v06067; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v26068; SI-NEXT:    v_or_b32_e32 v2, v3, v26069; SI-NEXT:    v_cndmask_b32_e32 v0, v2, v1, vcc6070; SI-NEXT:    v_lshrrev_b32_e32 v1, 16, v06071; SI-NEXT:    v_cvt_f32_f16_e32 v3, v46072; SI-NEXT:    v_cvt_f32_f16_e32 v4, v56073; SI-NEXT:    v_cvt_f32_f16_e32 v0, v06074; SI-NEXT:    v_cvt_f32_f16_e32 v1, v16075; SI-NEXT:    v_sub_f32_e32 v0, v4, v06076; SI-NEXT:    v_sub_f32_e32 v1, v3, v16077; SI-NEXT:    s_setpc_b64 s[30:31]6078;6079; VI-LABEL: fadd_select_fneg_fneg_v2f16:6080; VI:       ; %bb.0:6081; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6082; VI-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v06083; VI-NEXT:    v_cndmask_b32_e32 v0, v2, v1, vcc6084; VI-NEXT:    v_sub_f16_sdwa v1, v3, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_16085; VI-NEXT:    v_sub_f16_e32 v0, v3, v06086; VI-NEXT:    v_or_b32_e32 v0, v0, v16087; VI-NEXT:    s_setpc_b64 s[30:31]6088;6089; GFX11-LABEL: fadd_select_fneg_fneg_v2f16:6090; GFX11:       ; %bb.0:6091; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6092; GFX11-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v06093; GFX11-NEXT:    v_cndmask_b32_e32 v0, v2, v1, vcc_lo6094; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)6095; GFX11-NEXT:    v_pk_add_f16 v0, v3, v0 neg_lo:[0,1] neg_hi:[0,1]6096; GFX11-NEXT:    s_setpc_b64 s[30:31]6097  %cmp = icmp eq i32 %arg0, 06098  %neg.x = fneg <2 x half> %x6099  %neg.y = fneg <2 x half> %y6100  %select = select i1 %cmp, <2 x half> %neg.x, <2 x half> %neg.y6101  %add = fadd <2 x half> %select, %z6102  ret <2 x half> %add6103}6104 6105declare i32 @llvm.amdgcn.workitem.id.x() #16106declare half @llvm.sin.f16(half) #16107declare half @llvm.trunc.f16(half) #16108declare half @llvm.round.f16(half) #16109declare half @llvm.rint.f16(half) #16110declare half @llvm.nearbyint.f16(half) #16111declare half @llvm.roundeven.f16(half) #16112declare half @llvm.canonicalize.f16(half) #16113declare half @llvm.minnum.f16(half, half) #16114declare half @llvm.maxnum.f16(half, half) #16115declare half @llvm.fma.f16(half, half, half) #16116declare <2 x half> @llvm.fma.v2f16(<2 x half>, <2 x half>, <2 x half>)6117declare half @llvm.fmuladd.f16(half, half, half) #16118declare <4 x half> @llvm.fmuladd.v4f16(<4 x half>, <4 x half>, <4 x half>) #16119 6120attributes #0 = { nounwind "denormal-fp-math-f32"="preserve-sign,preserve-sign" }6121attributes #1 = { nounwind readnone }6122attributes #2 = { nounwind }6123attributes #3 = { nounwind "no-signed-zeros-fp-math"="true" }6124attributes #4 = { nounwind "amdgpu-ieee"="false" "denormal-fp-math-f32"="preserve-sign,preserve-sign" }6125;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:6126; GFX11-NSZ-FAKE16: {{.*}}6127; GFX11-SAFE-FAKE16: {{.*}}6128