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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=amdgcn -mcpu=hawaii -start-before=amdgpu-unify-divergent-exit-nodes -mattr=+flat-for-global < %s | FileCheck -enable-var-scope --check-prefixes=GCN,GCN-SAFE,SI,SI-SAFE %s3; RUN: llc -enable-no-signed-zeros-fp-math -mtriple=amdgcn -mcpu=hawaii -mattr=+flat-for-global -start-before=amdgpu-unify-divergent-exit-nodes < %s | FileCheck -enable-var-scope --check-prefixes=GCN,GCN-NSZ,SI,SI-NSZ %s4 5; RUN: llc -mtriple=amdgcn -mcpu=fiji -start-before=amdgpu-unify-divergent-exit-nodes < %s | FileCheck -enable-var-scope --check-prefixes=GCN,GCN-SAFE,VI,VI-SAFE %s6; RUN: llc -enable-no-signed-zeros-fp-math -mtriple=amdgcn -mcpu=fiji -start-before=amdgpu-unify-divergent-exit-nodes < %s | FileCheck -enable-var-scope --check-prefixes=GCN,GCN-NSZ,VI,VI-NSZ %s7 8; --------------------------------------------------------------------------------9; fadd tests10; --------------------------------------------------------------------------------11 12define amdgpu_kernel void @v_fneg_add_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {13; SI-SAFE-LABEL: v_fneg_add_f32:14; SI-SAFE: ; %bb.0:15; SI-SAFE-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x916; SI-SAFE-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd17; SI-SAFE-NEXT: v_lshlrev_b32_e32 v4, 2, v018; SI-SAFE-NEXT: s_waitcnt lgkmcnt(0)19; SI-SAFE-NEXT: v_mov_b32_e32 v1, s320; SI-SAFE-NEXT: v_add_i32_e32 v0, vcc, s2, v421; SI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc22; SI-SAFE-NEXT: v_mov_b32_e32 v3, s523; SI-SAFE-NEXT: v_add_i32_e32 v2, vcc, s4, v424; SI-SAFE-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc25; SI-SAFE-NEXT: flat_load_dword v5, v[0:1] glc26; SI-SAFE-NEXT: s_waitcnt vmcnt(0)27; SI-SAFE-NEXT: flat_load_dword v2, v[2:3] glc28; SI-SAFE-NEXT: s_waitcnt vmcnt(0)29; SI-SAFE-NEXT: v_mov_b32_e32 v1, s130; SI-SAFE-NEXT: v_add_i32_e32 v0, vcc, s0, v431; SI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc32; SI-SAFE-NEXT: v_add_f32_e32 v2, v5, v233; SI-SAFE-NEXT: v_xor_b32_e32 v2, 0x80000000, v234; SI-SAFE-NEXT: flat_store_dword v[0:1], v235; SI-SAFE-NEXT: s_endpgm36;37; SI-NSZ-LABEL: v_fneg_add_f32:38; SI-NSZ: ; %bb.0:39; SI-NSZ-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x940; SI-NSZ-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd41; SI-NSZ-NEXT: v_lshlrev_b32_e32 v4, 2, v042; SI-NSZ-NEXT: s_waitcnt lgkmcnt(0)43; SI-NSZ-NEXT: v_mov_b32_e32 v1, s344; SI-NSZ-NEXT: v_add_i32_e32 v0, vcc, s2, v445; SI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc46; SI-NSZ-NEXT: v_mov_b32_e32 v3, s547; SI-NSZ-NEXT: v_add_i32_e32 v2, vcc, s4, v448; SI-NSZ-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc49; SI-NSZ-NEXT: flat_load_dword v5, v[0:1] glc50; SI-NSZ-NEXT: s_waitcnt vmcnt(0)51; SI-NSZ-NEXT: flat_load_dword v2, v[2:3] glc52; SI-NSZ-NEXT: s_waitcnt vmcnt(0)53; SI-NSZ-NEXT: v_mov_b32_e32 v1, s154; SI-NSZ-NEXT: v_add_i32_e32 v0, vcc, s0, v455; SI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc56; SI-NSZ-NEXT: v_sub_f32_e64 v2, -v5, v257; SI-NSZ-NEXT: flat_store_dword v[0:1], v258; SI-NSZ-NEXT: s_endpgm59;60; VI-SAFE-LABEL: v_fneg_add_f32:61; VI-SAFE: ; %bb.0:62; VI-SAFE-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2463; VI-SAFE-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x3464; VI-SAFE-NEXT: v_lshlrev_b32_e32 v4, 2, v065; VI-SAFE-NEXT: s_waitcnt lgkmcnt(0)66; VI-SAFE-NEXT: v_mov_b32_e32 v1, s367; VI-SAFE-NEXT: v_add_u32_e32 v0, vcc, s2, v468; VI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc69; VI-SAFE-NEXT: v_mov_b32_e32 v3, s570; VI-SAFE-NEXT: v_add_u32_e32 v2, vcc, s4, v471; VI-SAFE-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc72; VI-SAFE-NEXT: flat_load_dword v5, v[0:1] glc73; VI-SAFE-NEXT: s_waitcnt vmcnt(0)74; VI-SAFE-NEXT: flat_load_dword v2, v[2:3] glc75; VI-SAFE-NEXT: s_waitcnt vmcnt(0)76; VI-SAFE-NEXT: v_mov_b32_e32 v1, s177; VI-SAFE-NEXT: v_add_u32_e32 v0, vcc, s0, v478; VI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc79; VI-SAFE-NEXT: v_add_f32_e32 v2, v5, v280; VI-SAFE-NEXT: v_xor_b32_e32 v2, 0x80000000, v281; VI-SAFE-NEXT: flat_store_dword v[0:1], v282; VI-SAFE-NEXT: s_endpgm83;84; VI-NSZ-LABEL: v_fneg_add_f32:85; VI-NSZ: ; %bb.0:86; VI-NSZ-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2487; VI-NSZ-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x3488; VI-NSZ-NEXT: v_lshlrev_b32_e32 v4, 2, v089; VI-NSZ-NEXT: s_waitcnt lgkmcnt(0)90; VI-NSZ-NEXT: v_mov_b32_e32 v1, s391; VI-NSZ-NEXT: v_add_u32_e32 v0, vcc, s2, v492; VI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc93; VI-NSZ-NEXT: v_mov_b32_e32 v3, s594; VI-NSZ-NEXT: v_add_u32_e32 v2, vcc, s4, v495; VI-NSZ-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc96; VI-NSZ-NEXT: flat_load_dword v5, v[0:1] glc97; VI-NSZ-NEXT: s_waitcnt vmcnt(0)98; VI-NSZ-NEXT: flat_load_dword v2, v[2:3] glc99; VI-NSZ-NEXT: s_waitcnt vmcnt(0)100; VI-NSZ-NEXT: v_mov_b32_e32 v1, s1101; VI-NSZ-NEXT: v_add_u32_e32 v0, vcc, s0, v4102; VI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc103; VI-NSZ-NEXT: v_sub_f32_e64 v2, -v5, v2104; VI-NSZ-NEXT: flat_store_dword v[0:1], v2105; VI-NSZ-NEXT: s_endpgm106 %tid = call i32 @llvm.amdgcn.workitem.id.x()107 %tid.ext = sext i32 %tid to i64108 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext109 %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext110 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext111 %a = load volatile float, ptr addrspace(1) %a.gep112 %b = load volatile float, ptr addrspace(1) %b.gep113 %add = fadd float %a, %b114 %fneg = fneg float %add115 store float %fneg, ptr addrspace(1) %out.gep116 ret void117}118 119define amdgpu_kernel void @v_fneg_add_store_use_add_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {120; SI-LABEL: v_fneg_add_store_use_add_f32:121; SI: ; %bb.0:122; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9123; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd124; SI-NEXT: v_lshlrev_b32_e32 v2, 2, v0125; SI-NEXT: s_waitcnt lgkmcnt(0)126; SI-NEXT: v_mov_b32_e32 v1, s3127; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v2128; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc129; SI-NEXT: v_mov_b32_e32 v3, s5130; SI-NEXT: v_add_i32_e32 v2, vcc, s4, v2131; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc132; SI-NEXT: flat_load_dword v4, v[0:1] glc133; SI-NEXT: s_waitcnt vmcnt(0)134; SI-NEXT: flat_load_dword v2, v[2:3] glc135; SI-NEXT: s_waitcnt vmcnt(0)136; SI-NEXT: v_mov_b32_e32 v0, s0137; SI-NEXT: v_mov_b32_e32 v1, s1138; SI-NEXT: v_add_f32_e32 v2, v4, v2139; SI-NEXT: v_xor_b32_e32 v3, 0x80000000, v2140; SI-NEXT: flat_store_dword v[0:1], v3141; SI-NEXT: s_waitcnt vmcnt(0)142; SI-NEXT: flat_store_dword v[0:1], v2143; SI-NEXT: s_waitcnt vmcnt(0)144; SI-NEXT: s_endpgm145;146; VI-LABEL: v_fneg_add_store_use_add_f32:147; VI: ; %bb.0:148; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24149; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34150; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0151; VI-NEXT: s_waitcnt lgkmcnt(0)152; VI-NEXT: v_mov_b32_e32 v1, s3153; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2154; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc155; VI-NEXT: v_mov_b32_e32 v3, s5156; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v2157; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc158; VI-NEXT: flat_load_dword v4, v[0:1] glc159; VI-NEXT: s_waitcnt vmcnt(0)160; VI-NEXT: flat_load_dword v2, v[2:3] glc161; VI-NEXT: s_waitcnt vmcnt(0)162; VI-NEXT: v_mov_b32_e32 v0, s0163; VI-NEXT: v_mov_b32_e32 v1, s1164; VI-NEXT: v_add_f32_e32 v2, v4, v2165; VI-NEXT: v_xor_b32_e32 v3, 0x80000000, v2166; VI-NEXT: flat_store_dword v[0:1], v3167; VI-NEXT: s_waitcnt vmcnt(0)168; VI-NEXT: flat_store_dword v[0:1], v2169; VI-NEXT: s_waitcnt vmcnt(0)170; VI-NEXT: s_endpgm171 %tid = call i32 @llvm.amdgcn.workitem.id.x()172 %tid.ext = sext i32 %tid to i64173 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext174 %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext175 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext176 %a = load volatile float, ptr addrspace(1) %a.gep177 %b = load volatile float, ptr addrspace(1) %b.gep178 %add = fadd float %a, %b179 %fneg = fneg float %add180 store volatile float %fneg, ptr addrspace(1) %out181 store volatile float %add, ptr addrspace(1) %out182 ret void183}184 185define amdgpu_kernel void @v_fneg_add_multi_use_add_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {186; SI-SAFE-LABEL: v_fneg_add_multi_use_add_f32:187; SI-SAFE: ; %bb.0:188; SI-SAFE-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9189; SI-SAFE-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd190; SI-SAFE-NEXT: v_lshlrev_b32_e32 v2, 2, v0191; SI-SAFE-NEXT: s_waitcnt lgkmcnt(0)192; SI-SAFE-NEXT: v_mov_b32_e32 v1, s3193; SI-SAFE-NEXT: v_add_i32_e32 v0, vcc, s2, v2194; SI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc195; SI-SAFE-NEXT: v_mov_b32_e32 v3, s5196; SI-SAFE-NEXT: v_add_i32_e32 v2, vcc, s4, v2197; SI-SAFE-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc198; SI-SAFE-NEXT: flat_load_dword v4, v[0:1] glc199; SI-SAFE-NEXT: s_waitcnt vmcnt(0)200; SI-SAFE-NEXT: flat_load_dword v2, v[2:3] glc201; SI-SAFE-NEXT: s_waitcnt vmcnt(0)202; SI-SAFE-NEXT: v_mov_b32_e32 v0, s0203; SI-SAFE-NEXT: v_mov_b32_e32 v1, s1204; SI-SAFE-NEXT: v_add_f32_e32 v2, v4, v2205; SI-SAFE-NEXT: v_xor_b32_e32 v3, 0x80000000, v2206; SI-SAFE-NEXT: v_mul_f32_e32 v2, 4.0, v2207; SI-SAFE-NEXT: flat_store_dword v[0:1], v3208; SI-SAFE-NEXT: s_waitcnt vmcnt(0)209; SI-SAFE-NEXT: flat_store_dword v[0:1], v2210; SI-SAFE-NEXT: s_waitcnt vmcnt(0)211; SI-SAFE-NEXT: s_endpgm212;213; SI-NSZ-LABEL: v_fneg_add_multi_use_add_f32:214; SI-NSZ: ; %bb.0:215; SI-NSZ-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9216; SI-NSZ-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd217; SI-NSZ-NEXT: v_lshlrev_b32_e32 v2, 2, v0218; SI-NSZ-NEXT: s_waitcnt lgkmcnt(0)219; SI-NSZ-NEXT: v_mov_b32_e32 v1, s3220; SI-NSZ-NEXT: v_add_i32_e32 v0, vcc, s2, v2221; SI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc222; SI-NSZ-NEXT: v_mov_b32_e32 v3, s5223; SI-NSZ-NEXT: v_add_i32_e32 v2, vcc, s4, v2224; SI-NSZ-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc225; SI-NSZ-NEXT: flat_load_dword v4, v[0:1] glc226; SI-NSZ-NEXT: s_waitcnt vmcnt(0)227; SI-NSZ-NEXT: flat_load_dword v2, v[2:3] glc228; SI-NSZ-NEXT: s_waitcnt vmcnt(0)229; SI-NSZ-NEXT: v_mov_b32_e32 v0, s0230; SI-NSZ-NEXT: v_mov_b32_e32 v1, s1231; SI-NSZ-NEXT: v_sub_f32_e64 v2, -v4, v2232; SI-NSZ-NEXT: v_mul_f32_e32 v3, -4.0, v2233; SI-NSZ-NEXT: flat_store_dword v[0:1], v2234; SI-NSZ-NEXT: s_waitcnt vmcnt(0)235; SI-NSZ-NEXT: flat_store_dword v[0:1], v3236; SI-NSZ-NEXT: s_waitcnt vmcnt(0)237; SI-NSZ-NEXT: s_endpgm238;239; VI-SAFE-LABEL: v_fneg_add_multi_use_add_f32:240; VI-SAFE: ; %bb.0:241; VI-SAFE-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24242; VI-SAFE-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34243; VI-SAFE-NEXT: v_lshlrev_b32_e32 v2, 2, v0244; VI-SAFE-NEXT: s_waitcnt lgkmcnt(0)245; VI-SAFE-NEXT: v_mov_b32_e32 v1, s3246; VI-SAFE-NEXT: v_add_u32_e32 v0, vcc, s2, v2247; VI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc248; VI-SAFE-NEXT: v_mov_b32_e32 v3, s5249; VI-SAFE-NEXT: v_add_u32_e32 v2, vcc, s4, v2250; VI-SAFE-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc251; VI-SAFE-NEXT: flat_load_dword v4, v[0:1] glc252; VI-SAFE-NEXT: s_waitcnt vmcnt(0)253; VI-SAFE-NEXT: flat_load_dword v2, v[2:3] glc254; VI-SAFE-NEXT: s_waitcnt vmcnt(0)255; VI-SAFE-NEXT: v_mov_b32_e32 v0, s0256; VI-SAFE-NEXT: v_mov_b32_e32 v1, s1257; VI-SAFE-NEXT: v_add_f32_e32 v2, v4, v2258; VI-SAFE-NEXT: v_xor_b32_e32 v3, 0x80000000, v2259; VI-SAFE-NEXT: v_mul_f32_e32 v2, 4.0, v2260; VI-SAFE-NEXT: flat_store_dword v[0:1], v3261; VI-SAFE-NEXT: s_waitcnt vmcnt(0)262; VI-SAFE-NEXT: flat_store_dword v[0:1], v2263; VI-SAFE-NEXT: s_waitcnt vmcnt(0)264; VI-SAFE-NEXT: s_endpgm265;266; VI-NSZ-LABEL: v_fneg_add_multi_use_add_f32:267; VI-NSZ: ; %bb.0:268; VI-NSZ-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24269; VI-NSZ-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34270; VI-NSZ-NEXT: v_lshlrev_b32_e32 v2, 2, v0271; VI-NSZ-NEXT: s_waitcnt lgkmcnt(0)272; VI-NSZ-NEXT: v_mov_b32_e32 v1, s3273; VI-NSZ-NEXT: v_add_u32_e32 v0, vcc, s2, v2274; VI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc275; VI-NSZ-NEXT: v_mov_b32_e32 v3, s5276; VI-NSZ-NEXT: v_add_u32_e32 v2, vcc, s4, v2277; VI-NSZ-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc278; VI-NSZ-NEXT: flat_load_dword v4, v[0:1] glc279; VI-NSZ-NEXT: s_waitcnt vmcnt(0)280; VI-NSZ-NEXT: flat_load_dword v2, v[2:3] glc281; VI-NSZ-NEXT: s_waitcnt vmcnt(0)282; VI-NSZ-NEXT: v_mov_b32_e32 v0, s0283; VI-NSZ-NEXT: v_mov_b32_e32 v1, s1284; VI-NSZ-NEXT: v_sub_f32_e64 v2, -v4, v2285; VI-NSZ-NEXT: v_mul_f32_e32 v3, -4.0, v2286; VI-NSZ-NEXT: flat_store_dword v[0:1], v2287; VI-NSZ-NEXT: s_waitcnt vmcnt(0)288; VI-NSZ-NEXT: flat_store_dword v[0:1], v3289; VI-NSZ-NEXT: s_waitcnt vmcnt(0)290; VI-NSZ-NEXT: s_endpgm291 %tid = call i32 @llvm.amdgcn.workitem.id.x()292 %tid.ext = sext i32 %tid to i64293 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext294 %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext295 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext296 %a = load volatile float, ptr addrspace(1) %a.gep297 %b = load volatile float, ptr addrspace(1) %b.gep298 %add = fadd float %a, %b299 %fneg = fneg float %add300 %use1 = fmul float %add, 4.0301 store volatile float %fneg, ptr addrspace(1) %out302 store volatile float %use1, ptr addrspace(1) %out303 ret void304}305 306define amdgpu_kernel void @v_fneg_add_fneg_x_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {307; SI-SAFE-LABEL: v_fneg_add_fneg_x_f32:308; SI-SAFE: ; %bb.0:309; SI-SAFE-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9310; SI-SAFE-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd311; SI-SAFE-NEXT: v_lshlrev_b32_e32 v2, 2, v0312; SI-SAFE-NEXT: s_waitcnt lgkmcnt(0)313; SI-SAFE-NEXT: v_mov_b32_e32 v1, s3314; SI-SAFE-NEXT: v_add_i32_e32 v0, vcc, s2, v2315; SI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc316; SI-SAFE-NEXT: v_mov_b32_e32 v3, s5317; SI-SAFE-NEXT: v_add_i32_e32 v2, vcc, s4, v2318; SI-SAFE-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc319; SI-SAFE-NEXT: flat_load_dword v0, v[0:1] glc320; SI-SAFE-NEXT: s_waitcnt vmcnt(0)321; SI-SAFE-NEXT: flat_load_dword v1, v[2:3] glc322; SI-SAFE-NEXT: s_waitcnt vmcnt(0)323; SI-SAFE-NEXT: v_sub_f32_e32 v0, v1, v0324; SI-SAFE-NEXT: v_xor_b32_e32 v2, 0x80000000, v0325; SI-SAFE-NEXT: v_mov_b32_e32 v0, s0326; SI-SAFE-NEXT: v_mov_b32_e32 v1, s1327; SI-SAFE-NEXT: flat_store_dword v[0:1], v2328; SI-SAFE-NEXT: s_waitcnt vmcnt(0)329; SI-SAFE-NEXT: s_endpgm330;331; SI-NSZ-LABEL: v_fneg_add_fneg_x_f32:332; SI-NSZ: ; %bb.0:333; SI-NSZ-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9334; SI-NSZ-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd335; SI-NSZ-NEXT: v_lshlrev_b32_e32 v2, 2, v0336; SI-NSZ-NEXT: s_waitcnt lgkmcnt(0)337; SI-NSZ-NEXT: v_mov_b32_e32 v1, s3338; SI-NSZ-NEXT: v_add_i32_e32 v0, vcc, s2, v2339; SI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc340; SI-NSZ-NEXT: v_mov_b32_e32 v3, s5341; SI-NSZ-NEXT: v_add_i32_e32 v2, vcc, s4, v2342; SI-NSZ-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc343; SI-NSZ-NEXT: flat_load_dword v0, v[0:1] glc344; SI-NSZ-NEXT: s_waitcnt vmcnt(0)345; SI-NSZ-NEXT: flat_load_dword v1, v[2:3] glc346; SI-NSZ-NEXT: s_waitcnt vmcnt(0)347; SI-NSZ-NEXT: v_sub_f32_e32 v2, v0, v1348; SI-NSZ-NEXT: v_mov_b32_e32 v0, s0349; SI-NSZ-NEXT: v_mov_b32_e32 v1, s1350; SI-NSZ-NEXT: flat_store_dword v[0:1], v2351; SI-NSZ-NEXT: s_waitcnt vmcnt(0)352; SI-NSZ-NEXT: s_endpgm353;354; VI-SAFE-LABEL: v_fneg_add_fneg_x_f32:355; VI-SAFE: ; %bb.0:356; VI-SAFE-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24357; VI-SAFE-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34358; VI-SAFE-NEXT: v_lshlrev_b32_e32 v2, 2, v0359; VI-SAFE-NEXT: s_waitcnt lgkmcnt(0)360; VI-SAFE-NEXT: v_mov_b32_e32 v1, s3361; VI-SAFE-NEXT: v_add_u32_e32 v0, vcc, s2, v2362; VI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc363; VI-SAFE-NEXT: v_mov_b32_e32 v3, s5364; VI-SAFE-NEXT: v_add_u32_e32 v2, vcc, s4, v2365; VI-SAFE-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc366; VI-SAFE-NEXT: flat_load_dword v0, v[0:1] glc367; VI-SAFE-NEXT: s_waitcnt vmcnt(0)368; VI-SAFE-NEXT: flat_load_dword v1, v[2:3] glc369; VI-SAFE-NEXT: s_waitcnt vmcnt(0)370; VI-SAFE-NEXT: v_sub_f32_e32 v0, v1, v0371; VI-SAFE-NEXT: v_xor_b32_e32 v2, 0x80000000, v0372; VI-SAFE-NEXT: v_mov_b32_e32 v0, s0373; VI-SAFE-NEXT: v_mov_b32_e32 v1, s1374; VI-SAFE-NEXT: flat_store_dword v[0:1], v2375; VI-SAFE-NEXT: s_waitcnt vmcnt(0)376; VI-SAFE-NEXT: s_endpgm377;378; VI-NSZ-LABEL: v_fneg_add_fneg_x_f32:379; VI-NSZ: ; %bb.0:380; VI-NSZ-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24381; VI-NSZ-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34382; VI-NSZ-NEXT: v_lshlrev_b32_e32 v2, 2, v0383; VI-NSZ-NEXT: s_waitcnt lgkmcnt(0)384; VI-NSZ-NEXT: v_mov_b32_e32 v1, s3385; VI-NSZ-NEXT: v_add_u32_e32 v0, vcc, s2, v2386; VI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc387; VI-NSZ-NEXT: v_mov_b32_e32 v3, s5388; VI-NSZ-NEXT: v_add_u32_e32 v2, vcc, s4, v2389; VI-NSZ-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc390; VI-NSZ-NEXT: flat_load_dword v0, v[0:1] glc391; VI-NSZ-NEXT: s_waitcnt vmcnt(0)392; VI-NSZ-NEXT: flat_load_dword v1, v[2:3] glc393; VI-NSZ-NEXT: s_waitcnt vmcnt(0)394; VI-NSZ-NEXT: v_sub_f32_e32 v2, v0, v1395; VI-NSZ-NEXT: v_mov_b32_e32 v0, s0396; VI-NSZ-NEXT: v_mov_b32_e32 v1, s1397; VI-NSZ-NEXT: flat_store_dword v[0:1], v2398; VI-NSZ-NEXT: s_waitcnt vmcnt(0)399; VI-NSZ-NEXT: s_endpgm400 %tid = call i32 @llvm.amdgcn.workitem.id.x()401 %tid.ext = sext i32 %tid to i64402 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext403 %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext404 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext405 %a = load volatile float, ptr addrspace(1) %a.gep406 %b = load volatile float, ptr addrspace(1) %b.gep407 %fneg.a = fneg float %a408 %add = fadd float %fneg.a, %b409 %fneg = fneg float %add410 store volatile float %fneg, ptr addrspace(1) %out411 ret void412}413 414define amdgpu_kernel void @v_fneg_add_x_fneg_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {415; SI-SAFE-LABEL: v_fneg_add_x_fneg_f32:416; SI-SAFE: ; %bb.0:417; SI-SAFE-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9418; SI-SAFE-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd419; SI-SAFE-NEXT: v_lshlrev_b32_e32 v2, 2, v0420; SI-SAFE-NEXT: s_waitcnt lgkmcnt(0)421; SI-SAFE-NEXT: v_mov_b32_e32 v1, s3422; SI-SAFE-NEXT: v_add_i32_e32 v0, vcc, s2, v2423; SI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc424; SI-SAFE-NEXT: v_mov_b32_e32 v3, s5425; SI-SAFE-NEXT: v_add_i32_e32 v2, vcc, s4, v2426; SI-SAFE-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc427; SI-SAFE-NEXT: flat_load_dword v0, v[0:1] glc428; SI-SAFE-NEXT: s_waitcnt vmcnt(0)429; SI-SAFE-NEXT: flat_load_dword v1, v[2:3] glc430; SI-SAFE-NEXT: s_waitcnt vmcnt(0)431; SI-SAFE-NEXT: v_sub_f32_e32 v0, v0, v1432; SI-SAFE-NEXT: v_xor_b32_e32 v2, 0x80000000, v0433; SI-SAFE-NEXT: v_mov_b32_e32 v0, s0434; SI-SAFE-NEXT: v_mov_b32_e32 v1, s1435; SI-SAFE-NEXT: flat_store_dword v[0:1], v2436; SI-SAFE-NEXT: s_waitcnt vmcnt(0)437; SI-SAFE-NEXT: s_endpgm438;439; SI-NSZ-LABEL: v_fneg_add_x_fneg_f32:440; SI-NSZ: ; %bb.0:441; SI-NSZ-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9442; SI-NSZ-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd443; SI-NSZ-NEXT: v_lshlrev_b32_e32 v2, 2, v0444; SI-NSZ-NEXT: s_waitcnt lgkmcnt(0)445; SI-NSZ-NEXT: v_mov_b32_e32 v1, s3446; SI-NSZ-NEXT: v_add_i32_e32 v0, vcc, s2, v2447; SI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc448; SI-NSZ-NEXT: v_mov_b32_e32 v3, s5449; SI-NSZ-NEXT: v_add_i32_e32 v2, vcc, s4, v2450; SI-NSZ-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc451; SI-NSZ-NEXT: flat_load_dword v0, v[0:1] glc452; SI-NSZ-NEXT: s_waitcnt vmcnt(0)453; SI-NSZ-NEXT: flat_load_dword v1, v[2:3] glc454; SI-NSZ-NEXT: s_waitcnt vmcnt(0)455; SI-NSZ-NEXT: v_sub_f32_e32 v2, v1, v0456; SI-NSZ-NEXT: v_mov_b32_e32 v0, s0457; SI-NSZ-NEXT: v_mov_b32_e32 v1, s1458; SI-NSZ-NEXT: flat_store_dword v[0:1], v2459; SI-NSZ-NEXT: s_waitcnt vmcnt(0)460; SI-NSZ-NEXT: s_endpgm461;462; VI-SAFE-LABEL: v_fneg_add_x_fneg_f32:463; VI-SAFE: ; %bb.0:464; VI-SAFE-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24465; VI-SAFE-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34466; VI-SAFE-NEXT: v_lshlrev_b32_e32 v2, 2, v0467; VI-SAFE-NEXT: s_waitcnt lgkmcnt(0)468; VI-SAFE-NEXT: v_mov_b32_e32 v1, s3469; VI-SAFE-NEXT: v_add_u32_e32 v0, vcc, s2, v2470; VI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc471; VI-SAFE-NEXT: v_mov_b32_e32 v3, s5472; VI-SAFE-NEXT: v_add_u32_e32 v2, vcc, s4, v2473; VI-SAFE-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc474; VI-SAFE-NEXT: flat_load_dword v0, v[0:1] glc475; VI-SAFE-NEXT: s_waitcnt vmcnt(0)476; VI-SAFE-NEXT: flat_load_dword v1, v[2:3] glc477; VI-SAFE-NEXT: s_waitcnt vmcnt(0)478; VI-SAFE-NEXT: v_sub_f32_e32 v0, v0, v1479; VI-SAFE-NEXT: v_xor_b32_e32 v2, 0x80000000, v0480; VI-SAFE-NEXT: v_mov_b32_e32 v0, s0481; VI-SAFE-NEXT: v_mov_b32_e32 v1, s1482; VI-SAFE-NEXT: flat_store_dword v[0:1], v2483; VI-SAFE-NEXT: s_waitcnt vmcnt(0)484; VI-SAFE-NEXT: s_endpgm485;486; VI-NSZ-LABEL: v_fneg_add_x_fneg_f32:487; VI-NSZ: ; %bb.0:488; VI-NSZ-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24489; VI-NSZ-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34490; VI-NSZ-NEXT: v_lshlrev_b32_e32 v2, 2, v0491; VI-NSZ-NEXT: s_waitcnt lgkmcnt(0)492; VI-NSZ-NEXT: v_mov_b32_e32 v1, s3493; VI-NSZ-NEXT: v_add_u32_e32 v0, vcc, s2, v2494; VI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc495; VI-NSZ-NEXT: v_mov_b32_e32 v3, s5496; VI-NSZ-NEXT: v_add_u32_e32 v2, vcc, s4, v2497; VI-NSZ-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc498; VI-NSZ-NEXT: flat_load_dword v0, v[0:1] glc499; VI-NSZ-NEXT: s_waitcnt vmcnt(0)500; VI-NSZ-NEXT: flat_load_dword v1, v[2:3] glc501; VI-NSZ-NEXT: s_waitcnt vmcnt(0)502; VI-NSZ-NEXT: v_sub_f32_e32 v2, v1, v0503; VI-NSZ-NEXT: v_mov_b32_e32 v0, s0504; VI-NSZ-NEXT: v_mov_b32_e32 v1, s1505; VI-NSZ-NEXT: flat_store_dword v[0:1], v2506; VI-NSZ-NEXT: s_waitcnt vmcnt(0)507; VI-NSZ-NEXT: s_endpgm508 %tid = call i32 @llvm.amdgcn.workitem.id.x()509 %tid.ext = sext i32 %tid to i64510 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext511 %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext512 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext513 %a = load volatile float, ptr addrspace(1) %a.gep514 %b = load volatile float, ptr addrspace(1) %b.gep515 %fneg.b = fneg float %b516 %add = fadd float %a, %fneg.b517 %fneg = fneg float %add518 store volatile float %fneg, ptr addrspace(1) %out519 ret void520}521 522define amdgpu_kernel void @v_fneg_add_fneg_fneg_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {523; SI-SAFE-LABEL: v_fneg_add_fneg_fneg_f32:524; SI-SAFE: ; %bb.0:525; SI-SAFE-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9526; SI-SAFE-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd527; SI-SAFE-NEXT: v_lshlrev_b32_e32 v2, 2, v0528; SI-SAFE-NEXT: s_waitcnt lgkmcnt(0)529; SI-SAFE-NEXT: v_mov_b32_e32 v1, s3530; SI-SAFE-NEXT: v_add_i32_e32 v0, vcc, s2, v2531; SI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc532; SI-SAFE-NEXT: v_mov_b32_e32 v3, s5533; SI-SAFE-NEXT: v_add_i32_e32 v2, vcc, s4, v2534; SI-SAFE-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc535; SI-SAFE-NEXT: flat_load_dword v0, v[0:1] glc536; SI-SAFE-NEXT: s_waitcnt vmcnt(0)537; SI-SAFE-NEXT: flat_load_dword v1, v[2:3] glc538; SI-SAFE-NEXT: s_waitcnt vmcnt(0)539; SI-SAFE-NEXT: v_sub_f32_e64 v0, -v0, v1540; SI-SAFE-NEXT: v_xor_b32_e32 v2, 0x80000000, v0541; SI-SAFE-NEXT: v_mov_b32_e32 v0, s0542; SI-SAFE-NEXT: v_mov_b32_e32 v1, s1543; SI-SAFE-NEXT: flat_store_dword v[0:1], v2544; SI-SAFE-NEXT: s_waitcnt vmcnt(0)545; SI-SAFE-NEXT: s_endpgm546;547; SI-NSZ-LABEL: v_fneg_add_fneg_fneg_f32:548; SI-NSZ: ; %bb.0:549; SI-NSZ-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9550; SI-NSZ-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd551; SI-NSZ-NEXT: v_lshlrev_b32_e32 v2, 2, v0552; SI-NSZ-NEXT: s_waitcnt lgkmcnt(0)553; SI-NSZ-NEXT: v_mov_b32_e32 v1, s3554; SI-NSZ-NEXT: v_add_i32_e32 v0, vcc, s2, v2555; SI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc556; SI-NSZ-NEXT: v_mov_b32_e32 v3, s5557; SI-NSZ-NEXT: v_add_i32_e32 v2, vcc, s4, v2558; SI-NSZ-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc559; SI-NSZ-NEXT: flat_load_dword v0, v[0:1] glc560; SI-NSZ-NEXT: s_waitcnt vmcnt(0)561; SI-NSZ-NEXT: flat_load_dword v1, v[2:3] glc562; SI-NSZ-NEXT: s_waitcnt vmcnt(0)563; SI-NSZ-NEXT: v_add_f32_e32 v2, v0, v1564; SI-NSZ-NEXT: v_mov_b32_e32 v0, s0565; SI-NSZ-NEXT: v_mov_b32_e32 v1, s1566; SI-NSZ-NEXT: flat_store_dword v[0:1], v2567; SI-NSZ-NEXT: s_waitcnt vmcnt(0)568; SI-NSZ-NEXT: s_endpgm569;570; VI-SAFE-LABEL: v_fneg_add_fneg_fneg_f32:571; VI-SAFE: ; %bb.0:572; VI-SAFE-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24573; VI-SAFE-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34574; VI-SAFE-NEXT: v_lshlrev_b32_e32 v2, 2, v0575; VI-SAFE-NEXT: s_waitcnt lgkmcnt(0)576; VI-SAFE-NEXT: v_mov_b32_e32 v1, s3577; VI-SAFE-NEXT: v_add_u32_e32 v0, vcc, s2, v2578; VI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc579; VI-SAFE-NEXT: v_mov_b32_e32 v3, s5580; VI-SAFE-NEXT: v_add_u32_e32 v2, vcc, s4, v2581; VI-SAFE-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc582; VI-SAFE-NEXT: flat_load_dword v0, v[0:1] glc583; VI-SAFE-NEXT: s_waitcnt vmcnt(0)584; VI-SAFE-NEXT: flat_load_dword v1, v[2:3] glc585; VI-SAFE-NEXT: s_waitcnt vmcnt(0)586; VI-SAFE-NEXT: v_sub_f32_e64 v0, -v0, v1587; VI-SAFE-NEXT: v_xor_b32_e32 v2, 0x80000000, v0588; VI-SAFE-NEXT: v_mov_b32_e32 v0, s0589; VI-SAFE-NEXT: v_mov_b32_e32 v1, s1590; VI-SAFE-NEXT: flat_store_dword v[0:1], v2591; VI-SAFE-NEXT: s_waitcnt vmcnt(0)592; VI-SAFE-NEXT: s_endpgm593;594; VI-NSZ-LABEL: v_fneg_add_fneg_fneg_f32:595; VI-NSZ: ; %bb.0:596; VI-NSZ-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24597; VI-NSZ-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34598; VI-NSZ-NEXT: v_lshlrev_b32_e32 v2, 2, v0599; VI-NSZ-NEXT: s_waitcnt lgkmcnt(0)600; VI-NSZ-NEXT: v_mov_b32_e32 v1, s3601; VI-NSZ-NEXT: v_add_u32_e32 v0, vcc, s2, v2602; VI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc603; VI-NSZ-NEXT: v_mov_b32_e32 v3, s5604; VI-NSZ-NEXT: v_add_u32_e32 v2, vcc, s4, v2605; VI-NSZ-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc606; VI-NSZ-NEXT: flat_load_dword v0, v[0:1] glc607; VI-NSZ-NEXT: s_waitcnt vmcnt(0)608; VI-NSZ-NEXT: flat_load_dword v1, v[2:3] glc609; VI-NSZ-NEXT: s_waitcnt vmcnt(0)610; VI-NSZ-NEXT: v_add_f32_e32 v2, v0, v1611; VI-NSZ-NEXT: v_mov_b32_e32 v0, s0612; VI-NSZ-NEXT: v_mov_b32_e32 v1, s1613; VI-NSZ-NEXT: flat_store_dword v[0:1], v2614; VI-NSZ-NEXT: s_waitcnt vmcnt(0)615; VI-NSZ-NEXT: s_endpgm616 %tid = call i32 @llvm.amdgcn.workitem.id.x()617 %tid.ext = sext i32 %tid to i64618 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext619 %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext620 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext621 %a = load volatile float, ptr addrspace(1) %a.gep622 %b = load volatile float, ptr addrspace(1) %b.gep623 %fneg.a = fneg float %a624 %fneg.b = fneg float %b625 %add = fadd float %fneg.a, %fneg.b626 %fneg = fneg float %add627 store volatile float %fneg, ptr addrspace(1) %out628 ret void629}630 631define amdgpu_kernel void @v_fneg_add_store_use_fneg_x_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {632; SI-SAFE-LABEL: v_fneg_add_store_use_fneg_x_f32:633; SI-SAFE: ; %bb.0:634; SI-SAFE-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9635; SI-SAFE-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd636; SI-SAFE-NEXT: v_lshlrev_b32_e32 v2, 2, v0637; SI-SAFE-NEXT: s_waitcnt lgkmcnt(0)638; SI-SAFE-NEXT: v_mov_b32_e32 v1, s3639; SI-SAFE-NEXT: v_add_i32_e32 v0, vcc, s2, v2640; SI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc641; SI-SAFE-NEXT: v_mov_b32_e32 v3, s5642; SI-SAFE-NEXT: v_add_i32_e32 v2, vcc, s4, v2643; SI-SAFE-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc644; SI-SAFE-NEXT: flat_load_dword v4, v[0:1] glc645; SI-SAFE-NEXT: s_waitcnt vmcnt(0)646; SI-SAFE-NEXT: flat_load_dword v2, v[2:3] glc647; SI-SAFE-NEXT: s_waitcnt vmcnt(0)648; SI-SAFE-NEXT: v_mov_b32_e32 v0, s0649; SI-SAFE-NEXT: v_mov_b32_e32 v1, s1650; SI-SAFE-NEXT: v_xor_b32_e32 v3, 0x80000000, v4651; SI-SAFE-NEXT: v_sub_f32_e32 v2, v2, v4652; SI-SAFE-NEXT: v_xor_b32_e32 v2, 0x80000000, v2653; SI-SAFE-NEXT: flat_store_dword v[0:1], v2654; SI-SAFE-NEXT: s_waitcnt vmcnt(0)655; SI-SAFE-NEXT: flat_store_dword v[0:1], v3656; SI-SAFE-NEXT: s_waitcnt vmcnt(0)657; SI-SAFE-NEXT: s_endpgm658;659; SI-NSZ-LABEL: v_fneg_add_store_use_fneg_x_f32:660; SI-NSZ: ; %bb.0:661; SI-NSZ-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9662; SI-NSZ-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd663; SI-NSZ-NEXT: v_lshlrev_b32_e32 v2, 2, v0664; SI-NSZ-NEXT: s_waitcnt lgkmcnt(0)665; SI-NSZ-NEXT: v_mov_b32_e32 v1, s3666; SI-NSZ-NEXT: v_add_i32_e32 v0, vcc, s2, v2667; SI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc668; SI-NSZ-NEXT: v_mov_b32_e32 v3, s5669; SI-NSZ-NEXT: v_add_i32_e32 v2, vcc, s4, v2670; SI-NSZ-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc671; SI-NSZ-NEXT: flat_load_dword v4, v[0:1] glc672; SI-NSZ-NEXT: s_waitcnt vmcnt(0)673; SI-NSZ-NEXT: flat_load_dword v2, v[2:3] glc674; SI-NSZ-NEXT: s_waitcnt vmcnt(0)675; SI-NSZ-NEXT: v_mov_b32_e32 v0, s0676; SI-NSZ-NEXT: v_mov_b32_e32 v1, s1677; SI-NSZ-NEXT: v_xor_b32_e32 v3, 0x80000000, v4678; SI-NSZ-NEXT: v_sub_f32_e32 v2, v4, v2679; SI-NSZ-NEXT: flat_store_dword v[0:1], v2680; SI-NSZ-NEXT: s_waitcnt vmcnt(0)681; SI-NSZ-NEXT: flat_store_dword v[0:1], v3682; SI-NSZ-NEXT: s_waitcnt vmcnt(0)683; SI-NSZ-NEXT: s_endpgm684;685; VI-SAFE-LABEL: v_fneg_add_store_use_fneg_x_f32:686; VI-SAFE: ; %bb.0:687; VI-SAFE-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24688; VI-SAFE-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34689; VI-SAFE-NEXT: v_lshlrev_b32_e32 v2, 2, v0690; VI-SAFE-NEXT: s_waitcnt lgkmcnt(0)691; VI-SAFE-NEXT: v_mov_b32_e32 v1, s3692; VI-SAFE-NEXT: v_add_u32_e32 v0, vcc, s2, v2693; VI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc694; VI-SAFE-NEXT: v_mov_b32_e32 v3, s5695; VI-SAFE-NEXT: v_add_u32_e32 v2, vcc, s4, v2696; VI-SAFE-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc697; VI-SAFE-NEXT: flat_load_dword v4, v[0:1] glc698; VI-SAFE-NEXT: s_waitcnt vmcnt(0)699; VI-SAFE-NEXT: flat_load_dword v2, v[2:3] glc700; VI-SAFE-NEXT: s_waitcnt vmcnt(0)701; VI-SAFE-NEXT: v_mov_b32_e32 v0, s0702; VI-SAFE-NEXT: v_mov_b32_e32 v1, s1703; VI-SAFE-NEXT: v_xor_b32_e32 v3, 0x80000000, v4704; VI-SAFE-NEXT: v_sub_f32_e32 v2, v2, v4705; VI-SAFE-NEXT: v_xor_b32_e32 v2, 0x80000000, v2706; VI-SAFE-NEXT: flat_store_dword v[0:1], v2707; VI-SAFE-NEXT: s_waitcnt vmcnt(0)708; VI-SAFE-NEXT: flat_store_dword v[0:1], v3709; VI-SAFE-NEXT: s_waitcnt vmcnt(0)710; VI-SAFE-NEXT: s_endpgm711;712; VI-NSZ-LABEL: v_fneg_add_store_use_fneg_x_f32:713; VI-NSZ: ; %bb.0:714; VI-NSZ-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24715; VI-NSZ-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34716; VI-NSZ-NEXT: v_lshlrev_b32_e32 v2, 2, v0717; VI-NSZ-NEXT: s_waitcnt lgkmcnt(0)718; VI-NSZ-NEXT: v_mov_b32_e32 v1, s3719; VI-NSZ-NEXT: v_add_u32_e32 v0, vcc, s2, v2720; VI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc721; VI-NSZ-NEXT: v_mov_b32_e32 v3, s5722; VI-NSZ-NEXT: v_add_u32_e32 v2, vcc, s4, v2723; VI-NSZ-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc724; VI-NSZ-NEXT: flat_load_dword v4, v[0:1] glc725; VI-NSZ-NEXT: s_waitcnt vmcnt(0)726; VI-NSZ-NEXT: flat_load_dword v2, v[2:3] glc727; VI-NSZ-NEXT: s_waitcnt vmcnt(0)728; VI-NSZ-NEXT: v_mov_b32_e32 v0, s0729; VI-NSZ-NEXT: v_mov_b32_e32 v1, s1730; VI-NSZ-NEXT: v_xor_b32_e32 v3, 0x80000000, v4731; VI-NSZ-NEXT: v_sub_f32_e32 v2, v4, v2732; VI-NSZ-NEXT: flat_store_dword v[0:1], v2733; VI-NSZ-NEXT: s_waitcnt vmcnt(0)734; VI-NSZ-NEXT: flat_store_dword v[0:1], v3735; VI-NSZ-NEXT: s_waitcnt vmcnt(0)736; VI-NSZ-NEXT: s_endpgm737 %tid = call i32 @llvm.amdgcn.workitem.id.x()738 %tid.ext = sext i32 %tid to i64739 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext740 %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext741 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext742 %a = load volatile float, ptr addrspace(1) %a.gep743 %b = load volatile float, ptr addrspace(1) %b.gep744 %fneg.a = fneg float %a745 %add = fadd float %fneg.a, %b746 %fneg = fneg float %add747 store volatile float %fneg, ptr addrspace(1) %out748 store volatile float %fneg.a, ptr addrspace(1) %out749 ret void750}751 752define amdgpu_kernel void @v_fneg_add_multi_use_fneg_x_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr, float %c) #0 {753; SI-SAFE-LABEL: v_fneg_add_multi_use_fneg_x_f32:754; SI-SAFE: ; %bb.0:755; SI-SAFE-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9756; SI-SAFE-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0xd757; SI-SAFE-NEXT: v_lshlrev_b32_e32 v2, 2, v0758; SI-SAFE-NEXT: s_waitcnt lgkmcnt(0)759; SI-SAFE-NEXT: v_mov_b32_e32 v1, s3760; SI-SAFE-NEXT: v_add_i32_e32 v0, vcc, s2, v2761; SI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc762; SI-SAFE-NEXT: v_mov_b32_e32 v3, s7763; SI-SAFE-NEXT: v_add_i32_e32 v2, vcc, s6, v2764; SI-SAFE-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc765; SI-SAFE-NEXT: flat_load_dword v4, v[0:1] glc766; SI-SAFE-NEXT: s_waitcnt vmcnt(0)767; SI-SAFE-NEXT: flat_load_dword v2, v[2:3] glc768; SI-SAFE-NEXT: s_waitcnt vmcnt(0)769; SI-SAFE-NEXT: s_load_dword s2, s[4:5], 0xf770; SI-SAFE-NEXT: v_mov_b32_e32 v0, s0771; SI-SAFE-NEXT: v_mov_b32_e32 v1, s1772; SI-SAFE-NEXT: s_waitcnt lgkmcnt(0)773; SI-SAFE-NEXT: v_mul_f32_e64 v3, -v4, s2774; SI-SAFE-NEXT: v_sub_f32_e32 v2, v2, v4775; SI-SAFE-NEXT: v_xor_b32_e32 v2, 0x80000000, v2776; SI-SAFE-NEXT: flat_store_dword v[0:1], v2777; SI-SAFE-NEXT: s_waitcnt vmcnt(0)778; SI-SAFE-NEXT: flat_store_dword v[0:1], v3779; SI-SAFE-NEXT: s_waitcnt vmcnt(0)780; SI-SAFE-NEXT: s_endpgm781;782; SI-NSZ-LABEL: v_fneg_add_multi_use_fneg_x_f32:783; SI-NSZ: ; %bb.0:784; SI-NSZ-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9785; SI-NSZ-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0xd786; SI-NSZ-NEXT: v_lshlrev_b32_e32 v2, 2, v0787; SI-NSZ-NEXT: s_waitcnt lgkmcnt(0)788; SI-NSZ-NEXT: v_mov_b32_e32 v1, s3789; SI-NSZ-NEXT: v_add_i32_e32 v0, vcc, s2, v2790; SI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc791; SI-NSZ-NEXT: v_mov_b32_e32 v3, s7792; SI-NSZ-NEXT: v_add_i32_e32 v2, vcc, s6, v2793; SI-NSZ-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc794; SI-NSZ-NEXT: flat_load_dword v4, v[0:1] glc795; SI-NSZ-NEXT: s_waitcnt vmcnt(0)796; SI-NSZ-NEXT: flat_load_dword v2, v[2:3] glc797; SI-NSZ-NEXT: s_waitcnt vmcnt(0)798; SI-NSZ-NEXT: s_load_dword s2, s[4:5], 0xf799; SI-NSZ-NEXT: v_mov_b32_e32 v0, s0800; SI-NSZ-NEXT: v_mov_b32_e32 v1, s1801; SI-NSZ-NEXT: s_waitcnt lgkmcnt(0)802; SI-NSZ-NEXT: v_mul_f32_e64 v3, -v4, s2803; SI-NSZ-NEXT: v_sub_f32_e32 v2, v4, v2804; SI-NSZ-NEXT: flat_store_dword v[0:1], v2805; SI-NSZ-NEXT: s_waitcnt vmcnt(0)806; SI-NSZ-NEXT: flat_store_dword v[0:1], v3807; SI-NSZ-NEXT: s_waitcnt vmcnt(0)808; SI-NSZ-NEXT: s_endpgm809;810; VI-SAFE-LABEL: v_fneg_add_multi_use_fneg_x_f32:811; VI-SAFE: ; %bb.0:812; VI-SAFE-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24813; VI-SAFE-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34814; VI-SAFE-NEXT: v_lshlrev_b32_e32 v2, 2, v0815; VI-SAFE-NEXT: s_waitcnt lgkmcnt(0)816; VI-SAFE-NEXT: v_mov_b32_e32 v1, s3817; VI-SAFE-NEXT: v_add_u32_e32 v0, vcc, s2, v2818; VI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc819; VI-SAFE-NEXT: v_mov_b32_e32 v3, s7820; VI-SAFE-NEXT: v_add_u32_e32 v2, vcc, s6, v2821; VI-SAFE-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc822; VI-SAFE-NEXT: flat_load_dword v4, v[0:1] glc823; VI-SAFE-NEXT: s_waitcnt vmcnt(0)824; VI-SAFE-NEXT: flat_load_dword v2, v[2:3] glc825; VI-SAFE-NEXT: s_waitcnt vmcnt(0)826; VI-SAFE-NEXT: s_load_dword s2, s[4:5], 0x3c827; VI-SAFE-NEXT: v_mov_b32_e32 v0, s0828; VI-SAFE-NEXT: v_mov_b32_e32 v1, s1829; VI-SAFE-NEXT: s_waitcnt lgkmcnt(0)830; VI-SAFE-NEXT: v_mul_f32_e64 v3, -v4, s2831; VI-SAFE-NEXT: v_sub_f32_e32 v2, v2, v4832; VI-SAFE-NEXT: v_xor_b32_e32 v2, 0x80000000, v2833; VI-SAFE-NEXT: flat_store_dword v[0:1], v2834; VI-SAFE-NEXT: s_waitcnt vmcnt(0)835; VI-SAFE-NEXT: flat_store_dword v[0:1], v3836; VI-SAFE-NEXT: s_waitcnt vmcnt(0)837; VI-SAFE-NEXT: s_endpgm838;839; VI-NSZ-LABEL: v_fneg_add_multi_use_fneg_x_f32:840; VI-NSZ: ; %bb.0:841; VI-NSZ-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24842; VI-NSZ-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34843; VI-NSZ-NEXT: v_lshlrev_b32_e32 v2, 2, v0844; VI-NSZ-NEXT: s_waitcnt lgkmcnt(0)845; VI-NSZ-NEXT: v_mov_b32_e32 v1, s3846; VI-NSZ-NEXT: v_add_u32_e32 v0, vcc, s2, v2847; VI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc848; VI-NSZ-NEXT: v_mov_b32_e32 v3, s7849; VI-NSZ-NEXT: v_add_u32_e32 v2, vcc, s6, v2850; VI-NSZ-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc851; VI-NSZ-NEXT: flat_load_dword v4, v[0:1] glc852; VI-NSZ-NEXT: s_waitcnt vmcnt(0)853; VI-NSZ-NEXT: flat_load_dword v2, v[2:3] glc854; VI-NSZ-NEXT: s_waitcnt vmcnt(0)855; VI-NSZ-NEXT: s_load_dword s2, s[4:5], 0x3c856; VI-NSZ-NEXT: v_mov_b32_e32 v0, s0857; VI-NSZ-NEXT: v_mov_b32_e32 v1, s1858; VI-NSZ-NEXT: s_waitcnt lgkmcnt(0)859; VI-NSZ-NEXT: v_mul_f32_e64 v3, -v4, s2860; VI-NSZ-NEXT: v_sub_f32_e32 v2, v4, v2861; VI-NSZ-NEXT: flat_store_dword v[0:1], v2862; VI-NSZ-NEXT: s_waitcnt vmcnt(0)863; VI-NSZ-NEXT: flat_store_dword v[0:1], v3864; VI-NSZ-NEXT: s_waitcnt vmcnt(0)865; VI-NSZ-NEXT: s_endpgm866 %tid = call i32 @llvm.amdgcn.workitem.id.x()867 %tid.ext = sext i32 %tid to i64868 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext869 %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext870 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext871 %a = load volatile float, ptr addrspace(1) %a.gep872 %b = load volatile float, ptr addrspace(1) %b.gep873 %fneg.a = fneg float %a874 %add = fadd float %fneg.a, %b875 %fneg = fneg float %add876 %use1 = fmul float %fneg.a, %c877 store volatile float %fneg, ptr addrspace(1) %out878 store volatile float %use1, ptr addrspace(1) %out879 ret void880}881 882; This one asserted with -enable-no-signed-zeros-fp-math883define amdgpu_ps float @fneg_fadd_0_safe(float inreg %tmp2, float inreg %tmp6, <4 x i32> %arg) local_unnamed_addr #0 {884; SI-LABEL: fneg_fadd_0_safe:885; SI: ; %bb.0: ; %.entry886; SI-NEXT: v_div_scale_f32 v0, s[2:3], s1, s1, 1.0887; SI-NEXT: v_rcp_f32_e32 v1, v0888; SI-NEXT: v_div_scale_f32 v2, vcc, 1.0, s1, 1.0889; SI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3890; SI-NEXT: v_fma_f32 v3, -v0, v1, 1.0891; SI-NEXT: v_fma_f32 v1, v3, v1, v1892; SI-NEXT: v_mul_f32_e32 v3, v2, v1893; SI-NEXT: v_fma_f32 v4, -v0, v3, v2894; SI-NEXT: v_fma_f32 v3, v4, v1, v3895; SI-NEXT: v_fma_f32 v0, -v0, v3, v2896; SI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0897; SI-NEXT: v_div_fmas_f32 v0, v0, v1, v3898; SI-NEXT: v_div_fixup_f32 v0, v0, s1, 1.0899; SI-NEXT: v_mad_f32 v0, v0, 0, 0900; SI-NEXT: v_mov_b32_e32 v1, s0901; SI-NEXT: v_cmp_ngt_f32_e32 vcc, s0, v0902; SI-NEXT: v_cndmask_b32_e64 v0, -v0, v1, vcc903; SI-NEXT: v_mov_b32_e32 v1, 0x7fc00000904; SI-NEXT: v_cmp_nlt_f32_e32 vcc, 0, v0905; SI-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc906; SI-NEXT: ; return to shader part epilog907;908; VI-LABEL: fneg_fadd_0_safe:909; VI: ; %bb.0: ; %.entry910; VI-NEXT: v_div_scale_f32 v0, s[2:3], s1, s1, 1.0911; VI-NEXT: v_div_scale_f32 v1, vcc, 1.0, s1, 1.0912; VI-NEXT: v_rcp_f32_e32 v2, v0913; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3914; VI-NEXT: v_fma_f32 v3, -v0, v2, 1.0915; VI-NEXT: v_fma_f32 v2, v3, v2, v2916; VI-NEXT: v_mul_f32_e32 v3, v1, v2917; VI-NEXT: v_fma_f32 v4, -v0, v3, v1918; VI-NEXT: v_fma_f32 v3, v4, v2, v3919; VI-NEXT: v_fma_f32 v0, -v0, v3, v1920; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0921; VI-NEXT: v_div_fmas_f32 v0, v0, v2, v3922; VI-NEXT: v_mov_b32_e32 v2, s0923; VI-NEXT: v_mov_b32_e32 v1, 0x7fc00000924; VI-NEXT: v_div_fixup_f32 v0, v0, s1, 1.0925; VI-NEXT: v_mad_f32 v0, v0, 0, 0926; VI-NEXT: v_cmp_ngt_f32_e32 vcc, s0, v0927; VI-NEXT: v_cndmask_b32_e64 v0, -v0, v2, vcc928; VI-NEXT: v_cmp_nlt_f32_e32 vcc, 0, v0929; VI-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc930; VI-NEXT: ; return to shader part epilog931.entry:932 %tmp7 = fdiv float 1.000000e+00, %tmp6933 %tmp8 = fmul float 0.000000e+00, %tmp7934 %tmp9 = fmul reassoc nnan arcp contract float 0.000000e+00, %tmp8935 %.i188 = fadd float %tmp9, 0.000000e+00936 %tmp10 = fcmp uge float %.i188, %tmp2937 %tmp11 = fneg float %.i188938 %.i092 = select i1 %tmp10, float %tmp2, float %tmp11939 %tmp12 = fcmp ule float %.i092, 0.000000e+00940 %.i198 = select i1 %tmp12, float 0.000000e+00, float 0x7FF8000000000000941 ret float %.i198942}943 944define amdgpu_ps float @fneg_fadd_0_nsz(float inreg %tmp2, float inreg %tmp6, <4 x i32> %arg) local_unnamed_addr {945; GCN-LABEL: fneg_fadd_0_nsz:946; GCN: ; %bb.0: ; %.entry947; GCN-NEXT: v_rcp_f32_e32 v0, s1948; GCN-NEXT: v_mov_b32_e32 v1, s0949; GCN-NEXT: v_mul_f32_e32 v0, 0, v0950; GCN-NEXT: v_cmp_ngt_f32_e32 vcc, s0, v0951; GCN-NEXT: v_cndmask_b32_e64 v0, -v0, v1, vcc952; GCN-NEXT: v_mov_b32_e32 v1, 0x7fc00000953; GCN-NEXT: v_cmp_nlt_f32_e32 vcc, 0, v0954; GCN-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc955; GCN-NEXT: ; return to shader part epilog956.entry:957 %tmp7 = fdiv afn float 1.000000e+00, %tmp6958 %tmp8 = fmul float 0.000000e+00, %tmp7959 %tmp9 = fmul reassoc nnan arcp contract float 0.000000e+00, %tmp8960 %.i188 = fadd nsz float %tmp9, 0.000000e+00961 %tmp10 = fcmp uge float %.i188, %tmp2962 %tmp11 = fneg float %.i188963 %.i092 = select i1 %tmp10, float %tmp2, float %tmp11964 %tmp12 = fcmp ule float %.i092, 0.000000e+00965 %.i198 = select i1 %tmp12, float 0.000000e+00, float 0x7FF8000000000000966 ret float %.i198967}968 969; --------------------------------------------------------------------------------970; fmul tests971; --------------------------------------------------------------------------------972 973define amdgpu_kernel void @v_fneg_mul_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {974; SI-LABEL: v_fneg_mul_f32:975; SI: ; %bb.0:976; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9977; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd978; SI-NEXT: v_lshlrev_b32_e32 v4, 2, v0979; SI-NEXT: s_waitcnt lgkmcnt(0)980; SI-NEXT: v_mov_b32_e32 v1, s3981; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v4982; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc983; SI-NEXT: v_mov_b32_e32 v3, s5984; SI-NEXT: v_add_i32_e32 v2, vcc, s4, v4985; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc986; SI-NEXT: flat_load_dword v5, v[0:1] glc987; SI-NEXT: s_waitcnt vmcnt(0)988; SI-NEXT: flat_load_dword v2, v[2:3] glc989; SI-NEXT: s_waitcnt vmcnt(0)990; SI-NEXT: v_mov_b32_e32 v1, s1991; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v4992; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc993; SI-NEXT: v_mul_f32_e64 v2, v5, -v2994; SI-NEXT: flat_store_dword v[0:1], v2995; SI-NEXT: s_endpgm996;997; VI-LABEL: v_fneg_mul_f32:998; VI: ; %bb.0:999; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241000; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x341001; VI-NEXT: v_lshlrev_b32_e32 v4, 2, v01002; VI-NEXT: s_waitcnt lgkmcnt(0)1003; VI-NEXT: v_mov_b32_e32 v1, s31004; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v41005; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1006; VI-NEXT: v_mov_b32_e32 v3, s51007; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v41008; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc1009; VI-NEXT: flat_load_dword v5, v[0:1] glc1010; VI-NEXT: s_waitcnt vmcnt(0)1011; VI-NEXT: flat_load_dword v2, v[2:3] glc1012; VI-NEXT: s_waitcnt vmcnt(0)1013; VI-NEXT: v_mov_b32_e32 v1, s11014; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v41015; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1016; VI-NEXT: v_mul_f32_e64 v2, v5, -v21017; VI-NEXT: flat_store_dword v[0:1], v21018; VI-NEXT: s_endpgm1019 %tid = call i32 @llvm.amdgcn.workitem.id.x()1020 %tid.ext = sext i32 %tid to i641021 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext1022 %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext1023 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext1024 %a = load volatile float, ptr addrspace(1) %a.gep1025 %b = load volatile float, ptr addrspace(1) %b.gep1026 %mul = fmul float %a, %b1027 %fneg = fneg float %mul1028 store float %fneg, ptr addrspace(1) %out.gep1029 ret void1030}1031 1032define amdgpu_kernel void @v_fneg_mul_store_use_mul_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {1033; SI-LABEL: v_fneg_mul_store_use_mul_f32:1034; SI: ; %bb.0:1035; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91036; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd1037; SI-NEXT: v_lshlrev_b32_e32 v2, 2, v01038; SI-NEXT: s_waitcnt lgkmcnt(0)1039; SI-NEXT: v_mov_b32_e32 v1, s31040; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v21041; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1042; SI-NEXT: v_mov_b32_e32 v3, s51043; SI-NEXT: v_add_i32_e32 v2, vcc, s4, v21044; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc1045; SI-NEXT: flat_load_dword v4, v[0:1] glc1046; SI-NEXT: s_waitcnt vmcnt(0)1047; SI-NEXT: flat_load_dword v2, v[2:3] glc1048; SI-NEXT: s_waitcnt vmcnt(0)1049; SI-NEXT: v_mov_b32_e32 v0, s01050; SI-NEXT: v_mov_b32_e32 v1, s11051; SI-NEXT: v_mul_f32_e32 v2, v4, v21052; SI-NEXT: v_xor_b32_e32 v3, 0x80000000, v21053; SI-NEXT: flat_store_dword v[0:1], v31054; SI-NEXT: s_waitcnt vmcnt(0)1055; SI-NEXT: flat_store_dword v[0:1], v21056; SI-NEXT: s_waitcnt vmcnt(0)1057; SI-NEXT: s_endpgm1058;1059; VI-LABEL: v_fneg_mul_store_use_mul_f32:1060; VI: ; %bb.0:1061; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241062; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x341063; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v01064; VI-NEXT: s_waitcnt lgkmcnt(0)1065; VI-NEXT: v_mov_b32_e32 v1, s31066; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v21067; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1068; VI-NEXT: v_mov_b32_e32 v3, s51069; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v21070; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc1071; VI-NEXT: flat_load_dword v4, v[0:1] glc1072; VI-NEXT: s_waitcnt vmcnt(0)1073; VI-NEXT: flat_load_dword v2, v[2:3] glc1074; VI-NEXT: s_waitcnt vmcnt(0)1075; VI-NEXT: v_mov_b32_e32 v0, s01076; VI-NEXT: v_mov_b32_e32 v1, s11077; VI-NEXT: v_mul_f32_e32 v2, v4, v21078; VI-NEXT: v_xor_b32_e32 v3, 0x80000000, v21079; VI-NEXT: flat_store_dword v[0:1], v31080; VI-NEXT: s_waitcnt vmcnt(0)1081; VI-NEXT: flat_store_dword v[0:1], v21082; VI-NEXT: s_waitcnt vmcnt(0)1083; VI-NEXT: s_endpgm1084 %tid = call i32 @llvm.amdgcn.workitem.id.x()1085 %tid.ext = sext i32 %tid to i641086 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext1087 %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext1088 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext1089 %a = load volatile float, ptr addrspace(1) %a.gep1090 %b = load volatile float, ptr addrspace(1) %b.gep1091 %mul = fmul float %a, %b1092 %fneg = fneg float %mul1093 store volatile float %fneg, ptr addrspace(1) %out1094 store volatile float %mul, ptr addrspace(1) %out1095 ret void1096}1097 1098define amdgpu_kernel void @v_fneg_mul_multi_use_mul_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {1099; SI-LABEL: v_fneg_mul_multi_use_mul_f32:1100; SI: ; %bb.0:1101; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91102; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd1103; SI-NEXT: v_lshlrev_b32_e32 v2, 2, v01104; SI-NEXT: s_waitcnt lgkmcnt(0)1105; SI-NEXT: v_mov_b32_e32 v1, s31106; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v21107; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1108; SI-NEXT: v_mov_b32_e32 v3, s51109; SI-NEXT: v_add_i32_e32 v2, vcc, s4, v21110; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc1111; SI-NEXT: flat_load_dword v4, v[0:1] glc1112; SI-NEXT: s_waitcnt vmcnt(0)1113; SI-NEXT: flat_load_dword v2, v[2:3] glc1114; SI-NEXT: s_waitcnt vmcnt(0)1115; SI-NEXT: v_mov_b32_e32 v0, s01116; SI-NEXT: v_mov_b32_e32 v1, s11117; SI-NEXT: v_mul_f32_e64 v2, v4, -v21118; SI-NEXT: v_mul_f32_e32 v3, -4.0, v21119; SI-NEXT: flat_store_dword v[0:1], v21120; SI-NEXT: s_waitcnt vmcnt(0)1121; SI-NEXT: flat_store_dword v[0:1], v31122; SI-NEXT: s_waitcnt vmcnt(0)1123; SI-NEXT: s_endpgm1124;1125; VI-LABEL: v_fneg_mul_multi_use_mul_f32:1126; VI: ; %bb.0:1127; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241128; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x341129; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v01130; VI-NEXT: s_waitcnt lgkmcnt(0)1131; VI-NEXT: v_mov_b32_e32 v1, s31132; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v21133; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1134; VI-NEXT: v_mov_b32_e32 v3, s51135; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v21136; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc1137; VI-NEXT: flat_load_dword v4, v[0:1] glc1138; VI-NEXT: s_waitcnt vmcnt(0)1139; VI-NEXT: flat_load_dword v2, v[2:3] glc1140; VI-NEXT: s_waitcnt vmcnt(0)1141; VI-NEXT: v_mov_b32_e32 v0, s01142; VI-NEXT: v_mov_b32_e32 v1, s11143; VI-NEXT: v_mul_f32_e64 v2, v4, -v21144; VI-NEXT: v_mul_f32_e32 v3, -4.0, v21145; VI-NEXT: flat_store_dword v[0:1], v21146; VI-NEXT: s_waitcnt vmcnt(0)1147; VI-NEXT: flat_store_dword v[0:1], v31148; VI-NEXT: s_waitcnt vmcnt(0)1149; VI-NEXT: s_endpgm1150 %tid = call i32 @llvm.amdgcn.workitem.id.x()1151 %tid.ext = sext i32 %tid to i641152 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext1153 %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext1154 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext1155 %a = load volatile float, ptr addrspace(1) %a.gep1156 %b = load volatile float, ptr addrspace(1) %b.gep1157 %mul = fmul float %a, %b1158 %fneg = fneg float %mul1159 %use1 = fmul float %mul, 4.01160 store volatile float %fneg, ptr addrspace(1) %out1161 store volatile float %use1, ptr addrspace(1) %out1162 ret void1163}1164 1165define amdgpu_kernel void @v_fneg_mul_fneg_x_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {1166; SI-LABEL: v_fneg_mul_fneg_x_f32:1167; SI: ; %bb.0:1168; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91169; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd1170; SI-NEXT: v_lshlrev_b32_e32 v2, 2, v01171; SI-NEXT: s_waitcnt lgkmcnt(0)1172; SI-NEXT: v_mov_b32_e32 v1, s31173; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v21174; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1175; SI-NEXT: v_mov_b32_e32 v3, s51176; SI-NEXT: v_add_i32_e32 v2, vcc, s4, v21177; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc1178; SI-NEXT: flat_load_dword v0, v[0:1] glc1179; SI-NEXT: s_waitcnt vmcnt(0)1180; SI-NEXT: flat_load_dword v1, v[2:3] glc1181; SI-NEXT: s_waitcnt vmcnt(0)1182; SI-NEXT: v_mul_f32_e32 v2, v0, v11183; SI-NEXT: v_mov_b32_e32 v0, s01184; SI-NEXT: v_mov_b32_e32 v1, s11185; SI-NEXT: flat_store_dword v[0:1], v21186; SI-NEXT: s_waitcnt vmcnt(0)1187; SI-NEXT: s_endpgm1188;1189; VI-LABEL: v_fneg_mul_fneg_x_f32:1190; VI: ; %bb.0:1191; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241192; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x341193; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v01194; VI-NEXT: s_waitcnt lgkmcnt(0)1195; VI-NEXT: v_mov_b32_e32 v1, s31196; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v21197; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1198; VI-NEXT: v_mov_b32_e32 v3, s51199; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v21200; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc1201; VI-NEXT: flat_load_dword v0, v[0:1] glc1202; VI-NEXT: s_waitcnt vmcnt(0)1203; VI-NEXT: flat_load_dword v1, v[2:3] glc1204; VI-NEXT: s_waitcnt vmcnt(0)1205; VI-NEXT: v_mul_f32_e32 v2, v0, v11206; VI-NEXT: v_mov_b32_e32 v0, s01207; VI-NEXT: v_mov_b32_e32 v1, s11208; VI-NEXT: flat_store_dword v[0:1], v21209; VI-NEXT: s_waitcnt vmcnt(0)1210; VI-NEXT: s_endpgm1211 %tid = call i32 @llvm.amdgcn.workitem.id.x()1212 %tid.ext = sext i32 %tid to i641213 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext1214 %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext1215 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext1216 %a = load volatile float, ptr addrspace(1) %a.gep1217 %b = load volatile float, ptr addrspace(1) %b.gep1218 %fneg.a = fneg float %a1219 %mul = fmul float %fneg.a, %b1220 %fneg = fneg float %mul1221 store volatile float %fneg, ptr addrspace(1) %out1222 ret void1223}1224 1225define amdgpu_kernel void @v_fneg_mul_x_fneg_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {1226; SI-LABEL: v_fneg_mul_x_fneg_f32:1227; SI: ; %bb.0:1228; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91229; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd1230; SI-NEXT: v_lshlrev_b32_e32 v2, 2, v01231; SI-NEXT: s_waitcnt lgkmcnt(0)1232; SI-NEXT: v_mov_b32_e32 v1, s31233; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v21234; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1235; SI-NEXT: v_mov_b32_e32 v3, s51236; SI-NEXT: v_add_i32_e32 v2, vcc, s4, v21237; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc1238; SI-NEXT: flat_load_dword v0, v[0:1] glc1239; SI-NEXT: s_waitcnt vmcnt(0)1240; SI-NEXT: flat_load_dword v1, v[2:3] glc1241; SI-NEXT: s_waitcnt vmcnt(0)1242; SI-NEXT: v_mul_f32_e32 v2, v0, v11243; SI-NEXT: v_mov_b32_e32 v0, s01244; SI-NEXT: v_mov_b32_e32 v1, s11245; SI-NEXT: flat_store_dword v[0:1], v21246; SI-NEXT: s_waitcnt vmcnt(0)1247; SI-NEXT: s_endpgm1248;1249; VI-LABEL: v_fneg_mul_x_fneg_f32:1250; VI: ; %bb.0:1251; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241252; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x341253; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v01254; VI-NEXT: s_waitcnt lgkmcnt(0)1255; VI-NEXT: v_mov_b32_e32 v1, s31256; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v21257; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1258; VI-NEXT: v_mov_b32_e32 v3, s51259; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v21260; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc1261; VI-NEXT: flat_load_dword v0, v[0:1] glc1262; VI-NEXT: s_waitcnt vmcnt(0)1263; VI-NEXT: flat_load_dword v1, v[2:3] glc1264; VI-NEXT: s_waitcnt vmcnt(0)1265; VI-NEXT: v_mul_f32_e32 v2, v0, v11266; VI-NEXT: v_mov_b32_e32 v0, s01267; VI-NEXT: v_mov_b32_e32 v1, s11268; VI-NEXT: flat_store_dword v[0:1], v21269; VI-NEXT: s_waitcnt vmcnt(0)1270; VI-NEXT: s_endpgm1271 %tid = call i32 @llvm.amdgcn.workitem.id.x()1272 %tid.ext = sext i32 %tid to i641273 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext1274 %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext1275 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext1276 %a = load volatile float, ptr addrspace(1) %a.gep1277 %b = load volatile float, ptr addrspace(1) %b.gep1278 %fneg.b = fneg float %b1279 %mul = fmul float %a, %fneg.b1280 %fneg = fneg float %mul1281 store volatile float %fneg, ptr addrspace(1) %out1282 ret void1283}1284 1285define amdgpu_kernel void @v_fneg_mul_fneg_fneg_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {1286; SI-LABEL: v_fneg_mul_fneg_fneg_f32:1287; SI: ; %bb.0:1288; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91289; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd1290; SI-NEXT: v_lshlrev_b32_e32 v2, 2, v01291; SI-NEXT: s_waitcnt lgkmcnt(0)1292; SI-NEXT: v_mov_b32_e32 v1, s31293; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v21294; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1295; SI-NEXT: v_mov_b32_e32 v3, s51296; SI-NEXT: v_add_i32_e32 v2, vcc, s4, v21297; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc1298; SI-NEXT: flat_load_dword v0, v[0:1] glc1299; SI-NEXT: s_waitcnt vmcnt(0)1300; SI-NEXT: flat_load_dword v1, v[2:3] glc1301; SI-NEXT: s_waitcnt vmcnt(0)1302; SI-NEXT: v_mul_f32_e64 v2, v0, -v11303; SI-NEXT: v_mov_b32_e32 v0, s01304; SI-NEXT: v_mov_b32_e32 v1, s11305; SI-NEXT: flat_store_dword v[0:1], v21306; SI-NEXT: s_waitcnt vmcnt(0)1307; SI-NEXT: s_endpgm1308;1309; VI-LABEL: v_fneg_mul_fneg_fneg_f32:1310; VI: ; %bb.0:1311; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241312; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x341313; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v01314; VI-NEXT: s_waitcnt lgkmcnt(0)1315; VI-NEXT: v_mov_b32_e32 v1, s31316; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v21317; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1318; VI-NEXT: v_mov_b32_e32 v3, s51319; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v21320; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc1321; VI-NEXT: flat_load_dword v0, v[0:1] glc1322; VI-NEXT: s_waitcnt vmcnt(0)1323; VI-NEXT: flat_load_dword v1, v[2:3] glc1324; VI-NEXT: s_waitcnt vmcnt(0)1325; VI-NEXT: v_mul_f32_e64 v2, v0, -v11326; VI-NEXT: v_mov_b32_e32 v0, s01327; VI-NEXT: v_mov_b32_e32 v1, s11328; VI-NEXT: flat_store_dword v[0:1], v21329; VI-NEXT: s_waitcnt vmcnt(0)1330; VI-NEXT: s_endpgm1331 %tid = call i32 @llvm.amdgcn.workitem.id.x()1332 %tid.ext = sext i32 %tid to i641333 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext1334 %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext1335 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext1336 %a = load volatile float, ptr addrspace(1) %a.gep1337 %b = load volatile float, ptr addrspace(1) %b.gep1338 %fneg.a = fneg float %a1339 %fneg.b = fneg float %b1340 %mul = fmul float %fneg.a, %fneg.b1341 %fneg = fneg float %mul1342 store volatile float %fneg, ptr addrspace(1) %out1343 ret void1344}1345 1346define amdgpu_kernel void @v_fneg_mul_store_use_fneg_x_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {1347; SI-LABEL: v_fneg_mul_store_use_fneg_x_f32:1348; SI: ; %bb.0:1349; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91350; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd1351; SI-NEXT: v_lshlrev_b32_e32 v2, 2, v01352; SI-NEXT: s_waitcnt lgkmcnt(0)1353; SI-NEXT: v_mov_b32_e32 v1, s31354; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v21355; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1356; SI-NEXT: v_mov_b32_e32 v3, s51357; SI-NEXT: v_add_i32_e32 v2, vcc, s4, v21358; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc1359; SI-NEXT: flat_load_dword v4, v[0:1] glc1360; SI-NEXT: s_waitcnt vmcnt(0)1361; SI-NEXT: flat_load_dword v2, v[2:3] glc1362; SI-NEXT: s_waitcnt vmcnt(0)1363; SI-NEXT: v_mov_b32_e32 v0, s01364; SI-NEXT: v_mov_b32_e32 v1, s11365; SI-NEXT: v_xor_b32_e32 v3, 0x80000000, v41366; SI-NEXT: v_mul_f32_e32 v2, v4, v21367; SI-NEXT: flat_store_dword v[0:1], v21368; SI-NEXT: s_waitcnt vmcnt(0)1369; SI-NEXT: flat_store_dword v[0:1], v31370; SI-NEXT: s_waitcnt vmcnt(0)1371; SI-NEXT: s_endpgm1372;1373; VI-LABEL: v_fneg_mul_store_use_fneg_x_f32:1374; VI: ; %bb.0:1375; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241376; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x341377; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v01378; VI-NEXT: s_waitcnt lgkmcnt(0)1379; VI-NEXT: v_mov_b32_e32 v1, s31380; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v21381; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1382; VI-NEXT: v_mov_b32_e32 v3, s51383; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v21384; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc1385; VI-NEXT: flat_load_dword v4, v[0:1] glc1386; VI-NEXT: s_waitcnt vmcnt(0)1387; VI-NEXT: flat_load_dword v2, v[2:3] glc1388; VI-NEXT: s_waitcnt vmcnt(0)1389; VI-NEXT: v_mov_b32_e32 v0, s01390; VI-NEXT: v_mov_b32_e32 v1, s11391; VI-NEXT: v_xor_b32_e32 v3, 0x80000000, v41392; VI-NEXT: v_mul_f32_e32 v2, v4, v21393; VI-NEXT: flat_store_dword v[0:1], v21394; VI-NEXT: s_waitcnt vmcnt(0)1395; VI-NEXT: flat_store_dword v[0:1], v31396; VI-NEXT: s_waitcnt vmcnt(0)1397; VI-NEXT: s_endpgm1398 %tid = call i32 @llvm.amdgcn.workitem.id.x()1399 %tid.ext = sext i32 %tid to i641400 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext1401 %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext1402 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext1403 %a = load volatile float, ptr addrspace(1) %a.gep1404 %b = load volatile float, ptr addrspace(1) %b.gep1405 %fneg.a = fneg float %a1406 %mul = fmul float %fneg.a, %b1407 %fneg = fneg float %mul1408 store volatile float %fneg, ptr addrspace(1) %out1409 store volatile float %fneg.a, ptr addrspace(1) %out1410 ret void1411}1412 1413define amdgpu_kernel void @v_fneg_mul_multi_use_fneg_x_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr, float %c) #0 {1414; SI-LABEL: v_fneg_mul_multi_use_fneg_x_f32:1415; SI: ; %bb.0:1416; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91417; SI-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0xd1418; SI-NEXT: v_lshlrev_b32_e32 v2, 2, v01419; SI-NEXT: s_waitcnt lgkmcnt(0)1420; SI-NEXT: v_mov_b32_e32 v1, s31421; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v21422; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1423; SI-NEXT: v_mov_b32_e32 v3, s71424; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v21425; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc1426; SI-NEXT: flat_load_dword v4, v[0:1] glc1427; SI-NEXT: s_waitcnt vmcnt(0)1428; SI-NEXT: flat_load_dword v2, v[2:3] glc1429; SI-NEXT: s_waitcnt vmcnt(0)1430; SI-NEXT: s_load_dword s2, s[4:5], 0xf1431; SI-NEXT: v_mov_b32_e32 v0, s01432; SI-NEXT: v_mov_b32_e32 v1, s11433; SI-NEXT: s_waitcnt lgkmcnt(0)1434; SI-NEXT: v_mul_f32_e64 v3, -v4, s21435; SI-NEXT: v_mul_f32_e32 v2, v4, v21436; SI-NEXT: flat_store_dword v[0:1], v21437; SI-NEXT: s_waitcnt vmcnt(0)1438; SI-NEXT: flat_store_dword v[0:1], v31439; SI-NEXT: s_waitcnt vmcnt(0)1440; SI-NEXT: s_endpgm1441;1442; VI-LABEL: v_fneg_mul_multi_use_fneg_x_f32:1443; VI: ; %bb.0:1444; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241445; VI-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x341446; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v01447; VI-NEXT: s_waitcnt lgkmcnt(0)1448; VI-NEXT: v_mov_b32_e32 v1, s31449; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v21450; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1451; VI-NEXT: v_mov_b32_e32 v3, s71452; VI-NEXT: v_add_u32_e32 v2, vcc, s6, v21453; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc1454; VI-NEXT: flat_load_dword v4, v[0:1] glc1455; VI-NEXT: s_waitcnt vmcnt(0)1456; VI-NEXT: flat_load_dword v2, v[2:3] glc1457; VI-NEXT: s_waitcnt vmcnt(0)1458; VI-NEXT: s_load_dword s2, s[4:5], 0x3c1459; VI-NEXT: v_mov_b32_e32 v0, s01460; VI-NEXT: v_mov_b32_e32 v1, s11461; VI-NEXT: s_waitcnt lgkmcnt(0)1462; VI-NEXT: v_mul_f32_e64 v3, -v4, s21463; VI-NEXT: v_mul_f32_e32 v2, v4, v21464; VI-NEXT: flat_store_dword v[0:1], v21465; VI-NEXT: s_waitcnt vmcnt(0)1466; VI-NEXT: flat_store_dword v[0:1], v31467; VI-NEXT: s_waitcnt vmcnt(0)1468; VI-NEXT: s_endpgm1469 %tid = call i32 @llvm.amdgcn.workitem.id.x()1470 %tid.ext = sext i32 %tid to i641471 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext1472 %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext1473 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext1474 %a = load volatile float, ptr addrspace(1) %a.gep1475 %b = load volatile float, ptr addrspace(1) %b.gep1476 %fneg.a = fneg float %a1477 %mul = fmul float %fneg.a, %b1478 %fneg = fneg float %mul1479 %use1 = fmul float %fneg.a, %c1480 store volatile float %fneg, ptr addrspace(1) %out1481 store volatile float %use1, ptr addrspace(1) %out1482 ret void1483}1484 1485; --------------------------------------------------------------------------------1486; fminnum tests1487; --------------------------------------------------------------------------------1488 1489define amdgpu_kernel void @v_fneg_minnum_f32_ieee(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {1490; SI-LABEL: v_fneg_minnum_f32_ieee:1491; SI: ; %bb.0:1492; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91493; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd1494; SI-NEXT: v_lshlrev_b32_e32 v4, 2, v01495; SI-NEXT: s_waitcnt lgkmcnt(0)1496; SI-NEXT: v_mov_b32_e32 v1, s31497; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v41498; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1499; SI-NEXT: v_mov_b32_e32 v3, s51500; SI-NEXT: v_add_i32_e32 v2, vcc, s4, v41501; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc1502; SI-NEXT: flat_load_dword v5, v[0:1] glc1503; SI-NEXT: s_waitcnt vmcnt(0)1504; SI-NEXT: flat_load_dword v2, v[2:3] glc1505; SI-NEXT: s_waitcnt vmcnt(0)1506; SI-NEXT: v_mov_b32_e32 v1, s11507; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v41508; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1509; SI-NEXT: v_mul_f32_e32 v3, -1.0, v51510; SI-NEXT: v_mul_f32_e32 v2, -1.0, v21511; SI-NEXT: v_max_f32_e32 v2, v3, v21512; SI-NEXT: flat_store_dword v[0:1], v21513; SI-NEXT: s_endpgm1514;1515; VI-LABEL: v_fneg_minnum_f32_ieee:1516; VI: ; %bb.0:1517; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241518; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x341519; VI-NEXT: v_lshlrev_b32_e32 v4, 2, v01520; VI-NEXT: s_waitcnt lgkmcnt(0)1521; VI-NEXT: v_mov_b32_e32 v1, s31522; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v41523; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1524; VI-NEXT: v_mov_b32_e32 v3, s51525; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v41526; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc1527; VI-NEXT: flat_load_dword v5, v[0:1] glc1528; VI-NEXT: s_waitcnt vmcnt(0)1529; VI-NEXT: flat_load_dword v2, v[2:3] glc1530; VI-NEXT: s_waitcnt vmcnt(0)1531; VI-NEXT: v_mov_b32_e32 v1, s11532; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v41533; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1534; VI-NEXT: v_mul_f32_e32 v3, -1.0, v51535; VI-NEXT: v_mul_f32_e32 v2, -1.0, v21536; VI-NEXT: v_max_f32_e32 v2, v3, v21537; VI-NEXT: flat_store_dword v[0:1], v21538; VI-NEXT: s_endpgm1539 %tid = call i32 @llvm.amdgcn.workitem.id.x()1540 %tid.ext = sext i32 %tid to i641541 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext1542 %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext1543 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext1544 %a = load volatile float, ptr addrspace(1) %a.gep1545 %b = load volatile float, ptr addrspace(1) %b.gep1546 %min = call float @llvm.minnum.f32(float %a, float %b)1547 %fneg = fneg float %min1548 store float %fneg, ptr addrspace(1) %out.gep1549 ret void1550}1551 1552define amdgpu_ps float @v_fneg_minnum_f32_no_ieee(float %a, float %b) #0 {1553; GCN-LABEL: v_fneg_minnum_f32_no_ieee:1554; GCN: ; %bb.0:1555; GCN-NEXT: v_max_f32_e64 v0, -v0, -v11556; GCN-NEXT: ; return to shader part epilog1557 %min = call float @llvm.minnum.f32(float %a, float %b)1558 %fneg = fneg float %min1559 ret float %fneg1560}1561 1562define amdgpu_kernel void @v_fneg_self_minnum_f32_ieee(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) #0 {1563; SI-LABEL: v_fneg_self_minnum_f32_ieee:1564; SI: ; %bb.0:1565; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91566; SI-NEXT: v_lshlrev_b32_e32 v2, 2, v01567; SI-NEXT: s_waitcnt lgkmcnt(0)1568; SI-NEXT: v_mov_b32_e32 v1, s31569; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v21570; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1571; SI-NEXT: flat_load_dword v3, v[0:1] glc1572; SI-NEXT: s_waitcnt vmcnt(0)1573; SI-NEXT: v_mov_b32_e32 v1, s11574; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v21575; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1576; SI-NEXT: v_mul_f32_e32 v2, -1.0, v31577; SI-NEXT: v_max_f32_e32 v2, v2, v21578; SI-NEXT: flat_store_dword v[0:1], v21579; SI-NEXT: s_endpgm1580;1581; VI-LABEL: v_fneg_self_minnum_f32_ieee:1582; VI: ; %bb.0:1583; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241584; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v01585; VI-NEXT: s_waitcnt lgkmcnt(0)1586; VI-NEXT: v_mov_b32_e32 v1, s31587; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v21588; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1589; VI-NEXT: flat_load_dword v3, v[0:1] glc1590; VI-NEXT: s_waitcnt vmcnt(0)1591; VI-NEXT: v_mov_b32_e32 v1, s11592; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v21593; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1594; VI-NEXT: v_mul_f32_e32 v2, -1.0, v31595; VI-NEXT: v_max_f32_e32 v2, v2, v21596; VI-NEXT: flat_store_dword v[0:1], v21597; VI-NEXT: s_endpgm1598 %tid = call i32 @llvm.amdgcn.workitem.id.x()1599 %tid.ext = sext i32 %tid to i641600 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext1601 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext1602 %a = load volatile float, ptr addrspace(1) %a.gep1603 %min = call float @llvm.minnum.f32(float %a, float %a)1604 %min.fneg = fneg float %min1605 store float %min.fneg, ptr addrspace(1) %out.gep1606 ret void1607}1608 1609define amdgpu_ps float @v_fneg_self_minnum_f32_no_ieee(float %a) #0 {1610; GCN-LABEL: v_fneg_self_minnum_f32_no_ieee:1611; GCN: ; %bb.0:1612; GCN-NEXT: v_max_f32_e64 v0, -v0, -v01613; GCN-NEXT: ; return to shader part epilog1614 %min = call float @llvm.minnum.f32(float %a, float %a)1615 %min.fneg = fneg float %min1616 ret float %min.fneg1617}1618 1619define amdgpu_kernel void @v_fneg_posk_minnum_f32_ieee(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) #0 {1620; SI-LABEL: v_fneg_posk_minnum_f32_ieee:1621; SI: ; %bb.0:1622; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91623; SI-NEXT: v_lshlrev_b32_e32 v2, 2, v01624; SI-NEXT: s_waitcnt lgkmcnt(0)1625; SI-NEXT: v_mov_b32_e32 v1, s31626; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v21627; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1628; SI-NEXT: flat_load_dword v3, v[0:1] glc1629; SI-NEXT: s_waitcnt vmcnt(0)1630; SI-NEXT: v_mov_b32_e32 v1, s11631; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v21632; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1633; SI-NEXT: v_mul_f32_e32 v2, -1.0, v31634; SI-NEXT: v_max_f32_e32 v2, -4.0, v21635; SI-NEXT: flat_store_dword v[0:1], v21636; SI-NEXT: s_endpgm1637;1638; VI-LABEL: v_fneg_posk_minnum_f32_ieee:1639; VI: ; %bb.0:1640; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241641; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v01642; VI-NEXT: s_waitcnt lgkmcnt(0)1643; VI-NEXT: v_mov_b32_e32 v1, s31644; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v21645; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1646; VI-NEXT: flat_load_dword v3, v[0:1] glc1647; VI-NEXT: s_waitcnt vmcnt(0)1648; VI-NEXT: v_mov_b32_e32 v1, s11649; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v21650; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1651; VI-NEXT: v_mul_f32_e32 v2, -1.0, v31652; VI-NEXT: v_max_f32_e32 v2, -4.0, v21653; VI-NEXT: flat_store_dword v[0:1], v21654; VI-NEXT: s_endpgm1655 %tid = call i32 @llvm.amdgcn.workitem.id.x()1656 %tid.ext = sext i32 %tid to i641657 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext1658 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext1659 %a = load volatile float, ptr addrspace(1) %a.gep1660 %min = call float @llvm.minnum.f32(float 4.0, float %a)1661 %fneg = fneg float %min1662 store float %fneg, ptr addrspace(1) %out.gep1663 ret void1664}1665 1666define amdgpu_ps float @v_fneg_posk_minnum_f32_no_ieee(float %a) #0 {1667; GCN-LABEL: v_fneg_posk_minnum_f32_no_ieee:1668; GCN: ; %bb.0:1669; GCN-NEXT: v_max_f32_e64 v0, -v0, -4.01670; GCN-NEXT: ; return to shader part epilog1671 %min = call float @llvm.minnum.f32(float 4.0, float %a)1672 %fneg = fneg float %min1673 ret float %fneg1674}1675 1676define amdgpu_kernel void @v_fneg_negk_minnum_f32_ieee(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) #0 {1677; SI-LABEL: v_fneg_negk_minnum_f32_ieee:1678; SI: ; %bb.0:1679; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91680; SI-NEXT: v_lshlrev_b32_e32 v2, 2, v01681; SI-NEXT: s_waitcnt lgkmcnt(0)1682; SI-NEXT: v_mov_b32_e32 v1, s31683; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v21684; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1685; SI-NEXT: flat_load_dword v3, v[0:1] glc1686; SI-NEXT: s_waitcnt vmcnt(0)1687; SI-NEXT: v_mov_b32_e32 v1, s11688; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v21689; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1690; SI-NEXT: v_mul_f32_e32 v2, -1.0, v31691; SI-NEXT: v_max_f32_e32 v2, 4.0, v21692; SI-NEXT: flat_store_dword v[0:1], v21693; SI-NEXT: s_endpgm1694;1695; VI-LABEL: v_fneg_negk_minnum_f32_ieee:1696; VI: ; %bb.0:1697; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241698; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v01699; VI-NEXT: s_waitcnt lgkmcnt(0)1700; VI-NEXT: v_mov_b32_e32 v1, s31701; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v21702; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1703; VI-NEXT: flat_load_dword v3, v[0:1] glc1704; VI-NEXT: s_waitcnt vmcnt(0)1705; VI-NEXT: v_mov_b32_e32 v1, s11706; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v21707; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1708; VI-NEXT: v_mul_f32_e32 v2, -1.0, v31709; VI-NEXT: v_max_f32_e32 v2, 4.0, v21710; VI-NEXT: flat_store_dword v[0:1], v21711; VI-NEXT: s_endpgm1712 %tid = call i32 @llvm.amdgcn.workitem.id.x()1713 %tid.ext = sext i32 %tid to i641714 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext1715 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext1716 %a = load volatile float, ptr addrspace(1) %a.gep1717 %min = call float @llvm.minnum.f32(float -4.0, float %a)1718 %fneg = fneg float %min1719 store float %fneg, ptr addrspace(1) %out.gep1720 ret void1721}1722 1723define amdgpu_ps float @v_fneg_negk_minnum_f32_no_ieee(float %a) #0 {1724; GCN-LABEL: v_fneg_negk_minnum_f32_no_ieee:1725; GCN: ; %bb.0:1726; GCN-NEXT: v_max_f32_e64 v0, -v0, 4.01727; GCN-NEXT: ; return to shader part epilog1728 %min = call float @llvm.minnum.f32(float -4.0, float %a)1729 %fneg = fneg float %min1730 ret float %fneg1731}1732 1733define amdgpu_kernel void @v_fneg_0_minnum_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) #0 {1734; SI-LABEL: v_fneg_0_minnum_f32:1735; SI: ; %bb.0:1736; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91737; SI-NEXT: v_lshlrev_b32_e32 v2, 2, v01738; SI-NEXT: s_waitcnt lgkmcnt(0)1739; SI-NEXT: v_mov_b32_e32 v1, s31740; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v21741; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1742; SI-NEXT: flat_load_dword v3, v[0:1] glc1743; SI-NEXT: s_waitcnt vmcnt(0)1744; SI-NEXT: v_mov_b32_e32 v1, s11745; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v21746; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1747; SI-NEXT: v_min_f32_e32 v2, 0, v31748; SI-NEXT: v_xor_b32_e32 v2, 0x80000000, v21749; SI-NEXT: flat_store_dword v[0:1], v21750; SI-NEXT: s_endpgm1751;1752; VI-LABEL: v_fneg_0_minnum_f32:1753; VI: ; %bb.0:1754; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241755; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v01756; VI-NEXT: s_waitcnt lgkmcnt(0)1757; VI-NEXT: v_mov_b32_e32 v1, s31758; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v21759; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1760; VI-NEXT: flat_load_dword v3, v[0:1] glc1761; VI-NEXT: s_waitcnt vmcnt(0)1762; VI-NEXT: v_mov_b32_e32 v1, s11763; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v21764; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1765; VI-NEXT: v_min_f32_e32 v2, 0, v31766; VI-NEXT: v_xor_b32_e32 v2, 0x80000000, v21767; VI-NEXT: flat_store_dword v[0:1], v21768; VI-NEXT: s_endpgm1769 %tid = call i32 @llvm.amdgcn.workitem.id.x()1770 %tid.ext = sext i32 %tid to i641771 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext1772 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext1773 %a = load volatile float, ptr addrspace(1) %a.gep1774 %min = call nnan float @llvm.minnum.f32(float 0.0, float %a)1775 %fneg = fneg float %min1776 store float %fneg, ptr addrspace(1) %out.gep1777 ret void1778}1779 1780define amdgpu_kernel void @v_fneg_neg0_minnum_f32_ieee(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) #0 {1781; SI-LABEL: v_fneg_neg0_minnum_f32_ieee:1782; SI: ; %bb.0:1783; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91784; SI-NEXT: v_lshlrev_b32_e32 v2, 2, v01785; SI-NEXT: s_waitcnt lgkmcnt(0)1786; SI-NEXT: v_mov_b32_e32 v1, s31787; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v21788; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1789; SI-NEXT: flat_load_dword v3, v[0:1] glc1790; SI-NEXT: s_waitcnt vmcnt(0)1791; SI-NEXT: v_mov_b32_e32 v1, s11792; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v21793; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1794; SI-NEXT: v_mul_f32_e32 v2, -1.0, v31795; SI-NEXT: v_max_f32_e32 v2, 0, v21796; SI-NEXT: flat_store_dword v[0:1], v21797; SI-NEXT: s_endpgm1798;1799; VI-LABEL: v_fneg_neg0_minnum_f32_ieee:1800; VI: ; %bb.0:1801; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241802; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v01803; VI-NEXT: s_waitcnt lgkmcnt(0)1804; VI-NEXT: v_mov_b32_e32 v1, s31805; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v21806; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1807; VI-NEXT: flat_load_dword v3, v[0:1] glc1808; VI-NEXT: s_waitcnt vmcnt(0)1809; VI-NEXT: v_mov_b32_e32 v1, s11810; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v21811; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1812; VI-NEXT: v_mul_f32_e32 v2, -1.0, v31813; VI-NEXT: v_max_f32_e32 v2, 0, v21814; VI-NEXT: flat_store_dword v[0:1], v21815; VI-NEXT: s_endpgm1816 %tid = call i32 @llvm.amdgcn.workitem.id.x()1817 %tid.ext = sext i32 %tid to i641818 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext1819 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext1820 %a = load volatile float, ptr addrspace(1) %a.gep1821 %min = call float @llvm.minnum.f32(float -0.0, float %a)1822 %fneg = fneg float %min1823 store float %fneg, ptr addrspace(1) %out.gep1824 ret void1825}1826 1827define amdgpu_kernel void @v_fneg_inv2pi_minnum_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) #0 {1828; SI-LABEL: v_fneg_inv2pi_minnum_f32:1829; SI: ; %bb.0:1830; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91831; SI-NEXT: v_lshlrev_b32_e32 v2, 2, v01832; SI-NEXT: s_waitcnt lgkmcnt(0)1833; SI-NEXT: v_mov_b32_e32 v1, s31834; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v21835; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1836; SI-NEXT: flat_load_dword v3, v[0:1] glc1837; SI-NEXT: s_waitcnt vmcnt(0)1838; SI-NEXT: v_mov_b32_e32 v1, s11839; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v21840; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1841; SI-NEXT: v_mul_f32_e32 v2, -1.0, v31842; SI-NEXT: v_max_f32_e32 v2, 0xbe22f983, v21843; SI-NEXT: flat_store_dword v[0:1], v21844; SI-NEXT: s_endpgm1845;1846; VI-LABEL: v_fneg_inv2pi_minnum_f32:1847; VI: ; %bb.0:1848; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241849; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v01850; VI-NEXT: s_waitcnt lgkmcnt(0)1851; VI-NEXT: v_mov_b32_e32 v1, s31852; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v21853; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1854; VI-NEXT: flat_load_dword v3, v[0:1] glc1855; VI-NEXT: s_waitcnt vmcnt(0)1856; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v21857; VI-NEXT: v_mov_b32_e32 v1, s11858; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1859; VI-NEXT: v_mul_f32_e32 v2, 1.0, v31860; VI-NEXT: v_min_f32_e32 v2, 0.15915494, v21861; VI-NEXT: v_xor_b32_e32 v2, 0x80000000, v21862; VI-NEXT: flat_store_dword v[0:1], v21863; VI-NEXT: s_endpgm1864 %tid = call i32 @llvm.amdgcn.workitem.id.x()1865 %tid.ext = sext i32 %tid to i641866 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext1867 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext1868 %a = load volatile float, ptr addrspace(1) %a.gep1869 %min = call float @llvm.minnum.f32(float 0x3FC45F3060000000, float %a)1870 %fneg = fneg float %min1871 store float %fneg, ptr addrspace(1) %out.gep1872 ret void1873}1874 1875define amdgpu_kernel void @v_fneg_neg_inv2pi_minnum_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) #0 {1876; SI-LABEL: v_fneg_neg_inv2pi_minnum_f32:1877; SI: ; %bb.0:1878; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91879; SI-NEXT: v_lshlrev_b32_e32 v2, 2, v01880; SI-NEXT: s_waitcnt lgkmcnt(0)1881; SI-NEXT: v_mov_b32_e32 v1, s31882; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v21883; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1884; SI-NEXT: flat_load_dword v3, v[0:1] glc1885; SI-NEXT: s_waitcnt vmcnt(0)1886; SI-NEXT: v_mov_b32_e32 v1, s11887; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v21888; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1889; SI-NEXT: v_mul_f32_e32 v2, -1.0, v31890; SI-NEXT: v_max_f32_e32 v2, 0x3e22f983, v21891; SI-NEXT: flat_store_dword v[0:1], v21892; SI-NEXT: s_endpgm1893;1894; VI-LABEL: v_fneg_neg_inv2pi_minnum_f32:1895; VI: ; %bb.0:1896; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241897; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v01898; VI-NEXT: s_waitcnt lgkmcnt(0)1899; VI-NEXT: v_mov_b32_e32 v1, s31900; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v21901; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1902; VI-NEXT: flat_load_dword v3, v[0:1] glc1903; VI-NEXT: s_waitcnt vmcnt(0)1904; VI-NEXT: v_mov_b32_e32 v1, s11905; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v21906; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1907; VI-NEXT: v_mul_f32_e32 v2, -1.0, v31908; VI-NEXT: v_max_f32_e32 v2, 0.15915494, v21909; VI-NEXT: flat_store_dword v[0:1], v21910; VI-NEXT: s_endpgm1911 %tid = call i32 @llvm.amdgcn.workitem.id.x()1912 %tid.ext = sext i32 %tid to i641913 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext1914 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext1915 %a = load volatile float, ptr addrspace(1) %a.gep1916 %min = call float @llvm.minnum.f32(float 0xBFC45F3060000000, float %a)1917 %fneg = fneg float %min1918 store float %fneg, ptr addrspace(1) %out.gep1919 ret void1920}1921 1922define amdgpu_kernel void @v_fneg_inv2pi_minnum_f16(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) #0 {1923; SI-LABEL: v_fneg_inv2pi_minnum_f16:1924; SI: ; %bb.0:1925; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91926; SI-NEXT: v_lshlrev_b32_e32 v2, 1, v01927; SI-NEXT: s_waitcnt lgkmcnt(0)1928; SI-NEXT: v_mov_b32_e32 v1, s31929; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v21930; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1931; SI-NEXT: flat_load_ushort v0, v[0:1] glc1932; SI-NEXT: s_waitcnt vmcnt(0)1933; SI-NEXT: v_mov_b32_e32 v1, s11934; SI-NEXT: v_cvt_f32_f16_e64 v0, -v01935; SI-NEXT: v_max_f32_e32 v0, 0xbe230000, v01936; SI-NEXT: v_cvt_f16_f32_e32 v3, v01937; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v21938; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1939; SI-NEXT: flat_store_short v[0:1], v31940; SI-NEXT: s_endpgm1941;1942; VI-LABEL: v_fneg_inv2pi_minnum_f16:1943; VI: ; %bb.0:1944; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241945; VI-NEXT: v_lshlrev_b32_e32 v2, 1, v01946; VI-NEXT: s_waitcnt lgkmcnt(0)1947; VI-NEXT: v_mov_b32_e32 v1, s31948; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v21949; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1950; VI-NEXT: flat_load_ushort v3, v[0:1] glc1951; VI-NEXT: s_waitcnt vmcnt(0)1952; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v21953; VI-NEXT: v_mov_b32_e32 v1, s11954; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1955; VI-NEXT: v_max_f16_e32 v2, v3, v31956; VI-NEXT: v_min_f16_e32 v2, 0.15915494, v21957; VI-NEXT: v_xor_b32_e32 v2, 0x8000, v21958; VI-NEXT: flat_store_short v[0:1], v21959; VI-NEXT: s_endpgm1960 %tid = call i32 @llvm.amdgcn.workitem.id.x()1961 %tid.ext = sext i32 %tid to i641962 %a.gep = getelementptr inbounds half, ptr addrspace(1) %a.ptr, i64 %tid.ext1963 %out.gep = getelementptr inbounds half, ptr addrspace(1) %out, i64 %tid.ext1964 %a = load volatile half, ptr addrspace(1) %a.gep1965 %min = call half @llvm.minnum.f16(half 0xH3118, half %a)1966 %fneg = fsub half -0.000000e+00, %min1967 store half %fneg, ptr addrspace(1) %out.gep1968 ret void1969}1970 1971define amdgpu_kernel void @v_fneg_neg_inv2pi_minnum_f16(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) #0 {1972; SI-LABEL: v_fneg_neg_inv2pi_minnum_f16:1973; SI: ; %bb.0:1974; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91975; SI-NEXT: v_lshlrev_b32_e32 v2, 1, v01976; SI-NEXT: s_waitcnt lgkmcnt(0)1977; SI-NEXT: v_mov_b32_e32 v1, s31978; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v21979; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1980; SI-NEXT: flat_load_ushort v0, v[0:1] glc1981; SI-NEXT: s_waitcnt vmcnt(0)1982; SI-NEXT: v_mov_b32_e32 v1, s11983; SI-NEXT: v_cvt_f32_f16_e64 v0, -v01984; SI-NEXT: v_max_f32_e32 v0, 0x3e230000, v01985; SI-NEXT: v_cvt_f16_f32_e32 v3, v01986; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v21987; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1988; SI-NEXT: flat_store_short v[0:1], v31989; SI-NEXT: s_endpgm1990;1991; VI-LABEL: v_fneg_neg_inv2pi_minnum_f16:1992; VI: ; %bb.0:1993; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241994; VI-NEXT: v_lshlrev_b32_e32 v2, 1, v01995; VI-NEXT: s_waitcnt lgkmcnt(0)1996; VI-NEXT: v_mov_b32_e32 v1, s31997; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v21998; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1999; VI-NEXT: flat_load_ushort v3, v[0:1] glc2000; VI-NEXT: s_waitcnt vmcnt(0)2001; VI-NEXT: v_mov_b32_e32 v1, s12002; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v22003; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc2004; VI-NEXT: v_max_f16_e64 v2, -v3, -v32005; VI-NEXT: v_max_f16_e32 v2, 0.15915494, v22006; VI-NEXT: flat_store_short v[0:1], v22007; VI-NEXT: s_endpgm2008 %tid = call i32 @llvm.amdgcn.workitem.id.x()2009 %tid.ext = sext i32 %tid to i642010 %a.gep = getelementptr inbounds half, ptr addrspace(1) %a.ptr, i64 %tid.ext2011 %out.gep = getelementptr inbounds half, ptr addrspace(1) %out, i64 %tid.ext2012 %a = load volatile half, ptr addrspace(1) %a.gep2013 %min = call half @llvm.minnum.f16(half 0xHB118, half %a)2014 %fneg = fsub half -0.000000e+00, %min2015 store half %fneg, ptr addrspace(1) %out.gep2016 ret void2017}2018 2019define amdgpu_kernel void @v_fneg_inv2pi_minnum_f64(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) #0 {2020; SI-LABEL: v_fneg_inv2pi_minnum_f64:2021; SI: ; %bb.0:2022; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x92023; SI-NEXT: v_lshlrev_b32_e32 v2, 3, v02024; SI-NEXT: s_waitcnt lgkmcnt(0)2025; SI-NEXT: v_mov_b32_e32 v1, s32026; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v22027; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc2028; SI-NEXT: flat_load_dwordx2 v[0:1], v[0:1] glc2029; SI-NEXT: s_waitcnt vmcnt(0)2030; SI-NEXT: s_mov_b32 s2, 0x6dc9c8822031; SI-NEXT: s_mov_b32 s3, 0xbfc45f302032; SI-NEXT: v_mov_b32_e32 v3, s12033; SI-NEXT: v_add_i32_e32 v2, vcc, s0, v22034; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc2035; SI-NEXT: v_max_f64 v[0:1], -v[0:1], -v[0:1]2036; SI-NEXT: v_max_f64 v[0:1], v[0:1], s[2:3]2037; SI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]2038; SI-NEXT: s_endpgm2039;2040; VI-LABEL: v_fneg_inv2pi_minnum_f64:2041; VI: ; %bb.0:2042; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x242043; VI-NEXT: v_lshlrev_b32_e32 v2, 3, v02044; VI-NEXT: s_waitcnt lgkmcnt(0)2045; VI-NEXT: v_mov_b32_e32 v1, s32046; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v22047; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc2048; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1] glc2049; VI-NEXT: s_waitcnt vmcnt(0)2050; VI-NEXT: v_mov_b32_e32 v3, s12051; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v22052; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc2053; VI-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]2054; VI-NEXT: v_min_f64 v[0:1], v[0:1], 0.159154943091895322055; VI-NEXT: v_xor_b32_e32 v1, 0x80000000, v12056; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]2057; VI-NEXT: s_endpgm2058 %tid = call i32 @llvm.amdgcn.workitem.id.x()2059 %tid.ext = sext i32 %tid to i642060 %a.gep = getelementptr inbounds double, ptr addrspace(1) %a.ptr, i64 %tid.ext2061 %out.gep = getelementptr inbounds double, ptr addrspace(1) %out, i64 %tid.ext2062 %a = load volatile double, ptr addrspace(1) %a.gep2063 %min = call double @llvm.minnum.f64(double 0x3fc45f306dc9c882, double %a)2064 %fneg = fsub double -0.000000e+00, %min2065 store double %fneg, ptr addrspace(1) %out.gep2066 ret void2067}2068 2069define amdgpu_kernel void @v_fneg_neg_inv2pi_minnum_f64(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) #0 {2070; SI-LABEL: v_fneg_neg_inv2pi_minnum_f64:2071; SI: ; %bb.0:2072; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x92073; SI-NEXT: v_lshlrev_b32_e32 v2, 3, v02074; SI-NEXT: s_waitcnt lgkmcnt(0)2075; SI-NEXT: v_mov_b32_e32 v1, s32076; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v22077; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc2078; SI-NEXT: flat_load_dwordx2 v[0:1], v[0:1] glc2079; SI-NEXT: s_waitcnt vmcnt(0)2080; SI-NEXT: s_mov_b32 s2, 0x6dc9c8822081; SI-NEXT: s_mov_b32 s3, 0x3fc45f302082; SI-NEXT: v_mov_b32_e32 v3, s12083; SI-NEXT: v_add_i32_e32 v2, vcc, s0, v22084; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc2085; SI-NEXT: v_max_f64 v[0:1], -v[0:1], -v[0:1]2086; SI-NEXT: v_max_f64 v[0:1], v[0:1], s[2:3]2087; SI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]2088; SI-NEXT: s_endpgm2089;2090; VI-LABEL: v_fneg_neg_inv2pi_minnum_f64:2091; VI: ; %bb.0:2092; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x242093; VI-NEXT: v_lshlrev_b32_e32 v2, 3, v02094; VI-NEXT: s_waitcnt lgkmcnt(0)2095; VI-NEXT: v_mov_b32_e32 v1, s32096; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v22097; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc2098; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1] glc2099; VI-NEXT: s_waitcnt vmcnt(0)2100; VI-NEXT: v_mov_b32_e32 v3, s12101; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v22102; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc2103; VI-NEXT: v_max_f64 v[0:1], -v[0:1], -v[0:1]2104; VI-NEXT: v_max_f64 v[0:1], v[0:1], 0.159154943091895322105; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]2106; VI-NEXT: s_endpgm2107 %tid = call i32 @llvm.amdgcn.workitem.id.x()2108 %tid.ext = sext i32 %tid to i642109 %a.gep = getelementptr inbounds double, ptr addrspace(1) %a.ptr, i64 %tid.ext2110 %out.gep = getelementptr inbounds double, ptr addrspace(1) %out, i64 %tid.ext2111 %a = load volatile double, ptr addrspace(1) %a.gep2112 %min = call double @llvm.minnum.f64(double 0xbfc45f306dc9c882, double %a)2113 %fneg = fsub double -0.000000e+00, %min2114 store double %fneg, ptr addrspace(1) %out.gep2115 ret void2116}2117 2118define amdgpu_ps float @v_fneg_neg0_minnum_f32_no_ieee(float %a) #0 {2119; GCN-LABEL: v_fneg_neg0_minnum_f32_no_ieee:2120; GCN: ; %bb.0:2121; GCN-NEXT: v_max_f32_e64 v0, -v0, 02122; GCN-NEXT: ; return to shader part epilog2123 %min = call float @llvm.minnum.f32(float -0.0, float %a)2124 %fneg = fneg float %min2125 ret float %fneg2126}2127 2128define amdgpu_kernel void @v_fneg_0_minnum_foldable_use_f32_ieee(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {2129; SI-LABEL: v_fneg_0_minnum_foldable_use_f32_ieee:2130; SI: ; %bb.0:2131; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x92132; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd2133; SI-NEXT: v_lshlrev_b32_e32 v2, 2, v02134; SI-NEXT: s_waitcnt lgkmcnt(0)2135; SI-NEXT: v_mov_b32_e32 v1, s32136; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v22137; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc2138; SI-NEXT: v_mov_b32_e32 v3, s52139; SI-NEXT: flat_load_dword v4, v[0:1] glc2140; SI-NEXT: s_waitcnt vmcnt(0)2141; SI-NEXT: v_add_i32_e32 v0, vcc, s4, v22142; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v3, vcc2143; SI-NEXT: flat_load_dword v3, v[0:1] glc2144; SI-NEXT: s_waitcnt vmcnt(0)2145; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v22146; SI-NEXT: v_mov_b32_e32 v1, s12147; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc2148; SI-NEXT: v_mul_f32_e32 v2, 1.0, v42149; SI-NEXT: v_min_f32_e32 v2, 0, v22150; SI-NEXT: v_mul_f32_e64 v2, -v2, v32151; SI-NEXT: flat_store_dword v[0:1], v22152; SI-NEXT: s_endpgm2153;2154; VI-LABEL: v_fneg_0_minnum_foldable_use_f32_ieee:2155; VI: ; %bb.0:2156; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x242157; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x342158; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v02159; VI-NEXT: s_waitcnt lgkmcnt(0)2160; VI-NEXT: v_mov_b32_e32 v1, s32161; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v22162; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc2163; VI-NEXT: v_mov_b32_e32 v3, s52164; VI-NEXT: flat_load_dword v4, v[0:1] glc2165; VI-NEXT: s_waitcnt vmcnt(0)2166; VI-NEXT: v_add_u32_e32 v0, vcc, s4, v22167; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v3, vcc2168; VI-NEXT: flat_load_dword v3, v[0:1] glc2169; VI-NEXT: s_waitcnt vmcnt(0)2170; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v22171; VI-NEXT: v_mov_b32_e32 v1, s12172; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc2173; VI-NEXT: v_mul_f32_e32 v2, 1.0, v42174; VI-NEXT: v_min_f32_e32 v2, 0, v22175; VI-NEXT: v_mul_f32_e64 v2, -v2, v32176; VI-NEXT: flat_store_dword v[0:1], v22177; VI-NEXT: s_endpgm2178 %tid = call i32 @llvm.amdgcn.workitem.id.x()2179 %tid.ext = sext i32 %tid to i642180 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext2181 %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext2182 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext2183 %a = load volatile float, ptr addrspace(1) %a.gep2184 %b = load volatile float, ptr addrspace(1) %b.gep2185 %min = call float @llvm.minnum.f32(float 0.0, float %a)2186 %fneg = fneg float %min2187 %mul = fmul float %fneg, %b2188 store float %mul, ptr addrspace(1) %out.gep2189 ret void2190}2191 2192define amdgpu_kernel void @v_fneg_inv2pi_minnum_foldable_use_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {2193; SI-LABEL: v_fneg_inv2pi_minnum_foldable_use_f32:2194; SI: ; %bb.0:2195; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x92196; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd2197; SI-NEXT: v_lshlrev_b32_e32 v2, 2, v02198; SI-NEXT: s_waitcnt lgkmcnt(0)2199; SI-NEXT: v_mov_b32_e32 v1, s32200; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v22201; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc2202; SI-NEXT: v_mov_b32_e32 v3, s52203; SI-NEXT: flat_load_dword v4, v[0:1] glc2204; SI-NEXT: s_waitcnt vmcnt(0)2205; SI-NEXT: v_add_i32_e32 v0, vcc, s4, v22206; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v3, vcc2207; SI-NEXT: flat_load_dword v3, v[0:1] glc2208; SI-NEXT: s_waitcnt vmcnt(0)2209; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v22210; SI-NEXT: v_mov_b32_e32 v1, s12211; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc2212; SI-NEXT: v_mul_f32_e32 v2, -1.0, v42213; SI-NEXT: v_max_f32_e32 v2, 0xbe22f983, v22214; SI-NEXT: v_mul_f32_e32 v2, v2, v32215; SI-NEXT: flat_store_dword v[0:1], v22216; SI-NEXT: s_endpgm2217;2218; VI-LABEL: v_fneg_inv2pi_minnum_foldable_use_f32:2219; VI: ; %bb.0:2220; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x242221; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x342222; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v02223; VI-NEXT: s_waitcnt lgkmcnt(0)2224; VI-NEXT: v_mov_b32_e32 v1, s32225; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v22226; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc2227; VI-NEXT: v_mov_b32_e32 v3, s52228; VI-NEXT: flat_load_dword v4, v[0:1] glc2229; VI-NEXT: s_waitcnt vmcnt(0)2230; VI-NEXT: v_add_u32_e32 v0, vcc, s4, v22231; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v3, vcc2232; VI-NEXT: flat_load_dword v3, v[0:1] glc2233; VI-NEXT: s_waitcnt vmcnt(0)2234; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v22235; VI-NEXT: v_mov_b32_e32 v1, s12236; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc2237; VI-NEXT: v_mul_f32_e32 v2, 1.0, v42238; VI-NEXT: v_min_f32_e32 v2, 0.15915494, v22239; VI-NEXT: v_mul_f32_e64 v2, -v2, v32240; VI-NEXT: flat_store_dword v[0:1], v22241; VI-NEXT: s_endpgm2242 %tid = call i32 @llvm.amdgcn.workitem.id.x()2243 %tid.ext = sext i32 %tid to i642244 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext2245 %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext2246 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext2247 %a = load volatile float, ptr addrspace(1) %a.gep2248 %b = load volatile float, ptr addrspace(1) %b.gep2249 %min = call float @llvm.minnum.f32(float 0x3FC45F3060000000, float %a)2250 %fneg = fneg float %min2251 %mul = fmul float %fneg, %b2252 store float %mul, ptr addrspace(1) %out.gep2253 ret void2254}2255 2256define amdgpu_ps float @v_fneg_0_minnum_foldable_use_f32_no_ieee(float %a, float %b) #0 {2257; GCN-LABEL: v_fneg_0_minnum_foldable_use_f32_no_ieee:2258; GCN: ; %bb.0:2259; GCN-NEXT: v_min_f32_e32 v0, 0, v02260; GCN-NEXT: v_mul_f32_e64 v0, -v0, v12261; GCN-NEXT: ; return to shader part epilog2262 %min = call float @llvm.minnum.f32(float 0.0, float %a)2263 %fneg = fneg float %min2264 %mul = fmul float %fneg, %b2265 ret float %mul2266}2267 2268define amdgpu_kernel void @v_fneg_minnum_multi_use_minnum_f32_ieee(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {2269; SI-LABEL: v_fneg_minnum_multi_use_minnum_f32_ieee:2270; SI: ; %bb.0:2271; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x92272; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd2273; SI-NEXT: v_lshlrev_b32_e32 v2, 2, v02274; SI-NEXT: s_waitcnt lgkmcnt(0)2275; SI-NEXT: v_mov_b32_e32 v1, s32276; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v22277; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc2278; SI-NEXT: v_mov_b32_e32 v3, s52279; SI-NEXT: v_add_i32_e32 v2, vcc, s4, v22280; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc2281; SI-NEXT: flat_load_dword v4, v[0:1] glc2282; SI-NEXT: s_waitcnt vmcnt(0)2283; SI-NEXT: flat_load_dword v2, v[2:3] glc2284; SI-NEXT: s_waitcnt vmcnt(0)2285; SI-NEXT: v_mov_b32_e32 v0, s02286; SI-NEXT: v_mov_b32_e32 v1, s12287; SI-NEXT: v_mul_f32_e32 v3, -1.0, v42288; SI-NEXT: v_mul_f32_e32 v2, -1.0, v22289; SI-NEXT: v_max_f32_e32 v2, v3, v22290; SI-NEXT: v_mul_f32_e32 v3, -4.0, v22291; SI-NEXT: flat_store_dword v[0:1], v22292; SI-NEXT: s_waitcnt vmcnt(0)2293; SI-NEXT: flat_store_dword v[0:1], v32294; SI-NEXT: s_waitcnt vmcnt(0)2295; SI-NEXT: s_endpgm2296;2297; VI-LABEL: v_fneg_minnum_multi_use_minnum_f32_ieee:2298; VI: ; %bb.0:2299; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x242300; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x342301; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v02302; VI-NEXT: s_waitcnt lgkmcnt(0)2303; VI-NEXT: v_mov_b32_e32 v1, s32304; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v22305; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc2306; VI-NEXT: v_mov_b32_e32 v3, s52307; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v22308; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc2309; VI-NEXT: flat_load_dword v4, v[0:1] glc2310; VI-NEXT: s_waitcnt vmcnt(0)2311; VI-NEXT: flat_load_dword v2, v[2:3] glc2312; VI-NEXT: s_waitcnt vmcnt(0)2313; VI-NEXT: v_mov_b32_e32 v0, s02314; VI-NEXT: v_mov_b32_e32 v1, s12315; VI-NEXT: v_mul_f32_e32 v3, -1.0, v42316; VI-NEXT: v_mul_f32_e32 v2, -1.0, v22317; VI-NEXT: v_max_f32_e32 v2, v3, v22318; VI-NEXT: v_mul_f32_e32 v3, -4.0, v22319; VI-NEXT: flat_store_dword v[0:1], v22320; VI-NEXT: s_waitcnt vmcnt(0)2321; VI-NEXT: flat_store_dword v[0:1], v32322; VI-NEXT: s_waitcnt vmcnt(0)2323; VI-NEXT: s_endpgm2324 %tid = call i32 @llvm.amdgcn.workitem.id.x()2325 %tid.ext = sext i32 %tid to i642326 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext2327 %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext2328 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext2329 %a = load volatile float, ptr addrspace(1) %a.gep2330 %b = load volatile float, ptr addrspace(1) %b.gep2331 %min = call float @llvm.minnum.f32(float %a, float %b)2332 %fneg = fneg float %min2333 %use1 = fmul float %min, 4.02334 store volatile float %fneg, ptr addrspace(1) %out2335 store volatile float %use1, ptr addrspace(1) %out2336 ret void2337}2338 2339define amdgpu_ps <2 x float> @v_fneg_minnum_multi_use_minnum_f32_no_ieee(float %a, float %b) #0 {2340; GCN-LABEL: v_fneg_minnum_multi_use_minnum_f32_no_ieee:2341; GCN: ; %bb.0:2342; GCN-NEXT: v_max_f32_e64 v0, -v0, -v12343; GCN-NEXT: v_mul_f32_e32 v1, -4.0, v02344; GCN-NEXT: ; return to shader part epilog2345 %min = call float @llvm.minnum.f32(float %a, float %b)2346 %fneg = fneg float %min2347 %use1 = fmul float %min, 4.02348 %ins0 = insertelement <2 x float> poison, float %fneg, i32 02349 %ins1 = insertelement <2 x float> %ins0, float %use1, i32 12350 ret <2 x float> %ins12351}2352 2353; --------------------------------------------------------------------------------2354; fmaxnum tests2355; --------------------------------------------------------------------------------2356 2357define amdgpu_kernel void @v_fneg_maxnum_f32_ieee(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {2358; SI-LABEL: v_fneg_maxnum_f32_ieee:2359; SI: ; %bb.0:2360; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x92361; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd2362; SI-NEXT: v_lshlrev_b32_e32 v4, 2, v02363; SI-NEXT: s_waitcnt lgkmcnt(0)2364; SI-NEXT: v_mov_b32_e32 v1, s32365; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v42366; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc2367; SI-NEXT: v_mov_b32_e32 v3, s52368; SI-NEXT: v_add_i32_e32 v2, vcc, s4, v42369; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc2370; SI-NEXT: flat_load_dword v5, v[0:1] glc2371; SI-NEXT: s_waitcnt vmcnt(0)2372; SI-NEXT: flat_load_dword v2, v[2:3] glc2373; SI-NEXT: s_waitcnt vmcnt(0)2374; SI-NEXT: v_mov_b32_e32 v1, s12375; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v42376; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc2377; SI-NEXT: v_mul_f32_e32 v3, -1.0, v52378; SI-NEXT: v_mul_f32_e32 v2, -1.0, v22379; SI-NEXT: v_min_f32_e32 v2, v3, v22380; SI-NEXT: flat_store_dword v[0:1], v22381; SI-NEXT: s_endpgm2382;2383; VI-LABEL: v_fneg_maxnum_f32_ieee:2384; VI: ; %bb.0:2385; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x242386; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x342387; VI-NEXT: v_lshlrev_b32_e32 v4, 2, v02388; VI-NEXT: s_waitcnt lgkmcnt(0)2389; VI-NEXT: v_mov_b32_e32 v1, s32390; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v42391; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc2392; VI-NEXT: v_mov_b32_e32 v3, s52393; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v42394; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc2395; VI-NEXT: flat_load_dword v5, v[0:1] glc2396; VI-NEXT: s_waitcnt vmcnt(0)2397; VI-NEXT: flat_load_dword v2, v[2:3] glc2398; VI-NEXT: s_waitcnt vmcnt(0)2399; VI-NEXT: v_mov_b32_e32 v1, s12400; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v42401; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc2402; VI-NEXT: v_mul_f32_e32 v3, -1.0, v52403; VI-NEXT: v_mul_f32_e32 v2, -1.0, v22404; VI-NEXT: v_min_f32_e32 v2, v3, v22405; VI-NEXT: flat_store_dword v[0:1], v22406; VI-NEXT: s_endpgm2407 %tid = call i32 @llvm.amdgcn.workitem.id.x()2408 %tid.ext = sext i32 %tid to i642409 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext2410 %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext2411 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext2412 %a = load volatile float, ptr addrspace(1) %a.gep2413 %b = load volatile float, ptr addrspace(1) %b.gep2414 %max = call float @llvm.maxnum.f32(float %a, float %b)2415 %fneg = fneg float %max2416 store float %fneg, ptr addrspace(1) %out.gep2417 ret void2418}2419 2420define amdgpu_ps float @v_fneg_maxnum_f32_no_ieee(float %a, float %b) #0 {2421; GCN-LABEL: v_fneg_maxnum_f32_no_ieee:2422; GCN: ; %bb.0:2423; GCN-NEXT: v_min_f32_e64 v0, -v0, -v12424; GCN-NEXT: ; return to shader part epilog2425 %max = call float @llvm.maxnum.f32(float %a, float %b)2426 %fneg = fneg float %max2427 ret float %fneg2428}2429 2430define amdgpu_kernel void @v_fneg_self_maxnum_f32_ieee(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) #0 {2431; SI-LABEL: v_fneg_self_maxnum_f32_ieee:2432; SI: ; %bb.0:2433; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x92434; SI-NEXT: v_lshlrev_b32_e32 v2, 2, v02435; SI-NEXT: s_waitcnt lgkmcnt(0)2436; SI-NEXT: v_mov_b32_e32 v1, s32437; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v22438; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc2439; SI-NEXT: flat_load_dword v3, v[0:1] glc2440; SI-NEXT: s_waitcnt vmcnt(0)2441; SI-NEXT: v_mov_b32_e32 v1, s12442; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v22443; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc2444; SI-NEXT: v_mul_f32_e32 v2, -1.0, v32445; SI-NEXT: v_min_f32_e32 v2, v2, v22446; SI-NEXT: flat_store_dword v[0:1], v22447; SI-NEXT: s_endpgm2448;2449; VI-LABEL: v_fneg_self_maxnum_f32_ieee:2450; VI: ; %bb.0:2451; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x242452; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v02453; VI-NEXT: s_waitcnt lgkmcnt(0)2454; VI-NEXT: v_mov_b32_e32 v1, s32455; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v22456; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc2457; VI-NEXT: flat_load_dword v3, v[0:1] glc2458; VI-NEXT: s_waitcnt vmcnt(0)2459; VI-NEXT: v_mov_b32_e32 v1, s12460; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v22461; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc2462; VI-NEXT: v_mul_f32_e32 v2, -1.0, v32463; VI-NEXT: v_min_f32_e32 v2, v2, v22464; VI-NEXT: flat_store_dword v[0:1], v22465; VI-NEXT: s_endpgm2466 %tid = call i32 @llvm.amdgcn.workitem.id.x()2467 %tid.ext = sext i32 %tid to i642468 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext2469 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext2470 %a = load volatile float, ptr addrspace(1) %a.gep2471 %max = call float @llvm.maxnum.f32(float %a, float %a)2472 %max.fneg = fneg float %max2473 store float %max.fneg, ptr addrspace(1) %out.gep2474 ret void2475}2476 2477define amdgpu_ps float @v_fneg_self_maxnum_f32_no_ieee(float %a) #0 {2478; GCN-LABEL: v_fneg_self_maxnum_f32_no_ieee:2479; GCN: ; %bb.0:2480; GCN-NEXT: v_min_f32_e64 v0, -v0, -v02481; GCN-NEXT: ; return to shader part epilog2482 %max = call float @llvm.maxnum.f32(float %a, float %a)2483 %max.fneg = fneg float %max2484 ret float %max.fneg2485}2486 2487define amdgpu_kernel void @v_fneg_posk_maxnum_f32_ieee(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) #0 {2488; SI-LABEL: v_fneg_posk_maxnum_f32_ieee:2489; SI: ; %bb.0:2490; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x92491; SI-NEXT: v_lshlrev_b32_e32 v2, 2, v02492; SI-NEXT: s_waitcnt lgkmcnt(0)2493; SI-NEXT: v_mov_b32_e32 v1, s32494; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v22495; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc2496; SI-NEXT: flat_load_dword v3, v[0:1] glc2497; SI-NEXT: s_waitcnt vmcnt(0)2498; SI-NEXT: v_mov_b32_e32 v1, s12499; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v22500; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc2501; SI-NEXT: v_mul_f32_e32 v2, -1.0, v32502; SI-NEXT: v_min_f32_e32 v2, -4.0, v22503; SI-NEXT: flat_store_dword v[0:1], v22504; SI-NEXT: s_endpgm2505;2506; VI-LABEL: v_fneg_posk_maxnum_f32_ieee:2507; VI: ; %bb.0:2508; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x242509; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v02510; VI-NEXT: s_waitcnt lgkmcnt(0)2511; VI-NEXT: v_mov_b32_e32 v1, s32512; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v22513; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc2514; VI-NEXT: flat_load_dword v3, v[0:1] glc2515; VI-NEXT: s_waitcnt vmcnt(0)2516; VI-NEXT: v_mov_b32_e32 v1, s12517; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v22518; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc2519; VI-NEXT: v_mul_f32_e32 v2, -1.0, v32520; VI-NEXT: v_min_f32_e32 v2, -4.0, v22521; VI-NEXT: flat_store_dword v[0:1], v22522; VI-NEXT: s_endpgm2523 %tid = call i32 @llvm.amdgcn.workitem.id.x()2524 %tid.ext = sext i32 %tid to i642525 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext2526 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext2527 %a = load volatile float, ptr addrspace(1) %a.gep2528 %max = call float @llvm.maxnum.f32(float 4.0, float %a)2529 %fneg = fneg float %max2530 store float %fneg, ptr addrspace(1) %out.gep2531 ret void2532}2533 2534define amdgpu_ps float @v_fneg_posk_maxnum_f32_no_ieee(float %a) #0 {2535; GCN-LABEL: v_fneg_posk_maxnum_f32_no_ieee:2536; GCN: ; %bb.0:2537; GCN-NEXT: v_min_f32_e64 v0, -v0, -4.02538; GCN-NEXT: ; return to shader part epilog2539 %max = call float @llvm.maxnum.f32(float 4.0, float %a)2540 %fneg = fneg float %max2541 ret float %fneg2542}2543 2544define amdgpu_kernel void @v_fneg_negk_maxnum_f32_ieee(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) #0 {2545; SI-LABEL: v_fneg_negk_maxnum_f32_ieee:2546; SI: ; %bb.0:2547; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x92548; SI-NEXT: v_lshlrev_b32_e32 v2, 2, v02549; SI-NEXT: s_waitcnt lgkmcnt(0)2550; SI-NEXT: v_mov_b32_e32 v1, s32551; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v22552; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc2553; SI-NEXT: flat_load_dword v3, v[0:1] glc2554; SI-NEXT: s_waitcnt vmcnt(0)2555; SI-NEXT: v_mov_b32_e32 v1, s12556; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v22557; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc2558; SI-NEXT: v_mul_f32_e32 v2, -1.0, v32559; SI-NEXT: v_min_f32_e32 v2, 4.0, v22560; SI-NEXT: flat_store_dword v[0:1], v22561; SI-NEXT: s_endpgm2562;2563; VI-LABEL: v_fneg_negk_maxnum_f32_ieee:2564; VI: ; %bb.0:2565; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x242566; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v02567; VI-NEXT: s_waitcnt lgkmcnt(0)2568; VI-NEXT: v_mov_b32_e32 v1, s32569; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v22570; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc2571; VI-NEXT: flat_load_dword v3, v[0:1] glc2572; VI-NEXT: s_waitcnt vmcnt(0)2573; VI-NEXT: v_mov_b32_e32 v1, s12574; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v22575; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc2576; VI-NEXT: v_mul_f32_e32 v2, -1.0, v32577; VI-NEXT: v_min_f32_e32 v2, 4.0, v22578; VI-NEXT: flat_store_dword v[0:1], v22579; VI-NEXT: s_endpgm2580 %tid = call i32 @llvm.amdgcn.workitem.id.x()2581 %tid.ext = sext i32 %tid to i642582 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext2583 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext2584 %a = load volatile float, ptr addrspace(1) %a.gep2585 %max = call float @llvm.maxnum.f32(float -4.0, float %a)2586 %fneg = fneg float %max2587 store float %fneg, ptr addrspace(1) %out.gep2588 ret void2589}2590 2591define amdgpu_ps float @v_fneg_negk_maxnum_f32_no_ieee(float %a) #0 {2592; GCN-LABEL: v_fneg_negk_maxnum_f32_no_ieee:2593; GCN: ; %bb.0:2594; GCN-NEXT: v_min_f32_e64 v0, -v0, 4.02595; GCN-NEXT: ; return to shader part epilog2596 %max = call float @llvm.maxnum.f32(float -4.0, float %a)2597 %fneg = fneg float %max2598 ret float %fneg2599}2600 2601define amdgpu_kernel void @v_fneg_0_maxnum_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) #0 {2602; SI-LABEL: v_fneg_0_maxnum_f32:2603; SI: ; %bb.0:2604; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x92605; SI-NEXT: v_lshlrev_b32_e32 v2, 2, v02606; SI-NEXT: s_waitcnt lgkmcnt(0)2607; SI-NEXT: v_mov_b32_e32 v1, s32608; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v22609; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc2610; SI-NEXT: flat_load_dword v3, v[0:1] glc2611; SI-NEXT: s_waitcnt vmcnt(0)2612; SI-NEXT: v_mov_b32_e32 v1, s12613; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v22614; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc2615; SI-NEXT: v_max_f32_e32 v2, 0, v32616; SI-NEXT: v_xor_b32_e32 v2, 0x80000000, v22617; SI-NEXT: flat_store_dword v[0:1], v22618; SI-NEXT: s_endpgm2619;2620; VI-LABEL: v_fneg_0_maxnum_f32:2621; VI: ; %bb.0:2622; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x242623; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v02624; VI-NEXT: s_waitcnt lgkmcnt(0)2625; VI-NEXT: v_mov_b32_e32 v1, s32626; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v22627; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc2628; VI-NEXT: flat_load_dword v3, v[0:1] glc2629; VI-NEXT: s_waitcnt vmcnt(0)2630; VI-NEXT: v_mov_b32_e32 v1, s12631; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v22632; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc2633; VI-NEXT: v_max_f32_e32 v2, 0, v32634; VI-NEXT: v_xor_b32_e32 v2, 0x80000000, v22635; VI-NEXT: flat_store_dword v[0:1], v22636; VI-NEXT: s_endpgm2637 %tid = call i32 @llvm.amdgcn.workitem.id.x()2638 %tid.ext = sext i32 %tid to i642639 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext2640 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext2641 %a = load volatile float, ptr addrspace(1) %a.gep2642 %max = call nnan float @llvm.maxnum.f32(float 0.0, float %a)2643 %fneg = fneg float %max2644 store float %fneg, ptr addrspace(1) %out.gep2645 ret void2646}2647 2648define amdgpu_kernel void @v_fneg_neg0_maxnum_f32_ieee(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) #0 {2649; SI-LABEL: v_fneg_neg0_maxnum_f32_ieee:2650; SI: ; %bb.0:2651; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x92652; SI-NEXT: v_lshlrev_b32_e32 v2, 2, v02653; SI-NEXT: s_waitcnt lgkmcnt(0)2654; SI-NEXT: v_mov_b32_e32 v1, s32655; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v22656; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc2657; SI-NEXT: flat_load_dword v3, v[0:1] glc2658; SI-NEXT: s_waitcnt vmcnt(0)2659; SI-NEXT: v_mov_b32_e32 v1, s12660; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v22661; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc2662; SI-NEXT: v_mul_f32_e32 v2, -1.0, v32663; SI-NEXT: v_min_f32_e32 v2, 0, v22664; SI-NEXT: flat_store_dword v[0:1], v22665; SI-NEXT: s_endpgm2666;2667; VI-LABEL: v_fneg_neg0_maxnum_f32_ieee:2668; VI: ; %bb.0:2669; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x242670; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v02671; VI-NEXT: s_waitcnt lgkmcnt(0)2672; VI-NEXT: v_mov_b32_e32 v1, s32673; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v22674; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc2675; VI-NEXT: flat_load_dword v3, v[0:1] glc2676; VI-NEXT: s_waitcnt vmcnt(0)2677; VI-NEXT: v_mov_b32_e32 v1, s12678; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v22679; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc2680; VI-NEXT: v_mul_f32_e32 v2, -1.0, v32681; VI-NEXT: v_min_f32_e32 v2, 0, v22682; VI-NEXT: flat_store_dword v[0:1], v22683; VI-NEXT: s_endpgm2684 %tid = call i32 @llvm.amdgcn.workitem.id.x()2685 %tid.ext = sext i32 %tid to i642686 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext2687 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext2688 %a = load volatile float, ptr addrspace(1) %a.gep2689 %max = call float @llvm.maxnum.f32(float -0.0, float %a)2690 %fneg = fneg float %max2691 store float %fneg, ptr addrspace(1) %out.gep2692 ret void2693}2694 2695define amdgpu_ps float @v_fneg_neg0_maxnum_f32_no_ieee(float %a) #0 {2696; GCN-LABEL: v_fneg_neg0_maxnum_f32_no_ieee:2697; GCN: ; %bb.0:2698; GCN-NEXT: v_min_f32_e64 v0, -v0, 02699; GCN-NEXT: ; return to shader part epilog2700 %max = call float @llvm.maxnum.f32(float -0.0, float %a)2701 %fneg = fneg float %max2702 ret float %fneg2703}2704 2705define amdgpu_kernel void @v_fneg_0_maxnum_foldable_use_f32_ieee(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {2706; SI-LABEL: v_fneg_0_maxnum_foldable_use_f32_ieee:2707; SI: ; %bb.0:2708; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x92709; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd2710; SI-NEXT: v_lshlrev_b32_e32 v2, 2, v02711; SI-NEXT: s_waitcnt lgkmcnt(0)2712; SI-NEXT: v_mov_b32_e32 v1, s32713; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v22714; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc2715; SI-NEXT: v_mov_b32_e32 v3, s52716; SI-NEXT: flat_load_dword v4, v[0:1] glc2717; SI-NEXT: s_waitcnt vmcnt(0)2718; SI-NEXT: v_add_i32_e32 v0, vcc, s4, v22719; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v3, vcc2720; SI-NEXT: flat_load_dword v3, v[0:1] glc2721; SI-NEXT: s_waitcnt vmcnt(0)2722; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v22723; SI-NEXT: v_mov_b32_e32 v1, s12724; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc2725; SI-NEXT: v_mul_f32_e32 v2, 1.0, v42726; SI-NEXT: v_max_f32_e32 v2, 0, v22727; SI-NEXT: v_mul_f32_e64 v2, -v2, v32728; SI-NEXT: flat_store_dword v[0:1], v22729; SI-NEXT: s_endpgm2730;2731; VI-LABEL: v_fneg_0_maxnum_foldable_use_f32_ieee:2732; VI: ; %bb.0:2733; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x242734; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x342735; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v02736; VI-NEXT: s_waitcnt lgkmcnt(0)2737; VI-NEXT: v_mov_b32_e32 v1, s32738; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v22739; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc2740; VI-NEXT: v_mov_b32_e32 v3, s52741; VI-NEXT: flat_load_dword v4, v[0:1] glc2742; VI-NEXT: s_waitcnt vmcnt(0)2743; VI-NEXT: v_add_u32_e32 v0, vcc, s4, v22744; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v3, vcc2745; VI-NEXT: flat_load_dword v3, v[0:1] glc2746; VI-NEXT: s_waitcnt vmcnt(0)2747; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v22748; VI-NEXT: v_mov_b32_e32 v1, s12749; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc2750; VI-NEXT: v_mul_f32_e32 v2, 1.0, v42751; VI-NEXT: v_max_f32_e32 v2, 0, v22752; VI-NEXT: v_mul_f32_e64 v2, -v2, v32753; VI-NEXT: flat_store_dword v[0:1], v22754; VI-NEXT: s_endpgm2755 %tid = call i32 @llvm.amdgcn.workitem.id.x()2756 %tid.ext = sext i32 %tid to i642757 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext2758 %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext2759 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext2760 %a = load volatile float, ptr addrspace(1) %a.gep2761 %b = load volatile float, ptr addrspace(1) %b.gep2762 %max = call float @llvm.maxnum.f32(float 0.0, float %a)2763 %fneg = fneg float %max2764 %mul = fmul float %fneg, %b2765 store float %mul, ptr addrspace(1) %out.gep2766 ret void2767}2768 2769define amdgpu_ps float @v_fneg_0_maxnum_foldable_use_f32_no_ieee(float %a, float %b) #0 {2770; GCN-LABEL: v_fneg_0_maxnum_foldable_use_f32_no_ieee:2771; GCN: ; %bb.0:2772; GCN-NEXT: v_max_f32_e32 v0, 0, v02773; GCN-NEXT: v_mul_f32_e64 v0, -v0, v12774; GCN-NEXT: ; return to shader part epilog2775 %max = call float @llvm.maxnum.f32(float 0.0, float %a)2776 %fneg = fneg float %max2777 %mul = fmul float %fneg, %b2778 ret float %mul2779}2780 2781define amdgpu_kernel void @v_fneg_maxnum_multi_use_maxnum_f32_ieee(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {2782; SI-LABEL: v_fneg_maxnum_multi_use_maxnum_f32_ieee:2783; SI: ; %bb.0:2784; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x92785; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd2786; SI-NEXT: v_lshlrev_b32_e32 v2, 2, v02787; SI-NEXT: s_waitcnt lgkmcnt(0)2788; SI-NEXT: v_mov_b32_e32 v1, s32789; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v22790; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc2791; SI-NEXT: v_mov_b32_e32 v3, s52792; SI-NEXT: v_add_i32_e32 v2, vcc, s4, v22793; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc2794; SI-NEXT: flat_load_dword v4, v[0:1] glc2795; SI-NEXT: s_waitcnt vmcnt(0)2796; SI-NEXT: flat_load_dword v2, v[2:3] glc2797; SI-NEXT: s_waitcnt vmcnt(0)2798; SI-NEXT: v_mov_b32_e32 v0, s02799; SI-NEXT: v_mov_b32_e32 v1, s12800; SI-NEXT: v_mul_f32_e32 v3, -1.0, v42801; SI-NEXT: v_mul_f32_e32 v2, -1.0, v22802; SI-NEXT: v_min_f32_e32 v2, v3, v22803; SI-NEXT: v_mul_f32_e32 v3, -4.0, v22804; SI-NEXT: flat_store_dword v[0:1], v22805; SI-NEXT: s_waitcnt vmcnt(0)2806; SI-NEXT: flat_store_dword v[0:1], v32807; SI-NEXT: s_waitcnt vmcnt(0)2808; SI-NEXT: s_endpgm2809;2810; VI-LABEL: v_fneg_maxnum_multi_use_maxnum_f32_ieee:2811; VI: ; %bb.0:2812; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x242813; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x342814; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v02815; VI-NEXT: s_waitcnt lgkmcnt(0)2816; VI-NEXT: v_mov_b32_e32 v1, s32817; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v22818; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc2819; VI-NEXT: v_mov_b32_e32 v3, s52820; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v22821; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc2822; VI-NEXT: flat_load_dword v4, v[0:1] glc2823; VI-NEXT: s_waitcnt vmcnt(0)2824; VI-NEXT: flat_load_dword v2, v[2:3] glc2825; VI-NEXT: s_waitcnt vmcnt(0)2826; VI-NEXT: v_mov_b32_e32 v0, s02827; VI-NEXT: v_mov_b32_e32 v1, s12828; VI-NEXT: v_mul_f32_e32 v3, -1.0, v42829; VI-NEXT: v_mul_f32_e32 v2, -1.0, v22830; VI-NEXT: v_min_f32_e32 v2, v3, v22831; VI-NEXT: v_mul_f32_e32 v3, -4.0, v22832; VI-NEXT: flat_store_dword v[0:1], v22833; VI-NEXT: s_waitcnt vmcnt(0)2834; VI-NEXT: flat_store_dword v[0:1], v32835; VI-NEXT: s_waitcnt vmcnt(0)2836; VI-NEXT: s_endpgm2837 %tid = call i32 @llvm.amdgcn.workitem.id.x()2838 %tid.ext = sext i32 %tid to i642839 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext2840 %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext2841 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext2842 %a = load volatile float, ptr addrspace(1) %a.gep2843 %b = load volatile float, ptr addrspace(1) %b.gep2844 %max = call float @llvm.maxnum.f32(float %a, float %b)2845 %fneg = fneg float %max2846 %use1 = fmul float %max, 4.02847 store volatile float %fneg, ptr addrspace(1) %out2848 store volatile float %use1, ptr addrspace(1) %out2849 ret void2850}2851 2852define amdgpu_ps <2 x float> @v_fneg_maxnum_multi_use_maxnum_f32_no_ieee(float %a, float %b) #0 {2853; GCN-LABEL: v_fneg_maxnum_multi_use_maxnum_f32_no_ieee:2854; GCN: ; %bb.0:2855; GCN-NEXT: v_min_f32_e64 v0, -v0, -v12856; GCN-NEXT: v_mul_f32_e32 v1, -4.0, v02857; GCN-NEXT: ; return to shader part epilog2858 %max = call float @llvm.maxnum.f32(float %a, float %b)2859 %fneg = fneg float %max2860 %use1 = fmul float %max, 4.02861 %ins0 = insertelement <2 x float> poison, float %fneg, i32 02862 %ins1 = insertelement <2 x float> %ins0, float %use1, i32 12863 ret <2 x float> %ins12864}2865 2866; --------------------------------------------------------------------------------2867; fma tests2868; --------------------------------------------------------------------------------2869 2870define amdgpu_kernel void @v_fneg_fma_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr, ptr addrspace(1) %c.ptr) #0 {2871; SI-SAFE-LABEL: v_fneg_fma_f32:2872; SI-SAFE: ; %bb.0:2873; SI-SAFE-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x92874; SI-SAFE-NEXT: v_lshlrev_b32_e32 v6, 2, v02875; SI-SAFE-NEXT: s_waitcnt lgkmcnt(0)2876; SI-SAFE-NEXT: v_mov_b32_e32 v1, s32877; SI-SAFE-NEXT: v_add_i32_e32 v0, vcc, s2, v62878; SI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc2879; SI-SAFE-NEXT: v_mov_b32_e32 v3, s52880; SI-SAFE-NEXT: v_add_i32_e32 v2, vcc, s4, v62881; SI-SAFE-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc2882; SI-SAFE-NEXT: v_mov_b32_e32 v5, s72883; SI-SAFE-NEXT: v_add_i32_e32 v4, vcc, s6, v62884; SI-SAFE-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc2885; SI-SAFE-NEXT: flat_load_dword v7, v[0:1] glc2886; SI-SAFE-NEXT: s_waitcnt vmcnt(0)2887; SI-SAFE-NEXT: flat_load_dword v2, v[2:3] glc2888; SI-SAFE-NEXT: s_waitcnt vmcnt(0)2889; SI-SAFE-NEXT: flat_load_dword v3, v[4:5] glc2890; SI-SAFE-NEXT: s_waitcnt vmcnt(0)2891; SI-SAFE-NEXT: v_mov_b32_e32 v1, s12892; SI-SAFE-NEXT: v_add_i32_e32 v0, vcc, s0, v62893; SI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc2894; SI-SAFE-NEXT: v_fma_f32 v2, v7, v2, v32895; SI-SAFE-NEXT: v_xor_b32_e32 v2, 0x80000000, v22896; SI-SAFE-NEXT: flat_store_dword v[0:1], v22897; SI-SAFE-NEXT: s_endpgm2898;2899; SI-NSZ-LABEL: v_fneg_fma_f32:2900; SI-NSZ: ; %bb.0:2901; SI-NSZ-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x92902; SI-NSZ-NEXT: v_lshlrev_b32_e32 v6, 2, v02903; SI-NSZ-NEXT: s_waitcnt lgkmcnt(0)2904; SI-NSZ-NEXT: v_mov_b32_e32 v1, s32905; SI-NSZ-NEXT: v_add_i32_e32 v0, vcc, s2, v62906; SI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc2907; SI-NSZ-NEXT: v_mov_b32_e32 v3, s52908; SI-NSZ-NEXT: v_add_i32_e32 v2, vcc, s4, v62909; SI-NSZ-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc2910; SI-NSZ-NEXT: v_mov_b32_e32 v5, s72911; SI-NSZ-NEXT: v_add_i32_e32 v4, vcc, s6, v62912; SI-NSZ-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc2913; SI-NSZ-NEXT: flat_load_dword v7, v[0:1] glc2914; SI-NSZ-NEXT: s_waitcnt vmcnt(0)2915; SI-NSZ-NEXT: flat_load_dword v2, v[2:3] glc2916; SI-NSZ-NEXT: s_waitcnt vmcnt(0)2917; SI-NSZ-NEXT: flat_load_dword v3, v[4:5] glc2918; SI-NSZ-NEXT: s_waitcnt vmcnt(0)2919; SI-NSZ-NEXT: v_mov_b32_e32 v1, s12920; SI-NSZ-NEXT: v_add_i32_e32 v0, vcc, s0, v62921; SI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc2922; SI-NSZ-NEXT: v_fma_f32 v2, v7, -v2, -v32923; SI-NSZ-NEXT: flat_store_dword v[0:1], v22924; SI-NSZ-NEXT: s_endpgm2925;2926; VI-SAFE-LABEL: v_fneg_fma_f32:2927; VI-SAFE: ; %bb.0:2928; VI-SAFE-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x242929; VI-SAFE-NEXT: v_lshlrev_b32_e32 v6, 2, v02930; VI-SAFE-NEXT: s_waitcnt lgkmcnt(0)2931; VI-SAFE-NEXT: v_mov_b32_e32 v1, s32932; VI-SAFE-NEXT: v_add_u32_e32 v0, vcc, s2, v62933; VI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc2934; VI-SAFE-NEXT: v_mov_b32_e32 v3, s52935; VI-SAFE-NEXT: v_add_u32_e32 v2, vcc, s4, v62936; VI-SAFE-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc2937; VI-SAFE-NEXT: v_mov_b32_e32 v5, s72938; VI-SAFE-NEXT: v_add_u32_e32 v4, vcc, s6, v62939; VI-SAFE-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc2940; VI-SAFE-NEXT: flat_load_dword v7, v[0:1] glc2941; VI-SAFE-NEXT: s_waitcnt vmcnt(0)2942; VI-SAFE-NEXT: flat_load_dword v2, v[2:3] glc2943; VI-SAFE-NEXT: s_waitcnt vmcnt(0)2944; VI-SAFE-NEXT: flat_load_dword v3, v[4:5] glc2945; VI-SAFE-NEXT: s_waitcnt vmcnt(0)2946; VI-SAFE-NEXT: v_mov_b32_e32 v1, s12947; VI-SAFE-NEXT: v_add_u32_e32 v0, vcc, s0, v62948; VI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc2949; VI-SAFE-NEXT: v_fma_f32 v2, v7, v2, v32950; VI-SAFE-NEXT: v_xor_b32_e32 v2, 0x80000000, v22951; VI-SAFE-NEXT: flat_store_dword v[0:1], v22952; VI-SAFE-NEXT: s_endpgm2953;2954; VI-NSZ-LABEL: v_fneg_fma_f32:2955; VI-NSZ: ; %bb.0:2956; VI-NSZ-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x242957; VI-NSZ-NEXT: v_lshlrev_b32_e32 v6, 2, v02958; VI-NSZ-NEXT: s_waitcnt lgkmcnt(0)2959; VI-NSZ-NEXT: v_mov_b32_e32 v1, s32960; VI-NSZ-NEXT: v_add_u32_e32 v0, vcc, s2, v62961; VI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc2962; VI-NSZ-NEXT: v_mov_b32_e32 v3, s52963; VI-NSZ-NEXT: v_add_u32_e32 v2, vcc, s4, v62964; VI-NSZ-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc2965; VI-NSZ-NEXT: v_mov_b32_e32 v5, s72966; VI-NSZ-NEXT: v_add_u32_e32 v4, vcc, s6, v62967; VI-NSZ-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc2968; VI-NSZ-NEXT: flat_load_dword v7, v[0:1] glc2969; VI-NSZ-NEXT: s_waitcnt vmcnt(0)2970; VI-NSZ-NEXT: flat_load_dword v2, v[2:3] glc2971; VI-NSZ-NEXT: s_waitcnt vmcnt(0)2972; VI-NSZ-NEXT: flat_load_dword v3, v[4:5] glc2973; VI-NSZ-NEXT: s_waitcnt vmcnt(0)2974; VI-NSZ-NEXT: v_mov_b32_e32 v1, s12975; VI-NSZ-NEXT: v_add_u32_e32 v0, vcc, s0, v62976; VI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc2977; VI-NSZ-NEXT: v_fma_f32 v2, v7, -v2, -v32978; VI-NSZ-NEXT: flat_store_dword v[0:1], v22979; VI-NSZ-NEXT: s_endpgm2980 %tid = call i32 @llvm.amdgcn.workitem.id.x()2981 %tid.ext = sext i32 %tid to i642982 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext2983 %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext2984 %c.gep = getelementptr inbounds float, ptr addrspace(1) %c.ptr, i64 %tid.ext2985 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext2986 %a = load volatile float, ptr addrspace(1) %a.gep2987 %b = load volatile float, ptr addrspace(1) %b.gep2988 %c = load volatile float, ptr addrspace(1) %c.gep2989 %fma = call float @llvm.fma.f32(float %a, float %b, float %c)2990 %fneg = fneg float %fma2991 store float %fneg, ptr addrspace(1) %out.gep2992 ret void2993}2994 2995define amdgpu_kernel void @v_fneg_fma_store_use_fma_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr, ptr addrspace(1) %c.ptr) #0 {2996; SI-LABEL: v_fneg_fma_store_use_fma_f32:2997; SI: ; %bb.0:2998; SI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x92999; SI-NEXT: v_lshlrev_b32_e32 v4, 2, v03000; SI-NEXT: s_waitcnt lgkmcnt(0)3001; SI-NEXT: v_mov_b32_e32 v1, s33002; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v43003; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc3004; SI-NEXT: v_mov_b32_e32 v3, s53005; SI-NEXT: v_add_i32_e32 v2, vcc, s4, v43006; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc3007; SI-NEXT: v_mov_b32_e32 v5, s73008; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v43009; SI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc3010; SI-NEXT: flat_load_dword v6, v[0:1] glc3011; SI-NEXT: s_waitcnt vmcnt(0)3012; SI-NEXT: flat_load_dword v2, v[2:3] glc3013; SI-NEXT: s_waitcnt vmcnt(0)3014; SI-NEXT: flat_load_dword v3, v[4:5] glc3015; SI-NEXT: s_waitcnt vmcnt(0)3016; SI-NEXT: v_mov_b32_e32 v0, s03017; SI-NEXT: v_mov_b32_e32 v1, s13018; SI-NEXT: v_fma_f32 v2, v6, v2, v33019; SI-NEXT: v_xor_b32_e32 v3, 0x80000000, v23020; SI-NEXT: flat_store_dword v[0:1], v33021; SI-NEXT: s_waitcnt vmcnt(0)3022; SI-NEXT: flat_store_dword v[0:1], v23023; SI-NEXT: s_waitcnt vmcnt(0)3024; SI-NEXT: s_endpgm3025;3026; VI-LABEL: v_fneg_fma_store_use_fma_f32:3027; VI: ; %bb.0:3028; VI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x243029; VI-NEXT: v_lshlrev_b32_e32 v4, 2, v03030; VI-NEXT: s_waitcnt lgkmcnt(0)3031; VI-NEXT: v_mov_b32_e32 v1, s33032; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v43033; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc3034; VI-NEXT: v_mov_b32_e32 v3, s53035; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v43036; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc3037; VI-NEXT: v_mov_b32_e32 v5, s73038; VI-NEXT: v_add_u32_e32 v4, vcc, s6, v43039; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc3040; VI-NEXT: flat_load_dword v6, v[0:1] glc3041; VI-NEXT: s_waitcnt vmcnt(0)3042; VI-NEXT: flat_load_dword v2, v[2:3] glc3043; VI-NEXT: s_waitcnt vmcnt(0)3044; VI-NEXT: flat_load_dword v3, v[4:5] glc3045; VI-NEXT: s_waitcnt vmcnt(0)3046; VI-NEXT: v_mov_b32_e32 v0, s03047; VI-NEXT: v_mov_b32_e32 v1, s13048; VI-NEXT: v_fma_f32 v2, v6, v2, v33049; VI-NEXT: v_xor_b32_e32 v3, 0x80000000, v23050; VI-NEXT: flat_store_dword v[0:1], v33051; VI-NEXT: s_waitcnt vmcnt(0)3052; VI-NEXT: flat_store_dword v[0:1], v23053; VI-NEXT: s_waitcnt vmcnt(0)3054; VI-NEXT: s_endpgm3055 %tid = call i32 @llvm.amdgcn.workitem.id.x()3056 %tid.ext = sext i32 %tid to i643057 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext3058 %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext3059 %c.gep = getelementptr inbounds float, ptr addrspace(1) %c.ptr, i64 %tid.ext3060 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext3061 %a = load volatile float, ptr addrspace(1) %a.gep3062 %b = load volatile float, ptr addrspace(1) %b.gep3063 %c = load volatile float, ptr addrspace(1) %c.gep3064 %fma = call float @llvm.fma.f32(float %a, float %b, float %c)3065 %fneg = fneg float %fma3066 store volatile float %fneg, ptr addrspace(1) %out3067 store volatile float %fma, ptr addrspace(1) %out3068 ret void3069}3070 3071define amdgpu_kernel void @v_fneg_fma_multi_use_fma_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr, ptr addrspace(1) %c.ptr) #0 {3072; SI-SAFE-LABEL: v_fneg_fma_multi_use_fma_f32:3073; SI-SAFE: ; %bb.0:3074; SI-SAFE-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x93075; SI-SAFE-NEXT: v_lshlrev_b32_e32 v4, 2, v03076; SI-SAFE-NEXT: s_waitcnt lgkmcnt(0)3077; SI-SAFE-NEXT: v_mov_b32_e32 v1, s33078; SI-SAFE-NEXT: v_add_i32_e32 v0, vcc, s2, v43079; SI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc3080; SI-SAFE-NEXT: v_mov_b32_e32 v3, s53081; SI-SAFE-NEXT: v_add_i32_e32 v2, vcc, s4, v43082; SI-SAFE-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc3083; SI-SAFE-NEXT: v_mov_b32_e32 v5, s73084; SI-SAFE-NEXT: v_add_i32_e32 v4, vcc, s6, v43085; SI-SAFE-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc3086; SI-SAFE-NEXT: flat_load_dword v6, v[0:1] glc3087; SI-SAFE-NEXT: s_waitcnt vmcnt(0)3088; SI-SAFE-NEXT: flat_load_dword v2, v[2:3] glc3089; SI-SAFE-NEXT: s_waitcnt vmcnt(0)3090; SI-SAFE-NEXT: flat_load_dword v3, v[4:5] glc3091; SI-SAFE-NEXT: s_waitcnt vmcnt(0)3092; SI-SAFE-NEXT: v_mov_b32_e32 v0, s03093; SI-SAFE-NEXT: v_mov_b32_e32 v1, s13094; SI-SAFE-NEXT: v_fma_f32 v2, v6, v2, v33095; SI-SAFE-NEXT: v_xor_b32_e32 v3, 0x80000000, v23096; SI-SAFE-NEXT: v_mul_f32_e32 v2, 4.0, v23097; SI-SAFE-NEXT: flat_store_dword v[0:1], v33098; SI-SAFE-NEXT: s_waitcnt vmcnt(0)3099; SI-SAFE-NEXT: flat_store_dword v[0:1], v23100; SI-SAFE-NEXT: s_waitcnt vmcnt(0)3101; SI-SAFE-NEXT: s_endpgm3102;3103; SI-NSZ-LABEL: v_fneg_fma_multi_use_fma_f32:3104; SI-NSZ: ; %bb.0:3105; SI-NSZ-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x93106; SI-NSZ-NEXT: v_lshlrev_b32_e32 v4, 2, v03107; SI-NSZ-NEXT: s_waitcnt lgkmcnt(0)3108; SI-NSZ-NEXT: v_mov_b32_e32 v1, s33109; SI-NSZ-NEXT: v_add_i32_e32 v0, vcc, s2, v43110; SI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc3111; SI-NSZ-NEXT: v_mov_b32_e32 v3, s53112; SI-NSZ-NEXT: v_add_i32_e32 v2, vcc, s4, v43113; SI-NSZ-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc3114; SI-NSZ-NEXT: v_mov_b32_e32 v5, s73115; SI-NSZ-NEXT: v_add_i32_e32 v4, vcc, s6, v43116; SI-NSZ-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc3117; SI-NSZ-NEXT: flat_load_dword v6, v[0:1] glc3118; SI-NSZ-NEXT: s_waitcnt vmcnt(0)3119; SI-NSZ-NEXT: flat_load_dword v2, v[2:3] glc3120; SI-NSZ-NEXT: s_waitcnt vmcnt(0)3121; SI-NSZ-NEXT: flat_load_dword v3, v[4:5] glc3122; SI-NSZ-NEXT: s_waitcnt vmcnt(0)3123; SI-NSZ-NEXT: v_mov_b32_e32 v0, s03124; SI-NSZ-NEXT: v_mov_b32_e32 v1, s13125; SI-NSZ-NEXT: v_fma_f32 v2, v6, -v2, -v33126; SI-NSZ-NEXT: v_mul_f32_e32 v3, -4.0, v23127; SI-NSZ-NEXT: flat_store_dword v[0:1], v23128; SI-NSZ-NEXT: s_waitcnt vmcnt(0)3129; SI-NSZ-NEXT: flat_store_dword v[0:1], v33130; SI-NSZ-NEXT: s_waitcnt vmcnt(0)3131; SI-NSZ-NEXT: s_endpgm3132;3133; VI-SAFE-LABEL: v_fneg_fma_multi_use_fma_f32:3134; VI-SAFE: ; %bb.0:3135; VI-SAFE-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x243136; VI-SAFE-NEXT: v_lshlrev_b32_e32 v4, 2, v03137; VI-SAFE-NEXT: s_waitcnt lgkmcnt(0)3138; VI-SAFE-NEXT: v_mov_b32_e32 v1, s33139; VI-SAFE-NEXT: v_add_u32_e32 v0, vcc, s2, v43140; VI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc3141; VI-SAFE-NEXT: v_mov_b32_e32 v3, s53142; VI-SAFE-NEXT: v_add_u32_e32 v2, vcc, s4, v43143; VI-SAFE-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc3144; VI-SAFE-NEXT: v_mov_b32_e32 v5, s73145; VI-SAFE-NEXT: v_add_u32_e32 v4, vcc, s6, v43146; VI-SAFE-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc3147; VI-SAFE-NEXT: flat_load_dword v6, v[0:1] glc3148; VI-SAFE-NEXT: s_waitcnt vmcnt(0)3149; VI-SAFE-NEXT: flat_load_dword v2, v[2:3] glc3150; VI-SAFE-NEXT: s_waitcnt vmcnt(0)3151; VI-SAFE-NEXT: flat_load_dword v3, v[4:5] glc3152; VI-SAFE-NEXT: s_waitcnt vmcnt(0)3153; VI-SAFE-NEXT: v_mov_b32_e32 v0, s03154; VI-SAFE-NEXT: v_mov_b32_e32 v1, s13155; VI-SAFE-NEXT: v_fma_f32 v2, v6, v2, v33156; VI-SAFE-NEXT: v_xor_b32_e32 v3, 0x80000000, v23157; VI-SAFE-NEXT: v_mul_f32_e32 v2, 4.0, v23158; VI-SAFE-NEXT: flat_store_dword v[0:1], v33159; VI-SAFE-NEXT: s_waitcnt vmcnt(0)3160; VI-SAFE-NEXT: flat_store_dword v[0:1], v23161; VI-SAFE-NEXT: s_waitcnt vmcnt(0)3162; VI-SAFE-NEXT: s_endpgm3163;3164; VI-NSZ-LABEL: v_fneg_fma_multi_use_fma_f32:3165; VI-NSZ: ; %bb.0:3166; VI-NSZ-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x243167; VI-NSZ-NEXT: v_lshlrev_b32_e32 v4, 2, v03168; VI-NSZ-NEXT: s_waitcnt lgkmcnt(0)3169; VI-NSZ-NEXT: v_mov_b32_e32 v1, s33170; VI-NSZ-NEXT: v_add_u32_e32 v0, vcc, s2, v43171; VI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc3172; VI-NSZ-NEXT: v_mov_b32_e32 v3, s53173; VI-NSZ-NEXT: v_add_u32_e32 v2, vcc, s4, v43174; VI-NSZ-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc3175; VI-NSZ-NEXT: v_mov_b32_e32 v5, s73176; VI-NSZ-NEXT: v_add_u32_e32 v4, vcc, s6, v43177; VI-NSZ-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc3178; VI-NSZ-NEXT: flat_load_dword v6, v[0:1] glc3179; VI-NSZ-NEXT: s_waitcnt vmcnt(0)3180; VI-NSZ-NEXT: flat_load_dword v2, v[2:3] glc3181; VI-NSZ-NEXT: s_waitcnt vmcnt(0)3182; VI-NSZ-NEXT: flat_load_dword v3, v[4:5] glc3183; VI-NSZ-NEXT: s_waitcnt vmcnt(0)3184; VI-NSZ-NEXT: v_mov_b32_e32 v0, s03185; VI-NSZ-NEXT: v_mov_b32_e32 v1, s13186; VI-NSZ-NEXT: v_fma_f32 v2, v6, -v2, -v33187; VI-NSZ-NEXT: v_mul_f32_e32 v3, -4.0, v23188; VI-NSZ-NEXT: flat_store_dword v[0:1], v23189; VI-NSZ-NEXT: s_waitcnt vmcnt(0)3190; VI-NSZ-NEXT: flat_store_dword v[0:1], v33191; VI-NSZ-NEXT: s_waitcnt vmcnt(0)3192; VI-NSZ-NEXT: s_endpgm3193 %tid = call i32 @llvm.amdgcn.workitem.id.x()3194 %tid.ext = sext i32 %tid to i643195 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext3196 %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext3197 %c.gep = getelementptr inbounds float, ptr addrspace(1) %c.ptr, i64 %tid.ext3198 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext3199 %a = load volatile float, ptr addrspace(1) %a.gep3200 %b = load volatile float, ptr addrspace(1) %b.gep3201 %c = load volatile float, ptr addrspace(1) %c.gep3202 %fma = call float @llvm.fma.f32(float %a, float %b, float %c)3203 %fneg = fneg float %fma3204 %use1 = fmul float %fma, 4.03205 store volatile float %fneg, ptr addrspace(1) %out3206 store volatile float %use1, ptr addrspace(1) %out3207 ret void3208}3209 3210define amdgpu_kernel void @v_fneg_fma_fneg_x_y_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr, ptr addrspace(1) %c.ptr) #0 {3211; SI-SAFE-LABEL: v_fneg_fma_fneg_x_y_f32:3212; SI-SAFE: ; %bb.0:3213; SI-SAFE-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x93214; SI-SAFE-NEXT: v_lshlrev_b32_e32 v4, 2, v03215; SI-SAFE-NEXT: s_waitcnt lgkmcnt(0)3216; SI-SAFE-NEXT: v_mov_b32_e32 v1, s33217; SI-SAFE-NEXT: v_add_i32_e32 v0, vcc, s2, v43218; SI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc3219; SI-SAFE-NEXT: v_mov_b32_e32 v3, s53220; SI-SAFE-NEXT: v_add_i32_e32 v2, vcc, s4, v43221; SI-SAFE-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc3222; SI-SAFE-NEXT: v_mov_b32_e32 v5, s73223; SI-SAFE-NEXT: v_add_i32_e32 v4, vcc, s6, v43224; SI-SAFE-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc3225; SI-SAFE-NEXT: flat_load_dword v0, v[0:1] glc3226; SI-SAFE-NEXT: s_waitcnt vmcnt(0)3227; SI-SAFE-NEXT: flat_load_dword v1, v[2:3] glc3228; SI-SAFE-NEXT: s_waitcnt vmcnt(0)3229; SI-SAFE-NEXT: flat_load_dword v2, v[4:5] glc3230; SI-SAFE-NEXT: s_waitcnt vmcnt(0)3231; SI-SAFE-NEXT: v_fma_f32 v0, -v0, v1, v23232; SI-SAFE-NEXT: v_xor_b32_e32 v2, 0x80000000, v03233; SI-SAFE-NEXT: v_mov_b32_e32 v0, s03234; SI-SAFE-NEXT: v_mov_b32_e32 v1, s13235; SI-SAFE-NEXT: flat_store_dword v[0:1], v23236; SI-SAFE-NEXT: s_waitcnt vmcnt(0)3237; SI-SAFE-NEXT: s_endpgm3238;3239; SI-NSZ-LABEL: v_fneg_fma_fneg_x_y_f32:3240; SI-NSZ: ; %bb.0:3241; SI-NSZ-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x93242; SI-NSZ-NEXT: v_lshlrev_b32_e32 v4, 2, v03243; SI-NSZ-NEXT: s_waitcnt lgkmcnt(0)3244; SI-NSZ-NEXT: v_mov_b32_e32 v1, s33245; SI-NSZ-NEXT: v_add_i32_e32 v0, vcc, s2, v43246; SI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc3247; SI-NSZ-NEXT: v_mov_b32_e32 v3, s53248; SI-NSZ-NEXT: v_add_i32_e32 v2, vcc, s4, v43249; SI-NSZ-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc3250; SI-NSZ-NEXT: v_mov_b32_e32 v5, s73251; SI-NSZ-NEXT: v_add_i32_e32 v4, vcc, s6, v43252; SI-NSZ-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc3253; SI-NSZ-NEXT: flat_load_dword v0, v[0:1] glc3254; SI-NSZ-NEXT: s_waitcnt vmcnt(0)3255; SI-NSZ-NEXT: flat_load_dword v1, v[2:3] glc3256; SI-NSZ-NEXT: s_waitcnt vmcnt(0)3257; SI-NSZ-NEXT: flat_load_dword v2, v[4:5] glc3258; SI-NSZ-NEXT: s_waitcnt vmcnt(0)3259; SI-NSZ-NEXT: v_fma_f32 v2, v0, v1, -v23260; SI-NSZ-NEXT: v_mov_b32_e32 v0, s03261; SI-NSZ-NEXT: v_mov_b32_e32 v1, s13262; SI-NSZ-NEXT: flat_store_dword v[0:1], v23263; SI-NSZ-NEXT: s_waitcnt vmcnt(0)3264; SI-NSZ-NEXT: s_endpgm3265;3266; VI-SAFE-LABEL: v_fneg_fma_fneg_x_y_f32:3267; VI-SAFE: ; %bb.0:3268; VI-SAFE-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x243269; VI-SAFE-NEXT: v_lshlrev_b32_e32 v4, 2, v03270; VI-SAFE-NEXT: s_waitcnt lgkmcnt(0)3271; VI-SAFE-NEXT: v_mov_b32_e32 v1, s33272; VI-SAFE-NEXT: v_add_u32_e32 v0, vcc, s2, v43273; VI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc3274; VI-SAFE-NEXT: v_mov_b32_e32 v3, s53275; VI-SAFE-NEXT: v_add_u32_e32 v2, vcc, s4, v43276; VI-SAFE-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc3277; VI-SAFE-NEXT: v_mov_b32_e32 v5, s73278; VI-SAFE-NEXT: v_add_u32_e32 v4, vcc, s6, v43279; VI-SAFE-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc3280; VI-SAFE-NEXT: flat_load_dword v0, v[0:1] glc3281; VI-SAFE-NEXT: s_waitcnt vmcnt(0)3282; VI-SAFE-NEXT: flat_load_dword v1, v[2:3] glc3283; VI-SAFE-NEXT: s_waitcnt vmcnt(0)3284; VI-SAFE-NEXT: flat_load_dword v2, v[4:5] glc3285; VI-SAFE-NEXT: s_waitcnt vmcnt(0)3286; VI-SAFE-NEXT: v_fma_f32 v0, -v0, v1, v23287; VI-SAFE-NEXT: v_xor_b32_e32 v2, 0x80000000, v03288; VI-SAFE-NEXT: v_mov_b32_e32 v0, s03289; VI-SAFE-NEXT: v_mov_b32_e32 v1, s13290; VI-SAFE-NEXT: flat_store_dword v[0:1], v23291; VI-SAFE-NEXT: s_waitcnt vmcnt(0)3292; VI-SAFE-NEXT: s_endpgm3293;3294; VI-NSZ-LABEL: v_fneg_fma_fneg_x_y_f32:3295; VI-NSZ: ; %bb.0:3296; VI-NSZ-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x243297; VI-NSZ-NEXT: v_lshlrev_b32_e32 v4, 2, v03298; VI-NSZ-NEXT: s_waitcnt lgkmcnt(0)3299; VI-NSZ-NEXT: v_mov_b32_e32 v1, s33300; VI-NSZ-NEXT: v_add_u32_e32 v0, vcc, s2, v43301; VI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc3302; VI-NSZ-NEXT: v_mov_b32_e32 v3, s53303; VI-NSZ-NEXT: v_add_u32_e32 v2, vcc, s4, v43304; VI-NSZ-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc3305; VI-NSZ-NEXT: v_mov_b32_e32 v5, s73306; VI-NSZ-NEXT: v_add_u32_e32 v4, vcc, s6, v43307; VI-NSZ-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc3308; VI-NSZ-NEXT: flat_load_dword v0, v[0:1] glc3309; VI-NSZ-NEXT: s_waitcnt vmcnt(0)3310; VI-NSZ-NEXT: flat_load_dword v1, v[2:3] glc3311; VI-NSZ-NEXT: s_waitcnt vmcnt(0)3312; VI-NSZ-NEXT: flat_load_dword v2, v[4:5] glc3313; VI-NSZ-NEXT: s_waitcnt vmcnt(0)3314; VI-NSZ-NEXT: v_fma_f32 v2, v0, v1, -v23315; VI-NSZ-NEXT: v_mov_b32_e32 v0, s03316; VI-NSZ-NEXT: v_mov_b32_e32 v1, s13317; VI-NSZ-NEXT: flat_store_dword v[0:1], v23318; VI-NSZ-NEXT: s_waitcnt vmcnt(0)3319; VI-NSZ-NEXT: s_endpgm3320 %tid = call i32 @llvm.amdgcn.workitem.id.x()3321 %tid.ext = sext i32 %tid to i643322 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext3323 %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext3324 %c.gep = getelementptr inbounds float, ptr addrspace(1) %c.ptr, i64 %tid.ext3325 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext3326 %a = load volatile float, ptr addrspace(1) %a.gep3327 %b = load volatile float, ptr addrspace(1) %b.gep3328 %c = load volatile float, ptr addrspace(1) %c.gep3329 %fneg.a = fneg float %a3330 %fma = call float @llvm.fma.f32(float %fneg.a, float %b, float %c)3331 %fneg = fneg float %fma3332 store volatile float %fneg, ptr addrspace(1) %out3333 ret void3334}3335 3336define amdgpu_kernel void @v_fneg_fma_x_fneg_y_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr, ptr addrspace(1) %c.ptr) #0 {3337; SI-SAFE-LABEL: v_fneg_fma_x_fneg_y_f32:3338; SI-SAFE: ; %bb.0:3339; SI-SAFE-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x93340; SI-SAFE-NEXT: v_lshlrev_b32_e32 v4, 2, v03341; SI-SAFE-NEXT: s_waitcnt lgkmcnt(0)3342; SI-SAFE-NEXT: v_mov_b32_e32 v1, s33343; SI-SAFE-NEXT: v_add_i32_e32 v0, vcc, s2, v43344; SI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc3345; SI-SAFE-NEXT: v_mov_b32_e32 v3, s73346; SI-SAFE-NEXT: v_add_i32_e32 v2, vcc, s6, v43347; SI-SAFE-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc3348; SI-SAFE-NEXT: v_mov_b32_e32 v5, s53349; SI-SAFE-NEXT: v_add_i32_e32 v4, vcc, s4, v43350; SI-SAFE-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc3351; SI-SAFE-NEXT: flat_load_dword v0, v[0:1] glc3352; SI-SAFE-NEXT: s_waitcnt vmcnt(0)3353; SI-SAFE-NEXT: flat_load_dword v1, v[4:5] glc3354; SI-SAFE-NEXT: s_waitcnt vmcnt(0)3355; SI-SAFE-NEXT: flat_load_dword v2, v[2:3] glc3356; SI-SAFE-NEXT: s_waitcnt vmcnt(0)3357; SI-SAFE-NEXT: v_fma_f32 v0, v0, -v1, v23358; SI-SAFE-NEXT: v_xor_b32_e32 v2, 0x80000000, v03359; SI-SAFE-NEXT: v_mov_b32_e32 v0, s03360; SI-SAFE-NEXT: v_mov_b32_e32 v1, s13361; SI-SAFE-NEXT: flat_store_dword v[0:1], v23362; SI-SAFE-NEXT: s_waitcnt vmcnt(0)3363; SI-SAFE-NEXT: s_endpgm3364;3365; SI-NSZ-LABEL: v_fneg_fma_x_fneg_y_f32:3366; SI-NSZ: ; %bb.0:3367; SI-NSZ-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x93368; SI-NSZ-NEXT: v_lshlrev_b32_e32 v4, 2, v03369; SI-NSZ-NEXT: s_waitcnt lgkmcnt(0)3370; SI-NSZ-NEXT: v_mov_b32_e32 v1, s33371; SI-NSZ-NEXT: v_add_i32_e32 v0, vcc, s2, v43372; SI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc3373; SI-NSZ-NEXT: v_mov_b32_e32 v3, s73374; SI-NSZ-NEXT: v_add_i32_e32 v2, vcc, s6, v43375; SI-NSZ-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc3376; SI-NSZ-NEXT: v_mov_b32_e32 v5, s53377; SI-NSZ-NEXT: v_add_i32_e32 v4, vcc, s4, v43378; SI-NSZ-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc3379; SI-NSZ-NEXT: flat_load_dword v0, v[0:1] glc3380; SI-NSZ-NEXT: s_waitcnt vmcnt(0)3381; SI-NSZ-NEXT: flat_load_dword v1, v[4:5] glc3382; SI-NSZ-NEXT: s_waitcnt vmcnt(0)3383; SI-NSZ-NEXT: flat_load_dword v2, v[2:3] glc3384; SI-NSZ-NEXT: s_waitcnt vmcnt(0)3385; SI-NSZ-NEXT: v_fma_f32 v2, v0, v1, -v23386; SI-NSZ-NEXT: v_mov_b32_e32 v0, s03387; SI-NSZ-NEXT: v_mov_b32_e32 v1, s13388; SI-NSZ-NEXT: flat_store_dword v[0:1], v23389; SI-NSZ-NEXT: s_waitcnt vmcnt(0)3390; SI-NSZ-NEXT: s_endpgm3391;3392; VI-SAFE-LABEL: v_fneg_fma_x_fneg_y_f32:3393; VI-SAFE: ; %bb.0:3394; VI-SAFE-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x243395; VI-SAFE-NEXT: v_lshlrev_b32_e32 v4, 2, v03396; VI-SAFE-NEXT: s_waitcnt lgkmcnt(0)3397; VI-SAFE-NEXT: v_mov_b32_e32 v1, s33398; VI-SAFE-NEXT: v_add_u32_e32 v0, vcc, s2, v43399; VI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc3400; VI-SAFE-NEXT: v_mov_b32_e32 v3, s73401; VI-SAFE-NEXT: v_add_u32_e32 v2, vcc, s6, v43402; VI-SAFE-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc3403; VI-SAFE-NEXT: v_mov_b32_e32 v5, s53404; VI-SAFE-NEXT: v_add_u32_e32 v4, vcc, s4, v43405; VI-SAFE-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc3406; VI-SAFE-NEXT: flat_load_dword v0, v[0:1] glc3407; VI-SAFE-NEXT: s_waitcnt vmcnt(0)3408; VI-SAFE-NEXT: flat_load_dword v1, v[4:5] glc3409; VI-SAFE-NEXT: s_waitcnt vmcnt(0)3410; VI-SAFE-NEXT: flat_load_dword v2, v[2:3] glc3411; VI-SAFE-NEXT: s_waitcnt vmcnt(0)3412; VI-SAFE-NEXT: v_fma_f32 v0, v0, -v1, v23413; VI-SAFE-NEXT: v_xor_b32_e32 v2, 0x80000000, v03414; VI-SAFE-NEXT: v_mov_b32_e32 v0, s03415; VI-SAFE-NEXT: v_mov_b32_e32 v1, s13416; VI-SAFE-NEXT: flat_store_dword v[0:1], v23417; VI-SAFE-NEXT: s_waitcnt vmcnt(0)3418; VI-SAFE-NEXT: s_endpgm3419;3420; VI-NSZ-LABEL: v_fneg_fma_x_fneg_y_f32:3421; VI-NSZ: ; %bb.0:3422; VI-NSZ-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x243423; VI-NSZ-NEXT: v_lshlrev_b32_e32 v4, 2, v03424; VI-NSZ-NEXT: s_waitcnt lgkmcnt(0)3425; VI-NSZ-NEXT: v_mov_b32_e32 v1, s33426; VI-NSZ-NEXT: v_add_u32_e32 v0, vcc, s2, v43427; VI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc3428; VI-NSZ-NEXT: v_mov_b32_e32 v3, s73429; VI-NSZ-NEXT: v_add_u32_e32 v2, vcc, s6, v43430; VI-NSZ-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc3431; VI-NSZ-NEXT: v_mov_b32_e32 v5, s53432; VI-NSZ-NEXT: v_add_u32_e32 v4, vcc, s4, v43433; VI-NSZ-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc3434; VI-NSZ-NEXT: flat_load_dword v0, v[0:1] glc3435; VI-NSZ-NEXT: s_waitcnt vmcnt(0)3436; VI-NSZ-NEXT: flat_load_dword v1, v[4:5] glc3437; VI-NSZ-NEXT: s_waitcnt vmcnt(0)3438; VI-NSZ-NEXT: flat_load_dword v2, v[2:3] glc3439; VI-NSZ-NEXT: s_waitcnt vmcnt(0)3440; VI-NSZ-NEXT: v_fma_f32 v2, v0, v1, -v23441; VI-NSZ-NEXT: v_mov_b32_e32 v0, s03442; VI-NSZ-NEXT: v_mov_b32_e32 v1, s13443; VI-NSZ-NEXT: flat_store_dword v[0:1], v23444; VI-NSZ-NEXT: s_waitcnt vmcnt(0)3445; VI-NSZ-NEXT: s_endpgm3446 %tid = call i32 @llvm.amdgcn.workitem.id.x()3447 %tid.ext = sext i32 %tid to i643448 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext3449 %c.gep = getelementptr inbounds float, ptr addrspace(1) %c.ptr, i64 %tid.ext3450 %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext3451 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext3452 %a = load volatile float, ptr addrspace(1) %a.gep3453 %b = load volatile float, ptr addrspace(1) %b.gep3454 %c = load volatile float, ptr addrspace(1) %c.gep3455 %fneg.b = fneg float %b3456 %fma = call float @llvm.fma.f32(float %a, float %fneg.b, float %c)3457 %fneg = fneg float %fma3458 store volatile float %fneg, ptr addrspace(1) %out3459 ret void3460}3461 3462define amdgpu_kernel void @v_fneg_fma_fneg_fneg_y_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr, ptr addrspace(1) %c.ptr) #0 {3463; SI-SAFE-LABEL: v_fneg_fma_fneg_fneg_y_f32:3464; SI-SAFE: ; %bb.0:3465; SI-SAFE-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x93466; SI-SAFE-NEXT: v_lshlrev_b32_e32 v4, 2, v03467; SI-SAFE-NEXT: s_waitcnt lgkmcnt(0)3468; SI-SAFE-NEXT: v_mov_b32_e32 v1, s33469; SI-SAFE-NEXT: v_add_i32_e32 v0, vcc, s2, v43470; SI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc3471; SI-SAFE-NEXT: v_mov_b32_e32 v3, s53472; SI-SAFE-NEXT: v_add_i32_e32 v2, vcc, s4, v43473; SI-SAFE-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc3474; SI-SAFE-NEXT: v_mov_b32_e32 v5, s73475; SI-SAFE-NEXT: v_add_i32_e32 v4, vcc, s6, v43476; SI-SAFE-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc3477; SI-SAFE-NEXT: flat_load_dword v0, v[0:1] glc3478; SI-SAFE-NEXT: s_waitcnt vmcnt(0)3479; SI-SAFE-NEXT: flat_load_dword v1, v[2:3] glc3480; SI-SAFE-NEXT: s_waitcnt vmcnt(0)3481; SI-SAFE-NEXT: flat_load_dword v2, v[4:5] glc3482; SI-SAFE-NEXT: s_waitcnt vmcnt(0)3483; SI-SAFE-NEXT: v_fma_f32 v0, v0, v1, v23484; SI-SAFE-NEXT: v_xor_b32_e32 v2, 0x80000000, v03485; SI-SAFE-NEXT: v_mov_b32_e32 v0, s03486; SI-SAFE-NEXT: v_mov_b32_e32 v1, s13487; SI-SAFE-NEXT: flat_store_dword v[0:1], v23488; SI-SAFE-NEXT: s_waitcnt vmcnt(0)3489; SI-SAFE-NEXT: s_endpgm3490;3491; SI-NSZ-LABEL: v_fneg_fma_fneg_fneg_y_f32:3492; SI-NSZ: ; %bb.0:3493; SI-NSZ-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x93494; SI-NSZ-NEXT: v_lshlrev_b32_e32 v4, 2, v03495; SI-NSZ-NEXT: s_waitcnt lgkmcnt(0)3496; SI-NSZ-NEXT: v_mov_b32_e32 v1, s33497; SI-NSZ-NEXT: v_add_i32_e32 v0, vcc, s2, v43498; SI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc3499; SI-NSZ-NEXT: v_mov_b32_e32 v3, s53500; SI-NSZ-NEXT: v_add_i32_e32 v2, vcc, s4, v43501; SI-NSZ-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc3502; SI-NSZ-NEXT: v_mov_b32_e32 v5, s73503; SI-NSZ-NEXT: v_add_i32_e32 v4, vcc, s6, v43504; SI-NSZ-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc3505; SI-NSZ-NEXT: flat_load_dword v0, v[0:1] glc3506; SI-NSZ-NEXT: s_waitcnt vmcnt(0)3507; SI-NSZ-NEXT: flat_load_dword v1, v[2:3] glc3508; SI-NSZ-NEXT: s_waitcnt vmcnt(0)3509; SI-NSZ-NEXT: flat_load_dword v2, v[4:5] glc3510; SI-NSZ-NEXT: s_waitcnt vmcnt(0)3511; SI-NSZ-NEXT: v_fma_f32 v2, v0, -v1, -v23512; SI-NSZ-NEXT: v_mov_b32_e32 v0, s03513; SI-NSZ-NEXT: v_mov_b32_e32 v1, s13514; SI-NSZ-NEXT: flat_store_dword v[0:1], v23515; SI-NSZ-NEXT: s_waitcnt vmcnt(0)3516; SI-NSZ-NEXT: s_endpgm3517;3518; VI-SAFE-LABEL: v_fneg_fma_fneg_fneg_y_f32:3519; VI-SAFE: ; %bb.0:3520; VI-SAFE-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x243521; VI-SAFE-NEXT: v_lshlrev_b32_e32 v4, 2, v03522; VI-SAFE-NEXT: s_waitcnt lgkmcnt(0)3523; VI-SAFE-NEXT: v_mov_b32_e32 v1, s33524; VI-SAFE-NEXT: v_add_u32_e32 v0, vcc, s2, v43525; VI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc3526; VI-SAFE-NEXT: v_mov_b32_e32 v3, s53527; VI-SAFE-NEXT: v_add_u32_e32 v2, vcc, s4, v43528; VI-SAFE-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc3529; VI-SAFE-NEXT: v_mov_b32_e32 v5, s73530; VI-SAFE-NEXT: v_add_u32_e32 v4, vcc, s6, v43531; VI-SAFE-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc3532; VI-SAFE-NEXT: flat_load_dword v0, v[0:1] glc3533; VI-SAFE-NEXT: s_waitcnt vmcnt(0)3534; VI-SAFE-NEXT: flat_load_dword v1, v[2:3] glc3535; VI-SAFE-NEXT: s_waitcnt vmcnt(0)3536; VI-SAFE-NEXT: flat_load_dword v2, v[4:5] glc3537; VI-SAFE-NEXT: s_waitcnt vmcnt(0)3538; VI-SAFE-NEXT: v_fma_f32 v0, v0, v1, v23539; VI-SAFE-NEXT: v_xor_b32_e32 v2, 0x80000000, v03540; VI-SAFE-NEXT: v_mov_b32_e32 v0, s03541; VI-SAFE-NEXT: v_mov_b32_e32 v1, s13542; VI-SAFE-NEXT: flat_store_dword v[0:1], v23543; VI-SAFE-NEXT: s_waitcnt vmcnt(0)3544; VI-SAFE-NEXT: s_endpgm3545;3546; VI-NSZ-LABEL: v_fneg_fma_fneg_fneg_y_f32:3547; VI-NSZ: ; %bb.0:3548; VI-NSZ-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x243549; VI-NSZ-NEXT: v_lshlrev_b32_e32 v4, 2, v03550; VI-NSZ-NEXT: s_waitcnt lgkmcnt(0)3551; VI-NSZ-NEXT: v_mov_b32_e32 v1, s33552; VI-NSZ-NEXT: v_add_u32_e32 v0, vcc, s2, v43553; VI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc3554; VI-NSZ-NEXT: v_mov_b32_e32 v3, s53555; VI-NSZ-NEXT: v_add_u32_e32 v2, vcc, s4, v43556; VI-NSZ-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc3557; VI-NSZ-NEXT: v_mov_b32_e32 v5, s73558; VI-NSZ-NEXT: v_add_u32_e32 v4, vcc, s6, v43559; VI-NSZ-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc3560; VI-NSZ-NEXT: flat_load_dword v0, v[0:1] glc3561; VI-NSZ-NEXT: s_waitcnt vmcnt(0)3562; VI-NSZ-NEXT: flat_load_dword v1, v[2:3] glc3563; VI-NSZ-NEXT: s_waitcnt vmcnt(0)3564; VI-NSZ-NEXT: flat_load_dword v2, v[4:5] glc3565; VI-NSZ-NEXT: s_waitcnt vmcnt(0)3566; VI-NSZ-NEXT: v_fma_f32 v2, v0, -v1, -v23567; VI-NSZ-NEXT: v_mov_b32_e32 v0, s03568; VI-NSZ-NEXT: v_mov_b32_e32 v1, s13569; VI-NSZ-NEXT: flat_store_dword v[0:1], v23570; VI-NSZ-NEXT: s_waitcnt vmcnt(0)3571; VI-NSZ-NEXT: s_endpgm3572 %tid = call i32 @llvm.amdgcn.workitem.id.x()3573 %tid.ext = sext i32 %tid to i643574 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext3575 %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext3576 %c.gep = getelementptr inbounds float, ptr addrspace(1) %c.ptr, i64 %tid.ext3577 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext3578 %a = load volatile float, ptr addrspace(1) %a.gep3579 %b = load volatile float, ptr addrspace(1) %b.gep3580 %c = load volatile float, ptr addrspace(1) %c.gep3581 %fneg.a = fneg float %a3582 %fneg.b = fneg float %b3583 %fma = call float @llvm.fma.f32(float %fneg.a, float %fneg.b, float %c)3584 %fneg = fneg float %fma3585 store volatile float %fneg, ptr addrspace(1) %out3586 ret void3587}3588 3589define amdgpu_kernel void @v_fneg_fma_fneg_x_fneg_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr, ptr addrspace(1) %c.ptr) #0 {3590; SI-SAFE-LABEL: v_fneg_fma_fneg_x_fneg_f32:3591; SI-SAFE: ; %bb.0:3592; SI-SAFE-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x93593; SI-SAFE-NEXT: v_lshlrev_b32_e32 v4, 2, v03594; SI-SAFE-NEXT: s_waitcnt lgkmcnt(0)3595; SI-SAFE-NEXT: v_mov_b32_e32 v1, s33596; SI-SAFE-NEXT: v_add_i32_e32 v0, vcc, s2, v43597; SI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc3598; SI-SAFE-NEXT: v_mov_b32_e32 v3, s53599; SI-SAFE-NEXT: v_add_i32_e32 v2, vcc, s4, v43600; SI-SAFE-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc3601; SI-SAFE-NEXT: v_mov_b32_e32 v5, s73602; SI-SAFE-NEXT: v_add_i32_e32 v4, vcc, s6, v43603; SI-SAFE-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc3604; SI-SAFE-NEXT: flat_load_dword v0, v[0:1] glc3605; SI-SAFE-NEXT: s_waitcnt vmcnt(0)3606; SI-SAFE-NEXT: flat_load_dword v1, v[2:3] glc3607; SI-SAFE-NEXT: s_waitcnt vmcnt(0)3608; SI-SAFE-NEXT: flat_load_dword v2, v[4:5] glc3609; SI-SAFE-NEXT: s_waitcnt vmcnt(0)3610; SI-SAFE-NEXT: v_fma_f32 v0, -v0, v1, -v23611; SI-SAFE-NEXT: v_xor_b32_e32 v2, 0x80000000, v03612; SI-SAFE-NEXT: v_mov_b32_e32 v0, s03613; SI-SAFE-NEXT: v_mov_b32_e32 v1, s13614; SI-SAFE-NEXT: flat_store_dword v[0:1], v23615; SI-SAFE-NEXT: s_waitcnt vmcnt(0)3616; SI-SAFE-NEXT: s_endpgm3617;3618; SI-NSZ-LABEL: v_fneg_fma_fneg_x_fneg_f32:3619; SI-NSZ: ; %bb.0:3620; SI-NSZ-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x93621; SI-NSZ-NEXT: v_lshlrev_b32_e32 v4, 2, v03622; SI-NSZ-NEXT: s_waitcnt lgkmcnt(0)3623; SI-NSZ-NEXT: v_mov_b32_e32 v1, s33624; SI-NSZ-NEXT: v_add_i32_e32 v0, vcc, s2, v43625; SI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc3626; SI-NSZ-NEXT: v_mov_b32_e32 v3, s53627; SI-NSZ-NEXT: v_add_i32_e32 v2, vcc, s4, v43628; SI-NSZ-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc3629; SI-NSZ-NEXT: v_mov_b32_e32 v5, s73630; SI-NSZ-NEXT: v_add_i32_e32 v4, vcc, s6, v43631; SI-NSZ-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc3632; SI-NSZ-NEXT: flat_load_dword v0, v[0:1] glc3633; SI-NSZ-NEXT: s_waitcnt vmcnt(0)3634; SI-NSZ-NEXT: flat_load_dword v1, v[2:3] glc3635; SI-NSZ-NEXT: s_waitcnt vmcnt(0)3636; SI-NSZ-NEXT: flat_load_dword v2, v[4:5] glc3637; SI-NSZ-NEXT: s_waitcnt vmcnt(0)3638; SI-NSZ-NEXT: v_fma_f32 v2, v0, v1, v23639; SI-NSZ-NEXT: v_mov_b32_e32 v0, s03640; SI-NSZ-NEXT: v_mov_b32_e32 v1, s13641; SI-NSZ-NEXT: flat_store_dword v[0:1], v23642; SI-NSZ-NEXT: s_waitcnt vmcnt(0)3643; SI-NSZ-NEXT: s_endpgm3644;3645; VI-SAFE-LABEL: v_fneg_fma_fneg_x_fneg_f32:3646; VI-SAFE: ; %bb.0:3647; VI-SAFE-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x243648; VI-SAFE-NEXT: v_lshlrev_b32_e32 v4, 2, v03649; VI-SAFE-NEXT: s_waitcnt lgkmcnt(0)3650; VI-SAFE-NEXT: v_mov_b32_e32 v1, s33651; VI-SAFE-NEXT: v_add_u32_e32 v0, vcc, s2, v43652; VI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc3653; VI-SAFE-NEXT: v_mov_b32_e32 v3, s53654; VI-SAFE-NEXT: v_add_u32_e32 v2, vcc, s4, v43655; VI-SAFE-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc3656; VI-SAFE-NEXT: v_mov_b32_e32 v5, s73657; VI-SAFE-NEXT: v_add_u32_e32 v4, vcc, s6, v43658; VI-SAFE-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc3659; VI-SAFE-NEXT: flat_load_dword v0, v[0:1] glc3660; VI-SAFE-NEXT: s_waitcnt vmcnt(0)3661; VI-SAFE-NEXT: flat_load_dword v1, v[2:3] glc3662; VI-SAFE-NEXT: s_waitcnt vmcnt(0)3663; VI-SAFE-NEXT: flat_load_dword v2, v[4:5] glc3664; VI-SAFE-NEXT: s_waitcnt vmcnt(0)3665; VI-SAFE-NEXT: v_fma_f32 v0, -v0, v1, -v23666; VI-SAFE-NEXT: v_xor_b32_e32 v2, 0x80000000, v03667; VI-SAFE-NEXT: v_mov_b32_e32 v0, s03668; VI-SAFE-NEXT: v_mov_b32_e32 v1, s13669; VI-SAFE-NEXT: flat_store_dword v[0:1], v23670; VI-SAFE-NEXT: s_waitcnt vmcnt(0)3671; VI-SAFE-NEXT: s_endpgm3672;3673; VI-NSZ-LABEL: v_fneg_fma_fneg_x_fneg_f32:3674; VI-NSZ: ; %bb.0:3675; VI-NSZ-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x243676; VI-NSZ-NEXT: v_lshlrev_b32_e32 v4, 2, v03677; VI-NSZ-NEXT: s_waitcnt lgkmcnt(0)3678; VI-NSZ-NEXT: v_mov_b32_e32 v1, s33679; VI-NSZ-NEXT: v_add_u32_e32 v0, vcc, s2, v43680; VI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc3681; VI-NSZ-NEXT: v_mov_b32_e32 v3, s53682; VI-NSZ-NEXT: v_add_u32_e32 v2, vcc, s4, v43683; VI-NSZ-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc3684; VI-NSZ-NEXT: v_mov_b32_e32 v5, s73685; VI-NSZ-NEXT: v_add_u32_e32 v4, vcc, s6, v43686; VI-NSZ-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc3687; VI-NSZ-NEXT: flat_load_dword v0, v[0:1] glc3688; VI-NSZ-NEXT: s_waitcnt vmcnt(0)3689; VI-NSZ-NEXT: flat_load_dword v1, v[2:3] glc3690; VI-NSZ-NEXT: s_waitcnt vmcnt(0)3691; VI-NSZ-NEXT: flat_load_dword v2, v[4:5] glc3692; VI-NSZ-NEXT: s_waitcnt vmcnt(0)3693; VI-NSZ-NEXT: v_fma_f32 v2, v0, v1, v23694; VI-NSZ-NEXT: v_mov_b32_e32 v0, s03695; VI-NSZ-NEXT: v_mov_b32_e32 v1, s13696; VI-NSZ-NEXT: flat_store_dword v[0:1], v23697; VI-NSZ-NEXT: s_waitcnt vmcnt(0)3698; VI-NSZ-NEXT: s_endpgm3699 %tid = call i32 @llvm.amdgcn.workitem.id.x()3700 %tid.ext = sext i32 %tid to i643701 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext3702 %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext3703 %c.gep = getelementptr inbounds float, ptr addrspace(1) %c.ptr, i64 %tid.ext3704 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext3705 %a = load volatile float, ptr addrspace(1) %a.gep3706 %b = load volatile float, ptr addrspace(1) %b.gep3707 %c = load volatile float, ptr addrspace(1) %c.gep3708 %fneg.a = fneg float %a3709 %fneg.c = fneg float %c3710 %fma = call float @llvm.fma.f32(float %fneg.a, float %b, float %fneg.c)3711 %fneg = fneg float %fma3712 store volatile float %fneg, ptr addrspace(1) %out3713 ret void3714}3715 3716define amdgpu_kernel void @v_fneg_fma_x_y_fneg_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr, ptr addrspace(1) %c.ptr) #0 {3717; SI-SAFE-LABEL: v_fneg_fma_x_y_fneg_f32:3718; SI-SAFE: ; %bb.0:3719; SI-SAFE-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x93720; SI-SAFE-NEXT: v_lshlrev_b32_e32 v4, 2, v03721; SI-SAFE-NEXT: s_waitcnt lgkmcnt(0)3722; SI-SAFE-NEXT: v_mov_b32_e32 v1, s33723; SI-SAFE-NEXT: v_add_i32_e32 v0, vcc, s2, v43724; SI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc3725; SI-SAFE-NEXT: v_mov_b32_e32 v3, s53726; SI-SAFE-NEXT: v_add_i32_e32 v2, vcc, s4, v43727; SI-SAFE-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc3728; SI-SAFE-NEXT: v_mov_b32_e32 v5, s73729; SI-SAFE-NEXT: v_add_i32_e32 v4, vcc, s6, v43730; SI-SAFE-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc3731; SI-SAFE-NEXT: flat_load_dword v0, v[0:1] glc3732; SI-SAFE-NEXT: s_waitcnt vmcnt(0)3733; SI-SAFE-NEXT: flat_load_dword v1, v[2:3] glc3734; SI-SAFE-NEXT: s_waitcnt vmcnt(0)3735; SI-SAFE-NEXT: flat_load_dword v2, v[4:5] glc3736; SI-SAFE-NEXT: s_waitcnt vmcnt(0)3737; SI-SAFE-NEXT: v_fma_f32 v0, v0, v1, -v23738; SI-SAFE-NEXT: v_xor_b32_e32 v2, 0x80000000, v03739; SI-SAFE-NEXT: v_mov_b32_e32 v0, s03740; SI-SAFE-NEXT: v_mov_b32_e32 v1, s13741; SI-SAFE-NEXT: flat_store_dword v[0:1], v23742; SI-SAFE-NEXT: s_waitcnt vmcnt(0)3743; SI-SAFE-NEXT: s_endpgm3744;3745; SI-NSZ-LABEL: v_fneg_fma_x_y_fneg_f32:3746; SI-NSZ: ; %bb.0:3747; SI-NSZ-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x93748; SI-NSZ-NEXT: v_lshlrev_b32_e32 v4, 2, v03749; SI-NSZ-NEXT: s_waitcnt lgkmcnt(0)3750; SI-NSZ-NEXT: v_mov_b32_e32 v1, s33751; SI-NSZ-NEXT: v_add_i32_e32 v0, vcc, s2, v43752; SI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc3753; SI-NSZ-NEXT: v_mov_b32_e32 v3, s53754; SI-NSZ-NEXT: v_add_i32_e32 v2, vcc, s4, v43755; SI-NSZ-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc3756; SI-NSZ-NEXT: v_mov_b32_e32 v5, s73757; SI-NSZ-NEXT: v_add_i32_e32 v4, vcc, s6, v43758; SI-NSZ-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc3759; SI-NSZ-NEXT: flat_load_dword v0, v[0:1] glc3760; SI-NSZ-NEXT: s_waitcnt vmcnt(0)3761; SI-NSZ-NEXT: flat_load_dword v1, v[2:3] glc3762; SI-NSZ-NEXT: s_waitcnt vmcnt(0)3763; SI-NSZ-NEXT: flat_load_dword v2, v[4:5] glc3764; SI-NSZ-NEXT: s_waitcnt vmcnt(0)3765; SI-NSZ-NEXT: v_fma_f32 v2, v0, -v1, v23766; SI-NSZ-NEXT: v_mov_b32_e32 v0, s03767; SI-NSZ-NEXT: v_mov_b32_e32 v1, s13768; SI-NSZ-NEXT: flat_store_dword v[0:1], v23769; SI-NSZ-NEXT: s_waitcnt vmcnt(0)3770; SI-NSZ-NEXT: s_endpgm3771;3772; VI-SAFE-LABEL: v_fneg_fma_x_y_fneg_f32:3773; VI-SAFE: ; %bb.0:3774; VI-SAFE-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x243775; VI-SAFE-NEXT: v_lshlrev_b32_e32 v4, 2, v03776; VI-SAFE-NEXT: s_waitcnt lgkmcnt(0)3777; VI-SAFE-NEXT: v_mov_b32_e32 v1, s33778; VI-SAFE-NEXT: v_add_u32_e32 v0, vcc, s2, v43779; VI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc3780; VI-SAFE-NEXT: v_mov_b32_e32 v3, s53781; VI-SAFE-NEXT: v_add_u32_e32 v2, vcc, s4, v43782; VI-SAFE-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc3783; VI-SAFE-NEXT: v_mov_b32_e32 v5, s73784; VI-SAFE-NEXT: v_add_u32_e32 v4, vcc, s6, v43785; VI-SAFE-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc3786; VI-SAFE-NEXT: flat_load_dword v0, v[0:1] glc3787; VI-SAFE-NEXT: s_waitcnt vmcnt(0)3788; VI-SAFE-NEXT: flat_load_dword v1, v[2:3] glc3789; VI-SAFE-NEXT: s_waitcnt vmcnt(0)3790; VI-SAFE-NEXT: flat_load_dword v2, v[4:5] glc3791; VI-SAFE-NEXT: s_waitcnt vmcnt(0)3792; VI-SAFE-NEXT: v_fma_f32 v0, v0, v1, -v23793; VI-SAFE-NEXT: v_xor_b32_e32 v2, 0x80000000, v03794; VI-SAFE-NEXT: v_mov_b32_e32 v0, s03795; VI-SAFE-NEXT: v_mov_b32_e32 v1, s13796; VI-SAFE-NEXT: flat_store_dword v[0:1], v23797; VI-SAFE-NEXT: s_waitcnt vmcnt(0)3798; VI-SAFE-NEXT: s_endpgm3799;3800; VI-NSZ-LABEL: v_fneg_fma_x_y_fneg_f32:3801; VI-NSZ: ; %bb.0:3802; VI-NSZ-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x243803; VI-NSZ-NEXT: v_lshlrev_b32_e32 v4, 2, v03804; VI-NSZ-NEXT: s_waitcnt lgkmcnt(0)3805; VI-NSZ-NEXT: v_mov_b32_e32 v1, s33806; VI-NSZ-NEXT: v_add_u32_e32 v0, vcc, s2, v43807; VI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc3808; VI-NSZ-NEXT: v_mov_b32_e32 v3, s53809; VI-NSZ-NEXT: v_add_u32_e32 v2, vcc, s4, v43810; VI-NSZ-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc3811; VI-NSZ-NEXT: v_mov_b32_e32 v5, s73812; VI-NSZ-NEXT: v_add_u32_e32 v4, vcc, s6, v43813; VI-NSZ-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc3814; VI-NSZ-NEXT: flat_load_dword v0, v[0:1] glc3815; VI-NSZ-NEXT: s_waitcnt vmcnt(0)3816; VI-NSZ-NEXT: flat_load_dword v1, v[2:3] glc3817; VI-NSZ-NEXT: s_waitcnt vmcnt(0)3818; VI-NSZ-NEXT: flat_load_dword v2, v[4:5] glc3819; VI-NSZ-NEXT: s_waitcnt vmcnt(0)3820; VI-NSZ-NEXT: v_fma_f32 v2, v0, -v1, v23821; VI-NSZ-NEXT: v_mov_b32_e32 v0, s03822; VI-NSZ-NEXT: v_mov_b32_e32 v1, s13823; VI-NSZ-NEXT: flat_store_dword v[0:1], v23824; VI-NSZ-NEXT: s_waitcnt vmcnt(0)3825; VI-NSZ-NEXT: s_endpgm3826 %tid = call i32 @llvm.amdgcn.workitem.id.x()3827 %tid.ext = sext i32 %tid to i643828 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext3829 %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext3830 %c.gep = getelementptr inbounds float, ptr addrspace(1) %c.ptr, i64 %tid.ext3831 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext3832 %a = load volatile float, ptr addrspace(1) %a.gep3833 %b = load volatile float, ptr addrspace(1) %b.gep3834 %c = load volatile float, ptr addrspace(1) %c.gep3835 %fneg.c = fneg float %c3836 %fma = call float @llvm.fma.f32(float %a, float %b, float %fneg.c)3837 %fneg = fneg float %fma3838 store volatile float %fneg, ptr addrspace(1) %out3839 ret void3840}3841 3842define amdgpu_kernel void @v_fneg_fma_store_use_fneg_x_y_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr, ptr addrspace(1) %c.ptr) #0 {3843; SI-SAFE-LABEL: v_fneg_fma_store_use_fneg_x_y_f32:3844; SI-SAFE: ; %bb.0:3845; SI-SAFE-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x93846; SI-SAFE-NEXT: v_lshlrev_b32_e32 v4, 2, v03847; SI-SAFE-NEXT: s_waitcnt lgkmcnt(0)3848; SI-SAFE-NEXT: v_mov_b32_e32 v1, s33849; SI-SAFE-NEXT: v_add_i32_e32 v0, vcc, s2, v43850; SI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc3851; SI-SAFE-NEXT: v_mov_b32_e32 v3, s53852; SI-SAFE-NEXT: v_add_i32_e32 v2, vcc, s4, v43853; SI-SAFE-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc3854; SI-SAFE-NEXT: v_mov_b32_e32 v5, s73855; SI-SAFE-NEXT: v_add_i32_e32 v4, vcc, s6, v43856; SI-SAFE-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc3857; SI-SAFE-NEXT: flat_load_dword v6, v[0:1] glc3858; SI-SAFE-NEXT: s_waitcnt vmcnt(0)3859; SI-SAFE-NEXT: flat_load_dword v2, v[2:3] glc3860; SI-SAFE-NEXT: s_waitcnt vmcnt(0)3861; SI-SAFE-NEXT: flat_load_dword v3, v[4:5] glc3862; SI-SAFE-NEXT: s_waitcnt vmcnt(0)3863; SI-SAFE-NEXT: v_mov_b32_e32 v0, s03864; SI-SAFE-NEXT: v_mov_b32_e32 v1, s13865; SI-SAFE-NEXT: v_xor_b32_e32 v4, 0x80000000, v63866; SI-SAFE-NEXT: v_fma_f32 v2, -v6, v2, v33867; SI-SAFE-NEXT: v_xor_b32_e32 v2, 0x80000000, v23868; SI-SAFE-NEXT: flat_store_dword v[0:1], v23869; SI-SAFE-NEXT: s_waitcnt vmcnt(0)3870; SI-SAFE-NEXT: flat_store_dword v[0:1], v43871; SI-SAFE-NEXT: s_waitcnt vmcnt(0)3872; SI-SAFE-NEXT: s_endpgm3873;3874; SI-NSZ-LABEL: v_fneg_fma_store_use_fneg_x_y_f32:3875; SI-NSZ: ; %bb.0:3876; SI-NSZ-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x93877; SI-NSZ-NEXT: v_lshlrev_b32_e32 v4, 2, v03878; SI-NSZ-NEXT: s_waitcnt lgkmcnt(0)3879; SI-NSZ-NEXT: v_mov_b32_e32 v1, s33880; SI-NSZ-NEXT: v_add_i32_e32 v0, vcc, s2, v43881; SI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc3882; SI-NSZ-NEXT: v_mov_b32_e32 v3, s53883; SI-NSZ-NEXT: v_add_i32_e32 v2, vcc, s4, v43884; SI-NSZ-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc3885; SI-NSZ-NEXT: v_mov_b32_e32 v5, s73886; SI-NSZ-NEXT: v_add_i32_e32 v4, vcc, s6, v43887; SI-NSZ-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc3888; SI-NSZ-NEXT: flat_load_dword v6, v[0:1] glc3889; SI-NSZ-NEXT: s_waitcnt vmcnt(0)3890; SI-NSZ-NEXT: flat_load_dword v2, v[2:3] glc3891; SI-NSZ-NEXT: s_waitcnt vmcnt(0)3892; SI-NSZ-NEXT: flat_load_dword v3, v[4:5] glc3893; SI-NSZ-NEXT: s_waitcnt vmcnt(0)3894; SI-NSZ-NEXT: v_mov_b32_e32 v0, s03895; SI-NSZ-NEXT: v_mov_b32_e32 v1, s13896; SI-NSZ-NEXT: v_xor_b32_e32 v4, 0x80000000, v63897; SI-NSZ-NEXT: v_fma_f32 v2, v6, v2, -v33898; SI-NSZ-NEXT: flat_store_dword v[0:1], v23899; SI-NSZ-NEXT: s_waitcnt vmcnt(0)3900; SI-NSZ-NEXT: flat_store_dword v[0:1], v43901; SI-NSZ-NEXT: s_waitcnt vmcnt(0)3902; SI-NSZ-NEXT: s_endpgm3903;3904; VI-SAFE-LABEL: v_fneg_fma_store_use_fneg_x_y_f32:3905; VI-SAFE: ; %bb.0:3906; VI-SAFE-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x243907; VI-SAFE-NEXT: v_lshlrev_b32_e32 v4, 2, v03908; VI-SAFE-NEXT: s_waitcnt lgkmcnt(0)3909; VI-SAFE-NEXT: v_mov_b32_e32 v1, s33910; VI-SAFE-NEXT: v_add_u32_e32 v0, vcc, s2, v43911; VI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc3912; VI-SAFE-NEXT: v_mov_b32_e32 v3, s53913; VI-SAFE-NEXT: v_add_u32_e32 v2, vcc, s4, v43914; VI-SAFE-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc3915; VI-SAFE-NEXT: v_mov_b32_e32 v5, s73916; VI-SAFE-NEXT: v_add_u32_e32 v4, vcc, s6, v43917; VI-SAFE-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc3918; VI-SAFE-NEXT: flat_load_dword v6, v[0:1] glc3919; VI-SAFE-NEXT: s_waitcnt vmcnt(0)3920; VI-SAFE-NEXT: flat_load_dword v2, v[2:3] glc3921; VI-SAFE-NEXT: s_waitcnt vmcnt(0)3922; VI-SAFE-NEXT: flat_load_dword v3, v[4:5] glc3923; VI-SAFE-NEXT: s_waitcnt vmcnt(0)3924; VI-SAFE-NEXT: v_mov_b32_e32 v0, s03925; VI-SAFE-NEXT: v_mov_b32_e32 v1, s13926; VI-SAFE-NEXT: v_xor_b32_e32 v4, 0x80000000, v63927; VI-SAFE-NEXT: v_fma_f32 v2, -v6, v2, v33928; VI-SAFE-NEXT: v_xor_b32_e32 v2, 0x80000000, v23929; VI-SAFE-NEXT: flat_store_dword v[0:1], v23930; VI-SAFE-NEXT: s_waitcnt vmcnt(0)3931; VI-SAFE-NEXT: flat_store_dword v[0:1], v43932; VI-SAFE-NEXT: s_waitcnt vmcnt(0)3933; VI-SAFE-NEXT: s_endpgm3934;3935; VI-NSZ-LABEL: v_fneg_fma_store_use_fneg_x_y_f32:3936; VI-NSZ: ; %bb.0:3937; VI-NSZ-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x243938; VI-NSZ-NEXT: v_lshlrev_b32_e32 v4, 2, v03939; VI-NSZ-NEXT: s_waitcnt lgkmcnt(0)3940; VI-NSZ-NEXT: v_mov_b32_e32 v1, s33941; VI-NSZ-NEXT: v_add_u32_e32 v0, vcc, s2, v43942; VI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc3943; VI-NSZ-NEXT: v_mov_b32_e32 v3, s53944; VI-NSZ-NEXT: v_add_u32_e32 v2, vcc, s4, v43945; VI-NSZ-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc3946; VI-NSZ-NEXT: v_mov_b32_e32 v5, s73947; VI-NSZ-NEXT: v_add_u32_e32 v4, vcc, s6, v43948; VI-NSZ-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc3949; VI-NSZ-NEXT: flat_load_dword v6, v[0:1] glc3950; VI-NSZ-NEXT: s_waitcnt vmcnt(0)3951; VI-NSZ-NEXT: flat_load_dword v2, v[2:3] glc3952; VI-NSZ-NEXT: s_waitcnt vmcnt(0)3953; VI-NSZ-NEXT: flat_load_dword v3, v[4:5] glc3954; VI-NSZ-NEXT: s_waitcnt vmcnt(0)3955; VI-NSZ-NEXT: v_mov_b32_e32 v0, s03956; VI-NSZ-NEXT: v_mov_b32_e32 v1, s13957; VI-NSZ-NEXT: v_xor_b32_e32 v4, 0x80000000, v63958; VI-NSZ-NEXT: v_fma_f32 v2, v6, v2, -v33959; VI-NSZ-NEXT: flat_store_dword v[0:1], v23960; VI-NSZ-NEXT: s_waitcnt vmcnt(0)3961; VI-NSZ-NEXT: flat_store_dword v[0:1], v43962; VI-NSZ-NEXT: s_waitcnt vmcnt(0)3963; VI-NSZ-NEXT: s_endpgm3964 %tid = call i32 @llvm.amdgcn.workitem.id.x()3965 %tid.ext = sext i32 %tid to i643966 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext3967 %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext3968 %c.gep = getelementptr inbounds float, ptr addrspace(1) %c.ptr, i64 %tid.ext3969 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext3970 %a = load volatile float, ptr addrspace(1) %a.gep3971 %b = load volatile float, ptr addrspace(1) %b.gep3972 %c = load volatile float, ptr addrspace(1) %c.gep3973 %fneg.a = fneg float %a3974 %fma = call float @llvm.fma.f32(float %fneg.a, float %b, float %c)3975 %fneg = fneg float %fma3976 store volatile float %fneg, ptr addrspace(1) %out3977 store volatile float %fneg.a, ptr addrspace(1) %out3978 ret void3979}3980 3981define amdgpu_kernel void @v_fneg_fma_multi_use_fneg_x_y_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr, ptr addrspace(1) %c.ptr, float %d) #0 {3982; SI-SAFE-LABEL: v_fneg_fma_multi_use_fneg_x_y_f32:3983; SI-SAFE: ; %bb.0:3984; SI-SAFE-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x93985; SI-SAFE-NEXT: v_lshlrev_b32_e32 v4, 2, v03986; SI-SAFE-NEXT: s_load_dword s0, s[4:5], 0x113987; SI-SAFE-NEXT: s_waitcnt lgkmcnt(0)3988; SI-SAFE-NEXT: v_mov_b32_e32 v1, s113989; SI-SAFE-NEXT: v_add_i32_e32 v0, vcc, s10, v43990; SI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc3991; SI-SAFE-NEXT: v_mov_b32_e32 v3, s133992; SI-SAFE-NEXT: v_add_i32_e32 v2, vcc, s12, v43993; SI-SAFE-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc3994; SI-SAFE-NEXT: v_mov_b32_e32 v5, s153995; SI-SAFE-NEXT: v_add_i32_e32 v4, vcc, s14, v43996; SI-SAFE-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc3997; SI-SAFE-NEXT: flat_load_dword v6, v[0:1] glc3998; SI-SAFE-NEXT: s_waitcnt vmcnt(0)3999; SI-SAFE-NEXT: flat_load_dword v2, v[2:3] glc4000; SI-SAFE-NEXT: s_waitcnt vmcnt(0)4001; SI-SAFE-NEXT: flat_load_dword v3, v[4:5] glc4002; SI-SAFE-NEXT: s_waitcnt vmcnt(0)4003; SI-SAFE-NEXT: v_mov_b32_e32 v0, s84004; SI-SAFE-NEXT: v_mov_b32_e32 v1, s94005; SI-SAFE-NEXT: v_fma_f32 v2, -v6, v2, v34006; SI-SAFE-NEXT: v_xor_b32_e32 v2, 0x80000000, v24007; SI-SAFE-NEXT: v_mul_f32_e64 v3, -v6, s04008; SI-SAFE-NEXT: flat_store_dword v[0:1], v24009; SI-SAFE-NEXT: s_waitcnt vmcnt(0)4010; SI-SAFE-NEXT: flat_store_dword v[0:1], v34011; SI-SAFE-NEXT: s_waitcnt vmcnt(0)4012; SI-SAFE-NEXT: s_endpgm4013;4014; SI-NSZ-LABEL: v_fneg_fma_multi_use_fneg_x_y_f32:4015; SI-NSZ: ; %bb.0:4016; SI-NSZ-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x94017; SI-NSZ-NEXT: v_lshlrev_b32_e32 v4, 2, v04018; SI-NSZ-NEXT: s_load_dword s0, s[4:5], 0x114019; SI-NSZ-NEXT: s_waitcnt lgkmcnt(0)4020; SI-NSZ-NEXT: v_mov_b32_e32 v1, s114021; SI-NSZ-NEXT: v_add_i32_e32 v0, vcc, s10, v44022; SI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc4023; SI-NSZ-NEXT: v_mov_b32_e32 v3, s134024; SI-NSZ-NEXT: v_add_i32_e32 v2, vcc, s12, v44025; SI-NSZ-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc4026; SI-NSZ-NEXT: v_mov_b32_e32 v5, s154027; SI-NSZ-NEXT: v_add_i32_e32 v4, vcc, s14, v44028; SI-NSZ-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc4029; SI-NSZ-NEXT: flat_load_dword v6, v[0:1] glc4030; SI-NSZ-NEXT: s_waitcnt vmcnt(0)4031; SI-NSZ-NEXT: flat_load_dword v2, v[2:3] glc4032; SI-NSZ-NEXT: s_waitcnt vmcnt(0)4033; SI-NSZ-NEXT: flat_load_dword v3, v[4:5] glc4034; SI-NSZ-NEXT: s_waitcnt vmcnt(0)4035; SI-NSZ-NEXT: v_mov_b32_e32 v0, s84036; SI-NSZ-NEXT: v_mov_b32_e32 v1, s94037; SI-NSZ-NEXT: v_fma_f32 v2, v6, v2, -v34038; SI-NSZ-NEXT: v_mul_f32_e64 v3, -v6, s04039; SI-NSZ-NEXT: flat_store_dword v[0:1], v24040; SI-NSZ-NEXT: s_waitcnt vmcnt(0)4041; SI-NSZ-NEXT: flat_store_dword v[0:1], v34042; SI-NSZ-NEXT: s_waitcnt vmcnt(0)4043; SI-NSZ-NEXT: s_endpgm4044;4045; VI-SAFE-LABEL: v_fneg_fma_multi_use_fneg_x_y_f32:4046; VI-SAFE: ; %bb.0:4047; VI-SAFE-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x244048; VI-SAFE-NEXT: v_lshlrev_b32_e32 v4, 2, v04049; VI-SAFE-NEXT: s_load_dword s0, s[4:5], 0x444050; VI-SAFE-NEXT: s_waitcnt lgkmcnt(0)4051; VI-SAFE-NEXT: v_mov_b32_e32 v1, s114052; VI-SAFE-NEXT: v_add_u32_e32 v0, vcc, s10, v44053; VI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc4054; VI-SAFE-NEXT: v_mov_b32_e32 v3, s134055; VI-SAFE-NEXT: v_add_u32_e32 v2, vcc, s12, v44056; VI-SAFE-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc4057; VI-SAFE-NEXT: v_mov_b32_e32 v5, s154058; VI-SAFE-NEXT: v_add_u32_e32 v4, vcc, s14, v44059; VI-SAFE-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc4060; VI-SAFE-NEXT: flat_load_dword v6, v[0:1] glc4061; VI-SAFE-NEXT: s_waitcnt vmcnt(0)4062; VI-SAFE-NEXT: flat_load_dword v2, v[2:3] glc4063; VI-SAFE-NEXT: s_waitcnt vmcnt(0)4064; VI-SAFE-NEXT: flat_load_dword v3, v[4:5] glc4065; VI-SAFE-NEXT: s_waitcnt vmcnt(0)4066; VI-SAFE-NEXT: v_mov_b32_e32 v0, s84067; VI-SAFE-NEXT: v_mov_b32_e32 v1, s94068; VI-SAFE-NEXT: v_fma_f32 v2, -v6, v2, v34069; VI-SAFE-NEXT: v_xor_b32_e32 v2, 0x80000000, v24070; VI-SAFE-NEXT: v_mul_f32_e64 v3, -v6, s04071; VI-SAFE-NEXT: flat_store_dword v[0:1], v24072; VI-SAFE-NEXT: s_waitcnt vmcnt(0)4073; VI-SAFE-NEXT: flat_store_dword v[0:1], v34074; VI-SAFE-NEXT: s_waitcnt vmcnt(0)4075; VI-SAFE-NEXT: s_endpgm4076;4077; VI-NSZ-LABEL: v_fneg_fma_multi_use_fneg_x_y_f32:4078; VI-NSZ: ; %bb.0:4079; VI-NSZ-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x244080; VI-NSZ-NEXT: v_lshlrev_b32_e32 v4, 2, v04081; VI-NSZ-NEXT: s_load_dword s0, s[4:5], 0x444082; VI-NSZ-NEXT: s_waitcnt lgkmcnt(0)4083; VI-NSZ-NEXT: v_mov_b32_e32 v1, s114084; VI-NSZ-NEXT: v_add_u32_e32 v0, vcc, s10, v44085; VI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc4086; VI-NSZ-NEXT: v_mov_b32_e32 v3, s134087; VI-NSZ-NEXT: v_add_u32_e32 v2, vcc, s12, v44088; VI-NSZ-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc4089; VI-NSZ-NEXT: v_mov_b32_e32 v5, s154090; VI-NSZ-NEXT: v_add_u32_e32 v4, vcc, s14, v44091; VI-NSZ-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc4092; VI-NSZ-NEXT: flat_load_dword v6, v[0:1] glc4093; VI-NSZ-NEXT: s_waitcnt vmcnt(0)4094; VI-NSZ-NEXT: flat_load_dword v2, v[2:3] glc4095; VI-NSZ-NEXT: s_waitcnt vmcnt(0)4096; VI-NSZ-NEXT: flat_load_dword v3, v[4:5] glc4097; VI-NSZ-NEXT: s_waitcnt vmcnt(0)4098; VI-NSZ-NEXT: v_mov_b32_e32 v0, s84099; VI-NSZ-NEXT: v_mov_b32_e32 v1, s94100; VI-NSZ-NEXT: v_fma_f32 v2, v6, v2, -v34101; VI-NSZ-NEXT: v_mul_f32_e64 v3, -v6, s04102; VI-NSZ-NEXT: flat_store_dword v[0:1], v24103; VI-NSZ-NEXT: s_waitcnt vmcnt(0)4104; VI-NSZ-NEXT: flat_store_dword v[0:1], v34105; VI-NSZ-NEXT: s_waitcnt vmcnt(0)4106; VI-NSZ-NEXT: s_endpgm4107 %tid = call i32 @llvm.amdgcn.workitem.id.x()4108 %tid.ext = sext i32 %tid to i644109 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext4110 %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext4111 %c.gep = getelementptr inbounds float, ptr addrspace(1) %c.ptr, i64 %tid.ext4112 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext4113 %a = load volatile float, ptr addrspace(1) %a.gep4114 %b = load volatile float, ptr addrspace(1) %b.gep4115 %c = load volatile float, ptr addrspace(1) %c.gep4116 %fneg.a = fneg float %a4117 %fma = call float @llvm.fma.f32(float %fneg.a, float %b, float %c)4118 %fneg = fneg float %fma4119 %use1 = fmul float %fneg.a, %d4120 store volatile float %fneg, ptr addrspace(1) %out4121 store volatile float %use1, ptr addrspace(1) %out4122 ret void4123}4124 4125; --------------------------------------------------------------------------------4126; fmad tests4127; --------------------------------------------------------------------------------4128 4129define amdgpu_kernel void @v_fneg_fmad_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr, ptr addrspace(1) %c.ptr) #0 {4130; SI-SAFE-LABEL: v_fneg_fmad_f32:4131; SI-SAFE: ; %bb.0:4132; SI-SAFE-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x94133; SI-SAFE-NEXT: v_lshlrev_b32_e32 v6, 2, v04134; SI-SAFE-NEXT: s_waitcnt lgkmcnt(0)4135; SI-SAFE-NEXT: v_mov_b32_e32 v1, s34136; SI-SAFE-NEXT: v_add_i32_e32 v0, vcc, s2, v64137; SI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc4138; SI-SAFE-NEXT: v_mov_b32_e32 v3, s54139; SI-SAFE-NEXT: v_add_i32_e32 v2, vcc, s4, v64140; SI-SAFE-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc4141; SI-SAFE-NEXT: v_mov_b32_e32 v5, s74142; SI-SAFE-NEXT: v_add_i32_e32 v4, vcc, s6, v64143; SI-SAFE-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc4144; SI-SAFE-NEXT: flat_load_dword v7, v[0:1] glc4145; SI-SAFE-NEXT: s_waitcnt vmcnt(0)4146; SI-SAFE-NEXT: flat_load_dword v2, v[2:3] glc4147; SI-SAFE-NEXT: s_waitcnt vmcnt(0)4148; SI-SAFE-NEXT: flat_load_dword v3, v[4:5] glc4149; SI-SAFE-NEXT: s_waitcnt vmcnt(0)4150; SI-SAFE-NEXT: v_mov_b32_e32 v1, s14151; SI-SAFE-NEXT: v_add_i32_e32 v0, vcc, s0, v64152; SI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc4153; SI-SAFE-NEXT: v_mac_f32_e32 v3, v7, v24154; SI-SAFE-NEXT: v_xor_b32_e32 v2, 0x80000000, v34155; SI-SAFE-NEXT: flat_store_dword v[0:1], v24156; SI-SAFE-NEXT: s_endpgm4157;4158; SI-NSZ-LABEL: v_fneg_fmad_f32:4159; SI-NSZ: ; %bb.0:4160; SI-NSZ-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x94161; SI-NSZ-NEXT: v_lshlrev_b32_e32 v6, 2, v04162; SI-NSZ-NEXT: s_waitcnt lgkmcnt(0)4163; SI-NSZ-NEXT: v_mov_b32_e32 v1, s34164; SI-NSZ-NEXT: v_add_i32_e32 v0, vcc, s2, v64165; SI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc4166; SI-NSZ-NEXT: v_mov_b32_e32 v3, s54167; SI-NSZ-NEXT: v_add_i32_e32 v2, vcc, s4, v64168; SI-NSZ-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc4169; SI-NSZ-NEXT: v_mov_b32_e32 v5, s74170; SI-NSZ-NEXT: v_add_i32_e32 v4, vcc, s6, v64171; SI-NSZ-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc4172; SI-NSZ-NEXT: flat_load_dword v7, v[0:1] glc4173; SI-NSZ-NEXT: s_waitcnt vmcnt(0)4174; SI-NSZ-NEXT: flat_load_dword v2, v[2:3] glc4175; SI-NSZ-NEXT: s_waitcnt vmcnt(0)4176; SI-NSZ-NEXT: flat_load_dword v3, v[4:5] glc4177; SI-NSZ-NEXT: s_waitcnt vmcnt(0)4178; SI-NSZ-NEXT: v_mov_b32_e32 v1, s14179; SI-NSZ-NEXT: v_add_i32_e32 v0, vcc, s0, v64180; SI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc4181; SI-NSZ-NEXT: v_mad_f32 v2, v7, -v2, -v34182; SI-NSZ-NEXT: flat_store_dword v[0:1], v24183; SI-NSZ-NEXT: s_endpgm4184;4185; VI-SAFE-LABEL: v_fneg_fmad_f32:4186; VI-SAFE: ; %bb.0:4187; VI-SAFE-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x244188; VI-SAFE-NEXT: v_lshlrev_b32_e32 v6, 2, v04189; VI-SAFE-NEXT: s_waitcnt lgkmcnt(0)4190; VI-SAFE-NEXT: v_mov_b32_e32 v1, s34191; VI-SAFE-NEXT: v_add_u32_e32 v0, vcc, s2, v64192; VI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc4193; VI-SAFE-NEXT: v_mov_b32_e32 v3, s54194; VI-SAFE-NEXT: v_add_u32_e32 v2, vcc, s4, v64195; VI-SAFE-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc4196; VI-SAFE-NEXT: v_mov_b32_e32 v5, s74197; VI-SAFE-NEXT: v_add_u32_e32 v4, vcc, s6, v64198; VI-SAFE-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc4199; VI-SAFE-NEXT: flat_load_dword v7, v[0:1] glc4200; VI-SAFE-NEXT: s_waitcnt vmcnt(0)4201; VI-SAFE-NEXT: flat_load_dword v2, v[2:3] glc4202; VI-SAFE-NEXT: s_waitcnt vmcnt(0)4203; VI-SAFE-NEXT: flat_load_dword v3, v[4:5] glc4204; VI-SAFE-NEXT: s_waitcnt vmcnt(0)4205; VI-SAFE-NEXT: v_mov_b32_e32 v1, s14206; VI-SAFE-NEXT: v_add_u32_e32 v0, vcc, s0, v64207; VI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc4208; VI-SAFE-NEXT: v_mac_f32_e32 v3, v7, v24209; VI-SAFE-NEXT: v_xor_b32_e32 v2, 0x80000000, v34210; VI-SAFE-NEXT: flat_store_dword v[0:1], v24211; VI-SAFE-NEXT: s_endpgm4212;4213; VI-NSZ-LABEL: v_fneg_fmad_f32:4214; VI-NSZ: ; %bb.0:4215; VI-NSZ-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x244216; VI-NSZ-NEXT: v_lshlrev_b32_e32 v6, 2, v04217; VI-NSZ-NEXT: s_waitcnt lgkmcnt(0)4218; VI-NSZ-NEXT: v_mov_b32_e32 v1, s34219; VI-NSZ-NEXT: v_add_u32_e32 v0, vcc, s2, v64220; VI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc4221; VI-NSZ-NEXT: v_mov_b32_e32 v3, s54222; VI-NSZ-NEXT: v_add_u32_e32 v2, vcc, s4, v64223; VI-NSZ-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc4224; VI-NSZ-NEXT: v_mov_b32_e32 v5, s74225; VI-NSZ-NEXT: v_add_u32_e32 v4, vcc, s6, v64226; VI-NSZ-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc4227; VI-NSZ-NEXT: flat_load_dword v7, v[0:1] glc4228; VI-NSZ-NEXT: s_waitcnt vmcnt(0)4229; VI-NSZ-NEXT: flat_load_dword v2, v[2:3] glc4230; VI-NSZ-NEXT: s_waitcnt vmcnt(0)4231; VI-NSZ-NEXT: flat_load_dword v3, v[4:5] glc4232; VI-NSZ-NEXT: s_waitcnt vmcnt(0)4233; VI-NSZ-NEXT: v_mov_b32_e32 v1, s14234; VI-NSZ-NEXT: v_add_u32_e32 v0, vcc, s0, v64235; VI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc4236; VI-NSZ-NEXT: v_mad_f32 v2, v7, -v2, -v34237; VI-NSZ-NEXT: flat_store_dword v[0:1], v24238; VI-NSZ-NEXT: s_endpgm4239 %tid = call i32 @llvm.amdgcn.workitem.id.x()4240 %tid.ext = sext i32 %tid to i644241 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext4242 %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext4243 %c.gep = getelementptr inbounds float, ptr addrspace(1) %c.ptr, i64 %tid.ext4244 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext4245 %a = load volatile float, ptr addrspace(1) %a.gep4246 %b = load volatile float, ptr addrspace(1) %b.gep4247 %c = load volatile float, ptr addrspace(1) %c.gep4248 %fma = call float @llvm.fmuladd.f32(float %a, float %b, float %c)4249 %fneg = fneg float %fma4250 store float %fneg, ptr addrspace(1) %out.gep4251 ret void4252}4253 4254define amdgpu_kernel void @v_fneg_fmad_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr, ptr addrspace(1) %c.ptr) #0 {4255; SI-SAFE-LABEL: v_fneg_fmad_v4f32:4256; SI-SAFE: ; %bb.0:4257; SI-SAFE-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x94258; SI-SAFE-NEXT: v_lshlrev_b32_e32 v12, 4, v04259; SI-SAFE-NEXT: s_waitcnt lgkmcnt(0)4260; SI-SAFE-NEXT: v_mov_b32_e32 v1, s34261; SI-SAFE-NEXT: v_add_i32_e32 v0, vcc, s2, v124262; SI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc4263; SI-SAFE-NEXT: v_mov_b32_e32 v2, s54264; SI-SAFE-NEXT: v_add_i32_e32 v4, vcc, s4, v124265; SI-SAFE-NEXT: v_addc_u32_e32 v5, vcc, 0, v2, vcc4266; SI-SAFE-NEXT: v_mov_b32_e32 v2, s74267; SI-SAFE-NEXT: v_add_i32_e32 v8, vcc, s6, v124268; SI-SAFE-NEXT: v_addc_u32_e32 v9, vcc, 0, v2, vcc4269; SI-SAFE-NEXT: flat_load_dwordx4 v[0:3], v[0:1] glc4270; SI-SAFE-NEXT: s_waitcnt vmcnt(0)4271; SI-SAFE-NEXT: flat_load_dwordx4 v[4:7], v[4:5] glc4272; SI-SAFE-NEXT: s_waitcnt vmcnt(0)4273; SI-SAFE-NEXT: flat_load_dwordx4 v[8:11], v[8:9] glc4274; SI-SAFE-NEXT: s_waitcnt vmcnt(0)4275; SI-SAFE-NEXT: v_mov_b32_e32 v13, s14276; SI-SAFE-NEXT: v_add_i32_e32 v12, vcc, s0, v124277; SI-SAFE-NEXT: v_addc_u32_e32 v13, vcc, 0, v13, vcc4278; SI-SAFE-NEXT: v_mad_f32 v0, v0, v4, v84279; SI-SAFE-NEXT: v_mad_f32 v1, v1, v5, v94280; SI-SAFE-NEXT: v_mad_f32 v2, v2, v6, v104281; SI-SAFE-NEXT: v_mac_f32_e32 v11, v3, v74282; SI-SAFE-NEXT: v_xor_b32_e32 v3, 0x80000000, v114283; SI-SAFE-NEXT: v_xor_b32_e32 v2, 0x80000000, v24284; SI-SAFE-NEXT: v_xor_b32_e32 v1, 0x80000000, v14285; SI-SAFE-NEXT: v_xor_b32_e32 v0, 0x80000000, v04286; SI-SAFE-NEXT: flat_store_dwordx4 v[12:13], v[0:3]4287; SI-SAFE-NEXT: s_endpgm4288;4289; SI-NSZ-LABEL: v_fneg_fmad_v4f32:4290; SI-NSZ: ; %bb.0:4291; SI-NSZ-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x94292; SI-NSZ-NEXT: v_lshlrev_b32_e32 v12, 4, v04293; SI-NSZ-NEXT: s_waitcnt lgkmcnt(0)4294; SI-NSZ-NEXT: v_mov_b32_e32 v1, s34295; SI-NSZ-NEXT: v_add_i32_e32 v0, vcc, s2, v124296; SI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc4297; SI-NSZ-NEXT: v_mov_b32_e32 v2, s54298; SI-NSZ-NEXT: v_add_i32_e32 v4, vcc, s4, v124299; SI-NSZ-NEXT: v_addc_u32_e32 v5, vcc, 0, v2, vcc4300; SI-NSZ-NEXT: v_mov_b32_e32 v2, s74301; SI-NSZ-NEXT: v_add_i32_e32 v8, vcc, s6, v124302; SI-NSZ-NEXT: v_addc_u32_e32 v9, vcc, 0, v2, vcc4303; SI-NSZ-NEXT: flat_load_dwordx4 v[0:3], v[0:1] glc4304; SI-NSZ-NEXT: s_waitcnt vmcnt(0)4305; SI-NSZ-NEXT: flat_load_dwordx4 v[4:7], v[4:5] glc4306; SI-NSZ-NEXT: s_waitcnt vmcnt(0)4307; SI-NSZ-NEXT: flat_load_dwordx4 v[8:11], v[8:9] glc4308; SI-NSZ-NEXT: s_waitcnt vmcnt(0)4309; SI-NSZ-NEXT: v_mov_b32_e32 v13, s14310; SI-NSZ-NEXT: v_add_i32_e32 v12, vcc, s0, v124311; SI-NSZ-NEXT: v_addc_u32_e32 v13, vcc, 0, v13, vcc4312; SI-NSZ-NEXT: v_mad_f32 v3, v3, -v7, -v114313; SI-NSZ-NEXT: v_mad_f32 v2, v2, -v6, -v104314; SI-NSZ-NEXT: v_mad_f32 v1, v1, -v5, -v94315; SI-NSZ-NEXT: v_mad_f32 v0, v0, -v4, -v84316; SI-NSZ-NEXT: flat_store_dwordx4 v[12:13], v[0:3]4317; SI-NSZ-NEXT: s_endpgm4318;4319; VI-SAFE-LABEL: v_fneg_fmad_v4f32:4320; VI-SAFE: ; %bb.0:4321; VI-SAFE-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x244322; VI-SAFE-NEXT: v_lshlrev_b32_e32 v12, 4, v04323; VI-SAFE-NEXT: s_waitcnt lgkmcnt(0)4324; VI-SAFE-NEXT: v_mov_b32_e32 v1, s34325; VI-SAFE-NEXT: v_add_u32_e32 v0, vcc, s2, v124326; VI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc4327; VI-SAFE-NEXT: v_mov_b32_e32 v2, s54328; VI-SAFE-NEXT: v_add_u32_e32 v4, vcc, s4, v124329; VI-SAFE-NEXT: v_addc_u32_e32 v5, vcc, 0, v2, vcc4330; VI-SAFE-NEXT: v_mov_b32_e32 v2, s74331; VI-SAFE-NEXT: v_add_u32_e32 v8, vcc, s6, v124332; VI-SAFE-NEXT: v_addc_u32_e32 v9, vcc, 0, v2, vcc4333; VI-SAFE-NEXT: flat_load_dwordx4 v[0:3], v[0:1] glc4334; VI-SAFE-NEXT: s_waitcnt vmcnt(0)4335; VI-SAFE-NEXT: flat_load_dwordx4 v[4:7], v[4:5] glc4336; VI-SAFE-NEXT: s_waitcnt vmcnt(0)4337; VI-SAFE-NEXT: flat_load_dwordx4 v[8:11], v[8:9] glc4338; VI-SAFE-NEXT: s_waitcnt vmcnt(0)4339; VI-SAFE-NEXT: v_mov_b32_e32 v13, s14340; VI-SAFE-NEXT: v_add_u32_e32 v12, vcc, s0, v124341; VI-SAFE-NEXT: v_addc_u32_e32 v13, vcc, 0, v13, vcc4342; VI-SAFE-NEXT: v_mad_f32 v0, v0, v4, v84343; VI-SAFE-NEXT: v_mad_f32 v1, v1, v5, v94344; VI-SAFE-NEXT: v_mad_f32 v2, v2, v6, v104345; VI-SAFE-NEXT: v_mac_f32_e32 v11, v3, v74346; VI-SAFE-NEXT: v_xor_b32_e32 v3, 0x80000000, v114347; VI-SAFE-NEXT: v_xor_b32_e32 v2, 0x80000000, v24348; VI-SAFE-NEXT: v_xor_b32_e32 v1, 0x80000000, v14349; VI-SAFE-NEXT: v_xor_b32_e32 v0, 0x80000000, v04350; VI-SAFE-NEXT: flat_store_dwordx4 v[12:13], v[0:3]4351; VI-SAFE-NEXT: s_endpgm4352;4353; VI-NSZ-LABEL: v_fneg_fmad_v4f32:4354; VI-NSZ: ; %bb.0:4355; VI-NSZ-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x244356; VI-NSZ-NEXT: v_lshlrev_b32_e32 v12, 4, v04357; VI-NSZ-NEXT: s_waitcnt lgkmcnt(0)4358; VI-NSZ-NEXT: v_mov_b32_e32 v1, s34359; VI-NSZ-NEXT: v_add_u32_e32 v0, vcc, s2, v124360; VI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc4361; VI-NSZ-NEXT: v_mov_b32_e32 v2, s54362; VI-NSZ-NEXT: v_add_u32_e32 v4, vcc, s4, v124363; VI-NSZ-NEXT: v_addc_u32_e32 v5, vcc, 0, v2, vcc4364; VI-NSZ-NEXT: v_mov_b32_e32 v2, s74365; VI-NSZ-NEXT: v_add_u32_e32 v8, vcc, s6, v124366; VI-NSZ-NEXT: v_addc_u32_e32 v9, vcc, 0, v2, vcc4367; VI-NSZ-NEXT: flat_load_dwordx4 v[0:3], v[0:1] glc4368; VI-NSZ-NEXT: s_waitcnt vmcnt(0)4369; VI-NSZ-NEXT: flat_load_dwordx4 v[4:7], v[4:5] glc4370; VI-NSZ-NEXT: s_waitcnt vmcnt(0)4371; VI-NSZ-NEXT: flat_load_dwordx4 v[8:11], v[8:9] glc4372; VI-NSZ-NEXT: s_waitcnt vmcnt(0)4373; VI-NSZ-NEXT: v_mov_b32_e32 v13, s14374; VI-NSZ-NEXT: v_add_u32_e32 v12, vcc, s0, v124375; VI-NSZ-NEXT: v_addc_u32_e32 v13, vcc, 0, v13, vcc4376; VI-NSZ-NEXT: v_mad_f32 v3, v3, -v7, -v114377; VI-NSZ-NEXT: v_mad_f32 v2, v2, -v6, -v104378; VI-NSZ-NEXT: v_mad_f32 v1, v1, -v5, -v94379; VI-NSZ-NEXT: v_mad_f32 v0, v0, -v4, -v84380; VI-NSZ-NEXT: flat_store_dwordx4 v[12:13], v[0:3]4381; VI-NSZ-NEXT: s_endpgm4382 %tid = call i32 @llvm.amdgcn.workitem.id.x()4383 %tid.ext = sext i32 %tid to i644384 %a.gep = getelementptr inbounds <4 x float>, ptr addrspace(1) %a.ptr, i64 %tid.ext4385 %b.gep = getelementptr inbounds <4 x float>, ptr addrspace(1) %b.ptr, i64 %tid.ext4386 %c.gep = getelementptr inbounds <4 x float>, ptr addrspace(1) %c.ptr, i64 %tid.ext4387 %out.gep = getelementptr inbounds <4 x float>, ptr addrspace(1) %out, i64 %tid.ext4388 %a = load volatile <4 x float>, ptr addrspace(1) %a.gep4389 %b = load volatile <4 x float>, ptr addrspace(1) %b.gep4390 %c = load volatile <4 x float>, ptr addrspace(1) %c.gep4391 %fma = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %c)4392 %fneg = fneg <4 x float> %fma4393 store <4 x float> %fneg, ptr addrspace(1) %out.gep4394 ret void4395}4396 4397define amdgpu_kernel void @v_fneg_fmad_multi_use_fmad_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr, ptr addrspace(1) %c.ptr) #0 {4398; SI-SAFE-LABEL: v_fneg_fmad_multi_use_fmad_f32:4399; SI-SAFE: ; %bb.0:4400; SI-SAFE-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x94401; SI-SAFE-NEXT: v_lshlrev_b32_e32 v4, 2, v04402; SI-SAFE-NEXT: s_waitcnt lgkmcnt(0)4403; SI-SAFE-NEXT: v_mov_b32_e32 v1, s34404; SI-SAFE-NEXT: v_add_i32_e32 v0, vcc, s2, v44405; SI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc4406; SI-SAFE-NEXT: v_mov_b32_e32 v3, s54407; SI-SAFE-NEXT: v_add_i32_e32 v2, vcc, s4, v44408; SI-SAFE-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc4409; SI-SAFE-NEXT: v_mov_b32_e32 v5, s74410; SI-SAFE-NEXT: v_add_i32_e32 v4, vcc, s6, v44411; SI-SAFE-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc4412; SI-SAFE-NEXT: flat_load_dword v6, v[0:1] glc4413; SI-SAFE-NEXT: s_waitcnt vmcnt(0)4414; SI-SAFE-NEXT: flat_load_dword v2, v[2:3] glc4415; SI-SAFE-NEXT: s_waitcnt vmcnt(0)4416; SI-SAFE-NEXT: flat_load_dword v3, v[4:5] glc4417; SI-SAFE-NEXT: s_waitcnt vmcnt(0)4418; SI-SAFE-NEXT: v_mov_b32_e32 v0, s04419; SI-SAFE-NEXT: v_mov_b32_e32 v1, s14420; SI-SAFE-NEXT: v_mac_f32_e32 v3, v6, v24421; SI-SAFE-NEXT: v_xor_b32_e32 v2, 0x80000000, v34422; SI-SAFE-NEXT: v_mul_f32_e32 v3, 4.0, v34423; SI-SAFE-NEXT: flat_store_dword v[0:1], v24424; SI-SAFE-NEXT: s_waitcnt vmcnt(0)4425; SI-SAFE-NEXT: flat_store_dword v[0:1], v34426; SI-SAFE-NEXT: s_waitcnt vmcnt(0)4427; SI-SAFE-NEXT: s_endpgm4428;4429; SI-NSZ-LABEL: v_fneg_fmad_multi_use_fmad_f32:4430; SI-NSZ: ; %bb.0:4431; SI-NSZ-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x94432; SI-NSZ-NEXT: v_lshlrev_b32_e32 v4, 2, v04433; SI-NSZ-NEXT: s_waitcnt lgkmcnt(0)4434; SI-NSZ-NEXT: v_mov_b32_e32 v1, s34435; SI-NSZ-NEXT: v_add_i32_e32 v0, vcc, s2, v44436; SI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc4437; SI-NSZ-NEXT: v_mov_b32_e32 v3, s54438; SI-NSZ-NEXT: v_add_i32_e32 v2, vcc, s4, v44439; SI-NSZ-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc4440; SI-NSZ-NEXT: v_mov_b32_e32 v5, s74441; SI-NSZ-NEXT: v_add_i32_e32 v4, vcc, s6, v44442; SI-NSZ-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc4443; SI-NSZ-NEXT: flat_load_dword v6, v[0:1] glc4444; SI-NSZ-NEXT: s_waitcnt vmcnt(0)4445; SI-NSZ-NEXT: flat_load_dword v2, v[2:3] glc4446; SI-NSZ-NEXT: s_waitcnt vmcnt(0)4447; SI-NSZ-NEXT: flat_load_dword v3, v[4:5] glc4448; SI-NSZ-NEXT: s_waitcnt vmcnt(0)4449; SI-NSZ-NEXT: v_mov_b32_e32 v0, s04450; SI-NSZ-NEXT: v_mov_b32_e32 v1, s14451; SI-NSZ-NEXT: v_mad_f32 v2, v6, -v2, -v34452; SI-NSZ-NEXT: v_mul_f32_e32 v3, -4.0, v24453; SI-NSZ-NEXT: flat_store_dword v[0:1], v24454; SI-NSZ-NEXT: s_waitcnt vmcnt(0)4455; SI-NSZ-NEXT: flat_store_dword v[0:1], v34456; SI-NSZ-NEXT: s_waitcnt vmcnt(0)4457; SI-NSZ-NEXT: s_endpgm4458;4459; VI-SAFE-LABEL: v_fneg_fmad_multi_use_fmad_f32:4460; VI-SAFE: ; %bb.0:4461; VI-SAFE-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x244462; VI-SAFE-NEXT: v_lshlrev_b32_e32 v4, 2, v04463; VI-SAFE-NEXT: s_waitcnt lgkmcnt(0)4464; VI-SAFE-NEXT: v_mov_b32_e32 v1, s34465; VI-SAFE-NEXT: v_add_u32_e32 v0, vcc, s2, v44466; VI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc4467; VI-SAFE-NEXT: v_mov_b32_e32 v3, s54468; VI-SAFE-NEXT: v_add_u32_e32 v2, vcc, s4, v44469; VI-SAFE-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc4470; VI-SAFE-NEXT: v_mov_b32_e32 v5, s74471; VI-SAFE-NEXT: v_add_u32_e32 v4, vcc, s6, v44472; VI-SAFE-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc4473; VI-SAFE-NEXT: flat_load_dword v6, v[0:1] glc4474; VI-SAFE-NEXT: s_waitcnt vmcnt(0)4475; VI-SAFE-NEXT: flat_load_dword v2, v[2:3] glc4476; VI-SAFE-NEXT: s_waitcnt vmcnt(0)4477; VI-SAFE-NEXT: flat_load_dword v3, v[4:5] glc4478; VI-SAFE-NEXT: s_waitcnt vmcnt(0)4479; VI-SAFE-NEXT: v_mov_b32_e32 v0, s04480; VI-SAFE-NEXT: v_mov_b32_e32 v1, s14481; VI-SAFE-NEXT: v_mac_f32_e32 v3, v6, v24482; VI-SAFE-NEXT: v_xor_b32_e32 v2, 0x80000000, v34483; VI-SAFE-NEXT: v_mul_f32_e32 v3, 4.0, v34484; VI-SAFE-NEXT: flat_store_dword v[0:1], v24485; VI-SAFE-NEXT: s_waitcnt vmcnt(0)4486; VI-SAFE-NEXT: flat_store_dword v[0:1], v34487; VI-SAFE-NEXT: s_waitcnt vmcnt(0)4488; VI-SAFE-NEXT: s_endpgm4489;4490; VI-NSZ-LABEL: v_fneg_fmad_multi_use_fmad_f32:4491; VI-NSZ: ; %bb.0:4492; VI-NSZ-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x244493; VI-NSZ-NEXT: v_lshlrev_b32_e32 v4, 2, v04494; VI-NSZ-NEXT: s_waitcnt lgkmcnt(0)4495; VI-NSZ-NEXT: v_mov_b32_e32 v1, s34496; VI-NSZ-NEXT: v_add_u32_e32 v0, vcc, s2, v44497; VI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc4498; VI-NSZ-NEXT: v_mov_b32_e32 v3, s54499; VI-NSZ-NEXT: v_add_u32_e32 v2, vcc, s4, v44500; VI-NSZ-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc4501; VI-NSZ-NEXT: v_mov_b32_e32 v5, s74502; VI-NSZ-NEXT: v_add_u32_e32 v4, vcc, s6, v44503; VI-NSZ-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc4504; VI-NSZ-NEXT: flat_load_dword v6, v[0:1] glc4505; VI-NSZ-NEXT: s_waitcnt vmcnt(0)4506; VI-NSZ-NEXT: flat_load_dword v2, v[2:3] glc4507; VI-NSZ-NEXT: s_waitcnt vmcnt(0)4508; VI-NSZ-NEXT: flat_load_dword v3, v[4:5] glc4509; VI-NSZ-NEXT: s_waitcnt vmcnt(0)4510; VI-NSZ-NEXT: v_mov_b32_e32 v0, s04511; VI-NSZ-NEXT: v_mov_b32_e32 v1, s14512; VI-NSZ-NEXT: v_mad_f32 v2, v6, -v2, -v34513; VI-NSZ-NEXT: v_mul_f32_e32 v3, -4.0, v24514; VI-NSZ-NEXT: flat_store_dword v[0:1], v24515; VI-NSZ-NEXT: s_waitcnt vmcnt(0)4516; VI-NSZ-NEXT: flat_store_dword v[0:1], v34517; VI-NSZ-NEXT: s_waitcnt vmcnt(0)4518; VI-NSZ-NEXT: s_endpgm4519 %tid = call i32 @llvm.amdgcn.workitem.id.x()4520 %tid.ext = sext i32 %tid to i644521 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext4522 %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext4523 %c.gep = getelementptr inbounds float, ptr addrspace(1) %c.ptr, i64 %tid.ext4524 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext4525 %a = load volatile float, ptr addrspace(1) %a.gep4526 %b = load volatile float, ptr addrspace(1) %b.gep4527 %c = load volatile float, ptr addrspace(1) %c.gep4528 %fma = call float @llvm.fmuladd.f32(float %a, float %b, float %c)4529 %fneg = fneg float %fma4530 %use1 = fmul float %fma, 4.04531 store volatile float %fneg, ptr addrspace(1) %out4532 store volatile float %use1, ptr addrspace(1) %out4533 ret void4534}4535 4536; --------------------------------------------------------------------------------4537; fp_extend tests4538; --------------------------------------------------------------------------------4539 4540define amdgpu_kernel void @v_fneg_fp_extend_f32_to_f64(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) #0 {4541; SI-LABEL: v_fneg_fp_extend_f32_to_f64:4542; SI: ; %bb.0:4543; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x94544; SI-NEXT: v_lshlrev_b32_e32 v1, 2, v04545; SI-NEXT: s_waitcnt lgkmcnt(0)4546; SI-NEXT: v_mov_b32_e32 v2, s34547; SI-NEXT: v_add_i32_e32 v1, vcc, s2, v14548; SI-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc4549; SI-NEXT: flat_load_dword v1, v[1:2] glc4550; SI-NEXT: s_waitcnt vmcnt(0)4551; SI-NEXT: v_lshlrev_b32_e32 v2, 3, v04552; SI-NEXT: v_mov_b32_e32 v3, s14553; SI-NEXT: v_add_i32_e32 v2, vcc, s0, v24554; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc4555; SI-NEXT: v_cvt_f64_f32_e64 v[0:1], -v14556; SI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]4557; SI-NEXT: s_endpgm4558;4559; VI-LABEL: v_fneg_fp_extend_f32_to_f64:4560; VI: ; %bb.0:4561; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x244562; VI-NEXT: v_lshlrev_b32_e32 v1, 2, v04563; VI-NEXT: s_waitcnt lgkmcnt(0)4564; VI-NEXT: v_mov_b32_e32 v2, s34565; VI-NEXT: v_add_u32_e32 v1, vcc, s2, v14566; VI-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc4567; VI-NEXT: flat_load_dword v1, v[1:2] glc4568; VI-NEXT: s_waitcnt vmcnt(0)4569; VI-NEXT: v_lshlrev_b32_e32 v2, 3, v04570; VI-NEXT: v_mov_b32_e32 v3, s14571; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v24572; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc4573; VI-NEXT: v_cvt_f64_f32_e64 v[0:1], -v14574; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]4575; VI-NEXT: s_endpgm4576 %tid = call i32 @llvm.amdgcn.workitem.id.x()4577 %tid.ext = sext i32 %tid to i644578 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext4579 %out.gep = getelementptr inbounds double, ptr addrspace(1) %out, i64 %tid.ext4580 %a = load volatile float, ptr addrspace(1) %a.gep4581 %fpext = fpext float %a to double4582 %fneg = fsub double -0.000000e+00, %fpext4583 store double %fneg, ptr addrspace(1) %out.gep4584 ret void4585}4586 4587define amdgpu_kernel void @v_fneg_fp_extend_fneg_f32_to_f64(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) #0 {4588; SI-LABEL: v_fneg_fp_extend_fneg_f32_to_f64:4589; SI: ; %bb.0:4590; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x94591; SI-NEXT: v_lshlrev_b32_e32 v1, 2, v04592; SI-NEXT: s_waitcnt lgkmcnt(0)4593; SI-NEXT: v_mov_b32_e32 v2, s34594; SI-NEXT: v_add_i32_e32 v1, vcc, s2, v14595; SI-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc4596; SI-NEXT: flat_load_dword v1, v[1:2] glc4597; SI-NEXT: s_waitcnt vmcnt(0)4598; SI-NEXT: v_lshlrev_b32_e32 v2, 3, v04599; SI-NEXT: v_mov_b32_e32 v3, s14600; SI-NEXT: v_add_i32_e32 v2, vcc, s0, v24601; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc4602; SI-NEXT: v_cvt_f64_f32_e32 v[0:1], v14603; SI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]4604; SI-NEXT: s_endpgm4605;4606; VI-LABEL: v_fneg_fp_extend_fneg_f32_to_f64:4607; VI: ; %bb.0:4608; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x244609; VI-NEXT: v_lshlrev_b32_e32 v1, 2, v04610; VI-NEXT: s_waitcnt lgkmcnt(0)4611; VI-NEXT: v_mov_b32_e32 v2, s34612; VI-NEXT: v_add_u32_e32 v1, vcc, s2, v14613; VI-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc4614; VI-NEXT: flat_load_dword v1, v[1:2] glc4615; VI-NEXT: s_waitcnt vmcnt(0)4616; VI-NEXT: v_lshlrev_b32_e32 v2, 3, v04617; VI-NEXT: v_mov_b32_e32 v3, s14618; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v24619; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc4620; VI-NEXT: v_cvt_f64_f32_e32 v[0:1], v14621; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]4622; VI-NEXT: s_endpgm4623 %tid = call i32 @llvm.amdgcn.workitem.id.x()4624 %tid.ext = sext i32 %tid to i644625 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext4626 %out.gep = getelementptr inbounds double, ptr addrspace(1) %out, i64 %tid.ext4627 %a = load volatile float, ptr addrspace(1) %a.gep4628 %fneg.a = fneg float %a4629 %fpext = fpext float %fneg.a to double4630 %fneg = fsub double -0.000000e+00, %fpext4631 store double %fneg, ptr addrspace(1) %out.gep4632 ret void4633}4634 4635define amdgpu_kernel void @v_fneg_fp_extend_store_use_fneg_f32_to_f64(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) #0 {4636; SI-LABEL: v_fneg_fp_extend_store_use_fneg_f32_to_f64:4637; SI: ; %bb.0:4638; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x94639; SI-NEXT: v_lshlrev_b32_e32 v1, 2, v04640; SI-NEXT: s_waitcnt lgkmcnt(0)4641; SI-NEXT: v_mov_b32_e32 v2, s34642; SI-NEXT: v_add_i32_e32 v1, vcc, s2, v14643; SI-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc4644; SI-NEXT: flat_load_dword v4, v[1:2] glc4645; SI-NEXT: s_waitcnt vmcnt(0)4646; SI-NEXT: v_lshlrev_b32_e32 v2, 3, v04647; SI-NEXT: v_mov_b32_e32 v3, s14648; SI-NEXT: v_add_i32_e32 v2, vcc, s0, v24649; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc4650; SI-NEXT: v_cvt_f64_f32_e32 v[0:1], v44651; SI-NEXT: v_xor_b32_e32 v4, 0x80000000, v44652; SI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]4653; SI-NEXT: s_waitcnt vmcnt(0)4654; SI-NEXT: flat_store_dword v[0:1], v44655; SI-NEXT: s_waitcnt vmcnt(0)4656; SI-NEXT: s_endpgm4657;4658; VI-LABEL: v_fneg_fp_extend_store_use_fneg_f32_to_f64:4659; VI: ; %bb.0:4660; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x244661; VI-NEXT: v_lshlrev_b32_e32 v1, 2, v04662; VI-NEXT: s_waitcnt lgkmcnt(0)4663; VI-NEXT: v_mov_b32_e32 v2, s34664; VI-NEXT: v_add_u32_e32 v1, vcc, s2, v14665; VI-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc4666; VI-NEXT: flat_load_dword v4, v[1:2] glc4667; VI-NEXT: s_waitcnt vmcnt(0)4668; VI-NEXT: v_lshlrev_b32_e32 v2, 3, v04669; VI-NEXT: v_mov_b32_e32 v3, s14670; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v24671; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc4672; VI-NEXT: v_cvt_f64_f32_e32 v[0:1], v44673; VI-NEXT: v_xor_b32_e32 v4, 0x80000000, v44674; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]4675; VI-NEXT: s_waitcnt vmcnt(0)4676; VI-NEXT: flat_store_dword v[0:1], v44677; VI-NEXT: s_waitcnt vmcnt(0)4678; VI-NEXT: s_endpgm4679 %tid = call i32 @llvm.amdgcn.workitem.id.x()4680 %tid.ext = sext i32 %tid to i644681 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext4682 %out.gep = getelementptr inbounds double, ptr addrspace(1) %out, i64 %tid.ext4683 %a = load volatile float, ptr addrspace(1) %a.gep4684 %fneg.a = fneg float %a4685 %fpext = fpext float %fneg.a to double4686 %fneg = fsub double -0.000000e+00, %fpext4687 store volatile double %fneg, ptr addrspace(1) %out.gep4688 store volatile float %fneg.a, ptr addrspace(1) poison4689 ret void4690}4691 4692define amdgpu_kernel void @v_fneg_multi_use_fp_extend_fneg_f32_to_f64(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) #0 {4693; SI-LABEL: v_fneg_multi_use_fp_extend_fneg_f32_to_f64:4694; SI: ; %bb.0:4695; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x94696; SI-NEXT: v_lshlrev_b32_e32 v1, 2, v04697; SI-NEXT: s_waitcnt lgkmcnt(0)4698; SI-NEXT: v_mov_b32_e32 v2, s34699; SI-NEXT: v_add_i32_e32 v1, vcc, s2, v14700; SI-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc4701; SI-NEXT: flat_load_dword v1, v[1:2] glc4702; SI-NEXT: s_waitcnt vmcnt(0)4703; SI-NEXT: v_lshlrev_b32_e32 v2, 3, v04704; SI-NEXT: v_mov_b32_e32 v3, s14705; SI-NEXT: v_add_i32_e32 v2, vcc, s0, v24706; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc4707; SI-NEXT: v_cvt_f64_f32_e32 v[0:1], v14708; SI-NEXT: v_xor_b32_e32 v5, 0x80000000, v14709; SI-NEXT: v_mov_b32_e32 v4, v04710; SI-NEXT: flat_store_dwordx2 v[2:3], v[4:5]4711; SI-NEXT: s_waitcnt vmcnt(0)4712; SI-NEXT: flat_store_dwordx2 v[0:1], v[0:1]4713; SI-NEXT: s_waitcnt vmcnt(0)4714; SI-NEXT: s_endpgm4715;4716; VI-LABEL: v_fneg_multi_use_fp_extend_fneg_f32_to_f64:4717; VI: ; %bb.0:4718; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x244719; VI-NEXT: v_lshlrev_b32_e32 v1, 2, v04720; VI-NEXT: s_waitcnt lgkmcnt(0)4721; VI-NEXT: v_mov_b32_e32 v2, s34722; VI-NEXT: v_add_u32_e32 v1, vcc, s2, v14723; VI-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc4724; VI-NEXT: flat_load_dword v1, v[1:2] glc4725; VI-NEXT: s_waitcnt vmcnt(0)4726; VI-NEXT: v_lshlrev_b32_e32 v2, 3, v04727; VI-NEXT: v_mov_b32_e32 v3, s14728; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v24729; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc4730; VI-NEXT: v_cvt_f64_f32_e32 v[0:1], v14731; VI-NEXT: v_xor_b32_e32 v5, 0x80000000, v14732; VI-NEXT: v_mov_b32_e32 v4, v04733; VI-NEXT: flat_store_dwordx2 v[2:3], v[4:5]4734; VI-NEXT: s_waitcnt vmcnt(0)4735; VI-NEXT: flat_store_dwordx2 v[0:1], v[0:1]4736; VI-NEXT: s_waitcnt vmcnt(0)4737; VI-NEXT: s_endpgm4738 %tid = call i32 @llvm.amdgcn.workitem.id.x()4739 %tid.ext = sext i32 %tid to i644740 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext4741 %out.gep = getelementptr inbounds double, ptr addrspace(1) %out, i64 %tid.ext4742 %a = load volatile float, ptr addrspace(1) %a.gep4743 %fpext = fpext float %a to double4744 %fneg = fsub double -0.000000e+00, %fpext4745 store volatile double %fneg, ptr addrspace(1) %out.gep4746 store volatile double %fpext, ptr addrspace(1) poison4747 ret void4748}4749 4750define amdgpu_kernel void @v_fneg_multi_foldable_use_fp_extend_fneg_f32_to_f64(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) #0 {4751; SI-LABEL: v_fneg_multi_foldable_use_fp_extend_fneg_f32_to_f64:4752; SI: ; %bb.0:4753; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x94754; SI-NEXT: v_lshlrev_b32_e32 v1, 2, v04755; SI-NEXT: s_waitcnt lgkmcnt(0)4756; SI-NEXT: v_mov_b32_e32 v2, s34757; SI-NEXT: v_add_i32_e32 v1, vcc, s2, v14758; SI-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc4759; SI-NEXT: flat_load_dword v1, v[1:2] glc4760; SI-NEXT: s_waitcnt vmcnt(0)4761; SI-NEXT: v_lshlrev_b32_e32 v2, 3, v04762; SI-NEXT: v_mov_b32_e32 v3, s14763; SI-NEXT: v_add_i32_e32 v2, vcc, s0, v24764; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc4765; SI-NEXT: v_cvt_f64_f32_e32 v[0:1], v14766; SI-NEXT: v_xor_b32_e32 v5, 0x80000000, v14767; SI-NEXT: v_mov_b32_e32 v4, v04768; SI-NEXT: v_mul_f64 v[0:1], v[0:1], 4.04769; SI-NEXT: flat_store_dwordx2 v[2:3], v[4:5]4770; SI-NEXT: s_waitcnt vmcnt(0)4771; SI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]4772; SI-NEXT: s_waitcnt vmcnt(0)4773; SI-NEXT: s_endpgm4774;4775; VI-LABEL: v_fneg_multi_foldable_use_fp_extend_fneg_f32_to_f64:4776; VI: ; %bb.0:4777; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x244778; VI-NEXT: v_lshlrev_b32_e32 v1, 2, v04779; VI-NEXT: v_lshlrev_b32_e32 v0, 3, v04780; VI-NEXT: s_waitcnt lgkmcnt(0)4781; VI-NEXT: v_mov_b32_e32 v2, s34782; VI-NEXT: v_add_u32_e32 v1, vcc, s2, v14783; VI-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc4784; VI-NEXT: flat_load_dword v1, v[1:2] glc4785; VI-NEXT: s_waitcnt vmcnt(0)4786; VI-NEXT: v_mov_b32_e32 v6, s14787; VI-NEXT: v_add_u32_e32 v5, vcc, s0, v04788; VI-NEXT: v_addc_u32_e32 v6, vcc, 0, v6, vcc4789; VI-NEXT: v_cvt_f64_f32_e32 v[1:2], v14790; VI-NEXT: v_mul_f64 v[3:4], v[1:2], 4.04791; VI-NEXT: v_xor_b32_e32 v2, 0x80000000, v24792; VI-NEXT: flat_store_dwordx2 v[5:6], v[1:2]4793; VI-NEXT: s_waitcnt vmcnt(0)4794; VI-NEXT: flat_store_dwordx2 v[5:6], v[3:4]4795; VI-NEXT: s_waitcnt vmcnt(0)4796; VI-NEXT: s_endpgm4797 %tid = call i32 @llvm.amdgcn.workitem.id.x()4798 %tid.ext = sext i32 %tid to i644799 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext4800 %out.gep = getelementptr inbounds double, ptr addrspace(1) %out, i64 %tid.ext4801 %a = load volatile float, ptr addrspace(1) %a.gep4802 %fpext = fpext float %a to double4803 %fneg = fsub double -0.000000e+00, %fpext4804 %mul = fmul double %fpext, 4.04805 store volatile double %fneg, ptr addrspace(1) %out.gep4806 store volatile double %mul, ptr addrspace(1) %out.gep4807 ret void4808}4809 4810; FIXME: Source modifiers not folded for f16->f324811define amdgpu_kernel void @v_fneg_multi_use_fp_extend_fneg_f16_to_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) #0 {4812; SI-LABEL: v_fneg_multi_use_fp_extend_fneg_f16_to_f32:4813; SI: ; %bb.0:4814; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x94815; SI-NEXT: v_lshlrev_b32_e32 v1, 1, v04816; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v04817; SI-NEXT: s_waitcnt lgkmcnt(0)4818; SI-NEXT: v_mov_b32_e32 v2, s34819; SI-NEXT: v_add_i32_e32 v1, vcc, s2, v14820; SI-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc4821; SI-NEXT: flat_load_ushort v1, v[1:2] glc4822; SI-NEXT: s_waitcnt vmcnt(0)4823; SI-NEXT: v_mov_b32_e32 v2, s14824; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v04825; SI-NEXT: v_cvt_f32_f16_e64 v4, -v14826; SI-NEXT: v_cvt_f32_f16_e32 v3, v14827; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc4828; SI-NEXT: flat_store_dword v[0:1], v44829; SI-NEXT: s_waitcnt vmcnt(0)4830; SI-NEXT: flat_store_dword v[0:1], v34831; SI-NEXT: s_waitcnt vmcnt(0)4832; SI-NEXT: s_endpgm4833;4834; VI-LABEL: v_fneg_multi_use_fp_extend_fneg_f16_to_f32:4835; VI: ; %bb.0:4836; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x244837; VI-NEXT: v_lshlrev_b32_e32 v1, 1, v04838; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v04839; VI-NEXT: s_waitcnt lgkmcnt(0)4840; VI-NEXT: v_mov_b32_e32 v2, s34841; VI-NEXT: v_add_u32_e32 v1, vcc, s2, v14842; VI-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc4843; VI-NEXT: flat_load_ushort v1, v[1:2] glc4844; VI-NEXT: s_waitcnt vmcnt(0)4845; VI-NEXT: v_mov_b32_e32 v2, s14846; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v04847; VI-NEXT: v_cvt_f32_f16_e32 v3, v14848; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc4849; VI-NEXT: v_xor_b32_e32 v2, 0x80000000, v34850; VI-NEXT: flat_store_dword v[0:1], v24851; VI-NEXT: s_waitcnt vmcnt(0)4852; VI-NEXT: flat_store_dword v[0:1], v34853; VI-NEXT: s_waitcnt vmcnt(0)4854; VI-NEXT: s_endpgm4855 %tid = call i32 @llvm.amdgcn.workitem.id.x()4856 %tid.ext = sext i32 %tid to i644857 %a.gep = getelementptr inbounds half, ptr addrspace(1) %a.ptr, i64 %tid.ext4858 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext4859 %a = load volatile half, ptr addrspace(1) %a.gep4860 %fpext = fpext half %a to float4861 %fneg = fneg float %fpext4862 store volatile float %fneg, ptr addrspace(1) %out.gep4863 store volatile float %fpext, ptr addrspace(1) %out.gep4864 ret void4865}4866 4867define amdgpu_kernel void @v_fneg_multi_foldable_use_fp_extend_fneg_f16_to_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) #0 {4868; SI-LABEL: v_fneg_multi_foldable_use_fp_extend_fneg_f16_to_f32:4869; SI: ; %bb.0:4870; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x94871; SI-NEXT: v_lshlrev_b32_e32 v1, 1, v04872; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v04873; SI-NEXT: s_waitcnt lgkmcnt(0)4874; SI-NEXT: v_mov_b32_e32 v2, s34875; SI-NEXT: v_add_i32_e32 v1, vcc, s2, v14876; SI-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc4877; SI-NEXT: flat_load_ushort v1, v[1:2] glc4878; SI-NEXT: s_waitcnt vmcnt(0)4879; SI-NEXT: v_mov_b32_e32 v2, s14880; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v04881; SI-NEXT: v_cvt_f32_f16_e32 v3, v14882; SI-NEXT: v_cvt_f32_f16_e64 v4, -v14883; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc4884; SI-NEXT: v_mul_f32_e32 v2, 4.0, v34885; SI-NEXT: flat_store_dword v[0:1], v44886; SI-NEXT: s_waitcnt vmcnt(0)4887; SI-NEXT: flat_store_dword v[0:1], v24888; SI-NEXT: s_waitcnt vmcnt(0)4889; SI-NEXT: s_endpgm4890;4891; VI-LABEL: v_fneg_multi_foldable_use_fp_extend_fneg_f16_to_f32:4892; VI: ; %bb.0:4893; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x244894; VI-NEXT: v_lshlrev_b32_e32 v1, 1, v04895; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v04896; VI-NEXT: s_waitcnt lgkmcnt(0)4897; VI-NEXT: v_mov_b32_e32 v2, s34898; VI-NEXT: v_add_u32_e32 v1, vcc, s2, v14899; VI-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc4900; VI-NEXT: flat_load_ushort v1, v[1:2] glc4901; VI-NEXT: s_waitcnt vmcnt(0)4902; VI-NEXT: v_mov_b32_e32 v2, s14903; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v04904; VI-NEXT: v_cvt_f32_f16_e32 v3, v14905; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc4906; VI-NEXT: v_xor_b32_e32 v2, 0x80000000, v34907; VI-NEXT: v_mul_f32_e32 v3, 4.0, v34908; VI-NEXT: flat_store_dword v[0:1], v24909; VI-NEXT: s_waitcnt vmcnt(0)4910; VI-NEXT: flat_store_dword v[0:1], v34911; VI-NEXT: s_waitcnt vmcnt(0)4912; VI-NEXT: s_endpgm4913 %tid = call i32 @llvm.amdgcn.workitem.id.x()4914 %tid.ext = sext i32 %tid to i644915 %a.gep = getelementptr inbounds half, ptr addrspace(1) %a.ptr, i64 %tid.ext4916 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext4917 %a = load volatile half, ptr addrspace(1) %a.gep4918 %fpext = fpext half %a to float4919 %fneg = fneg float %fpext4920 %mul = fmul float %fpext, 4.04921 store volatile float %fneg, ptr addrspace(1) %out.gep4922 store volatile float %mul, ptr addrspace(1) %out.gep4923 ret void4924}4925 4926; --------------------------------------------------------------------------------4927; fp_round tests4928; --------------------------------------------------------------------------------4929 4930define amdgpu_kernel void @v_fneg_fp_round_f64_to_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) #0 {4931; SI-LABEL: v_fneg_fp_round_f64_to_f32:4932; SI: ; %bb.0:4933; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x94934; SI-NEXT: v_lshlrev_b32_e32 v1, 3, v04935; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v04936; SI-NEXT: s_waitcnt lgkmcnt(0)4937; SI-NEXT: v_mov_b32_e32 v2, s34938; SI-NEXT: v_add_i32_e32 v1, vcc, s2, v14939; SI-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc4940; SI-NEXT: flat_load_dwordx2 v[1:2], v[1:2] glc4941; SI-NEXT: s_waitcnt vmcnt(0)4942; SI-NEXT: v_mov_b32_e32 v3, s14943; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v04944; SI-NEXT: v_cvt_f32_f64_e64 v2, -v[1:2]4945; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v3, vcc4946; SI-NEXT: flat_store_dword v[0:1], v24947; SI-NEXT: s_endpgm4948;4949; VI-LABEL: v_fneg_fp_round_f64_to_f32:4950; VI: ; %bb.0:4951; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x244952; VI-NEXT: v_lshlrev_b32_e32 v1, 3, v04953; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v04954; VI-NEXT: s_waitcnt lgkmcnt(0)4955; VI-NEXT: v_mov_b32_e32 v2, s34956; VI-NEXT: v_add_u32_e32 v1, vcc, s2, v14957; VI-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc4958; VI-NEXT: flat_load_dwordx2 v[1:2], v[1:2] glc4959; VI-NEXT: s_waitcnt vmcnt(0)4960; VI-NEXT: v_mov_b32_e32 v3, s14961; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v04962; VI-NEXT: v_cvt_f32_f64_e64 v2, -v[1:2]4963; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v3, vcc4964; VI-NEXT: flat_store_dword v[0:1], v24965; VI-NEXT: s_endpgm4966 %tid = call i32 @llvm.amdgcn.workitem.id.x()4967 %tid.ext = sext i32 %tid to i644968 %a.gep = getelementptr inbounds double, ptr addrspace(1) %a.ptr, i64 %tid.ext4969 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext4970 %a = load volatile double, ptr addrspace(1) %a.gep4971 %fpround = fptrunc double %a to float4972 %fneg = fneg float %fpround4973 store float %fneg, ptr addrspace(1) %out.gep4974 ret void4975}4976 4977define amdgpu_kernel void @v_fneg_fp_round_fneg_f64_to_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) #0 {4978; SI-LABEL: v_fneg_fp_round_fneg_f64_to_f32:4979; SI: ; %bb.0:4980; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x94981; SI-NEXT: v_lshlrev_b32_e32 v1, 3, v04982; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v04983; SI-NEXT: s_waitcnt lgkmcnt(0)4984; SI-NEXT: v_mov_b32_e32 v2, s34985; SI-NEXT: v_add_i32_e32 v1, vcc, s2, v14986; SI-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc4987; SI-NEXT: flat_load_dwordx2 v[1:2], v[1:2] glc4988; SI-NEXT: s_waitcnt vmcnt(0)4989; SI-NEXT: v_mov_b32_e32 v3, s14990; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v04991; SI-NEXT: v_cvt_f32_f64_e32 v2, v[1:2]4992; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v3, vcc4993; SI-NEXT: flat_store_dword v[0:1], v24994; SI-NEXT: s_endpgm4995;4996; VI-LABEL: v_fneg_fp_round_fneg_f64_to_f32:4997; VI: ; %bb.0:4998; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x244999; VI-NEXT: v_lshlrev_b32_e32 v1, 3, v05000; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v05001; VI-NEXT: s_waitcnt lgkmcnt(0)5002; VI-NEXT: v_mov_b32_e32 v2, s35003; VI-NEXT: v_add_u32_e32 v1, vcc, s2, v15004; VI-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc5005; VI-NEXT: flat_load_dwordx2 v[1:2], v[1:2] glc5006; VI-NEXT: s_waitcnt vmcnt(0)5007; VI-NEXT: v_mov_b32_e32 v3, s15008; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v05009; VI-NEXT: v_cvt_f32_f64_e32 v2, v[1:2]5010; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v3, vcc5011; VI-NEXT: flat_store_dword v[0:1], v25012; VI-NEXT: s_endpgm5013 %tid = call i32 @llvm.amdgcn.workitem.id.x()5014 %tid.ext = sext i32 %tid to i645015 %a.gep = getelementptr inbounds double, ptr addrspace(1) %a.ptr, i64 %tid.ext5016 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext5017 %a = load volatile double, ptr addrspace(1) %a.gep5018 %fneg.a = fsub nsz double -0.000000e+00, %a5019 %fpround = fptrunc double %fneg.a to float5020 %fneg = fneg float %fpround5021 store float %fneg, ptr addrspace(1) %out.gep5022 ret void5023}5024 5025define amdgpu_kernel void @v_fneg_fp_round_store_use_fneg_f64_to_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) #0 {5026; SI-LABEL: v_fneg_fp_round_store_use_fneg_f64_to_f32:5027; SI: ; %bb.0:5028; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x95029; SI-NEXT: v_lshlrev_b32_e32 v1, 3, v05030; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v05031; SI-NEXT: s_waitcnt lgkmcnt(0)5032; SI-NEXT: v_mov_b32_e32 v2, s35033; SI-NEXT: v_add_i32_e32 v1, vcc, s2, v15034; SI-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc5035; SI-NEXT: flat_load_dwordx2 v[1:2], v[1:2] glc5036; SI-NEXT: s_waitcnt vmcnt(0)5037; SI-NEXT: v_mov_b32_e32 v4, s15038; SI-NEXT: v_add_i32_e32 v3, vcc, s0, v05039; SI-NEXT: v_addc_u32_e32 v4, vcc, 0, v4, vcc5040; SI-NEXT: v_cvt_f32_f64_e32 v5, v[1:2]5041; SI-NEXT: v_xor_b32_e32 v2, 0x80000000, v25042; SI-NEXT: flat_store_dword v[3:4], v55043; SI-NEXT: s_waitcnt vmcnt(0)5044; SI-NEXT: flat_store_dwordx2 v[0:1], v[1:2]5045; SI-NEXT: s_waitcnt vmcnt(0)5046; SI-NEXT: s_endpgm5047;5048; VI-LABEL: v_fneg_fp_round_store_use_fneg_f64_to_f32:5049; VI: ; %bb.0:5050; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x245051; VI-NEXT: v_lshlrev_b32_e32 v1, 3, v05052; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v05053; VI-NEXT: s_waitcnt lgkmcnt(0)5054; VI-NEXT: v_mov_b32_e32 v2, s35055; VI-NEXT: v_add_u32_e32 v1, vcc, s2, v15056; VI-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc5057; VI-NEXT: flat_load_dwordx2 v[1:2], v[1:2] glc5058; VI-NEXT: s_waitcnt vmcnt(0)5059; VI-NEXT: v_mov_b32_e32 v4, s15060; VI-NEXT: v_add_u32_e32 v3, vcc, s0, v05061; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v4, vcc5062; VI-NEXT: v_cvt_f32_f64_e32 v5, v[1:2]5063; VI-NEXT: v_xor_b32_e32 v2, 0x80000000, v25064; VI-NEXT: flat_store_dword v[3:4], v55065; VI-NEXT: s_waitcnt vmcnt(0)5066; VI-NEXT: flat_store_dwordx2 v[0:1], v[1:2]5067; VI-NEXT: s_waitcnt vmcnt(0)5068; VI-NEXT: s_endpgm5069 %tid = call i32 @llvm.amdgcn.workitem.id.x()5070 %tid.ext = sext i32 %tid to i645071 %a.gep = getelementptr inbounds double, ptr addrspace(1) %a.ptr, i64 %tid.ext5072 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext5073 %a = load volatile double, ptr addrspace(1) %a.gep5074 %fneg.a = fsub double -0.000000e+00, %a5075 %fpround = fptrunc double %fneg.a to float5076 %fneg = fneg float %fpround5077 store volatile float %fneg, ptr addrspace(1) %out.gep5078 store volatile double %fneg.a, ptr addrspace(1) poison5079 ret void5080}5081 5082define amdgpu_kernel void @v_fneg_fp_round_multi_use_fneg_f64_to_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, double %c) #0 {5083; SI-LABEL: v_fneg_fp_round_multi_use_fneg_f64_to_f32:5084; SI: ; %bb.0:5085; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x95086; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd5087; SI-NEXT: v_lshlrev_b32_e32 v1, 3, v05088; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v05089; SI-NEXT: s_waitcnt lgkmcnt(0)5090; SI-NEXT: v_mov_b32_e32 v2, s35091; SI-NEXT: v_add_i32_e32 v1, vcc, s2, v15092; SI-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc5093; SI-NEXT: flat_load_dwordx2 v[1:2], v[1:2] glc5094; SI-NEXT: s_waitcnt vmcnt(0)5095; SI-NEXT: v_mov_b32_e32 v4, s15096; SI-NEXT: v_add_i32_e32 v3, vcc, s0, v05097; SI-NEXT: v_addc_u32_e32 v4, vcc, 0, v4, vcc5098; SI-NEXT: v_cvt_f32_f64_e32 v5, v[1:2]5099; SI-NEXT: v_mul_f64 v[0:1], -v[1:2], s[4:5]5100; SI-NEXT: flat_store_dword v[3:4], v55101; SI-NEXT: s_waitcnt vmcnt(0)5102; SI-NEXT: flat_store_dwordx2 v[0:1], v[0:1]5103; SI-NEXT: s_waitcnt vmcnt(0)5104; SI-NEXT: s_endpgm5105;5106; VI-LABEL: v_fneg_fp_round_multi_use_fneg_f64_to_f32:5107; VI: ; %bb.0:5108; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x245109; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x345110; VI-NEXT: v_lshlrev_b32_e32 v1, 3, v05111; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v05112; VI-NEXT: s_waitcnt lgkmcnt(0)5113; VI-NEXT: v_mov_b32_e32 v2, s35114; VI-NEXT: v_add_u32_e32 v1, vcc, s2, v15115; VI-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc5116; VI-NEXT: flat_load_dwordx2 v[1:2], v[1:2] glc5117; VI-NEXT: s_waitcnt vmcnt(0)5118; VI-NEXT: v_mov_b32_e32 v5, s15119; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v05120; VI-NEXT: v_mul_f64 v[3:4], -v[1:2], s[4:5]5121; VI-NEXT: v_cvt_f32_f64_e32 v2, v[1:2]5122; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v5, vcc5123; VI-NEXT: flat_store_dword v[0:1], v25124; VI-NEXT: s_waitcnt vmcnt(0)5125; VI-NEXT: flat_store_dwordx2 v[0:1], v[3:4]5126; VI-NEXT: s_waitcnt vmcnt(0)5127; VI-NEXT: s_endpgm5128 %tid = call i32 @llvm.amdgcn.workitem.id.x()5129 %tid.ext = sext i32 %tid to i645130 %a.gep = getelementptr inbounds double, ptr addrspace(1) %a.ptr, i64 %tid.ext5131 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext5132 %a = load volatile double, ptr addrspace(1) %a.gep5133 %fneg.a = fsub double -0.000000e+00, %a5134 %fpround = fptrunc double %fneg.a to float5135 %fneg = fneg float %fpround5136 %use1 = fmul double %fneg.a, %c5137 store volatile float %fneg, ptr addrspace(1) %out.gep5138 store volatile double %use1, ptr addrspace(1) poison5139 ret void5140}5141 5142define amdgpu_kernel void @v_fneg_fp_round_f32_to_f16(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) #0 {5143; SI-LABEL: v_fneg_fp_round_f32_to_f16:5144; SI: ; %bb.0:5145; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x95146; SI-NEXT: v_lshlrev_b32_e32 v1, 2, v05147; SI-NEXT: v_lshlrev_b32_e32 v0, 1, v05148; SI-NEXT: s_waitcnt lgkmcnt(0)5149; SI-NEXT: v_mov_b32_e32 v2, s35150; SI-NEXT: v_add_i32_e32 v1, vcc, s2, v15151; SI-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc5152; SI-NEXT: flat_load_dword v1, v[1:2] glc5153; SI-NEXT: s_waitcnt vmcnt(0)5154; SI-NEXT: v_mov_b32_e32 v2, s15155; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v05156; SI-NEXT: v_cvt_f16_f32_e64 v3, -v15157; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc5158; SI-NEXT: flat_store_short v[0:1], v35159; SI-NEXT: s_endpgm5160;5161; VI-LABEL: v_fneg_fp_round_f32_to_f16:5162; VI: ; %bb.0:5163; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x245164; VI-NEXT: v_lshlrev_b32_e32 v1, 2, v05165; VI-NEXT: v_lshlrev_b32_e32 v0, 1, v05166; VI-NEXT: s_waitcnt lgkmcnt(0)5167; VI-NEXT: v_mov_b32_e32 v2, s35168; VI-NEXT: v_add_u32_e32 v1, vcc, s2, v15169; VI-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc5170; VI-NEXT: flat_load_dword v1, v[1:2] glc5171; VI-NEXT: s_waitcnt vmcnt(0)5172; VI-NEXT: v_mov_b32_e32 v2, s15173; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v05174; VI-NEXT: v_cvt_f16_f32_e64 v3, -v15175; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc5176; VI-NEXT: flat_store_short v[0:1], v35177; VI-NEXT: s_endpgm5178 %tid = call i32 @llvm.amdgcn.workitem.id.x()5179 %tid.ext = sext i32 %tid to i645180 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext5181 %out.gep = getelementptr inbounds half, ptr addrspace(1) %out, i64 %tid.ext5182 %a = load volatile float, ptr addrspace(1) %a.gep5183 %fpround = fptrunc float %a to half5184 %fneg = fsub half -0.000000e+00, %fpround5185 store half %fneg, ptr addrspace(1) %out.gep5186 ret void5187}5188 5189define amdgpu_kernel void @v_fneg_fp_round_fneg_f32_to_f16(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) #0 {5190; SI-LABEL: v_fneg_fp_round_fneg_f32_to_f16:5191; SI: ; %bb.0:5192; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x95193; SI-NEXT: v_lshlrev_b32_e32 v1, 2, v05194; SI-NEXT: v_lshlrev_b32_e32 v0, 1, v05195; SI-NEXT: s_waitcnt lgkmcnt(0)5196; SI-NEXT: v_mov_b32_e32 v2, s35197; SI-NEXT: v_add_i32_e32 v1, vcc, s2, v15198; SI-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc5199; SI-NEXT: flat_load_dword v1, v[1:2] glc5200; SI-NEXT: s_waitcnt vmcnt(0)5201; SI-NEXT: v_mov_b32_e32 v2, s15202; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v05203; SI-NEXT: v_cvt_f16_f32_e32 v3, v15204; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc5205; SI-NEXT: flat_store_short v[0:1], v35206; SI-NEXT: s_endpgm5207;5208; VI-LABEL: v_fneg_fp_round_fneg_f32_to_f16:5209; VI: ; %bb.0:5210; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x245211; VI-NEXT: v_lshlrev_b32_e32 v1, 2, v05212; VI-NEXT: v_lshlrev_b32_e32 v0, 1, v05213; VI-NEXT: s_waitcnt lgkmcnt(0)5214; VI-NEXT: v_mov_b32_e32 v2, s35215; VI-NEXT: v_add_u32_e32 v1, vcc, s2, v15216; VI-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc5217; VI-NEXT: flat_load_dword v1, v[1:2] glc5218; VI-NEXT: s_waitcnt vmcnt(0)5219; VI-NEXT: v_mov_b32_e32 v2, s15220; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v05221; VI-NEXT: v_cvt_f16_f32_e32 v3, v15222; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc5223; VI-NEXT: flat_store_short v[0:1], v35224; VI-NEXT: s_endpgm5225 %tid = call i32 @llvm.amdgcn.workitem.id.x()5226 %tid.ext = sext i32 %tid to i645227 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext5228 %out.gep = getelementptr inbounds half, ptr addrspace(1) %out, i64 %tid.ext5229 %a = load volatile float, ptr addrspace(1) %a.gep5230 %fneg.a = fneg float %a5231 %fpround = fptrunc float %fneg.a to half5232 %fneg = fsub half -0.000000e+00, %fpround5233 store half %fneg, ptr addrspace(1) %out.gep5234 ret void5235}5236 5237define amdgpu_kernel void @v_fneg_multi_use_fp_round_fneg_f64_to_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) #0 {5238; SI-LABEL: v_fneg_multi_use_fp_round_fneg_f64_to_f32:5239; SI: ; %bb.0:5240; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x95241; SI-NEXT: v_lshlrev_b32_e32 v1, 3, v05242; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v05243; SI-NEXT: s_waitcnt lgkmcnt(0)5244; SI-NEXT: v_mov_b32_e32 v2, s35245; SI-NEXT: v_add_i32_e32 v1, vcc, s2, v15246; SI-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc5247; SI-NEXT: flat_load_dwordx2 v[1:2], v[1:2] glc5248; SI-NEXT: s_waitcnt vmcnt(0)5249; SI-NEXT: v_mov_b32_e32 v3, s15250; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v05251; SI-NEXT: v_cvt_f32_f64_e32 v2, v[1:2]5252; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v3, vcc5253; SI-NEXT: v_xor_b32_e32 v3, 0x80000000, v25254; SI-NEXT: flat_store_dword v[0:1], v35255; SI-NEXT: s_waitcnt vmcnt(0)5256; SI-NEXT: flat_store_dword v[0:1], v25257; SI-NEXT: s_waitcnt vmcnt(0)5258; SI-NEXT: s_endpgm5259;5260; VI-LABEL: v_fneg_multi_use_fp_round_fneg_f64_to_f32:5261; VI: ; %bb.0:5262; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x245263; VI-NEXT: v_lshlrev_b32_e32 v1, 3, v05264; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v05265; VI-NEXT: s_waitcnt lgkmcnt(0)5266; VI-NEXT: v_mov_b32_e32 v2, s35267; VI-NEXT: v_add_u32_e32 v1, vcc, s2, v15268; VI-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc5269; VI-NEXT: flat_load_dwordx2 v[1:2], v[1:2] glc5270; VI-NEXT: s_waitcnt vmcnt(0)5271; VI-NEXT: v_mov_b32_e32 v3, s15272; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v05273; VI-NEXT: v_cvt_f32_f64_e32 v2, v[1:2]5274; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v3, vcc5275; VI-NEXT: v_xor_b32_e32 v3, 0x80000000, v25276; VI-NEXT: flat_store_dword v[0:1], v35277; VI-NEXT: s_waitcnt vmcnt(0)5278; VI-NEXT: flat_store_dword v[0:1], v25279; VI-NEXT: s_waitcnt vmcnt(0)5280; VI-NEXT: s_endpgm5281 %tid = call i32 @llvm.amdgcn.workitem.id.x()5282 %tid.ext = sext i32 %tid to i645283 %a.gep = getelementptr inbounds double, ptr addrspace(1) %a.ptr, i64 %tid.ext5284 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext5285 %a = load volatile double, ptr addrspace(1) %a.gep5286 %fpround = fptrunc double %a to float5287 %fneg = fneg float %fpround5288 store volatile float %fneg, ptr addrspace(1) %out.gep5289 store volatile float %fpround, ptr addrspace(1) %out.gep5290 ret void5291}5292 5293define amdgpu_kernel void @v_fneg_fp_round_store_use_fneg_f32_to_f16(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) #0 {5294; SI-LABEL: v_fneg_fp_round_store_use_fneg_f32_to_f16:5295; SI: ; %bb.0:5296; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x95297; SI-NEXT: v_lshlrev_b32_e32 v1, 2, v05298; SI-NEXT: v_lshlrev_b32_e32 v0, 1, v05299; SI-NEXT: s_waitcnt lgkmcnt(0)5300; SI-NEXT: v_mov_b32_e32 v2, s35301; SI-NEXT: v_add_i32_e32 v1, vcc, s2, v15302; SI-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc5303; SI-NEXT: flat_load_dword v2, v[1:2] glc5304; SI-NEXT: s_waitcnt vmcnt(0)5305; SI-NEXT: v_mov_b32_e32 v1, s15306; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v05307; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc5308; SI-NEXT: v_cvt_f16_f32_e32 v3, v25309; SI-NEXT: v_xor_b32_e32 v2, 0x80000000, v25310; SI-NEXT: flat_store_short v[0:1], v35311; SI-NEXT: s_waitcnt vmcnt(0)5312; SI-NEXT: flat_store_dword v[0:1], v25313; SI-NEXT: s_waitcnt vmcnt(0)5314; SI-NEXT: s_endpgm5315;5316; VI-LABEL: v_fneg_fp_round_store_use_fneg_f32_to_f16:5317; VI: ; %bb.0:5318; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x245319; VI-NEXT: v_lshlrev_b32_e32 v1, 2, v05320; VI-NEXT: v_lshlrev_b32_e32 v0, 1, v05321; VI-NEXT: s_waitcnt lgkmcnt(0)5322; VI-NEXT: v_mov_b32_e32 v2, s35323; VI-NEXT: v_add_u32_e32 v1, vcc, s2, v15324; VI-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc5325; VI-NEXT: flat_load_dword v2, v[1:2] glc5326; VI-NEXT: s_waitcnt vmcnt(0)5327; VI-NEXT: v_mov_b32_e32 v1, s15328; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v05329; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc5330; VI-NEXT: v_cvt_f16_f32_e32 v3, v25331; VI-NEXT: v_xor_b32_e32 v2, 0x80000000, v25332; VI-NEXT: flat_store_short v[0:1], v35333; VI-NEXT: s_waitcnt vmcnt(0)5334; VI-NEXT: flat_store_dword v[0:1], v25335; VI-NEXT: s_waitcnt vmcnt(0)5336; VI-NEXT: s_endpgm5337 %tid = call i32 @llvm.amdgcn.workitem.id.x()5338 %tid.ext = sext i32 %tid to i645339 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext5340 %out.gep = getelementptr inbounds half, ptr addrspace(1) %out, i64 %tid.ext5341 %a = load volatile float, ptr addrspace(1) %a.gep5342 %fneg.a = fneg float %a5343 %fpround = fptrunc float %fneg.a to half5344 %fneg = fsub half -0.000000e+00, %fpround5345 store volatile half %fneg, ptr addrspace(1) %out.gep5346 store volatile float %fneg.a, ptr addrspace(1) poison5347 ret void5348}5349 5350define amdgpu_kernel void @v_fneg_fp_round_multi_use_fneg_f32_to_f16(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, float %c) #0 {5351; SI-LABEL: v_fneg_fp_round_multi_use_fneg_f32_to_f16:5352; SI: ; %bb.0:5353; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x95354; SI-NEXT: s_load_dword s4, s[4:5], 0xd5355; SI-NEXT: v_lshlrev_b32_e32 v1, 2, v05356; SI-NEXT: v_lshlrev_b32_e32 v0, 1, v05357; SI-NEXT: s_waitcnt lgkmcnt(0)5358; SI-NEXT: v_mov_b32_e32 v2, s35359; SI-NEXT: v_add_i32_e32 v1, vcc, s2, v15360; SI-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc5361; SI-NEXT: flat_load_dword v2, v[1:2] glc5362; SI-NEXT: s_waitcnt vmcnt(0)5363; SI-NEXT: v_mov_b32_e32 v1, s15364; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v05365; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc5366; SI-NEXT: v_cvt_f16_f32_e32 v3, v25367; SI-NEXT: v_mul_f32_e64 v2, -v2, s45368; SI-NEXT: flat_store_short v[0:1], v35369; SI-NEXT: s_waitcnt vmcnt(0)5370; SI-NEXT: flat_store_dword v[0:1], v25371; SI-NEXT: s_waitcnt vmcnt(0)5372; SI-NEXT: s_endpgm5373;5374; VI-LABEL: v_fneg_fp_round_multi_use_fneg_f32_to_f16:5375; VI: ; %bb.0:5376; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x245377; VI-NEXT: s_load_dword s4, s[4:5], 0x345378; VI-NEXT: v_lshlrev_b32_e32 v1, 2, v05379; VI-NEXT: v_lshlrev_b32_e32 v0, 1, v05380; VI-NEXT: s_waitcnt lgkmcnt(0)5381; VI-NEXT: v_mov_b32_e32 v2, s35382; VI-NEXT: v_add_u32_e32 v1, vcc, s2, v15383; VI-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc5384; VI-NEXT: flat_load_dword v2, v[1:2] glc5385; VI-NEXT: s_waitcnt vmcnt(0)5386; VI-NEXT: v_mov_b32_e32 v1, s15387; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v05388; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc5389; VI-NEXT: v_cvt_f16_f32_e32 v3, v25390; VI-NEXT: v_mul_f32_e64 v2, -v2, s45391; VI-NEXT: flat_store_short v[0:1], v35392; VI-NEXT: s_waitcnt vmcnt(0)5393; VI-NEXT: flat_store_dword v[0:1], v25394; VI-NEXT: s_waitcnt vmcnt(0)5395; VI-NEXT: s_endpgm5396 %tid = call i32 @llvm.amdgcn.workitem.id.x()5397 %tid.ext = sext i32 %tid to i645398 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext5399 %out.gep = getelementptr inbounds half, ptr addrspace(1) %out, i64 %tid.ext5400 %a = load volatile float, ptr addrspace(1) %a.gep5401 %fneg.a = fneg float %a5402 %fpround = fptrunc float %fneg.a to half5403 %fneg = fsub half -0.000000e+00, %fpround5404 %use1 = fmul float %fneg.a, %c5405 store volatile half %fneg, ptr addrspace(1) %out.gep5406 store volatile float %use1, ptr addrspace(1) poison5407 ret void5408}5409 5410; --------------------------------------------------------------------------------5411; rcp tests5412; --------------------------------------------------------------------------------5413 5414define amdgpu_kernel void @v_fneg_rcp_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) #0 {5415; SI-LABEL: v_fneg_rcp_f32:5416; SI: ; %bb.0:5417; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x95418; SI-NEXT: v_lshlrev_b32_e32 v2, 2, v05419; SI-NEXT: s_waitcnt lgkmcnt(0)5420; SI-NEXT: v_mov_b32_e32 v1, s35421; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v25422; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc5423; SI-NEXT: flat_load_dword v0, v[0:1] glc5424; SI-NEXT: s_waitcnt vmcnt(0)5425; SI-NEXT: v_mov_b32_e32 v1, s15426; SI-NEXT: v_rcp_f32_e64 v3, -v05427; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v25428; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc5429; SI-NEXT: flat_store_dword v[0:1], v35430; SI-NEXT: s_endpgm5431;5432; VI-LABEL: v_fneg_rcp_f32:5433; VI: ; %bb.0:5434; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x245435; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v05436; VI-NEXT: s_waitcnt lgkmcnt(0)5437; VI-NEXT: v_mov_b32_e32 v1, s35438; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v25439; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc5440; VI-NEXT: flat_load_dword v0, v[0:1] glc5441; VI-NEXT: s_waitcnt vmcnt(0)5442; VI-NEXT: v_mov_b32_e32 v1, s15443; VI-NEXT: v_rcp_f32_e64 v3, -v05444; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v25445; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc5446; VI-NEXT: flat_store_dword v[0:1], v35447; VI-NEXT: s_endpgm5448 %tid = call i32 @llvm.amdgcn.workitem.id.x()5449 %tid.ext = sext i32 %tid to i645450 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext5451 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext5452 %a = load volatile float, ptr addrspace(1) %a.gep5453 %rcp = call float @llvm.amdgcn.rcp.f32(float %a)5454 %fneg = fneg float %rcp5455 store float %fneg, ptr addrspace(1) %out.gep5456 ret void5457}5458 5459define amdgpu_kernel void @v_fneg_rcp_fneg_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) #0 {5460; SI-LABEL: v_fneg_rcp_fneg_f32:5461; SI: ; %bb.0:5462; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x95463; SI-NEXT: v_lshlrev_b32_e32 v2, 2, v05464; SI-NEXT: s_waitcnt lgkmcnt(0)5465; SI-NEXT: v_mov_b32_e32 v1, s35466; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v25467; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc5468; SI-NEXT: flat_load_dword v0, v[0:1] glc5469; SI-NEXT: s_waitcnt vmcnt(0)5470; SI-NEXT: v_mov_b32_e32 v1, s15471; SI-NEXT: v_rcp_f32_e32 v3, v05472; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v25473; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc5474; SI-NEXT: flat_store_dword v[0:1], v35475; SI-NEXT: s_endpgm5476;5477; VI-LABEL: v_fneg_rcp_fneg_f32:5478; VI: ; %bb.0:5479; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x245480; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v05481; VI-NEXT: s_waitcnt lgkmcnt(0)5482; VI-NEXT: v_mov_b32_e32 v1, s35483; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v25484; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc5485; VI-NEXT: flat_load_dword v0, v[0:1] glc5486; VI-NEXT: s_waitcnt vmcnt(0)5487; VI-NEXT: v_mov_b32_e32 v1, s15488; VI-NEXT: v_rcp_f32_e32 v3, v05489; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v25490; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc5491; VI-NEXT: flat_store_dword v[0:1], v35492; VI-NEXT: s_endpgm5493 %tid = call i32 @llvm.amdgcn.workitem.id.x()5494 %tid.ext = sext i32 %tid to i645495 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext5496 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext5497 %a = load volatile float, ptr addrspace(1) %a.gep5498 %fneg.a = fneg float %a5499 %rcp = call float @llvm.amdgcn.rcp.f32(float %fneg.a)5500 %fneg = fneg float %rcp5501 store float %fneg, ptr addrspace(1) %out.gep5502 ret void5503}5504 5505define amdgpu_kernel void @v_fneg_rcp_store_use_fneg_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) #0 {5506; SI-LABEL: v_fneg_rcp_store_use_fneg_f32:5507; SI: ; %bb.0:5508; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x95509; SI-NEXT: v_lshlrev_b32_e32 v2, 2, v05510; SI-NEXT: s_waitcnt lgkmcnt(0)5511; SI-NEXT: v_mov_b32_e32 v1, s35512; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v25513; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc5514; SI-NEXT: flat_load_dword v3, v[0:1] glc5515; SI-NEXT: s_waitcnt vmcnt(0)5516; SI-NEXT: v_mov_b32_e32 v1, s15517; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v25518; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc5519; SI-NEXT: v_rcp_f32_e32 v4, v35520; SI-NEXT: v_xor_b32_e32 v2, 0x80000000, v35521; SI-NEXT: flat_store_dword v[0:1], v45522; SI-NEXT: s_waitcnt vmcnt(0)5523; SI-NEXT: flat_store_dword v[0:1], v25524; SI-NEXT: s_waitcnt vmcnt(0)5525; SI-NEXT: s_endpgm5526;5527; VI-LABEL: v_fneg_rcp_store_use_fneg_f32:5528; VI: ; %bb.0:5529; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x245530; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v05531; VI-NEXT: s_waitcnt lgkmcnt(0)5532; VI-NEXT: v_mov_b32_e32 v1, s35533; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v25534; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc5535; VI-NEXT: flat_load_dword v3, v[0:1] glc5536; VI-NEXT: s_waitcnt vmcnt(0)5537; VI-NEXT: v_mov_b32_e32 v1, s15538; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v25539; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc5540; VI-NEXT: v_rcp_f32_e32 v4, v35541; VI-NEXT: v_xor_b32_e32 v2, 0x80000000, v35542; VI-NEXT: flat_store_dword v[0:1], v45543; VI-NEXT: s_waitcnt vmcnt(0)5544; VI-NEXT: flat_store_dword v[0:1], v25545; VI-NEXT: s_waitcnt vmcnt(0)5546; VI-NEXT: s_endpgm5547 %tid = call i32 @llvm.amdgcn.workitem.id.x()5548 %tid.ext = sext i32 %tid to i645549 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext5550 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext5551 %a = load volatile float, ptr addrspace(1) %a.gep5552 %fneg.a = fneg float %a5553 %rcp = call float @llvm.amdgcn.rcp.f32(float %fneg.a)5554 %fneg = fneg float %rcp5555 store volatile float %fneg, ptr addrspace(1) %out.gep5556 store volatile float %fneg.a, ptr addrspace(1) poison5557 ret void5558}5559 5560define amdgpu_kernel void @v_fneg_rcp_multi_use_fneg_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, float %c) #0 {5561; SI-LABEL: v_fneg_rcp_multi_use_fneg_f32:5562; SI: ; %bb.0:5563; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x95564; SI-NEXT: s_load_dword s4, s[4:5], 0xd5565; SI-NEXT: v_lshlrev_b32_e32 v2, 2, v05566; SI-NEXT: s_waitcnt lgkmcnt(0)5567; SI-NEXT: v_mov_b32_e32 v1, s35568; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v25569; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc5570; SI-NEXT: flat_load_dword v3, v[0:1] glc5571; SI-NEXT: s_waitcnt vmcnt(0)5572; SI-NEXT: v_mov_b32_e32 v1, s15573; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v25574; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc5575; SI-NEXT: v_rcp_f32_e32 v4, v35576; SI-NEXT: v_mul_f32_e64 v2, -v3, s45577; SI-NEXT: flat_store_dword v[0:1], v45578; SI-NEXT: s_waitcnt vmcnt(0)5579; SI-NEXT: flat_store_dword v[0:1], v25580; SI-NEXT: s_waitcnt vmcnt(0)5581; SI-NEXT: s_endpgm5582;5583; VI-LABEL: v_fneg_rcp_multi_use_fneg_f32:5584; VI: ; %bb.0:5585; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x245586; VI-NEXT: s_load_dword s4, s[4:5], 0x345587; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v05588; VI-NEXT: s_waitcnt lgkmcnt(0)5589; VI-NEXT: v_mov_b32_e32 v1, s35590; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v25591; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc5592; VI-NEXT: flat_load_dword v3, v[0:1] glc5593; VI-NEXT: s_waitcnt vmcnt(0)5594; VI-NEXT: v_mov_b32_e32 v1, s15595; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v25596; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc5597; VI-NEXT: v_rcp_f32_e32 v4, v35598; VI-NEXT: v_mul_f32_e64 v2, -v3, s45599; VI-NEXT: flat_store_dword v[0:1], v45600; VI-NEXT: s_waitcnt vmcnt(0)5601; VI-NEXT: flat_store_dword v[0:1], v25602; VI-NEXT: s_waitcnt vmcnt(0)5603; VI-NEXT: s_endpgm5604 %tid = call i32 @llvm.amdgcn.workitem.id.x()5605 %tid.ext = sext i32 %tid to i645606 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext5607 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext5608 %a = load volatile float, ptr addrspace(1) %a.gep5609 %fneg.a = fneg float %a5610 %rcp = call float @llvm.amdgcn.rcp.f32(float %fneg.a)5611 %fneg = fneg float %rcp5612 %use1 = fmul float %fneg.a, %c5613 store volatile float %fneg, ptr addrspace(1) %out.gep5614 store volatile float %use1, ptr addrspace(1) poison5615 ret void5616}5617 5618; --------------------------------------------------------------------------------5619; fmul_legacy tests5620; --------------------------------------------------------------------------------5621 5622define amdgpu_kernel void @v_fneg_mul_legacy_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {5623; SI-LABEL: v_fneg_mul_legacy_f32:5624; SI: ; %bb.0:5625; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x95626; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd5627; SI-NEXT: v_lshlrev_b32_e32 v4, 2, v05628; SI-NEXT: s_waitcnt lgkmcnt(0)5629; SI-NEXT: v_mov_b32_e32 v1, s35630; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v45631; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc5632; SI-NEXT: v_mov_b32_e32 v3, s55633; SI-NEXT: v_add_i32_e32 v2, vcc, s4, v45634; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc5635; SI-NEXT: flat_load_dword v5, v[0:1] glc5636; SI-NEXT: s_waitcnt vmcnt(0)5637; SI-NEXT: flat_load_dword v2, v[2:3] glc5638; SI-NEXT: s_waitcnt vmcnt(0)5639; SI-NEXT: v_mov_b32_e32 v1, s15640; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v45641; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc5642; SI-NEXT: v_mul_legacy_f32_e64 v2, v5, -v25643; SI-NEXT: flat_store_dword v[0:1], v25644; SI-NEXT: s_endpgm5645;5646; VI-LABEL: v_fneg_mul_legacy_f32:5647; VI: ; %bb.0:5648; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x245649; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x345650; VI-NEXT: v_lshlrev_b32_e32 v4, 2, v05651; VI-NEXT: s_waitcnt lgkmcnt(0)5652; VI-NEXT: v_mov_b32_e32 v1, s35653; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v45654; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc5655; VI-NEXT: v_mov_b32_e32 v3, s55656; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v45657; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc5658; VI-NEXT: flat_load_dword v5, v[0:1] glc5659; VI-NEXT: s_waitcnt vmcnt(0)5660; VI-NEXT: flat_load_dword v2, v[2:3] glc5661; VI-NEXT: s_waitcnt vmcnt(0)5662; VI-NEXT: v_mov_b32_e32 v1, s15663; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v45664; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc5665; VI-NEXT: v_mul_legacy_f32_e64 v2, v5, -v25666; VI-NEXT: flat_store_dword v[0:1], v25667; VI-NEXT: s_endpgm5668 %tid = call i32 @llvm.amdgcn.workitem.id.x()5669 %tid.ext = sext i32 %tid to i645670 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext5671 %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext5672 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext5673 %a = load volatile float, ptr addrspace(1) %a.gep5674 %b = load volatile float, ptr addrspace(1) %b.gep5675 %mul = call float @llvm.amdgcn.fmul.legacy(float %a, float %b)5676 %fneg = fneg float %mul5677 store float %fneg, ptr addrspace(1) %out.gep5678 ret void5679}5680 5681define amdgpu_kernel void @v_fneg_mul_legacy_store_use_mul_legacy_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {5682; SI-LABEL: v_fneg_mul_legacy_store_use_mul_legacy_f32:5683; SI: ; %bb.0:5684; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x95685; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd5686; SI-NEXT: v_lshlrev_b32_e32 v2, 2, v05687; SI-NEXT: s_waitcnt lgkmcnt(0)5688; SI-NEXT: v_mov_b32_e32 v1, s35689; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v25690; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc5691; SI-NEXT: v_mov_b32_e32 v3, s55692; SI-NEXT: v_add_i32_e32 v2, vcc, s4, v25693; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc5694; SI-NEXT: flat_load_dword v4, v[0:1] glc5695; SI-NEXT: s_waitcnt vmcnt(0)5696; SI-NEXT: flat_load_dword v2, v[2:3] glc5697; SI-NEXT: s_waitcnt vmcnt(0)5698; SI-NEXT: v_mov_b32_e32 v0, s05699; SI-NEXT: v_mov_b32_e32 v1, s15700; SI-NEXT: v_mul_legacy_f32_e32 v2, v4, v25701; SI-NEXT: v_xor_b32_e32 v3, 0x80000000, v25702; SI-NEXT: flat_store_dword v[0:1], v35703; SI-NEXT: s_waitcnt vmcnt(0)5704; SI-NEXT: flat_store_dword v[0:1], v25705; SI-NEXT: s_waitcnt vmcnt(0)5706; SI-NEXT: s_endpgm5707;5708; VI-LABEL: v_fneg_mul_legacy_store_use_mul_legacy_f32:5709; VI: ; %bb.0:5710; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x245711; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x345712; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v05713; VI-NEXT: s_waitcnt lgkmcnt(0)5714; VI-NEXT: v_mov_b32_e32 v1, s35715; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v25716; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc5717; VI-NEXT: v_mov_b32_e32 v3, s55718; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v25719; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc5720; VI-NEXT: flat_load_dword v4, v[0:1] glc5721; VI-NEXT: s_waitcnt vmcnt(0)5722; VI-NEXT: flat_load_dword v2, v[2:3] glc5723; VI-NEXT: s_waitcnt vmcnt(0)5724; VI-NEXT: v_mov_b32_e32 v0, s05725; VI-NEXT: v_mov_b32_e32 v1, s15726; VI-NEXT: v_mul_legacy_f32_e32 v2, v4, v25727; VI-NEXT: v_xor_b32_e32 v3, 0x80000000, v25728; VI-NEXT: flat_store_dword v[0:1], v35729; VI-NEXT: s_waitcnt vmcnt(0)5730; VI-NEXT: flat_store_dword v[0:1], v25731; VI-NEXT: s_waitcnt vmcnt(0)5732; VI-NEXT: s_endpgm5733 %tid = call i32 @llvm.amdgcn.workitem.id.x()5734 %tid.ext = sext i32 %tid to i645735 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext5736 %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext5737 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext5738 %a = load volatile float, ptr addrspace(1) %a.gep5739 %b = load volatile float, ptr addrspace(1) %b.gep5740 %mul = call float @llvm.amdgcn.fmul.legacy(float %a, float %b)5741 %fneg = fneg float %mul5742 store volatile float %fneg, ptr addrspace(1) %out5743 store volatile float %mul, ptr addrspace(1) %out5744 ret void5745}5746 5747define amdgpu_kernel void @v_fneg_mul_legacy_multi_use_mul_legacy_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {5748; SI-LABEL: v_fneg_mul_legacy_multi_use_mul_legacy_f32:5749; SI: ; %bb.0:5750; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x95751; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd5752; SI-NEXT: v_lshlrev_b32_e32 v2, 2, v05753; SI-NEXT: s_waitcnt lgkmcnt(0)5754; SI-NEXT: v_mov_b32_e32 v1, s35755; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v25756; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc5757; SI-NEXT: v_mov_b32_e32 v3, s55758; SI-NEXT: v_add_i32_e32 v2, vcc, s4, v25759; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc5760; SI-NEXT: flat_load_dword v4, v[0:1] glc5761; SI-NEXT: s_waitcnt vmcnt(0)5762; SI-NEXT: flat_load_dword v2, v[2:3] glc5763; SI-NEXT: s_waitcnt vmcnt(0)5764; SI-NEXT: v_mov_b32_e32 v0, s05765; SI-NEXT: v_mov_b32_e32 v1, s15766; SI-NEXT: v_mul_legacy_f32_e64 v2, v4, -v25767; SI-NEXT: v_mul_legacy_f32_e64 v3, -v2, 4.05768; SI-NEXT: flat_store_dword v[0:1], v25769; SI-NEXT: s_waitcnt vmcnt(0)5770; SI-NEXT: flat_store_dword v[0:1], v35771; SI-NEXT: s_waitcnt vmcnt(0)5772; SI-NEXT: s_endpgm5773;5774; VI-LABEL: v_fneg_mul_legacy_multi_use_mul_legacy_f32:5775; VI: ; %bb.0:5776; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x245777; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x345778; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v05779; VI-NEXT: s_waitcnt lgkmcnt(0)5780; VI-NEXT: v_mov_b32_e32 v1, s35781; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v25782; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc5783; VI-NEXT: v_mov_b32_e32 v3, s55784; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v25785; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc5786; VI-NEXT: flat_load_dword v4, v[0:1] glc5787; VI-NEXT: s_waitcnt vmcnt(0)5788; VI-NEXT: flat_load_dword v2, v[2:3] glc5789; VI-NEXT: s_waitcnt vmcnt(0)5790; VI-NEXT: v_mov_b32_e32 v0, s05791; VI-NEXT: v_mov_b32_e32 v1, s15792; VI-NEXT: v_mul_legacy_f32_e64 v2, v4, -v25793; VI-NEXT: v_mul_legacy_f32_e64 v3, -v2, 4.05794; VI-NEXT: flat_store_dword v[0:1], v25795; VI-NEXT: s_waitcnt vmcnt(0)5796; VI-NEXT: flat_store_dword v[0:1], v35797; VI-NEXT: s_waitcnt vmcnt(0)5798; VI-NEXT: s_endpgm5799 %tid = call i32 @llvm.amdgcn.workitem.id.x()5800 %tid.ext = sext i32 %tid to i645801 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext5802 %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext5803 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext5804 %a = load volatile float, ptr addrspace(1) %a.gep5805 %b = load volatile float, ptr addrspace(1) %b.gep5806 %mul = call float @llvm.amdgcn.fmul.legacy(float %a, float %b)5807 %fneg = fneg float %mul5808 %use1 = call float @llvm.amdgcn.fmul.legacy(float %mul, float 4.0)5809 store volatile float %fneg, ptr addrspace(1) %out5810 store volatile float %use1, ptr addrspace(1) %out5811 ret void5812}5813 5814define amdgpu_kernel void @v_fneg_mul_legacy_fneg_x_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {5815; SI-LABEL: v_fneg_mul_legacy_fneg_x_f32:5816; SI: ; %bb.0:5817; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x95818; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd5819; SI-NEXT: v_lshlrev_b32_e32 v2, 2, v05820; SI-NEXT: s_waitcnt lgkmcnt(0)5821; SI-NEXT: v_mov_b32_e32 v1, s35822; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v25823; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc5824; SI-NEXT: v_mov_b32_e32 v3, s55825; SI-NEXT: v_add_i32_e32 v2, vcc, s4, v25826; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc5827; SI-NEXT: flat_load_dword v0, v[0:1] glc5828; SI-NEXT: s_waitcnt vmcnt(0)5829; SI-NEXT: flat_load_dword v1, v[2:3] glc5830; SI-NEXT: s_waitcnt vmcnt(0)5831; SI-NEXT: v_mul_legacy_f32_e32 v2, v0, v15832; SI-NEXT: v_mov_b32_e32 v0, s05833; SI-NEXT: v_mov_b32_e32 v1, s15834; SI-NEXT: flat_store_dword v[0:1], v25835; SI-NEXT: s_waitcnt vmcnt(0)5836; SI-NEXT: s_endpgm5837;5838; VI-LABEL: v_fneg_mul_legacy_fneg_x_f32:5839; VI: ; %bb.0:5840; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x245841; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x345842; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v05843; VI-NEXT: s_waitcnt lgkmcnt(0)5844; VI-NEXT: v_mov_b32_e32 v1, s35845; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v25846; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc5847; VI-NEXT: v_mov_b32_e32 v3, s55848; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v25849; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc5850; VI-NEXT: flat_load_dword v0, v[0:1] glc5851; VI-NEXT: s_waitcnt vmcnt(0)5852; VI-NEXT: flat_load_dword v1, v[2:3] glc5853; VI-NEXT: s_waitcnt vmcnt(0)5854; VI-NEXT: v_mul_legacy_f32_e32 v2, v0, v15855; VI-NEXT: v_mov_b32_e32 v0, s05856; VI-NEXT: v_mov_b32_e32 v1, s15857; VI-NEXT: flat_store_dword v[0:1], v25858; VI-NEXT: s_waitcnt vmcnt(0)5859; VI-NEXT: s_endpgm5860 %tid = call i32 @llvm.amdgcn.workitem.id.x()5861 %tid.ext = sext i32 %tid to i645862 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext5863 %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext5864 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext5865 %a = load volatile float, ptr addrspace(1) %a.gep5866 %b = load volatile float, ptr addrspace(1) %b.gep5867 %fneg.a = fneg float %a5868 %mul = call float @llvm.amdgcn.fmul.legacy(float %fneg.a, float %b)5869 %fneg = fneg float %mul5870 store volatile float %fneg, ptr addrspace(1) %out5871 ret void5872}5873 5874define amdgpu_kernel void @v_fneg_mul_legacy_x_fneg_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {5875; SI-LABEL: v_fneg_mul_legacy_x_fneg_f32:5876; SI: ; %bb.0:5877; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x95878; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd5879; SI-NEXT: v_lshlrev_b32_e32 v2, 2, v05880; SI-NEXT: s_waitcnt lgkmcnt(0)5881; SI-NEXT: v_mov_b32_e32 v1, s35882; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v25883; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc5884; SI-NEXT: v_mov_b32_e32 v3, s55885; SI-NEXT: v_add_i32_e32 v2, vcc, s4, v25886; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc5887; SI-NEXT: flat_load_dword v0, v[0:1] glc5888; SI-NEXT: s_waitcnt vmcnt(0)5889; SI-NEXT: flat_load_dword v1, v[2:3] glc5890; SI-NEXT: s_waitcnt vmcnt(0)5891; SI-NEXT: v_mul_legacy_f32_e32 v2, v0, v15892; SI-NEXT: v_mov_b32_e32 v0, s05893; SI-NEXT: v_mov_b32_e32 v1, s15894; SI-NEXT: flat_store_dword v[0:1], v25895; SI-NEXT: s_waitcnt vmcnt(0)5896; SI-NEXT: s_endpgm5897;5898; VI-LABEL: v_fneg_mul_legacy_x_fneg_f32:5899; VI: ; %bb.0:5900; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x245901; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x345902; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v05903; VI-NEXT: s_waitcnt lgkmcnt(0)5904; VI-NEXT: v_mov_b32_e32 v1, s35905; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v25906; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc5907; VI-NEXT: v_mov_b32_e32 v3, s55908; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v25909; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc5910; VI-NEXT: flat_load_dword v0, v[0:1] glc5911; VI-NEXT: s_waitcnt vmcnt(0)5912; VI-NEXT: flat_load_dword v1, v[2:3] glc5913; VI-NEXT: s_waitcnt vmcnt(0)5914; VI-NEXT: v_mul_legacy_f32_e32 v2, v0, v15915; VI-NEXT: v_mov_b32_e32 v0, s05916; VI-NEXT: v_mov_b32_e32 v1, s15917; VI-NEXT: flat_store_dword v[0:1], v25918; VI-NEXT: s_waitcnt vmcnt(0)5919; VI-NEXT: s_endpgm5920 %tid = call i32 @llvm.amdgcn.workitem.id.x()5921 %tid.ext = sext i32 %tid to i645922 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext5923 %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext5924 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext5925 %a = load volatile float, ptr addrspace(1) %a.gep5926 %b = load volatile float, ptr addrspace(1) %b.gep5927 %fneg.b = fneg float %b5928 %mul = call float @llvm.amdgcn.fmul.legacy(float %a, float %fneg.b)5929 %fneg = fneg float %mul5930 store volatile float %fneg, ptr addrspace(1) %out5931 ret void5932}5933 5934define amdgpu_kernel void @v_fneg_mul_legacy_fneg_fneg_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {5935; SI-LABEL: v_fneg_mul_legacy_fneg_fneg_f32:5936; SI: ; %bb.0:5937; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x95938; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd5939; SI-NEXT: v_lshlrev_b32_e32 v2, 2, v05940; SI-NEXT: s_waitcnt lgkmcnt(0)5941; SI-NEXT: v_mov_b32_e32 v1, s35942; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v25943; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc5944; SI-NEXT: v_mov_b32_e32 v3, s55945; SI-NEXT: v_add_i32_e32 v2, vcc, s4, v25946; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc5947; SI-NEXT: flat_load_dword v0, v[0:1] glc5948; SI-NEXT: s_waitcnt vmcnt(0)5949; SI-NEXT: flat_load_dword v1, v[2:3] glc5950; SI-NEXT: s_waitcnt vmcnt(0)5951; SI-NEXT: v_mul_legacy_f32_e64 v2, v0, -v15952; SI-NEXT: v_mov_b32_e32 v0, s05953; SI-NEXT: v_mov_b32_e32 v1, s15954; SI-NEXT: flat_store_dword v[0:1], v25955; SI-NEXT: s_waitcnt vmcnt(0)5956; SI-NEXT: s_endpgm5957;5958; VI-LABEL: v_fneg_mul_legacy_fneg_fneg_f32:5959; VI: ; %bb.0:5960; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x245961; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x345962; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v05963; VI-NEXT: s_waitcnt lgkmcnt(0)5964; VI-NEXT: v_mov_b32_e32 v1, s35965; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v25966; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc5967; VI-NEXT: v_mov_b32_e32 v3, s55968; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v25969; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc5970; VI-NEXT: flat_load_dword v0, v[0:1] glc5971; VI-NEXT: s_waitcnt vmcnt(0)5972; VI-NEXT: flat_load_dword v1, v[2:3] glc5973; VI-NEXT: s_waitcnt vmcnt(0)5974; VI-NEXT: v_mul_legacy_f32_e64 v2, v0, -v15975; VI-NEXT: v_mov_b32_e32 v0, s05976; VI-NEXT: v_mov_b32_e32 v1, s15977; VI-NEXT: flat_store_dword v[0:1], v25978; VI-NEXT: s_waitcnt vmcnt(0)5979; VI-NEXT: s_endpgm5980 %tid = call i32 @llvm.amdgcn.workitem.id.x()5981 %tid.ext = sext i32 %tid to i645982 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext5983 %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext5984 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext5985 %a = load volatile float, ptr addrspace(1) %a.gep5986 %b = load volatile float, ptr addrspace(1) %b.gep5987 %fneg.a = fneg float %a5988 %fneg.b = fneg float %b5989 %mul = call float @llvm.amdgcn.fmul.legacy(float %fneg.a, float %fneg.b)5990 %fneg = fneg float %mul5991 store volatile float %fneg, ptr addrspace(1) %out5992 ret void5993}5994 5995define amdgpu_kernel void @v_fneg_mul_legacy_store_use_fneg_x_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {5996; SI-LABEL: v_fneg_mul_legacy_store_use_fneg_x_f32:5997; SI: ; %bb.0:5998; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x95999; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd6000; SI-NEXT: v_lshlrev_b32_e32 v2, 2, v06001; SI-NEXT: s_waitcnt lgkmcnt(0)6002; SI-NEXT: v_mov_b32_e32 v1, s36003; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v26004; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc6005; SI-NEXT: v_mov_b32_e32 v3, s56006; SI-NEXT: v_add_i32_e32 v2, vcc, s4, v26007; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc6008; SI-NEXT: flat_load_dword v4, v[0:1] glc6009; SI-NEXT: s_waitcnt vmcnt(0)6010; SI-NEXT: flat_load_dword v2, v[2:3] glc6011; SI-NEXT: s_waitcnt vmcnt(0)6012; SI-NEXT: v_mov_b32_e32 v0, s06013; SI-NEXT: v_mov_b32_e32 v1, s16014; SI-NEXT: v_xor_b32_e32 v3, 0x80000000, v46015; SI-NEXT: v_mul_legacy_f32_e32 v2, v4, v26016; SI-NEXT: flat_store_dword v[0:1], v26017; SI-NEXT: s_waitcnt vmcnt(0)6018; SI-NEXT: flat_store_dword v[0:1], v36019; SI-NEXT: s_waitcnt vmcnt(0)6020; SI-NEXT: s_endpgm6021;6022; VI-LABEL: v_fneg_mul_legacy_store_use_fneg_x_f32:6023; VI: ; %bb.0:6024; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x246025; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x346026; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v06027; VI-NEXT: s_waitcnt lgkmcnt(0)6028; VI-NEXT: v_mov_b32_e32 v1, s36029; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v26030; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc6031; VI-NEXT: v_mov_b32_e32 v3, s56032; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v26033; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc6034; VI-NEXT: flat_load_dword v4, v[0:1] glc6035; VI-NEXT: s_waitcnt vmcnt(0)6036; VI-NEXT: flat_load_dword v2, v[2:3] glc6037; VI-NEXT: s_waitcnt vmcnt(0)6038; VI-NEXT: v_mov_b32_e32 v0, s06039; VI-NEXT: v_mov_b32_e32 v1, s16040; VI-NEXT: v_xor_b32_e32 v3, 0x80000000, v46041; VI-NEXT: v_mul_legacy_f32_e32 v2, v4, v26042; VI-NEXT: flat_store_dword v[0:1], v26043; VI-NEXT: s_waitcnt vmcnt(0)6044; VI-NEXT: flat_store_dword v[0:1], v36045; VI-NEXT: s_waitcnt vmcnt(0)6046; VI-NEXT: s_endpgm6047 %tid = call i32 @llvm.amdgcn.workitem.id.x()6048 %tid.ext = sext i32 %tid to i646049 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext6050 %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext6051 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext6052 %a = load volatile float, ptr addrspace(1) %a.gep6053 %b = load volatile float, ptr addrspace(1) %b.gep6054 %fneg.a = fneg float %a6055 %mul = call float @llvm.amdgcn.fmul.legacy(float %fneg.a, float %b)6056 %fneg = fneg float %mul6057 store volatile float %fneg, ptr addrspace(1) %out6058 store volatile float %fneg.a, ptr addrspace(1) %out6059 ret void6060}6061 6062define amdgpu_kernel void @v_fneg_mul_legacy_multi_use_fneg_x_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr, float %c) #0 {6063; SI-LABEL: v_fneg_mul_legacy_multi_use_fneg_x_f32:6064; SI: ; %bb.0:6065; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x96066; SI-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0xd6067; SI-NEXT: v_lshlrev_b32_e32 v2, 2, v06068; SI-NEXT: s_waitcnt lgkmcnt(0)6069; SI-NEXT: v_mov_b32_e32 v1, s36070; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v26071; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc6072; SI-NEXT: v_mov_b32_e32 v3, s76073; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v26074; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc6075; SI-NEXT: flat_load_dword v4, v[0:1] glc6076; SI-NEXT: s_waitcnt vmcnt(0)6077; SI-NEXT: flat_load_dword v2, v[2:3] glc6078; SI-NEXT: s_waitcnt vmcnt(0)6079; SI-NEXT: s_load_dword s2, s[4:5], 0xf6080; SI-NEXT: v_mov_b32_e32 v0, s06081; SI-NEXT: v_mov_b32_e32 v1, s16082; SI-NEXT: s_waitcnt lgkmcnt(0)6083; SI-NEXT: v_mul_legacy_f32_e64 v3, -v4, s26084; SI-NEXT: v_mul_legacy_f32_e32 v2, v4, v26085; SI-NEXT: flat_store_dword v[0:1], v26086; SI-NEXT: s_waitcnt vmcnt(0)6087; SI-NEXT: flat_store_dword v[0:1], v36088; SI-NEXT: s_waitcnt vmcnt(0)6089; SI-NEXT: s_endpgm6090;6091; VI-LABEL: v_fneg_mul_legacy_multi_use_fneg_x_f32:6092; VI: ; %bb.0:6093; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x246094; VI-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x346095; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v06096; VI-NEXT: s_waitcnt lgkmcnt(0)6097; VI-NEXT: v_mov_b32_e32 v1, s36098; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v26099; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc6100; VI-NEXT: v_mov_b32_e32 v3, s76101; VI-NEXT: v_add_u32_e32 v2, vcc, s6, v26102; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc6103; VI-NEXT: flat_load_dword v4, v[0:1] glc6104; VI-NEXT: s_waitcnt vmcnt(0)6105; VI-NEXT: flat_load_dword v2, v[2:3] glc6106; VI-NEXT: s_waitcnt vmcnt(0)6107; VI-NEXT: s_load_dword s2, s[4:5], 0x3c6108; VI-NEXT: v_mov_b32_e32 v0, s06109; VI-NEXT: v_mov_b32_e32 v1, s16110; VI-NEXT: s_waitcnt lgkmcnt(0)6111; VI-NEXT: v_mul_legacy_f32_e64 v3, -v4, s26112; VI-NEXT: v_mul_legacy_f32_e32 v2, v4, v26113; VI-NEXT: flat_store_dword v[0:1], v26114; VI-NEXT: s_waitcnt vmcnt(0)6115; VI-NEXT: flat_store_dword v[0:1], v36116; VI-NEXT: s_waitcnt vmcnt(0)6117; VI-NEXT: s_endpgm6118 %tid = call i32 @llvm.amdgcn.workitem.id.x()6119 %tid.ext = sext i32 %tid to i646120 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext6121 %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext6122 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext6123 %a = load volatile float, ptr addrspace(1) %a.gep6124 %b = load volatile float, ptr addrspace(1) %b.gep6125 %fneg.a = fneg float %a6126 %mul = call float @llvm.amdgcn.fmul.legacy(float %fneg.a, float %b)6127 %fneg = fneg float %mul6128 %use1 = call float @llvm.amdgcn.fmul.legacy(float %fneg.a, float %c)6129 store volatile float %fneg, ptr addrspace(1) %out6130 store volatile float %use1, ptr addrspace(1) %out6131 ret void6132}6133 6134; --------------------------------------------------------------------------------6135; sin tests6136; --------------------------------------------------------------------------------6137 6138define amdgpu_kernel void @v_fneg_sin_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) #0 {6139; SI-LABEL: v_fneg_sin_f32:6140; SI: ; %bb.0:6141; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x96142; SI-NEXT: v_lshlrev_b32_e32 v2, 2, v06143; SI-NEXT: s_waitcnt lgkmcnt(0)6144; SI-NEXT: v_mov_b32_e32 v1, s36145; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v26146; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc6147; SI-NEXT: flat_load_dword v0, v[0:1] glc6148; SI-NEXT: s_waitcnt vmcnt(0)6149; SI-NEXT: v_mov_b32_e32 v1, s16150; SI-NEXT: v_mul_f32_e32 v0, 0xbe22f983, v06151; SI-NEXT: v_fract_f32_e32 v0, v06152; SI-NEXT: v_sin_f32_e32 v3, v06153; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v26154; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc6155; SI-NEXT: flat_store_dword v[0:1], v36156; SI-NEXT: s_endpgm6157;6158; VI-LABEL: v_fneg_sin_f32:6159; VI: ; %bb.0:6160; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x246161; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v06162; VI-NEXT: s_waitcnt lgkmcnt(0)6163; VI-NEXT: v_mov_b32_e32 v1, s36164; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v26165; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc6166; VI-NEXT: flat_load_dword v0, v[0:1] glc6167; VI-NEXT: s_waitcnt vmcnt(0)6168; VI-NEXT: v_mov_b32_e32 v1, s16169; VI-NEXT: v_mul_f32_e32 v0, 0xbe22f983, v06170; VI-NEXT: v_fract_f32_e32 v0, v06171; VI-NEXT: v_sin_f32_e32 v3, v06172; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v26173; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc6174; VI-NEXT: flat_store_dword v[0:1], v36175; VI-NEXT: s_endpgm6176 %tid = call i32 @llvm.amdgcn.workitem.id.x()6177 %tid.ext = sext i32 %tid to i646178 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext6179 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext6180 %a = load volatile float, ptr addrspace(1) %a.gep6181 %sin = call float @llvm.sin.f32(float %a)6182 %fneg = fneg float %sin6183 store float %fneg, ptr addrspace(1) %out.gep6184 ret void6185}6186 6187define amdgpu_kernel void @v_fneg_amdgcn_sin_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) #0 {6188; SI-LABEL: v_fneg_amdgcn_sin_f32:6189; SI: ; %bb.0:6190; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x96191; SI-NEXT: v_lshlrev_b32_e32 v2, 2, v06192; SI-NEXT: s_waitcnt lgkmcnt(0)6193; SI-NEXT: v_mov_b32_e32 v1, s36194; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v26195; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc6196; SI-NEXT: flat_load_dword v0, v[0:1] glc6197; SI-NEXT: s_waitcnt vmcnt(0)6198; SI-NEXT: v_mov_b32_e32 v1, s16199; SI-NEXT: v_sin_f32_e64 v3, -v06200; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v26201; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc6202; SI-NEXT: flat_store_dword v[0:1], v36203; SI-NEXT: s_endpgm6204;6205; VI-LABEL: v_fneg_amdgcn_sin_f32:6206; VI: ; %bb.0:6207; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x246208; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v06209; VI-NEXT: s_waitcnt lgkmcnt(0)6210; VI-NEXT: v_mov_b32_e32 v1, s36211; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v26212; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc6213; VI-NEXT: flat_load_dword v0, v[0:1] glc6214; VI-NEXT: s_waitcnt vmcnt(0)6215; VI-NEXT: v_mov_b32_e32 v1, s16216; VI-NEXT: v_sin_f32_e64 v3, -v06217; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v26218; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc6219; VI-NEXT: flat_store_dword v[0:1], v36220; VI-NEXT: s_endpgm6221 %tid = call i32 @llvm.amdgcn.workitem.id.x()6222 %tid.ext = sext i32 %tid to i646223 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext6224 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext6225 %a = load volatile float, ptr addrspace(1) %a.gep6226 %sin = call float @llvm.amdgcn.sin.f32(float %a)6227 %fneg = fneg float %sin6228 store float %fneg, ptr addrspace(1) %out.gep6229 ret void6230}6231 6232; --------------------------------------------------------------------------------6233; ftrunc tests6234; --------------------------------------------------------------------------------6235 6236define amdgpu_kernel void @v_fneg_trunc_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) #0 {6237; SI-LABEL: v_fneg_trunc_f32:6238; SI: ; %bb.0:6239; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x96240; SI-NEXT: v_lshlrev_b32_e32 v2, 2, v06241; SI-NEXT: s_waitcnt lgkmcnt(0)6242; SI-NEXT: v_mov_b32_e32 v1, s36243; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v26244; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc6245; SI-NEXT: flat_load_dword v3, v[0:1] glc6246; SI-NEXT: s_waitcnt vmcnt(0)6247; SI-NEXT: v_mov_b32_e32 v1, s16248; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v26249; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc6250; SI-NEXT: v_trunc_f32_e64 v2, -v36251; SI-NEXT: flat_store_dword v[0:1], v26252; SI-NEXT: s_endpgm6253;6254; VI-LABEL: v_fneg_trunc_f32:6255; VI: ; %bb.0:6256; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x246257; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v06258; VI-NEXT: s_waitcnt lgkmcnt(0)6259; VI-NEXT: v_mov_b32_e32 v1, s36260; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v26261; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc6262; VI-NEXT: flat_load_dword v3, v[0:1] glc6263; VI-NEXT: s_waitcnt vmcnt(0)6264; VI-NEXT: v_mov_b32_e32 v1, s16265; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v26266; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc6267; VI-NEXT: v_trunc_f32_e64 v2, -v36268; VI-NEXT: flat_store_dword v[0:1], v26269; VI-NEXT: s_endpgm6270 %tid = call i32 @llvm.amdgcn.workitem.id.x()6271 %tid.ext = sext i32 %tid to i646272 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext6273 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext6274 %a = load volatile float, ptr addrspace(1) %a.gep6275 %trunc = call float @llvm.trunc.f32(float %a)6276 %fneg = fneg float %trunc6277 store float %fneg, ptr addrspace(1) %out.gep6278 ret void6279}6280 6281; --------------------------------------------------------------------------------6282; fround tests6283; --------------------------------------------------------------------------------6284 6285define amdgpu_kernel void @v_fneg_round_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) #0 {6286; SI-SAFE-LABEL: v_fneg_round_f32:6287; SI-SAFE: ; %bb.0:6288; SI-SAFE-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x96289; SI-SAFE-NEXT: v_lshlrev_b32_e32 v2, 2, v06290; SI-SAFE-NEXT: s_waitcnt lgkmcnt(0)6291; SI-SAFE-NEXT: v_mov_b32_e32 v1, s36292; SI-SAFE-NEXT: v_add_i32_e32 v0, vcc, s2, v26293; SI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc6294; SI-SAFE-NEXT: flat_load_dword v3, v[0:1] glc6295; SI-SAFE-NEXT: s_waitcnt vmcnt(0)6296; SI-SAFE-NEXT: v_add_i32_e32 v0, vcc, s0, v26297; SI-SAFE-NEXT: v_mov_b32_e32 v1, s16298; SI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc6299; SI-SAFE-NEXT: v_trunc_f32_e32 v2, v36300; SI-SAFE-NEXT: v_sub_f32_e32 v4, v3, v26301; SI-SAFE-NEXT: v_cmp_ge_f32_e64 s[0:1], |v4|, 0.56302; SI-SAFE-NEXT: v_cndmask_b32_e64 v4, 0, 1.0, s[0:1]6303; SI-SAFE-NEXT: s_brev_b32 s0, -26304; SI-SAFE-NEXT: v_bfi_b32 v3, s0, v4, v36305; SI-SAFE-NEXT: v_add_f32_e32 v2, v2, v36306; SI-SAFE-NEXT: v_xor_b32_e32 v2, 0x80000000, v26307; SI-SAFE-NEXT: flat_store_dword v[0:1], v26308; SI-SAFE-NEXT: s_endpgm6309;6310; SI-NSZ-LABEL: v_fneg_round_f32:6311; SI-NSZ: ; %bb.0:6312; SI-NSZ-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x96313; SI-NSZ-NEXT: v_lshlrev_b32_e32 v2, 2, v06314; SI-NSZ-NEXT: s_waitcnt lgkmcnt(0)6315; SI-NSZ-NEXT: v_mov_b32_e32 v1, s36316; SI-NSZ-NEXT: v_add_i32_e32 v0, vcc, s2, v26317; SI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc6318; SI-NSZ-NEXT: flat_load_dword v3, v[0:1] glc6319; SI-NSZ-NEXT: s_waitcnt vmcnt(0)6320; SI-NSZ-NEXT: v_add_i32_e32 v0, vcc, s0, v26321; SI-NSZ-NEXT: v_mov_b32_e32 v1, s16322; SI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc6323; SI-NSZ-NEXT: v_trunc_f32_e32 v2, v36324; SI-NSZ-NEXT: v_sub_f32_e32 v4, v3, v26325; SI-NSZ-NEXT: v_cmp_ge_f32_e64 s[0:1], |v4|, 0.56326; SI-NSZ-NEXT: v_cndmask_b32_e64 v4, 0, 1.0, s[0:1]6327; SI-NSZ-NEXT: s_brev_b32 s0, -26328; SI-NSZ-NEXT: v_bfi_b32 v3, s0, v4, v36329; SI-NSZ-NEXT: v_sub_f32_e64 v2, -v2, v36330; SI-NSZ-NEXT: flat_store_dword v[0:1], v26331; SI-NSZ-NEXT: s_endpgm6332;6333; VI-SAFE-LABEL: v_fneg_round_f32:6334; VI-SAFE: ; %bb.0:6335; VI-SAFE-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x246336; VI-SAFE-NEXT: v_lshlrev_b32_e32 v2, 2, v06337; VI-SAFE-NEXT: s_waitcnt lgkmcnt(0)6338; VI-SAFE-NEXT: v_mov_b32_e32 v1, s36339; VI-SAFE-NEXT: v_add_u32_e32 v0, vcc, s2, v26340; VI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc6341; VI-SAFE-NEXT: flat_load_dword v3, v[0:1] glc6342; VI-SAFE-NEXT: s_waitcnt vmcnt(0)6343; VI-SAFE-NEXT: v_add_u32_e32 v0, vcc, s0, v26344; VI-SAFE-NEXT: v_mov_b32_e32 v1, s16345; VI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc6346; VI-SAFE-NEXT: v_trunc_f32_e32 v2, v36347; VI-SAFE-NEXT: v_sub_f32_e32 v4, v3, v26348; VI-SAFE-NEXT: v_cmp_ge_f32_e64 s[0:1], |v4|, 0.56349; VI-SAFE-NEXT: v_cndmask_b32_e64 v4, 0, 1.0, s[0:1]6350; VI-SAFE-NEXT: s_brev_b32 s0, -26351; VI-SAFE-NEXT: v_bfi_b32 v3, s0, v4, v36352; VI-SAFE-NEXT: v_add_f32_e32 v2, v2, v36353; VI-SAFE-NEXT: v_xor_b32_e32 v2, 0x80000000, v26354; VI-SAFE-NEXT: flat_store_dword v[0:1], v26355; VI-SAFE-NEXT: s_endpgm6356;6357; VI-NSZ-LABEL: v_fneg_round_f32:6358; VI-NSZ: ; %bb.0:6359; VI-NSZ-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x246360; VI-NSZ-NEXT: v_lshlrev_b32_e32 v2, 2, v06361; VI-NSZ-NEXT: s_waitcnt lgkmcnt(0)6362; VI-NSZ-NEXT: v_mov_b32_e32 v1, s36363; VI-NSZ-NEXT: v_add_u32_e32 v0, vcc, s2, v26364; VI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc6365; VI-NSZ-NEXT: flat_load_dword v3, v[0:1] glc6366; VI-NSZ-NEXT: s_waitcnt vmcnt(0)6367; VI-NSZ-NEXT: v_add_u32_e32 v0, vcc, s0, v26368; VI-NSZ-NEXT: v_mov_b32_e32 v1, s16369; VI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc6370; VI-NSZ-NEXT: v_trunc_f32_e32 v2, v36371; VI-NSZ-NEXT: v_sub_f32_e32 v4, v3, v26372; VI-NSZ-NEXT: v_cmp_ge_f32_e64 s[0:1], |v4|, 0.56373; VI-NSZ-NEXT: v_cndmask_b32_e64 v4, 0, 1.0, s[0:1]6374; VI-NSZ-NEXT: s_brev_b32 s0, -26375; VI-NSZ-NEXT: v_bfi_b32 v3, s0, v4, v36376; VI-NSZ-NEXT: v_sub_f32_e64 v2, -v2, v36377; VI-NSZ-NEXT: flat_store_dword v[0:1], v26378; VI-NSZ-NEXT: s_endpgm6379 %tid = call i32 @llvm.amdgcn.workitem.id.x()6380 %tid.ext = sext i32 %tid to i646381 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext6382 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext6383 %a = load volatile float, ptr addrspace(1) %a.gep6384 %round = call float @llvm.round.f32(float %a)6385 %fneg = fneg float %round6386 store float %fneg, ptr addrspace(1) %out.gep6387 ret void6388}6389 6390; --------------------------------------------------------------------------------6391; rint tests6392; --------------------------------------------------------------------------------6393 6394define amdgpu_kernel void @v_fneg_rint_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) #0 {6395; SI-LABEL: v_fneg_rint_f32:6396; SI: ; %bb.0:6397; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x96398; SI-NEXT: v_lshlrev_b32_e32 v2, 2, v06399; SI-NEXT: s_waitcnt lgkmcnt(0)6400; SI-NEXT: v_mov_b32_e32 v1, s36401; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v26402; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc6403; SI-NEXT: flat_load_dword v3, v[0:1] glc6404; SI-NEXT: s_waitcnt vmcnt(0)6405; SI-NEXT: v_mov_b32_e32 v1, s16406; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v26407; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc6408; SI-NEXT: v_rndne_f32_e64 v2, -v36409; SI-NEXT: flat_store_dword v[0:1], v26410; SI-NEXT: s_endpgm6411;6412; VI-LABEL: v_fneg_rint_f32:6413; VI: ; %bb.0:6414; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x246415; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v06416; VI-NEXT: s_waitcnt lgkmcnt(0)6417; VI-NEXT: v_mov_b32_e32 v1, s36418; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v26419; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc6420; VI-NEXT: flat_load_dword v3, v[0:1] glc6421; VI-NEXT: s_waitcnt vmcnt(0)6422; VI-NEXT: v_mov_b32_e32 v1, s16423; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v26424; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc6425; VI-NEXT: v_rndne_f32_e64 v2, -v36426; VI-NEXT: flat_store_dword v[0:1], v26427; VI-NEXT: s_endpgm6428 %tid = call i32 @llvm.amdgcn.workitem.id.x()6429 %tid.ext = sext i32 %tid to i646430 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext6431 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext6432 %a = load volatile float, ptr addrspace(1) %a.gep6433 %rint = call float @llvm.rint.f32(float %a)6434 %fneg = fneg float %rint6435 store float %fneg, ptr addrspace(1) %out.gep6436 ret void6437}6438 6439; --------------------------------------------------------------------------------6440; nearbyint tests6441; --------------------------------------------------------------------------------6442 6443define amdgpu_kernel void @v_fneg_nearbyint_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) #0 {6444; SI-LABEL: v_fneg_nearbyint_f32:6445; SI: ; %bb.0:6446; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x96447; SI-NEXT: v_lshlrev_b32_e32 v2, 2, v06448; SI-NEXT: s_waitcnt lgkmcnt(0)6449; SI-NEXT: v_mov_b32_e32 v1, s36450; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v26451; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc6452; SI-NEXT: flat_load_dword v3, v[0:1] glc6453; SI-NEXT: s_waitcnt vmcnt(0)6454; SI-NEXT: v_mov_b32_e32 v1, s16455; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v26456; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc6457; SI-NEXT: v_rndne_f32_e64 v2, -v36458; SI-NEXT: flat_store_dword v[0:1], v26459; SI-NEXT: s_endpgm6460;6461; VI-LABEL: v_fneg_nearbyint_f32:6462; VI: ; %bb.0:6463; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x246464; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v06465; VI-NEXT: s_waitcnt lgkmcnt(0)6466; VI-NEXT: v_mov_b32_e32 v1, s36467; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v26468; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc6469; VI-NEXT: flat_load_dword v3, v[0:1] glc6470; VI-NEXT: s_waitcnt vmcnt(0)6471; VI-NEXT: v_mov_b32_e32 v1, s16472; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v26473; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc6474; VI-NEXT: v_rndne_f32_e64 v2, -v36475; VI-NEXT: flat_store_dword v[0:1], v26476; VI-NEXT: s_endpgm6477 %tid = call i32 @llvm.amdgcn.workitem.id.x()6478 %tid.ext = sext i32 %tid to i646479 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext6480 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext6481 %a = load volatile float, ptr addrspace(1) %a.gep6482 %nearbyint = call float @llvm.nearbyint.f32(float %a)6483 %fneg = fneg float %nearbyint6484 store float %fneg, ptr addrspace(1) %out.gep6485 ret void6486}6487 6488; --------------------------------------------------------------------------------6489; fcanonicalize tests6490; --------------------------------------------------------------------------------6491 6492define amdgpu_kernel void @v_fneg_canonicalize_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) #0 {6493; SI-LABEL: v_fneg_canonicalize_f32:6494; SI: ; %bb.0:6495; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x96496; SI-NEXT: v_lshlrev_b32_e32 v2, 2, v06497; SI-NEXT: s_waitcnt lgkmcnt(0)6498; SI-NEXT: v_mov_b32_e32 v1, s36499; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v26500; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc6501; SI-NEXT: flat_load_dword v3, v[0:1] glc6502; SI-NEXT: s_waitcnt vmcnt(0)6503; SI-NEXT: v_mov_b32_e32 v1, s16504; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v26505; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc6506; SI-NEXT: v_mul_f32_e32 v2, -1.0, v36507; SI-NEXT: flat_store_dword v[0:1], v26508; SI-NEXT: s_endpgm6509;6510; VI-LABEL: v_fneg_canonicalize_f32:6511; VI: ; %bb.0:6512; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x246513; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v06514; VI-NEXT: s_waitcnt lgkmcnt(0)6515; VI-NEXT: v_mov_b32_e32 v1, s36516; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v26517; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc6518; VI-NEXT: flat_load_dword v3, v[0:1] glc6519; VI-NEXT: s_waitcnt vmcnt(0)6520; VI-NEXT: v_mov_b32_e32 v1, s16521; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v26522; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc6523; VI-NEXT: v_mul_f32_e32 v2, -1.0, v36524; VI-NEXT: flat_store_dword v[0:1], v26525; VI-NEXT: s_endpgm6526 %tid = call i32 @llvm.amdgcn.workitem.id.x()6527 %tid.ext = sext i32 %tid to i646528 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext6529 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext6530 %a = load volatile float, ptr addrspace(1) %a.gep6531 %trunc = call float @llvm.canonicalize.f32(float %a)6532 %fneg = fneg float %trunc6533 store float %fneg, ptr addrspace(1) %out.gep6534 ret void6535}6536 6537; --------------------------------------------------------------------------------6538; vintrp tests6539; --------------------------------------------------------------------------------6540 6541define amdgpu_kernel void @v_fneg_interp_p1_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {6542; SI-LABEL: v_fneg_interp_p1_f32:6543; SI: ; %bb.0:6544; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x96545; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd6546; SI-NEXT: v_lshlrev_b32_e32 v4, 2, v06547; SI-NEXT: s_mov_b32 m0, 06548; SI-NEXT: s_waitcnt lgkmcnt(0)6549; SI-NEXT: v_mov_b32_e32 v1, s36550; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v46551; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc6552; SI-NEXT: v_mov_b32_e32 v3, s56553; SI-NEXT: v_add_i32_e32 v2, vcc, s4, v46554; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc6555; SI-NEXT: flat_load_dword v5, v[0:1] glc6556; SI-NEXT: s_waitcnt vmcnt(0)6557; SI-NEXT: flat_load_dword v2, v[2:3] glc6558; SI-NEXT: s_waitcnt vmcnt(0)6559; SI-NEXT: v_mov_b32_e32 v1, s16560; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v46561; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc6562; SI-NEXT: v_mul_f32_e64 v2, v5, -v26563; SI-NEXT: v_interp_p1_f32 v3, v2, attr0.x6564; SI-NEXT: v_interp_p1_f32 v2, v2, attr0.y6565; SI-NEXT: flat_store_dword v[0:1], v36566; SI-NEXT: s_waitcnt vmcnt(0)6567; SI-NEXT: flat_store_dword v[0:1], v26568; SI-NEXT: s_waitcnt vmcnt(0)6569; SI-NEXT: s_endpgm6570;6571; VI-LABEL: v_fneg_interp_p1_f32:6572; VI: ; %bb.0:6573; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x246574; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x346575; VI-NEXT: v_lshlrev_b32_e32 v4, 2, v06576; VI-NEXT: s_mov_b32 m0, 06577; VI-NEXT: s_waitcnt lgkmcnt(0)6578; VI-NEXT: v_mov_b32_e32 v1, s36579; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v46580; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc6581; VI-NEXT: v_mov_b32_e32 v3, s56582; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v46583; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc6584; VI-NEXT: flat_load_dword v5, v[0:1] glc6585; VI-NEXT: s_waitcnt vmcnt(0)6586; VI-NEXT: flat_load_dword v2, v[2:3] glc6587; VI-NEXT: s_waitcnt vmcnt(0)6588; VI-NEXT: v_mov_b32_e32 v1, s16589; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v46590; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc6591; VI-NEXT: v_mul_f32_e64 v2, v5, -v26592; VI-NEXT: v_interp_p1_f32_e32 v3, v2, attr0.x6593; VI-NEXT: v_interp_p1_f32_e32 v2, v2, attr0.y6594; VI-NEXT: flat_store_dword v[0:1], v36595; VI-NEXT: s_waitcnt vmcnt(0)6596; VI-NEXT: flat_store_dword v[0:1], v26597; VI-NEXT: s_waitcnt vmcnt(0)6598; VI-NEXT: s_endpgm6599 %tid = call i32 @llvm.amdgcn.workitem.id.x()6600 %tid.ext = sext i32 %tid to i646601 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext6602 %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext6603 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext6604 %a = load volatile float, ptr addrspace(1) %a.gep6605 %b = load volatile float, ptr addrspace(1) %b.gep6606 %mul = fmul float %a, %b6607 %fneg = fneg float %mul6608 %intrp0 = call float @llvm.amdgcn.interp.p1(float %fneg, i32 0, i32 0, i32 0)6609 %intrp1 = call float @llvm.amdgcn.interp.p1(float %fneg, i32 1, i32 0, i32 0)6610 store volatile float %intrp0, ptr addrspace(1) %out.gep6611 store volatile float %intrp1, ptr addrspace(1) %out.gep6612 ret void6613}6614 6615define amdgpu_kernel void @v_fneg_interp_p2_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {6616; SI-LABEL: v_fneg_interp_p2_f32:6617; SI: ; %bb.0:6618; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x96619; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd6620; SI-NEXT: v_lshlrev_b32_e32 v4, 2, v06621; SI-NEXT: v_mov_b32_e32 v6, 4.06622; SI-NEXT: s_mov_b32 m0, 06623; SI-NEXT: s_waitcnt lgkmcnt(0)6624; SI-NEXT: v_mov_b32_e32 v1, s36625; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v46626; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc6627; SI-NEXT: v_mov_b32_e32 v3, s56628; SI-NEXT: v_add_i32_e32 v2, vcc, s4, v46629; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc6630; SI-NEXT: flat_load_dword v5, v[0:1] glc6631; SI-NEXT: s_waitcnt vmcnt(0)6632; SI-NEXT: flat_load_dword v2, v[2:3] glc6633; SI-NEXT: s_waitcnt vmcnt(0)6634; SI-NEXT: v_mov_b32_e32 v1, s16635; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v46636; SI-NEXT: v_mov_b32_e32 v3, 4.06637; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc6638; SI-NEXT: v_mul_f32_e64 v2, v5, -v26639; SI-NEXT: v_interp_p2_f32 v6, v2, attr0.x6640; SI-NEXT: v_interp_p2_f32 v3, v2, attr0.y6641; SI-NEXT: flat_store_dword v[0:1], v66642; SI-NEXT: s_waitcnt vmcnt(0)6643; SI-NEXT: flat_store_dword v[0:1], v36644; SI-NEXT: s_waitcnt vmcnt(0)6645; SI-NEXT: s_endpgm6646;6647; VI-LABEL: v_fneg_interp_p2_f32:6648; VI: ; %bb.0:6649; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x246650; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x346651; VI-NEXT: v_lshlrev_b32_e32 v4, 2, v06652; VI-NEXT: v_mov_b32_e32 v6, 4.06653; VI-NEXT: s_mov_b32 m0, 06654; VI-NEXT: s_waitcnt lgkmcnt(0)6655; VI-NEXT: v_mov_b32_e32 v1, s36656; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v46657; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc6658; VI-NEXT: v_mov_b32_e32 v3, s56659; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v46660; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc6661; VI-NEXT: flat_load_dword v5, v[0:1] glc6662; VI-NEXT: s_waitcnt vmcnt(0)6663; VI-NEXT: flat_load_dword v2, v[2:3] glc6664; VI-NEXT: s_waitcnt vmcnt(0)6665; VI-NEXT: v_mov_b32_e32 v1, s16666; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v46667; VI-NEXT: v_mov_b32_e32 v3, 4.06668; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc6669; VI-NEXT: v_mul_f32_e64 v2, v5, -v26670; VI-NEXT: v_interp_p2_f32_e32 v6, v2, attr0.x6671; VI-NEXT: v_interp_p2_f32_e32 v3, v2, attr0.y6672; VI-NEXT: flat_store_dword v[0:1], v66673; VI-NEXT: s_waitcnt vmcnt(0)6674; VI-NEXT: flat_store_dword v[0:1], v36675; VI-NEXT: s_waitcnt vmcnt(0)6676; VI-NEXT: s_endpgm6677 %tid = call i32 @llvm.amdgcn.workitem.id.x()6678 %tid.ext = sext i32 %tid to i646679 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext6680 %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext6681 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext6682 %a = load volatile float, ptr addrspace(1) %a.gep6683 %b = load volatile float, ptr addrspace(1) %b.gep6684 %mul = fmul float %a, %b6685 %fneg = fneg float %mul6686 %intrp0 = call float @llvm.amdgcn.interp.p2(float 4.0, float %fneg, i32 0, i32 0, i32 0)6687 %intrp1 = call float @llvm.amdgcn.interp.p2(float 4.0, float %fneg, i32 1, i32 0, i32 0)6688 store volatile float %intrp0, ptr addrspace(1) %out.gep6689 store volatile float %intrp1, ptr addrspace(1) %out.gep6690 ret void6691}6692 6693; --------------------------------------------------------------------------------6694; CopyToReg tests6695; --------------------------------------------------------------------------------6696 6697define amdgpu_kernel void @v_fneg_copytoreg_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr, ptr addrspace(1) %c.ptr, i32 %d) #0 {6698; SI-LABEL: v_fneg_copytoreg_f32:6699; SI: ; %bb.0:6700; SI-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x96701; SI-NEXT: v_lshlrev_b32_e32 v6, 2, v06702; SI-NEXT: s_load_dword s0, s[4:5], 0x116703; SI-NEXT: s_waitcnt lgkmcnt(0)6704; SI-NEXT: v_mov_b32_e32 v1, s116705; SI-NEXT: v_add_i32_e32 v0, vcc, s10, v66706; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc6707; SI-NEXT: v_mov_b32_e32 v3, s136708; SI-NEXT: v_add_i32_e32 v2, vcc, s12, v66709; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc6710; SI-NEXT: v_mov_b32_e32 v5, s156711; SI-NEXT: v_add_i32_e32 v4, vcc, s14, v66712; SI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc6713; SI-NEXT: flat_load_dword v7, v[0:1] glc6714; SI-NEXT: s_waitcnt vmcnt(0)6715; SI-NEXT: flat_load_dword v3, v[2:3] glc6716; SI-NEXT: s_waitcnt vmcnt(0)6717; SI-NEXT: flat_load_dword v2, v[4:5] glc6718; SI-NEXT: s_waitcnt vmcnt(0)6719; SI-NEXT: v_mov_b32_e32 v1, s96720; SI-NEXT: v_add_i32_e32 v0, vcc, s8, v66721; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc6722; SI-NEXT: s_cmp_lg_u32 s0, 06723; SI-NEXT: v_mul_f32_e32 v3, v7, v36724; SI-NEXT: s_cbranch_scc0 .LBB105_26725; SI-NEXT: ; %bb.1: ; %endif6726; SI-NEXT: flat_store_dword v[0:1], v36727; SI-NEXT: s_waitcnt vmcnt(0)6728; SI-NEXT: s_endpgm6729; SI-NEXT: .LBB105_2: ; %if6730; SI-NEXT: v_xor_b32_e32 v4, 0x80000000, v36731; SI-NEXT: v_mul_f32_e32 v2, v4, v26732; SI-NEXT: flat_store_dword v[0:1], v26733; SI-NEXT: s_waitcnt vmcnt(0)6734; SI-NEXT: flat_store_dword v[0:1], v36735; SI-NEXT: s_waitcnt vmcnt(0)6736; SI-NEXT: s_endpgm6737;6738; VI-LABEL: v_fneg_copytoreg_f32:6739; VI: ; %bb.0:6740; VI-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x246741; VI-NEXT: v_lshlrev_b32_e32 v6, 2, v06742; VI-NEXT: s_load_dword s0, s[4:5], 0x446743; VI-NEXT: s_waitcnt lgkmcnt(0)6744; VI-NEXT: v_mov_b32_e32 v1, s116745; VI-NEXT: v_add_u32_e32 v0, vcc, s10, v66746; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc6747; VI-NEXT: v_mov_b32_e32 v3, s136748; VI-NEXT: v_add_u32_e32 v2, vcc, s12, v66749; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc6750; VI-NEXT: v_mov_b32_e32 v5, s156751; VI-NEXT: v_add_u32_e32 v4, vcc, s14, v66752; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc6753; VI-NEXT: flat_load_dword v7, v[0:1] glc6754; VI-NEXT: s_waitcnt vmcnt(0)6755; VI-NEXT: flat_load_dword v3, v[2:3] glc6756; VI-NEXT: s_waitcnt vmcnt(0)6757; VI-NEXT: flat_load_dword v2, v[4:5] glc6758; VI-NEXT: s_waitcnt vmcnt(0)6759; VI-NEXT: v_mov_b32_e32 v1, s96760; VI-NEXT: v_add_u32_e32 v0, vcc, s8, v66761; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc6762; VI-NEXT: s_cmp_lg_u32 s0, 06763; VI-NEXT: v_mul_f32_e32 v3, v7, v36764; VI-NEXT: s_cbranch_scc0 .LBB105_26765; VI-NEXT: ; %bb.1: ; %endif6766; VI-NEXT: flat_store_dword v[0:1], v36767; VI-NEXT: s_waitcnt vmcnt(0)6768; VI-NEXT: s_endpgm6769; VI-NEXT: .LBB105_2: ; %if6770; VI-NEXT: v_xor_b32_e32 v4, 0x80000000, v36771; VI-NEXT: v_mul_f32_e32 v2, v4, v26772; VI-NEXT: flat_store_dword v[0:1], v26773; VI-NEXT: s_waitcnt vmcnt(0)6774; VI-NEXT: flat_store_dword v[0:1], v36775; VI-NEXT: s_waitcnt vmcnt(0)6776; VI-NEXT: s_endpgm6777 %tid = call i32 @llvm.amdgcn.workitem.id.x()6778 %tid.ext = sext i32 %tid to i646779 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext6780 %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext6781 %c.gep = getelementptr inbounds float, ptr addrspace(1) %c.ptr, i64 %tid.ext6782 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext6783 %a = load volatile float, ptr addrspace(1) %a.gep6784 %b = load volatile float, ptr addrspace(1) %b.gep6785 %c = load volatile float, ptr addrspace(1) %c.gep6786 %mul = fmul float %a, %b6787 %fneg = fneg float %mul6788 %cmp0 = icmp eq i32 %d, 06789 br i1 %cmp0, label %if, label %endif6790 6791if:6792 %mul1 = fmul float %fneg, %c6793 store volatile float %mul1, ptr addrspace(1) %out.gep6794 br label %endif6795 6796endif:6797 store volatile float %mul, ptr addrspace(1) %out.gep6798 ret void6799}6800 6801; --------------------------------------------------------------------------------6802; inlineasm tests6803; --------------------------------------------------------------------------------6804 6805; Can't fold into use, so should fold into source6806define amdgpu_kernel void @v_fneg_inlineasm_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr, ptr addrspace(1) %c.ptr, i32 %d) #0 {6807; SI-LABEL: v_fneg_inlineasm_f32:6808; SI: ; %bb.0:6809; SI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x96810; SI-NEXT: v_lshlrev_b32_e32 v4, 2, v06811; SI-NEXT: s_waitcnt lgkmcnt(0)6812; SI-NEXT: v_mov_b32_e32 v1, s36813; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v46814; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc6815; SI-NEXT: v_mov_b32_e32 v3, s56816; SI-NEXT: v_add_i32_e32 v2, vcc, s4, v46817; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc6818; SI-NEXT: v_mov_b32_e32 v5, s76819; SI-NEXT: flat_load_dword v6, v[0:1] glc6820; SI-NEXT: s_waitcnt vmcnt(0)6821; SI-NEXT: flat_load_dword v2, v[2:3] glc6822; SI-NEXT: s_waitcnt vmcnt(0)6823; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v46824; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v5, vcc6825; SI-NEXT: flat_load_dword v0, v[0:1] glc6826; SI-NEXT: s_waitcnt vmcnt(0)6827; SI-NEXT: v_mov_b32_e32 v1, s16828; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v46829; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc6830; SI-NEXT: v_mul_f32_e64 v2, v6, -v26831; SI-NEXT: ;;#ASMSTART6832; SI-NEXT: ; use v26833; SI-NEXT: ;;#ASMEND6834; SI-NEXT: flat_store_dword v[0:1], v26835; SI-NEXT: s_waitcnt vmcnt(0)6836; SI-NEXT: s_endpgm6837;6838; VI-LABEL: v_fneg_inlineasm_f32:6839; VI: ; %bb.0:6840; VI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x246841; VI-NEXT: v_lshlrev_b32_e32 v4, 2, v06842; VI-NEXT: s_waitcnt lgkmcnt(0)6843; VI-NEXT: v_mov_b32_e32 v1, s36844; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v46845; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc6846; VI-NEXT: v_mov_b32_e32 v3, s56847; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v46848; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc6849; VI-NEXT: v_mov_b32_e32 v5, s76850; VI-NEXT: flat_load_dword v6, v[0:1] glc6851; VI-NEXT: s_waitcnt vmcnt(0)6852; VI-NEXT: flat_load_dword v2, v[2:3] glc6853; VI-NEXT: s_waitcnt vmcnt(0)6854; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v46855; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v5, vcc6856; VI-NEXT: flat_load_dword v0, v[0:1] glc6857; VI-NEXT: s_waitcnt vmcnt(0)6858; VI-NEXT: v_mov_b32_e32 v1, s16859; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v46860; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc6861; VI-NEXT: v_mul_f32_e64 v2, v6, -v26862; VI-NEXT: ;;#ASMSTART6863; VI-NEXT: ; use v26864; VI-NEXT: ;;#ASMEND6865; VI-NEXT: flat_store_dword v[0:1], v26866; VI-NEXT: s_waitcnt vmcnt(0)6867; VI-NEXT: s_endpgm6868 %tid = call i32 @llvm.amdgcn.workitem.id.x()6869 %tid.ext = sext i32 %tid to i646870 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext6871 %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext6872 %c.gep = getelementptr inbounds float, ptr addrspace(1) %c.ptr, i64 %tid.ext6873 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext6874 %a = load volatile float, ptr addrspace(1) %a.gep6875 %b = load volatile float, ptr addrspace(1) %b.gep6876 %c = load volatile float, ptr addrspace(1) %c.gep6877 %mul = fmul float %a, %b6878 %fneg = fneg float %mul6879 call void asm sideeffect "; use $0", "v"(float %fneg) #06880 store volatile float %fneg, ptr addrspace(1) %out.gep6881 ret void6882}6883 6884; --------------------------------------------------------------------------------6885; inlineasm tests6886; --------------------------------------------------------------------------------6887 6888; Can't fold into use, so should fold into source6889define amdgpu_kernel void @v_fneg_inlineasm_multi_use_src_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr, ptr addrspace(1) %c.ptr, i32 %d) #0 {6890; SI-LABEL: v_fneg_inlineasm_multi_use_src_f32:6891; SI: ; %bb.0:6892; SI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x96893; SI-NEXT: v_lshlrev_b32_e32 v4, 2, v06894; SI-NEXT: s_waitcnt lgkmcnt(0)6895; SI-NEXT: v_mov_b32_e32 v1, s36896; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v46897; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc6898; SI-NEXT: v_mov_b32_e32 v3, s56899; SI-NEXT: v_add_i32_e32 v2, vcc, s4, v46900; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc6901; SI-NEXT: v_mov_b32_e32 v5, s76902; SI-NEXT: flat_load_dword v6, v[0:1] glc6903; SI-NEXT: s_waitcnt vmcnt(0)6904; SI-NEXT: flat_load_dword v2, v[2:3] glc6905; SI-NEXT: s_waitcnt vmcnt(0)6906; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v46907; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v5, vcc6908; SI-NEXT: flat_load_dword v0, v[0:1] glc6909; SI-NEXT: s_waitcnt vmcnt(0)6910; SI-NEXT: v_mov_b32_e32 v1, s16911; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v46912; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc6913; SI-NEXT: v_mul_f32_e32 v2, v6, v26914; SI-NEXT: v_xor_b32_e32 v3, 0x80000000, v26915; SI-NEXT: ;;#ASMSTART6916; SI-NEXT: ; use v36917; SI-NEXT: ;;#ASMEND6918; SI-NEXT: flat_store_dword v[0:1], v26919; SI-NEXT: s_waitcnt vmcnt(0)6920; SI-NEXT: s_endpgm6921;6922; VI-LABEL: v_fneg_inlineasm_multi_use_src_f32:6923; VI: ; %bb.0:6924; VI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x246925; VI-NEXT: v_lshlrev_b32_e32 v4, 2, v06926; VI-NEXT: s_waitcnt lgkmcnt(0)6927; VI-NEXT: v_mov_b32_e32 v1, s36928; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v46929; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc6930; VI-NEXT: v_mov_b32_e32 v3, s56931; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v46932; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc6933; VI-NEXT: v_mov_b32_e32 v5, s76934; VI-NEXT: flat_load_dword v6, v[0:1] glc6935; VI-NEXT: s_waitcnt vmcnt(0)6936; VI-NEXT: flat_load_dword v2, v[2:3] glc6937; VI-NEXT: s_waitcnt vmcnt(0)6938; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v46939; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v5, vcc6940; VI-NEXT: flat_load_dword v0, v[0:1] glc6941; VI-NEXT: s_waitcnt vmcnt(0)6942; VI-NEXT: v_mov_b32_e32 v1, s16943; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v46944; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc6945; VI-NEXT: v_mul_f32_e32 v2, v6, v26946; VI-NEXT: v_xor_b32_e32 v3, 0x80000000, v26947; VI-NEXT: ;;#ASMSTART6948; VI-NEXT: ; use v36949; VI-NEXT: ;;#ASMEND6950; VI-NEXT: flat_store_dword v[0:1], v26951; VI-NEXT: s_waitcnt vmcnt(0)6952; VI-NEXT: s_endpgm6953 %tid = call i32 @llvm.amdgcn.workitem.id.x()6954 %tid.ext = sext i32 %tid to i646955 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext6956 %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext6957 %c.gep = getelementptr inbounds float, ptr addrspace(1) %c.ptr, i64 %tid.ext6958 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext6959 %a = load volatile float, ptr addrspace(1) %a.gep6960 %b = load volatile float, ptr addrspace(1) %b.gep6961 %c = load volatile float, ptr addrspace(1) %c.gep6962 %mul = fmul float %a, %b6963 %fneg = fneg float %mul6964 call void asm sideeffect "; use $0", "v"(float %fneg) #06965 store volatile float %mul, ptr addrspace(1) %out.gep6966 ret void6967}6968 6969; --------------------------------------------------------------------------------6970; code size regression tests6971; --------------------------------------------------------------------------------6972 6973; There are multiple users of the fneg that must use a VOP36974; instruction, so there is no penalty6975define amdgpu_kernel void @multiuse_fneg_2_vop3_users_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr, ptr addrspace(1) %c.ptr) #0 {6976; SI-LABEL: multiuse_fneg_2_vop3_users_f32:6977; SI: ; %bb.0:6978; SI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x96979; SI-NEXT: v_lshlrev_b32_e32 v4, 2, v06980; SI-NEXT: s_waitcnt lgkmcnt(0)6981; SI-NEXT: v_mov_b32_e32 v1, s36982; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v46983; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc6984; SI-NEXT: v_mov_b32_e32 v3, s56985; SI-NEXT: v_add_i32_e32 v2, vcc, s4, v46986; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc6987; SI-NEXT: v_mov_b32_e32 v5, s76988; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v46989; SI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc6990; SI-NEXT: flat_load_dword v6, v[0:1] glc6991; SI-NEXT: s_waitcnt vmcnt(0)6992; SI-NEXT: flat_load_dword v2, v[2:3] glc6993; SI-NEXT: s_waitcnt vmcnt(0)6994; SI-NEXT: flat_load_dword v3, v[4:5] glc6995; SI-NEXT: s_waitcnt vmcnt(0)6996; SI-NEXT: v_mov_b32_e32 v0, s06997; SI-NEXT: v_mov_b32_e32 v1, s16998; SI-NEXT: v_fma_f32 v2, -v6, v2, v36999; SI-NEXT: v_fma_f32 v3, -v6, v3, 2.07000; SI-NEXT: flat_store_dword v[0:1], v27001; SI-NEXT: s_waitcnt vmcnt(0)7002; SI-NEXT: flat_store_dword v[0:1], v37003; SI-NEXT: s_waitcnt vmcnt(0)7004; SI-NEXT: s_endpgm7005;7006; VI-LABEL: multiuse_fneg_2_vop3_users_f32:7007; VI: ; %bb.0:7008; VI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x247009; VI-NEXT: v_lshlrev_b32_e32 v4, 2, v07010; VI-NEXT: s_waitcnt lgkmcnt(0)7011; VI-NEXT: v_mov_b32_e32 v1, s37012; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v47013; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc7014; VI-NEXT: v_mov_b32_e32 v3, s57015; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v47016; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc7017; VI-NEXT: v_mov_b32_e32 v5, s77018; VI-NEXT: v_add_u32_e32 v4, vcc, s6, v47019; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc7020; VI-NEXT: flat_load_dword v6, v[0:1] glc7021; VI-NEXT: s_waitcnt vmcnt(0)7022; VI-NEXT: flat_load_dword v2, v[2:3] glc7023; VI-NEXT: s_waitcnt vmcnt(0)7024; VI-NEXT: flat_load_dword v3, v[4:5] glc7025; VI-NEXT: s_waitcnt vmcnt(0)7026; VI-NEXT: v_mov_b32_e32 v0, s07027; VI-NEXT: v_mov_b32_e32 v1, s17028; VI-NEXT: v_fma_f32 v2, -v6, v2, v37029; VI-NEXT: v_fma_f32 v3, -v6, v3, 2.07030; VI-NEXT: flat_store_dword v[0:1], v27031; VI-NEXT: s_waitcnt vmcnt(0)7032; VI-NEXT: flat_store_dword v[0:1], v37033; VI-NEXT: s_waitcnt vmcnt(0)7034; VI-NEXT: s_endpgm7035 %tid = call i32 @llvm.amdgcn.workitem.id.x()7036 %tid.ext = sext i32 %tid to i647037 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext7038 %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext7039 %c.gep = getelementptr inbounds float, ptr addrspace(1) %c.ptr, i64 %tid.ext7040 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext7041 %a = load volatile float, ptr addrspace(1) %a.gep7042 %b = load volatile float, ptr addrspace(1) %b.gep7043 %c = load volatile float, ptr addrspace(1) %c.gep7044 7045 %fneg.a = fneg float %a7046 %fma0 = call float @llvm.fma.f32(float %fneg.a, float %b, float %c)7047 %fma1 = call float @llvm.fma.f32(float %fneg.a, float %c, float 2.0)7048 7049 store volatile float %fma0, ptr addrspace(1) %out7050 store volatile float %fma1, ptr addrspace(1) %out7051 ret void7052}7053 7054; There are multiple users, but both require using a larger encoding7055; for the modifier.7056define amdgpu_kernel void @multiuse_fneg_2_vop2_users_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr, ptr addrspace(1) %c.ptr) #0 {7057; SI-LABEL: multiuse_fneg_2_vop2_users_f32:7058; SI: ; %bb.0:7059; SI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x97060; SI-NEXT: v_lshlrev_b32_e32 v4, 2, v07061; SI-NEXT: s_waitcnt lgkmcnt(0)7062; SI-NEXT: v_mov_b32_e32 v1, s37063; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v47064; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc7065; SI-NEXT: v_mov_b32_e32 v3, s57066; SI-NEXT: v_add_i32_e32 v2, vcc, s4, v47067; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc7068; SI-NEXT: v_mov_b32_e32 v5, s77069; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v47070; SI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc7071; SI-NEXT: flat_load_dword v6, v[0:1] glc7072; SI-NEXT: s_waitcnt vmcnt(0)7073; SI-NEXT: flat_load_dword v2, v[2:3] glc7074; SI-NEXT: s_waitcnt vmcnt(0)7075; SI-NEXT: flat_load_dword v3, v[4:5] glc7076; SI-NEXT: s_waitcnt vmcnt(0)7077; SI-NEXT: v_mov_b32_e32 v0, s07078; SI-NEXT: v_mov_b32_e32 v1, s17079; SI-NEXT: v_mul_f32_e64 v2, -v6, v27080; SI-NEXT: v_mul_f32_e64 v3, -v6, v37081; SI-NEXT: flat_store_dword v[0:1], v27082; SI-NEXT: s_waitcnt vmcnt(0)7083; SI-NEXT: flat_store_dword v[0:1], v37084; SI-NEXT: s_waitcnt vmcnt(0)7085; SI-NEXT: s_endpgm7086;7087; VI-LABEL: multiuse_fneg_2_vop2_users_f32:7088; VI: ; %bb.0:7089; VI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x247090; VI-NEXT: v_lshlrev_b32_e32 v4, 2, v07091; VI-NEXT: s_waitcnt lgkmcnt(0)7092; VI-NEXT: v_mov_b32_e32 v1, s37093; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v47094; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc7095; VI-NEXT: v_mov_b32_e32 v3, s57096; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v47097; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc7098; VI-NEXT: v_mov_b32_e32 v5, s77099; VI-NEXT: v_add_u32_e32 v4, vcc, s6, v47100; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc7101; VI-NEXT: flat_load_dword v6, v[0:1] glc7102; VI-NEXT: s_waitcnt vmcnt(0)7103; VI-NEXT: flat_load_dword v2, v[2:3] glc7104; VI-NEXT: s_waitcnt vmcnt(0)7105; VI-NEXT: flat_load_dword v3, v[4:5] glc7106; VI-NEXT: s_waitcnt vmcnt(0)7107; VI-NEXT: v_mov_b32_e32 v0, s07108; VI-NEXT: v_mov_b32_e32 v1, s17109; VI-NEXT: v_mul_f32_e64 v2, -v6, v27110; VI-NEXT: v_mul_f32_e64 v3, -v6, v37111; VI-NEXT: flat_store_dword v[0:1], v27112; VI-NEXT: s_waitcnt vmcnt(0)7113; VI-NEXT: flat_store_dword v[0:1], v37114; VI-NEXT: s_waitcnt vmcnt(0)7115; VI-NEXT: s_endpgm7116 %tid = call i32 @llvm.amdgcn.workitem.id.x()7117 %tid.ext = sext i32 %tid to i647118 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext7119 %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext7120 %c.gep = getelementptr inbounds float, ptr addrspace(1) %c.ptr, i64 %tid.ext7121 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext7122 %a = load volatile float, ptr addrspace(1) %a.gep7123 %b = load volatile float, ptr addrspace(1) %b.gep7124 %c = load volatile float, ptr addrspace(1) %c.gep7125 7126 %fneg.a = fneg float %a7127 %mul0 = fmul float %fneg.a, %b7128 %mul1 = fmul float %fneg.a, %c7129 7130 store volatile float %mul0, ptr addrspace(1) %out7131 store volatile float %mul1, ptr addrspace(1) %out7132 ret void7133}7134 7135; One user is VOP3 so has no cost to folding the modifier, the other does.7136define amdgpu_kernel void @multiuse_fneg_vop2_vop3_users_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr, ptr addrspace(1) %c.ptr) #0 {7137; SI-LABEL: multiuse_fneg_vop2_vop3_users_f32:7138; SI: ; %bb.0:7139; SI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x97140; SI-NEXT: v_lshlrev_b32_e32 v4, 2, v07141; SI-NEXT: s_waitcnt lgkmcnt(0)7142; SI-NEXT: v_mov_b32_e32 v1, s37143; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v47144; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc7145; SI-NEXT: v_mov_b32_e32 v3, s57146; SI-NEXT: v_add_i32_e32 v2, vcc, s4, v47147; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc7148; SI-NEXT: v_mov_b32_e32 v5, s77149; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v47150; SI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc7151; SI-NEXT: flat_load_dword v6, v[0:1] glc7152; SI-NEXT: s_waitcnt vmcnt(0)7153; SI-NEXT: flat_load_dword v2, v[2:3] glc7154; SI-NEXT: s_waitcnt vmcnt(0)7155; SI-NEXT: flat_load_dword v3, v[4:5] glc7156; SI-NEXT: s_waitcnt vmcnt(0)7157; SI-NEXT: v_mov_b32_e32 v0, s07158; SI-NEXT: v_mov_b32_e32 v1, s17159; SI-NEXT: v_fma_f32 v2, -v6, v2, 2.07160; SI-NEXT: v_mul_f32_e64 v3, -v6, v37161; SI-NEXT: flat_store_dword v[0:1], v27162; SI-NEXT: s_waitcnt vmcnt(0)7163; SI-NEXT: flat_store_dword v[0:1], v37164; SI-NEXT: s_waitcnt vmcnt(0)7165; SI-NEXT: s_endpgm7166;7167; VI-LABEL: multiuse_fneg_vop2_vop3_users_f32:7168; VI: ; %bb.0:7169; VI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x247170; VI-NEXT: v_lshlrev_b32_e32 v4, 2, v07171; VI-NEXT: s_waitcnt lgkmcnt(0)7172; VI-NEXT: v_mov_b32_e32 v1, s37173; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v47174; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc7175; VI-NEXT: v_mov_b32_e32 v3, s57176; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v47177; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc7178; VI-NEXT: v_mov_b32_e32 v5, s77179; VI-NEXT: v_add_u32_e32 v4, vcc, s6, v47180; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc7181; VI-NEXT: flat_load_dword v6, v[0:1] glc7182; VI-NEXT: s_waitcnt vmcnt(0)7183; VI-NEXT: flat_load_dword v2, v[2:3] glc7184; VI-NEXT: s_waitcnt vmcnt(0)7185; VI-NEXT: flat_load_dword v3, v[4:5] glc7186; VI-NEXT: s_waitcnt vmcnt(0)7187; VI-NEXT: v_mov_b32_e32 v0, s07188; VI-NEXT: v_mov_b32_e32 v1, s17189; VI-NEXT: v_fma_f32 v2, -v6, v2, 2.07190; VI-NEXT: v_mul_f32_e64 v3, -v6, v37191; VI-NEXT: flat_store_dword v[0:1], v27192; VI-NEXT: s_waitcnt vmcnt(0)7193; VI-NEXT: flat_store_dword v[0:1], v37194; VI-NEXT: s_waitcnt vmcnt(0)7195; VI-NEXT: s_endpgm7196 %tid = call i32 @llvm.amdgcn.workitem.id.x()7197 %tid.ext = sext i32 %tid to i647198 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext7199 %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext7200 %c.gep = getelementptr inbounds float, ptr addrspace(1) %c.ptr, i64 %tid.ext7201 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext7202 %a = load volatile float, ptr addrspace(1) %a.gep7203 %b = load volatile float, ptr addrspace(1) %b.gep7204 %c = load volatile float, ptr addrspace(1) %c.gep7205 7206 %fneg.a = fneg float %a7207 %fma0 = call float @llvm.fma.f32(float %fneg.a, float %b, float 2.0)7208 %mul1 = fmul float %fneg.a, %c7209 7210 store volatile float %fma0, ptr addrspace(1) %out7211 store volatile float %mul1, ptr addrspace(1) %out7212 ret void7213}7214 7215; The use of the fneg requires a code size increase, but folding into7216; the source does not7217define amdgpu_kernel void @free_fold_src_code_size_cost_use_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr, ptr addrspace(1) %c.ptr, ptr addrspace(1) %d.ptr) #0 {7218; SI-SAFE-LABEL: free_fold_src_code_size_cost_use_f32:7219; SI-SAFE: ; %bb.0:7220; SI-SAFE-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x97221; SI-SAFE-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x117222; SI-SAFE-NEXT: v_lshlrev_b32_e32 v6, 2, v07223; SI-SAFE-NEXT: s_waitcnt lgkmcnt(0)7224; SI-SAFE-NEXT: v_mov_b32_e32 v1, s117225; SI-SAFE-NEXT: v_add_i32_e32 v0, vcc, s10, v67226; SI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc7227; SI-SAFE-NEXT: v_mov_b32_e32 v3, s137228; SI-SAFE-NEXT: v_add_i32_e32 v2, vcc, s12, v67229; SI-SAFE-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc7230; SI-SAFE-NEXT: v_mov_b32_e32 v5, s157231; SI-SAFE-NEXT: v_add_i32_e32 v4, vcc, s14, v67232; SI-SAFE-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc7233; SI-SAFE-NEXT: v_mov_b32_e32 v7, s17234; SI-SAFE-NEXT: v_add_i32_e32 v6, vcc, s0, v67235; SI-SAFE-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc7236; SI-SAFE-NEXT: flat_load_dword v8, v[0:1] glc7237; SI-SAFE-NEXT: s_waitcnt vmcnt(0)7238; SI-SAFE-NEXT: flat_load_dword v2, v[2:3] glc7239; SI-SAFE-NEXT: s_waitcnt vmcnt(0)7240; SI-SAFE-NEXT: flat_load_dword v3, v[4:5] glc7241; SI-SAFE-NEXT: s_waitcnt vmcnt(0)7242; SI-SAFE-NEXT: flat_load_dword v4, v[6:7] glc7243; SI-SAFE-NEXT: s_waitcnt vmcnt(0)7244; SI-SAFE-NEXT: v_mov_b32_e32 v0, s87245; SI-SAFE-NEXT: v_mov_b32_e32 v1, s97246; SI-SAFE-NEXT: v_fma_f32 v2, v8, v2, 2.07247; SI-SAFE-NEXT: v_mul_f32_e64 v3, -v2, v37248; SI-SAFE-NEXT: v_mul_f32_e64 v2, -v2, v47249; SI-SAFE-NEXT: flat_store_dword v[0:1], v37250; SI-SAFE-NEXT: s_waitcnt vmcnt(0)7251; SI-SAFE-NEXT: flat_store_dword v[0:1], v27252; SI-SAFE-NEXT: s_waitcnt vmcnt(0)7253; SI-SAFE-NEXT: s_endpgm7254;7255; SI-NSZ-LABEL: free_fold_src_code_size_cost_use_f32:7256; SI-NSZ: ; %bb.0:7257; SI-NSZ-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x97258; SI-NSZ-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x117259; SI-NSZ-NEXT: v_lshlrev_b32_e32 v6, 2, v07260; SI-NSZ-NEXT: s_waitcnt lgkmcnt(0)7261; SI-NSZ-NEXT: v_mov_b32_e32 v1, s117262; SI-NSZ-NEXT: v_add_i32_e32 v0, vcc, s10, v67263; SI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc7264; SI-NSZ-NEXT: v_mov_b32_e32 v3, s137265; SI-NSZ-NEXT: v_add_i32_e32 v2, vcc, s12, v67266; SI-NSZ-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc7267; SI-NSZ-NEXT: v_mov_b32_e32 v5, s157268; SI-NSZ-NEXT: v_add_i32_e32 v4, vcc, s14, v67269; SI-NSZ-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc7270; SI-NSZ-NEXT: v_mov_b32_e32 v7, s17271; SI-NSZ-NEXT: v_add_i32_e32 v6, vcc, s0, v67272; SI-NSZ-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc7273; SI-NSZ-NEXT: flat_load_dword v8, v[0:1] glc7274; SI-NSZ-NEXT: s_waitcnt vmcnt(0)7275; SI-NSZ-NEXT: flat_load_dword v2, v[2:3] glc7276; SI-NSZ-NEXT: s_waitcnt vmcnt(0)7277; SI-NSZ-NEXT: flat_load_dword v3, v[4:5] glc7278; SI-NSZ-NEXT: s_waitcnt vmcnt(0)7279; SI-NSZ-NEXT: flat_load_dword v4, v[6:7] glc7280; SI-NSZ-NEXT: s_waitcnt vmcnt(0)7281; SI-NSZ-NEXT: v_mov_b32_e32 v0, s87282; SI-NSZ-NEXT: v_mov_b32_e32 v1, s97283; SI-NSZ-NEXT: v_fma_f32 v2, v8, -v2, -2.07284; SI-NSZ-NEXT: v_mul_f32_e32 v3, v2, v37285; SI-NSZ-NEXT: v_mul_f32_e32 v2, v2, v47286; SI-NSZ-NEXT: flat_store_dword v[0:1], v37287; SI-NSZ-NEXT: s_waitcnt vmcnt(0)7288; SI-NSZ-NEXT: flat_store_dword v[0:1], v27289; SI-NSZ-NEXT: s_waitcnt vmcnt(0)7290; SI-NSZ-NEXT: s_endpgm7291;7292; VI-SAFE-LABEL: free_fold_src_code_size_cost_use_f32:7293; VI-SAFE: ; %bb.0:7294; VI-SAFE-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x247295; VI-SAFE-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x447296; VI-SAFE-NEXT: v_lshlrev_b32_e32 v6, 2, v07297; VI-SAFE-NEXT: s_waitcnt lgkmcnt(0)7298; VI-SAFE-NEXT: v_mov_b32_e32 v1, s117299; VI-SAFE-NEXT: v_add_u32_e32 v0, vcc, s10, v67300; VI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc7301; VI-SAFE-NEXT: v_mov_b32_e32 v3, s137302; VI-SAFE-NEXT: v_add_u32_e32 v2, vcc, s12, v67303; VI-SAFE-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc7304; VI-SAFE-NEXT: v_mov_b32_e32 v5, s157305; VI-SAFE-NEXT: v_add_u32_e32 v4, vcc, s14, v67306; VI-SAFE-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc7307; VI-SAFE-NEXT: v_mov_b32_e32 v7, s17308; VI-SAFE-NEXT: v_add_u32_e32 v6, vcc, s0, v67309; VI-SAFE-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc7310; VI-SAFE-NEXT: flat_load_dword v8, v[0:1] glc7311; VI-SAFE-NEXT: s_waitcnt vmcnt(0)7312; VI-SAFE-NEXT: flat_load_dword v2, v[2:3] glc7313; VI-SAFE-NEXT: s_waitcnt vmcnt(0)7314; VI-SAFE-NEXT: flat_load_dword v3, v[4:5] glc7315; VI-SAFE-NEXT: s_waitcnt vmcnt(0)7316; VI-SAFE-NEXT: flat_load_dword v4, v[6:7] glc7317; VI-SAFE-NEXT: s_waitcnt vmcnt(0)7318; VI-SAFE-NEXT: v_mov_b32_e32 v0, s87319; VI-SAFE-NEXT: v_mov_b32_e32 v1, s97320; VI-SAFE-NEXT: v_fma_f32 v2, v8, v2, 2.07321; VI-SAFE-NEXT: v_mul_f32_e64 v3, -v2, v37322; VI-SAFE-NEXT: v_mul_f32_e64 v2, -v2, v47323; VI-SAFE-NEXT: flat_store_dword v[0:1], v37324; VI-SAFE-NEXT: s_waitcnt vmcnt(0)7325; VI-SAFE-NEXT: flat_store_dword v[0:1], v27326; VI-SAFE-NEXT: s_waitcnt vmcnt(0)7327; VI-SAFE-NEXT: s_endpgm7328;7329; VI-NSZ-LABEL: free_fold_src_code_size_cost_use_f32:7330; VI-NSZ: ; %bb.0:7331; VI-NSZ-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x247332; VI-NSZ-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x447333; VI-NSZ-NEXT: v_lshlrev_b32_e32 v6, 2, v07334; VI-NSZ-NEXT: s_waitcnt lgkmcnt(0)7335; VI-NSZ-NEXT: v_mov_b32_e32 v1, s117336; VI-NSZ-NEXT: v_add_u32_e32 v0, vcc, s10, v67337; VI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc7338; VI-NSZ-NEXT: v_mov_b32_e32 v3, s137339; VI-NSZ-NEXT: v_add_u32_e32 v2, vcc, s12, v67340; VI-NSZ-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc7341; VI-NSZ-NEXT: v_mov_b32_e32 v5, s157342; VI-NSZ-NEXT: v_add_u32_e32 v4, vcc, s14, v67343; VI-NSZ-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc7344; VI-NSZ-NEXT: v_mov_b32_e32 v7, s17345; VI-NSZ-NEXT: v_add_u32_e32 v6, vcc, s0, v67346; VI-NSZ-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc7347; VI-NSZ-NEXT: flat_load_dword v8, v[0:1] glc7348; VI-NSZ-NEXT: s_waitcnt vmcnt(0)7349; VI-NSZ-NEXT: flat_load_dword v2, v[2:3] glc7350; VI-NSZ-NEXT: s_waitcnt vmcnt(0)7351; VI-NSZ-NEXT: flat_load_dword v3, v[4:5] glc7352; VI-NSZ-NEXT: s_waitcnt vmcnt(0)7353; VI-NSZ-NEXT: flat_load_dword v4, v[6:7] glc7354; VI-NSZ-NEXT: s_waitcnt vmcnt(0)7355; VI-NSZ-NEXT: v_mov_b32_e32 v0, s87356; VI-NSZ-NEXT: v_mov_b32_e32 v1, s97357; VI-NSZ-NEXT: v_fma_f32 v2, v8, -v2, -2.07358; VI-NSZ-NEXT: v_mul_f32_e32 v3, v2, v37359; VI-NSZ-NEXT: v_mul_f32_e32 v2, v2, v47360; VI-NSZ-NEXT: flat_store_dword v[0:1], v37361; VI-NSZ-NEXT: s_waitcnt vmcnt(0)7362; VI-NSZ-NEXT: flat_store_dword v[0:1], v27363; VI-NSZ-NEXT: s_waitcnt vmcnt(0)7364; VI-NSZ-NEXT: s_endpgm7365 %tid = call i32 @llvm.amdgcn.workitem.id.x()7366 %tid.ext = sext i32 %tid to i647367 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext7368 %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext7369 %c.gep = getelementptr inbounds float, ptr addrspace(1) %c.ptr, i64 %tid.ext7370 %d.gep = getelementptr inbounds float, ptr addrspace(1) %d.ptr, i64 %tid.ext7371 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext7372 %a = load volatile float, ptr addrspace(1) %a.gep7373 %b = load volatile float, ptr addrspace(1) %b.gep7374 %c = load volatile float, ptr addrspace(1) %c.gep7375 %d = load volatile float, ptr addrspace(1) %d.gep7376 7377 %fma0 = call float @llvm.fma.f32(float %a, float %b, float 2.0)7378 %fneg.fma0 = fneg float %fma07379 %mul1 = fmul float %fneg.fma0, %c7380 %mul2 = fmul float %fneg.fma0, %d7381 7382 store volatile float %mul1, ptr addrspace(1) %out7383 store volatile float %mul2, ptr addrspace(1) %out7384 ret void7385}7386 7387define amdgpu_kernel void @free_fold_src_code_size_cost_use_f64(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr, ptr addrspace(1) %c.ptr, ptr addrspace(1) %d.ptr) #0 {7388; SI-LABEL: free_fold_src_code_size_cost_use_f64:7389; SI: ; %bb.0:7390; SI-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x97391; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x117392; SI-NEXT: v_lshlrev_b32_e32 v6, 3, v07393; SI-NEXT: s_waitcnt lgkmcnt(0)7394; SI-NEXT: v_mov_b32_e32 v1, s117395; SI-NEXT: v_add_i32_e32 v0, vcc, s10, v67396; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc7397; SI-NEXT: v_mov_b32_e32 v3, s137398; SI-NEXT: v_add_i32_e32 v2, vcc, s12, v67399; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc7400; SI-NEXT: v_mov_b32_e32 v5, s157401; SI-NEXT: v_add_i32_e32 v4, vcc, s14, v67402; SI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc7403; SI-NEXT: flat_load_dwordx2 v[0:1], v[0:1] glc7404; SI-NEXT: s_waitcnt vmcnt(0)7405; SI-NEXT: flat_load_dwordx2 v[2:3], v[2:3] glc7406; SI-NEXT: s_waitcnt vmcnt(0)7407; SI-NEXT: v_mov_b32_e32 v7, s17408; SI-NEXT: v_add_i32_e32 v6, vcc, s0, v67409; SI-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc7410; SI-NEXT: flat_load_dwordx2 v[4:5], v[4:5] glc7411; SI-NEXT: s_waitcnt vmcnt(0)7412; SI-NEXT: flat_load_dwordx2 v[6:7], v[6:7] glc7413; SI-NEXT: s_waitcnt vmcnt(0)7414; SI-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], 2.07415; SI-NEXT: v_mov_b32_e32 v2, s87416; SI-NEXT: v_mov_b32_e32 v3, s97417; SI-NEXT: v_mul_f64 v[4:5], -v[0:1], v[4:5]7418; SI-NEXT: v_mul_f64 v[0:1], -v[0:1], v[6:7]7419; SI-NEXT: flat_store_dwordx2 v[2:3], v[4:5]7420; SI-NEXT: s_waitcnt vmcnt(0)7421; SI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]7422; SI-NEXT: s_waitcnt vmcnt(0)7423; SI-NEXT: s_endpgm7424;7425; VI-LABEL: free_fold_src_code_size_cost_use_f64:7426; VI: ; %bb.0:7427; VI-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x247428; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x447429; VI-NEXT: v_lshlrev_b32_e32 v6, 3, v07430; VI-NEXT: s_waitcnt lgkmcnt(0)7431; VI-NEXT: v_mov_b32_e32 v1, s117432; VI-NEXT: v_add_u32_e32 v0, vcc, s10, v67433; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc7434; VI-NEXT: v_mov_b32_e32 v3, s137435; VI-NEXT: v_add_u32_e32 v2, vcc, s12, v67436; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc7437; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1] glc7438; VI-NEXT: s_waitcnt vmcnt(0)7439; VI-NEXT: flat_load_dwordx2 v[2:3], v[2:3] glc7440; VI-NEXT: s_waitcnt vmcnt(0)7441; VI-NEXT: v_mov_b32_e32 v5, s157442; VI-NEXT: v_add_u32_e32 v4, vcc, s14, v67443; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc7444; VI-NEXT: v_mov_b32_e32 v7, s17445; VI-NEXT: v_add_u32_e32 v6, vcc, s0, v67446; VI-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc7447; VI-NEXT: flat_load_dwordx2 v[4:5], v[4:5] glc7448; VI-NEXT: s_waitcnt vmcnt(0)7449; VI-NEXT: flat_load_dwordx2 v[6:7], v[6:7] glc7450; VI-NEXT: s_waitcnt vmcnt(0)7451; VI-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], 2.07452; VI-NEXT: v_mul_f64 v[2:3], -v[0:1], v[4:5]7453; VI-NEXT: v_mul_f64 v[0:1], -v[0:1], v[6:7]7454; VI-NEXT: v_mov_b32_e32 v4, s87455; VI-NEXT: v_mov_b32_e32 v5, s97456; VI-NEXT: flat_store_dwordx2 v[4:5], v[2:3]7457; VI-NEXT: s_waitcnt vmcnt(0)7458; VI-NEXT: flat_store_dwordx2 v[4:5], v[0:1]7459; VI-NEXT: s_waitcnt vmcnt(0)7460; VI-NEXT: s_endpgm7461 %tid = call i32 @llvm.amdgcn.workitem.id.x()7462 %tid.ext = sext i32 %tid to i647463 %a.gep = getelementptr inbounds double, ptr addrspace(1) %a.ptr, i64 %tid.ext7464 %b.gep = getelementptr inbounds double, ptr addrspace(1) %b.ptr, i64 %tid.ext7465 %c.gep = getelementptr inbounds double, ptr addrspace(1) %c.ptr, i64 %tid.ext7466 %d.gep = getelementptr inbounds double, ptr addrspace(1) %d.ptr, i64 %tid.ext7467 %out.gep = getelementptr inbounds double, ptr addrspace(1) %out, i64 %tid.ext7468 %a = load volatile double, ptr addrspace(1) %a.gep7469 %b = load volatile double, ptr addrspace(1) %b.gep7470 %c = load volatile double, ptr addrspace(1) %c.gep7471 %d = load volatile double, ptr addrspace(1) %d.gep7472 7473 %fma0 = call double @llvm.fma.f64(double %a, double %b, double 2.0)7474 %fneg.fma0 = fsub double -0.0, %fma07475 %mul1 = fmul double %fneg.fma0, %c7476 %mul2 = fmul double %fneg.fma0, %d7477 7478 store volatile double %mul1, ptr addrspace(1) %out7479 store volatile double %mul2, ptr addrspace(1) %out7480 ret void7481}7482 7483; %trunc.a has one fneg use, but it requires a code size increase and7484; %the fneg can instead be folded for free into the fma.7485define amdgpu_kernel void @one_use_cost_to_fold_into_src_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr, ptr addrspace(1) %c.ptr, ptr addrspace(1) %d.ptr) #0 {7486; SI-LABEL: one_use_cost_to_fold_into_src_f32:7487; SI: ; %bb.0:7488; SI-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x97489; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x117490; SI-NEXT: v_lshlrev_b32_e32 v6, 2, v07491; SI-NEXT: s_waitcnt lgkmcnt(0)7492; SI-NEXT: v_mov_b32_e32 v1, s117493; SI-NEXT: v_add_i32_e32 v0, vcc, s10, v67494; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc7495; SI-NEXT: v_mov_b32_e32 v3, s137496; SI-NEXT: v_add_i32_e32 v2, vcc, s12, v67497; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc7498; SI-NEXT: v_mov_b32_e32 v5, s157499; SI-NEXT: v_add_i32_e32 v4, vcc, s14, v67500; SI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc7501; SI-NEXT: flat_load_dword v8, v[0:1] glc7502; SI-NEXT: s_waitcnt vmcnt(0)7503; SI-NEXT: flat_load_dword v2, v[2:3] glc7504; SI-NEXT: s_waitcnt vmcnt(0)7505; SI-NEXT: flat_load_dword v3, v[4:5] glc7506; SI-NEXT: s_waitcnt vmcnt(0)7507; SI-NEXT: v_mov_b32_e32 v7, s17508; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v67509; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v7, vcc7510; SI-NEXT: flat_load_dword v0, v[0:1] glc7511; SI-NEXT: s_waitcnt vmcnt(0)7512; SI-NEXT: v_trunc_f32_e32 v0, v87513; SI-NEXT: v_fma_f32 v2, -v0, v2, v37514; SI-NEXT: v_mov_b32_e32 v0, s87515; SI-NEXT: v_mov_b32_e32 v1, s97516; SI-NEXT: flat_store_dword v[0:1], v27517; SI-NEXT: s_waitcnt vmcnt(0)7518; SI-NEXT: s_endpgm7519;7520; VI-LABEL: one_use_cost_to_fold_into_src_f32:7521; VI: ; %bb.0:7522; VI-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x247523; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x447524; VI-NEXT: v_lshlrev_b32_e32 v6, 2, v07525; VI-NEXT: s_waitcnt lgkmcnt(0)7526; VI-NEXT: v_mov_b32_e32 v1, s117527; VI-NEXT: v_add_u32_e32 v0, vcc, s10, v67528; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc7529; VI-NEXT: v_mov_b32_e32 v3, s137530; VI-NEXT: v_add_u32_e32 v2, vcc, s12, v67531; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc7532; VI-NEXT: v_mov_b32_e32 v5, s157533; VI-NEXT: v_add_u32_e32 v4, vcc, s14, v67534; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc7535; VI-NEXT: flat_load_dword v8, v[0:1] glc7536; VI-NEXT: s_waitcnt vmcnt(0)7537; VI-NEXT: flat_load_dword v2, v[2:3] glc7538; VI-NEXT: s_waitcnt vmcnt(0)7539; VI-NEXT: flat_load_dword v3, v[4:5] glc7540; VI-NEXT: s_waitcnt vmcnt(0)7541; VI-NEXT: v_mov_b32_e32 v7, s17542; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v67543; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v7, vcc7544; VI-NEXT: flat_load_dword v0, v[0:1] glc7545; VI-NEXT: s_waitcnt vmcnt(0)7546; VI-NEXT: v_trunc_f32_e32 v0, v87547; VI-NEXT: v_fma_f32 v2, -v0, v2, v37548; VI-NEXT: v_mov_b32_e32 v0, s87549; VI-NEXT: v_mov_b32_e32 v1, s97550; VI-NEXT: flat_store_dword v[0:1], v27551; VI-NEXT: s_waitcnt vmcnt(0)7552; VI-NEXT: s_endpgm7553 %tid = call i32 @llvm.amdgcn.workitem.id.x()7554 %tid.ext = sext i32 %tid to i647555 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext7556 %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext7557 %c.gep = getelementptr inbounds float, ptr addrspace(1) %c.ptr, i64 %tid.ext7558 %d.gep = getelementptr inbounds float, ptr addrspace(1) %d.ptr, i64 %tid.ext7559 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext7560 %a = load volatile float, ptr addrspace(1) %a.gep7561 %b = load volatile float, ptr addrspace(1) %b.gep7562 %c = load volatile float, ptr addrspace(1) %c.gep7563 %d = load volatile float, ptr addrspace(1) %d.gep7564 7565 %trunc.a = call float @llvm.trunc.f32(float %a)7566 %trunc.fneg.a = fneg float %trunc.a7567 %fma0 = call float @llvm.fma.f32(float %trunc.fneg.a, float %b, float %c)7568 store volatile float %fma0, ptr addrspace(1) %out7569 ret void7570}7571 7572define amdgpu_kernel void @multi_use_cost_to_fold_into_src(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr, ptr addrspace(1) %c.ptr, ptr addrspace(1) %d.ptr) #0 {7573; SI-LABEL: multi_use_cost_to_fold_into_src:7574; SI: ; %bb.0:7575; SI-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x97576; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x117577; SI-NEXT: v_lshlrev_b32_e32 v6, 2, v07578; SI-NEXT: s_waitcnt lgkmcnt(0)7579; SI-NEXT: v_mov_b32_e32 v1, s117580; SI-NEXT: v_add_i32_e32 v0, vcc, s10, v67581; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc7582; SI-NEXT: v_mov_b32_e32 v3, s137583; SI-NEXT: v_add_i32_e32 v2, vcc, s12, v67584; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc7585; SI-NEXT: v_mov_b32_e32 v5, s157586; SI-NEXT: v_add_i32_e32 v4, vcc, s14, v67587; SI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc7588; SI-NEXT: v_mov_b32_e32 v7, s17589; SI-NEXT: v_add_i32_e32 v6, vcc, s0, v67590; SI-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc7591; SI-NEXT: flat_load_dword v8, v[0:1] glc7592; SI-NEXT: s_waitcnt vmcnt(0)7593; SI-NEXT: flat_load_dword v2, v[2:3] glc7594; SI-NEXT: s_waitcnt vmcnt(0)7595; SI-NEXT: flat_load_dword v3, v[4:5] glc7596; SI-NEXT: s_waitcnt vmcnt(0)7597; SI-NEXT: flat_load_dword v4, v[6:7] glc7598; SI-NEXT: s_waitcnt vmcnt(0)7599; SI-NEXT: v_mov_b32_e32 v0, s87600; SI-NEXT: v_mov_b32_e32 v1, s97601; SI-NEXT: v_trunc_f32_e32 v5, v87602; SI-NEXT: v_fma_f32 v2, -v5, v2, v37603; SI-NEXT: v_mul_f32_e32 v3, v5, v47604; SI-NEXT: flat_store_dword v[0:1], v27605; SI-NEXT: s_waitcnt vmcnt(0)7606; SI-NEXT: flat_store_dword v[0:1], v37607; SI-NEXT: s_waitcnt vmcnt(0)7608; SI-NEXT: s_endpgm7609;7610; VI-LABEL: multi_use_cost_to_fold_into_src:7611; VI: ; %bb.0:7612; VI-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x247613; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x447614; VI-NEXT: v_lshlrev_b32_e32 v6, 2, v07615; VI-NEXT: s_waitcnt lgkmcnt(0)7616; VI-NEXT: v_mov_b32_e32 v1, s117617; VI-NEXT: v_add_u32_e32 v0, vcc, s10, v67618; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc7619; VI-NEXT: v_mov_b32_e32 v3, s137620; VI-NEXT: v_add_u32_e32 v2, vcc, s12, v67621; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc7622; VI-NEXT: v_mov_b32_e32 v5, s157623; VI-NEXT: v_add_u32_e32 v4, vcc, s14, v67624; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc7625; VI-NEXT: v_mov_b32_e32 v7, s17626; VI-NEXT: v_add_u32_e32 v6, vcc, s0, v67627; VI-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc7628; VI-NEXT: flat_load_dword v8, v[0:1] glc7629; VI-NEXT: s_waitcnt vmcnt(0)7630; VI-NEXT: flat_load_dword v2, v[2:3] glc7631; VI-NEXT: s_waitcnt vmcnt(0)7632; VI-NEXT: flat_load_dword v3, v[4:5] glc7633; VI-NEXT: s_waitcnt vmcnt(0)7634; VI-NEXT: flat_load_dword v4, v[6:7] glc7635; VI-NEXT: s_waitcnt vmcnt(0)7636; VI-NEXT: v_mov_b32_e32 v0, s87637; VI-NEXT: v_mov_b32_e32 v1, s97638; VI-NEXT: v_trunc_f32_e32 v5, v87639; VI-NEXT: v_fma_f32 v2, -v5, v2, v37640; VI-NEXT: v_mul_f32_e32 v3, v5, v47641; VI-NEXT: flat_store_dword v[0:1], v27642; VI-NEXT: s_waitcnt vmcnt(0)7643; VI-NEXT: flat_store_dword v[0:1], v37644; VI-NEXT: s_waitcnt vmcnt(0)7645; VI-NEXT: s_endpgm7646 %tid = call i32 @llvm.amdgcn.workitem.id.x()7647 %tid.ext = sext i32 %tid to i647648 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext7649 %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext7650 %c.gep = getelementptr inbounds float, ptr addrspace(1) %c.ptr, i64 %tid.ext7651 %d.gep = getelementptr inbounds float, ptr addrspace(1) %d.ptr, i64 %tid.ext7652 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext7653 %a = load volatile float, ptr addrspace(1) %a.gep7654 %b = load volatile float, ptr addrspace(1) %b.gep7655 %c = load volatile float, ptr addrspace(1) %c.gep7656 %d = load volatile float, ptr addrspace(1) %d.gep7657 7658 %trunc.a = call float @llvm.trunc.f32(float %a)7659 %trunc.fneg.a = fneg float %trunc.a7660 %fma0 = call float @llvm.fma.f32(float %trunc.fneg.a, float %b, float %c)7661 %mul1 = fmul float %trunc.a, %d7662 store volatile float %fma0, ptr addrspace(1) %out7663 store volatile float %mul1, ptr addrspace(1) %out7664 ret void7665}7666 7667; The AMDGPU combine to pull fneg into the FMA operands was being7668; undone by the generic combine to pull the fneg out of the fma if7669; !isFNegFree. We were reporting false for v2f32 even though it will7670; be split into f32 where it will be free.7671define <2 x float> @fneg_fma_fneg_dagcombine_loop(<2 x float> %arg, <2 x float> %arg1, <2 x float> %arg2) #0 {7672; GCN-LABEL: fneg_fma_fneg_dagcombine_loop:7673; GCN: ; %bb.0: ; %bb7674; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7675; GCN-NEXT: s_brev_b32 s4, 17676; GCN-NEXT: v_fma_f32 v3, v3, -v5, s47677; GCN-NEXT: v_fma_f32 v2, v2, -v4, s47678; GCN-NEXT: v_sub_f32_e32 v1, v3, v17679; GCN-NEXT: v_sub_f32_e32 v0, v2, v07680; GCN-NEXT: v_mul_f32_e32 v0, v0, v47681; GCN-NEXT: v_mul_f32_e32 v1, v1, v57682; GCN-NEXT: s_setpc_b64 s[30:31]7683bb:7684 %i3 = call fast <2 x float> @llvm.fma.v2f32(<2 x float> %arg1, <2 x float> %arg2, <2 x float> zeroinitializer)7685 %i4 = fadd fast <2 x float> %i3, %arg7686 %i5 = fneg <2 x float> %i47687 %i6 = fmul fast <2 x float> %i5, %arg27688 ret <2 x float> %i67689}7690 7691; This expects denormal flushing, so can't turn this fmul into fneg7692define float @nnan_fmul_neg1_to_fneg(float %x, float %y) #0 {7693; GCN-LABEL: nnan_fmul_neg1_to_fneg:7694; GCN: ; %bb.0:7695; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7696; GCN-NEXT: v_mul_f32_e64 v0, -v0, v17697; GCN-NEXT: s_setpc_b64 s[30:31]7698 %mul = fmul float %x, -1.07699 %add = fmul nnan float %mul, %y7700 ret float %add7701}7702 7703; It's legal to turn this fmul into an fneg since denormals are7704; preserved and we know an snan can't happen from the flag.7705define float @denormal_fmul_neg1_to_fneg(float %x, float %y) {7706; GCN-LABEL: denormal_fmul_neg1_to_fneg:7707; GCN: ; %bb.0:7708; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7709; GCN-NEXT: v_mul_f32_e64 v0, -v0, v17710; GCN-NEXT: s_setpc_b64 s[30:31]7711 %mul = fmul nnan float %x, -1.07712 %add = fmul float %mul, %y7713 ret float %add7714}7715 7716; know the source can't be an snan7717define float @denorm_snan_fmul_neg1_to_fneg(float %x, float %y) {7718; GCN-LABEL: denorm_snan_fmul_neg1_to_fneg:7719; GCN: ; %bb.0:7720; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7721; GCN-NEXT: v_mul_f32_e64 v0, v0, -v07722; GCN-NEXT: v_mul_f32_e32 v0, v0, v17723; GCN-NEXT: s_setpc_b64 s[30:31]7724 %canonical = fmul float %x, %x7725 %mul = fmul float %canonical, -1.07726 %add = fmul float %mul, %y7727 ret float %add7728}7729 7730define float @flush_snan_fmul_neg1_to_fneg(float %x, float %y) #0 {7731; GCN-LABEL: flush_snan_fmul_neg1_to_fneg:7732; GCN: ; %bb.0:7733; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7734; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v07735; GCN-NEXT: v_mul_f32_e64 v0, -v0, v17736; GCN-NEXT: s_setpc_b64 s[30:31]7737 %quiet = call float @llvm.canonicalize.f32(float %x)7738 %mul = fmul float %quiet, -1.07739 %add = fmul float %mul, %y7740 ret float %add7741}7742 7743define float @fadd_select_fneg_fneg_f32(i32 %arg0, float %x, float %y, float %z) {7744; GCN-LABEL: fadd_select_fneg_fneg_f32:7745; GCN: ; %bb.0:7746; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7747; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v07748; GCN-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc7749; GCN-NEXT: v_sub_f32_e32 v0, v3, v07750; GCN-NEXT: s_setpc_b64 s[30:31]7751 %cmp = icmp eq i32 %arg0, 07752 %neg.x = fneg float %x7753 %neg.y = fneg float %y7754 %select = select i1 %cmp, float %neg.x, float %neg.y7755 %add = fadd float %select, %z7756 ret float %add7757}7758 7759define double @fadd_select_fneg_fneg_f64(i32 %arg0, double %x, double %y, double %z) {7760; GCN-LABEL: fadd_select_fneg_fneg_f64:7761; GCN: ; %bb.0:7762; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7763; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v07764; GCN-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc7765; GCN-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc7766; GCN-NEXT: v_add_f64 v[0:1], v[5:6], -v[1:2]7767; GCN-NEXT: s_setpc_b64 s[30:31]7768 %cmp = icmp eq i32 %arg0, 07769 %neg.x = fneg double %x7770 %neg.y = fneg double %y7771 %select = select i1 %cmp, double %neg.x, double %neg.y7772 %add = fadd double %select, %z7773 ret double %add7774}7775 7776define half @fadd_select_fneg_fneg_f16(i32 %arg0, half %x, half %y, half %z) {7777; SI-LABEL: fadd_select_fneg_fneg_f16:7778; SI: ; %bb.0:7779; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7780; SI-NEXT: v_cvt_f16_f32_e32 v1, v17781; SI-NEXT: v_cvt_f16_f32_e32 v2, v27782; SI-NEXT: v_cvt_f16_f32_e32 v3, v37783; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v07784; SI-NEXT: v_cvt_f32_f16_e32 v1, v17785; SI-NEXT: v_cvt_f32_f16_e32 v2, v27786; SI-NEXT: v_cvt_f32_f16_e32 v3, v37787; SI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc7788; SI-NEXT: v_sub_f32_e32 v0, v3, v07789; SI-NEXT: s_setpc_b64 s[30:31]7790;7791; VI-LABEL: fadd_select_fneg_fneg_f16:7792; VI: ; %bb.0:7793; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7794; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v07795; VI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc7796; VI-NEXT: v_sub_f16_e32 v0, v3, v07797; VI-NEXT: s_setpc_b64 s[30:31]7798 %cmp = icmp eq i32 %arg0, 07799 %neg.x = fneg half %x7800 %neg.y = fneg half %y7801 %select = select i1 %cmp, half %neg.x, half %neg.y7802 %add = fadd half %select, %z7803 ret half %add7804}7805 7806; FIXME: Terrible code for SI7807define <2 x half> @fadd_select_fneg_fneg_v2f16(i32 %arg0, <2 x half> %x, <2 x half> %y, <2 x half> %z) {7808; SI-LABEL: fadd_select_fneg_fneg_v2f16:7809; SI: ; %bb.0:7810; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7811; SI-NEXT: v_cvt_f16_f32_e32 v2, v27812; SI-NEXT: v_cvt_f16_f32_e32 v1, v17813; SI-NEXT: v_cvt_f16_f32_e32 v3, v37814; SI-NEXT: v_cvt_f16_f32_e32 v5, v57815; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v27816; SI-NEXT: v_or_b32_e32 v1, v1, v27817; SI-NEXT: v_cvt_f16_f32_e32 v2, v47818; SI-NEXT: v_cvt_f16_f32_e32 v4, v67819; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v07820; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v27821; SI-NEXT: v_or_b32_e32 v2, v3, v27822; SI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc7823; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v07824; SI-NEXT: v_cvt_f32_f16_e32 v3, v47825; SI-NEXT: v_cvt_f32_f16_e32 v4, v57826; SI-NEXT: v_cvt_f32_f16_e32 v0, v07827; SI-NEXT: v_cvt_f32_f16_e32 v1, v17828; SI-NEXT: v_sub_f32_e32 v0, v4, v07829; SI-NEXT: v_sub_f32_e32 v1, v3, v17830; SI-NEXT: s_setpc_b64 s[30:31]7831;7832; VI-LABEL: fadd_select_fneg_fneg_v2f16:7833; VI: ; %bb.0:7834; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7835; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v07836; VI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc7837; VI-NEXT: v_sub_f16_sdwa v1, v3, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_17838; VI-NEXT: v_sub_f16_e32 v0, v3, v07839; VI-NEXT: v_or_b32_e32 v0, v0, v17840; VI-NEXT: s_setpc_b64 s[30:31]7841 %cmp = icmp eq i32 %arg0, 07842 %neg.x = fneg <2 x half> %x7843 %neg.y = fneg <2 x half> %y7844 %select = select i1 %cmp, <2 x half> %neg.x, <2 x half> %neg.y7845 %add = fadd <2 x half> %select, %z7846 ret <2 x half> %add7847}7848 7849; FIXME: This fneg should fold into select7850define float @v_fneg_select_f32(i32 %arg0, float %a, float %b, float %c) {7851; GCN-LABEL: v_fneg_select_f32:7852; GCN: ; %bb.0:7853; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7854; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v07855; GCN-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc7856; GCN-NEXT: v_xor_b32_e32 v0, 0x80000000, v07857; GCN-NEXT: s_setpc_b64 s[30:31]7858 %cond = icmp eq i32 %arg0, 07859 %select = select i1 %cond, float %a, float %b7860 %fneg = fneg float %select7861 ret float %fneg7862}7863 7864; FIXME: This fneg should fold into select7865define float @v_fneg_select_2_f32(i32 %arg0, float %a, float %b, float %c) {7866; GCN-LABEL: v_fneg_select_2_f32:7867; GCN: ; %bb.0:7868; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7869; GCN-NEXT: v_add_f32_e32 v1, 2.0, v17870; GCN-NEXT: v_add_f32_e32 v2, 4.0, v27871; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v07872; GCN-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc7873; GCN-NEXT: v_xor_b32_e32 v0, 0x80000000, v07874; GCN-NEXT: s_setpc_b64 s[30:31]7875 %cond = icmp eq i32 %arg0, 07876 %add.0 = fadd float %a, 2.07877 %add.1 = fadd float %b, 4.07878 %select = select i1 %cond, float %add.0, float %add.17879 %neg.select = fneg float %select7880 ret float %neg.select7881}7882 7883define amdgpu_kernel void @v_fneg_posk_select_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) {7884; SI-LABEL: v_fneg_posk_select_f32:7885; SI: ; %bb.0:7886; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x97887; SI-NEXT: v_lshlrev_b32_e32 v3, 2, v07888; SI-NEXT: s_waitcnt lgkmcnt(0)7889; SI-NEXT: v_mov_b32_e32 v2, s37890; SI-NEXT: v_add_i32_e32 v1, vcc, s2, v37891; SI-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc7892; SI-NEXT: flat_load_dword v4, v[1:2] glc7893; SI-NEXT: s_waitcnt vmcnt(0)7894; SI-NEXT: v_mov_b32_e32 v2, s17895; SI-NEXT: v_add_i32_e32 v1, vcc, s0, v37896; SI-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc7897; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v07898; SI-NEXT: v_cndmask_b32_e32 v0, 4.0, v4, vcc7899; SI-NEXT: v_xor_b32_e32 v0, 0x80000000, v07900; SI-NEXT: flat_store_dword v[1:2], v07901; SI-NEXT: s_endpgm7902;7903; VI-LABEL: v_fneg_posk_select_f32:7904; VI: ; %bb.0:7905; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x247906; VI-NEXT: v_lshlrev_b32_e32 v3, 2, v07907; VI-NEXT: s_waitcnt lgkmcnt(0)7908; VI-NEXT: v_mov_b32_e32 v2, s37909; VI-NEXT: v_add_u32_e32 v1, vcc, s2, v37910; VI-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc7911; VI-NEXT: flat_load_dword v4, v[1:2] glc7912; VI-NEXT: s_waitcnt vmcnt(0)7913; VI-NEXT: v_mov_b32_e32 v2, s17914; VI-NEXT: v_add_u32_e32 v1, vcc, s0, v37915; VI-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc7916; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v07917; VI-NEXT: v_cndmask_b32_e32 v0, 4.0, v4, vcc7918; VI-NEXT: v_xor_b32_e32 v0, 0x80000000, v07919; VI-NEXT: flat_store_dword v[1:2], v07920; VI-NEXT: s_endpgm7921 %tid = call i32 @llvm.amdgcn.workitem.id.x()7922 %tid.ext = sext i32 %tid to i647923 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext7924 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext7925 %a = load volatile float, ptr addrspace(1) %a.gep7926 %cond = icmp eq i32 %tid, 07927 %select = select i1 %cond, float 4.0, float %a7928 %fneg = fneg float %select7929 store float %fneg, ptr addrspace(1) %out.gep7930 ret void7931}7932 7933define amdgpu_kernel void @v_fneg_negk_select_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) {7934; SI-LABEL: v_fneg_negk_select_f32:7935; SI: ; %bb.0:7936; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x97937; SI-NEXT: v_lshlrev_b32_e32 v3, 2, v07938; SI-NEXT: s_waitcnt lgkmcnt(0)7939; SI-NEXT: v_mov_b32_e32 v2, s37940; SI-NEXT: v_add_i32_e32 v1, vcc, s2, v37941; SI-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc7942; SI-NEXT: flat_load_dword v4, v[1:2] glc7943; SI-NEXT: s_waitcnt vmcnt(0)7944; SI-NEXT: v_mov_b32_e32 v2, s17945; SI-NEXT: v_add_i32_e32 v1, vcc, s0, v37946; SI-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc7947; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v07948; SI-NEXT: v_cndmask_b32_e32 v0, -4.0, v4, vcc7949; SI-NEXT: v_xor_b32_e32 v0, 0x80000000, v07950; SI-NEXT: flat_store_dword v[1:2], v07951; SI-NEXT: s_endpgm7952;7953; VI-LABEL: v_fneg_negk_select_f32:7954; VI: ; %bb.0:7955; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x247956; VI-NEXT: v_lshlrev_b32_e32 v3, 2, v07957; VI-NEXT: s_waitcnt lgkmcnt(0)7958; VI-NEXT: v_mov_b32_e32 v2, s37959; VI-NEXT: v_add_u32_e32 v1, vcc, s2, v37960; VI-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc7961; VI-NEXT: flat_load_dword v4, v[1:2] glc7962; VI-NEXT: s_waitcnt vmcnt(0)7963; VI-NEXT: v_mov_b32_e32 v2, s17964; VI-NEXT: v_add_u32_e32 v1, vcc, s0, v37965; VI-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc7966; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v07967; VI-NEXT: v_cndmask_b32_e32 v0, -4.0, v4, vcc7968; VI-NEXT: v_xor_b32_e32 v0, 0x80000000, v07969; VI-NEXT: flat_store_dword v[1:2], v07970; VI-NEXT: s_endpgm7971 %tid = call i32 @llvm.amdgcn.workitem.id.x()7972 %tid.ext = sext i32 %tid to i647973 %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext7974 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext7975 %a = load volatile float, ptr addrspace(1) %a.gep7976 %cond = icmp eq i32 %tid, 07977 %select = select i1 %cond, float -4.0, float %a7978 %fneg = fneg float %select7979 store float %fneg, ptr addrspace(1) %out.gep7980 ret void7981}7982 7983declare i32 @llvm.amdgcn.workitem.id.x() #17984declare float @llvm.fma.f32(float, float, float) #17985declare <2 x float> @llvm.fma.v2f32(<2 x float>, <2 x float>, <2 x float>)7986declare float @llvm.fmuladd.f32(float, float, float) #17987declare <4 x float> @llvm.fmuladd.v4f32(<4 x float>, <4 x float>, <4 x float>) #17988declare float @llvm.sin.f32(float) #17989declare float @llvm.trunc.f32(float) #17990declare float @llvm.round.f32(float) #17991declare float @llvm.rint.f32(float) #17992declare float @llvm.nearbyint.f32(float) #17993declare float @llvm.canonicalize.f32(float) #17994declare float @llvm.minnum.f32(float, float) #17995declare float @llvm.maxnum.f32(float, float) #17996declare half @llvm.minnum.f16(half, half) #17997declare double @llvm.minnum.f64(double, double) #17998declare double @llvm.fma.f64(double, double, double) #17999 8000declare float @llvm.amdgcn.sin.f32(float) #18001declare float @llvm.amdgcn.rcp.f32(float) #18002declare float @llvm.amdgcn.rcp.legacy(float) #18003declare float @llvm.amdgcn.fmul.legacy(float, float) #18004declare float @llvm.amdgcn.interp.p1(float, i32, i32, i32) #08005declare float @llvm.amdgcn.interp.p2(float, float, i32, i32, i32) #08006 8007attributes #0 = { nounwind "denormal-fp-math-f32"="preserve-sign,preserve-sign" }8008attributes #1 = { nounwind readnone }8009attributes #2 = { nounwind }8010attributes #3 = { nounwind "no-signed-zeros-fp-math"="true" }8011;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:8012; GCN-NSZ: {{.*}}8013; GCN-SAFE: {{.*}}8014