brintos / llvm-project-archived public Read only

1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn -mcpu=hawaii -mattr=+flat-for-global < %s | FileCheck -enable-var-scope --check-prefixes=GCN,GCN-SAFE,SI,SI-SAFE %s3; RUN: llc -enable-no-signed-zeros-fp-math -mtriple=amdgcn -mcpu=hawaii -mattr=+flat-for-global -fp-contract=fast < %s | FileCheck -enable-var-scope --check-prefixes=GCN,GCN-NSZ,SI,SI-NSZ %s4 5; RUN: llc -mtriple=amdgcn -mcpu=fiji < %s | FileCheck -enable-var-scope --check-prefixes=GCN,GCN-SAFE,VI,VI-SAFE %s6; RUN: llc -enable-no-signed-zeros-fp-math -mtriple=amdgcn -mcpu=fiji -fp-contract=fast < %s | FileCheck -enable-var-scope --check-prefixes=GCN,GCN-NSZ,VI,VI-NSZ %s7 8; --------------------------------------------------------------------------------9; fadd tests10; --------------------------------------------------------------------------------11 12define float @v_fneg_add_f32(float %a, float %b) #0 {13; GCN-SAFE-LABEL: v_fneg_add_f32:14; GCN-SAFE:       ; %bb.0:15; GCN-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)16; GCN-SAFE-NEXT:    v_add_f32_e32 v0, v0, v117; GCN-SAFE-NEXT:    v_xor_b32_e32 v0, 0x80000000, v018; GCN-SAFE-NEXT:    s_setpc_b64 s[30:31]19;20; GCN-NSZ-LABEL: v_fneg_add_f32:21; GCN-NSZ:       ; %bb.0:22; GCN-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)23; GCN-NSZ-NEXT:    v_sub_f32_e64 v0, -v0, v124; GCN-NSZ-NEXT:    s_setpc_b64 s[30:31]25  %add = fadd float %a, %b26  %fneg = fneg float %add27  ret float %fneg28}29 30define { float, float } @v_fneg_add_store_use_add_f32(float %a, float %b) #0 {31; GCN-LABEL: v_fneg_add_store_use_add_f32:32; GCN:       ; %bb.0:33; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)34; GCN-NEXT:    v_add_f32_e32 v1, v0, v135; GCN-NEXT:    v_xor_b32_e32 v0, 0x80000000, v136; GCN-NEXT:    s_setpc_b64 s[30:31]37  %add = fadd float %a, %b38  %fneg = fneg float %add39  %insert.0 = insertvalue { float, float } poison, float %fneg, 040  %insert.1 = insertvalue { float, float } %insert.0, float %add, 141  ret { float, float } %insert.142}43 44define { float, float } @v_fneg_add_multi_use_add_f32(float %a, float %b) #0 {45; GCN-SAFE-LABEL: v_fneg_add_multi_use_add_f32:46; GCN-SAFE:       ; %bb.0:47; GCN-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)48; GCN-SAFE-NEXT:    v_add_f32_e32 v1, v0, v149; GCN-SAFE-NEXT:    v_xor_b32_e32 v0, 0x80000000, v150; GCN-SAFE-NEXT:    v_mul_f32_e32 v1, 4.0, v151; GCN-SAFE-NEXT:    s_setpc_b64 s[30:31]52;53; GCN-NSZ-LABEL: v_fneg_add_multi_use_add_f32:54; GCN-NSZ:       ; %bb.0:55; GCN-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)56; GCN-NSZ-NEXT:    v_sub_f32_e64 v0, -v0, v157; GCN-NSZ-NEXT:    v_mul_f32_e32 v1, -4.0, v058; GCN-NSZ-NEXT:    s_setpc_b64 s[30:31]59  %add = fadd float %a, %b60  %fneg = fneg float %add61  %use1 = fmul float %add, 4.062 63  %insert.0 = insertvalue { float, float } poison, float %fneg, 064  %insert.1 = insertvalue { float, float } %insert.0, float %use1, 165  ret { float, float } %insert.166}67 68define float @v_fneg_add_fneg_x_f32(float %a, float %b) #0 {69; GCN-SAFE-LABEL: v_fneg_add_fneg_x_f32:70; GCN-SAFE:       ; %bb.0:71; GCN-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)72; GCN-SAFE-NEXT:    v_sub_f32_e32 v0, v1, v073; GCN-SAFE-NEXT:    v_xor_b32_e32 v0, 0x80000000, v074; GCN-SAFE-NEXT:    s_setpc_b64 s[30:31]75;76; GCN-NSZ-LABEL: v_fneg_add_fneg_x_f32:77; GCN-NSZ:       ; %bb.0:78; GCN-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)79; GCN-NSZ-NEXT:    v_sub_f32_e32 v0, v0, v180; GCN-NSZ-NEXT:    s_setpc_b64 s[30:31]81  %fneg.a = fneg float %a82  %add = fadd float %fneg.a, %b83  %fneg = fneg float %add84  ret float %fneg85}86 87define float @v_fneg_add_x_fneg_f32(float %a, float %b) #0 {88; GCN-SAFE-LABEL: v_fneg_add_x_fneg_f32:89; GCN-SAFE:       ; %bb.0:90; GCN-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)91; GCN-SAFE-NEXT:    v_sub_f32_e32 v0, v0, v192; GCN-SAFE-NEXT:    v_xor_b32_e32 v0, 0x80000000, v093; GCN-SAFE-NEXT:    s_setpc_b64 s[30:31]94;95; GCN-NSZ-LABEL: v_fneg_add_x_fneg_f32:96; GCN-NSZ:       ; %bb.0:97; GCN-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)98; GCN-NSZ-NEXT:    v_sub_f32_e32 v0, v1, v099; GCN-NSZ-NEXT:    s_setpc_b64 s[30:31]100  %fneg.b = fneg float %b101  %add = fadd float %a, %fneg.b102  %fneg = fneg float %add103  ret float %fneg104}105 106define float @v_fneg_add_fneg_fneg_f32(float %a, float %b) #0 {107; GCN-SAFE-LABEL: v_fneg_add_fneg_fneg_f32:108; GCN-SAFE:       ; %bb.0:109; GCN-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)110; GCN-SAFE-NEXT:    v_sub_f32_e64 v0, -v0, v1111; GCN-SAFE-NEXT:    v_xor_b32_e32 v0, 0x80000000, v0112; GCN-SAFE-NEXT:    s_setpc_b64 s[30:31]113;114; GCN-NSZ-LABEL: v_fneg_add_fneg_fneg_f32:115; GCN-NSZ:       ; %bb.0:116; GCN-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)117; GCN-NSZ-NEXT:    v_add_f32_e32 v0, v0, v1118; GCN-NSZ-NEXT:    s_setpc_b64 s[30:31]119  %fneg.a = fneg float %a120  %fneg.b = fneg float %b121  %add = fadd float %fneg.a, %fneg.b122  %fneg = fneg float %add123  ret float %fneg124}125 126define { float, float } @v_fneg_add_store_use_fneg_x_f32(float %a, float %b) #0 {127; GCN-SAFE-LABEL: v_fneg_add_store_use_fneg_x_f32:128; GCN-SAFE:       ; %bb.0:129; GCN-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)130; GCN-SAFE-NEXT:    v_xor_b32_e32 v2, 0x80000000, v0131; GCN-SAFE-NEXT:    v_sub_f32_e32 v0, v1, v0132; GCN-SAFE-NEXT:    v_xor_b32_e32 v0, 0x80000000, v0133; GCN-SAFE-NEXT:    v_mov_b32_e32 v1, v2134; GCN-SAFE-NEXT:    s_setpc_b64 s[30:31]135;136; GCN-NSZ-LABEL: v_fneg_add_store_use_fneg_x_f32:137; GCN-NSZ:       ; %bb.0:138; GCN-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)139; GCN-NSZ-NEXT:    v_xor_b32_e32 v2, 0x80000000, v0140; GCN-NSZ-NEXT:    v_sub_f32_e32 v0, v0, v1141; GCN-NSZ-NEXT:    v_mov_b32_e32 v1, v2142; GCN-NSZ-NEXT:    s_setpc_b64 s[30:31]143  %fneg.a = fneg float %a144  %add = fadd float %fneg.a, %b145  %fneg = fneg float %add146  %insert.0 = insertvalue { float, float } poison, float %fneg, 0147  %insert.1 = insertvalue { float, float } %insert.0, float %fneg.a, 1148  ret { float, float } %insert.1149}150 151define { float, float } @v_fneg_add_multi_use_fneg_x_f32(float %a, float %b, float %c) #0 {152; GCN-SAFE-LABEL: v_fneg_add_multi_use_fneg_x_f32:153; GCN-SAFE:       ; %bb.0:154; GCN-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)155; GCN-SAFE-NEXT:    v_sub_f32_e32 v1, v1, v0156; GCN-SAFE-NEXT:    v_xor_b32_e32 v3, 0x80000000, v1157; GCN-SAFE-NEXT:    v_mul_f32_e64 v1, -v0, v2158; GCN-SAFE-NEXT:    v_mov_b32_e32 v0, v3159; GCN-SAFE-NEXT:    s_setpc_b64 s[30:31]160;161; GCN-NSZ-LABEL: v_fneg_add_multi_use_fneg_x_f32:162; GCN-NSZ:       ; %bb.0:163; GCN-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)164; GCN-NSZ-NEXT:    v_sub_f32_e32 v3, v0, v1165; GCN-NSZ-NEXT:    v_mul_f32_e64 v1, -v0, v2166; GCN-NSZ-NEXT:    v_mov_b32_e32 v0, v3167; GCN-NSZ-NEXT:    s_setpc_b64 s[30:31]168  %fneg.a = fneg float %a169  %add = fadd float %fneg.a, %b170  %fneg = fneg float %add171  %use1 = fmul float %fneg.a, %c172 173  %insert.0 = insertvalue { float, float } poison, float %fneg, 0174  %insert.1 = insertvalue { float, float } %insert.0, float %use1, 1175  ret { float, float } %insert.1176}177 178define amdgpu_ps float @fneg_fadd_0_safe_f32(float inreg %tmp2, float inreg %tmp6, <4 x i32> %arg) #0 {179; SI-LABEL: fneg_fadd_0_safe_f32:180; SI:       ; %bb.0: ; %.entry181; SI-NEXT:    v_div_scale_f32 v0, s[2:3], s1, s1, 1.0182; SI-NEXT:    v_rcp_f32_e32 v1, v0183; SI-NEXT:    v_div_scale_f32 v2, vcc, 1.0, s1, 1.0184; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3185; SI-NEXT:    v_fma_f32 v3, -v0, v1, 1.0186; SI-NEXT:    v_fma_f32 v1, v3, v1, v1187; SI-NEXT:    v_mul_f32_e32 v3, v2, v1188; SI-NEXT:    v_fma_f32 v4, -v0, v3, v2189; SI-NEXT:    v_fma_f32 v3, v4, v1, v3190; SI-NEXT:    v_fma_f32 v0, -v0, v3, v2191; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0192; SI-NEXT:    v_div_fmas_f32 v0, v0, v1, v3193; SI-NEXT:    v_div_fixup_f32 v0, v0, s1, 1.0194; SI-NEXT:    v_mad_f32 v0, v0, 0, 0195; SI-NEXT:    v_mov_b32_e32 v1, s0196; SI-NEXT:    v_cmp_ngt_f32_e32 vcc, s0, v0197; SI-NEXT:    v_cndmask_b32_e64 v0, -v0, v1, vcc198; SI-NEXT:    v_mov_b32_e32 v1, 0x7fc00000199; SI-NEXT:    v_cmp_nlt_f32_e32 vcc, 0, v0200; SI-NEXT:    v_cndmask_b32_e64 v0, v1, 0, vcc201; SI-NEXT:    ; return to shader part epilog202;203; VI-LABEL: fneg_fadd_0_safe_f32:204; VI:       ; %bb.0: ; %.entry205; VI-NEXT:    v_div_scale_f32 v0, s[2:3], s1, s1, 1.0206; VI-NEXT:    v_div_scale_f32 v1, vcc, 1.0, s1, 1.0207; VI-NEXT:    v_rcp_f32_e32 v2, v0208; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3209; VI-NEXT:    v_fma_f32 v3, -v0, v2, 1.0210; VI-NEXT:    v_fma_f32 v2, v3, v2, v2211; VI-NEXT:    v_mul_f32_e32 v3, v1, v2212; VI-NEXT:    v_fma_f32 v4, -v0, v3, v1213; VI-NEXT:    v_fma_f32 v3, v4, v2, v3214; VI-NEXT:    v_fma_f32 v0, -v0, v3, v1215; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0216; VI-NEXT:    v_div_fmas_f32 v0, v0, v2, v3217; VI-NEXT:    v_mov_b32_e32 v2, s0218; VI-NEXT:    v_mov_b32_e32 v1, 0x7fc00000219; VI-NEXT:    v_div_fixup_f32 v0, v0, s1, 1.0220; VI-NEXT:    v_mad_f32 v0, v0, 0, 0221; VI-NEXT:    v_cmp_ngt_f32_e32 vcc, s0, v0222; VI-NEXT:    v_cndmask_b32_e64 v0, -v0, v2, vcc223; VI-NEXT:    v_cmp_nlt_f32_e32 vcc, 0, v0224; VI-NEXT:    v_cndmask_b32_e64 v0, v1, 0, vcc225; VI-NEXT:    ; return to shader part epilog226.entry:227  %tmp7 = fdiv float 1.000000e+00, %tmp6228  %tmp8 = fmul float 0.000000e+00, %tmp7229  %tmp9 = fmul reassoc nnan arcp contract float 0.000000e+00, %tmp8230  %.i188 = fadd float %tmp9, 0.000000e+00231  %tmp10 = fcmp uge float %.i188, %tmp2232  %tmp11 = fneg float %.i188233  %.i092 = select i1 %tmp10, float %tmp2, float %tmp11234  %tmp12 = fcmp ule float %.i092, 0.000000e+00235  %.i198 = select i1 %tmp12, float 0.000000e+00, float 0x7FF8000000000000236  ret float %.i198237}238 239; This is a workaround because -enable-no-signed-zeros-fp-math does not set up240; function attribute unsafe-fp-math automatically. Combine with the previous test241; when that is done.242define amdgpu_ps float @fneg_fadd_0_nsz_f32(float inreg %tmp2, float inreg %tmp6, <4 x i32> %arg) #2 {243; GCN-LABEL: fneg_fadd_0_nsz_f32:244; GCN:       ; %bb.0: ; %.entry245; GCN-NEXT:    v_rcp_f32_e32 v0, s1246; GCN-NEXT:    v_mov_b32_e32 v1, s0247; GCN-NEXT:    v_mul_f32_e32 v0, 0, v0248; GCN-NEXT:    v_cmp_ngt_f32_e32 vcc, s0, v0249; GCN-NEXT:    v_cndmask_b32_e64 v0, -v0, v1, vcc250; GCN-NEXT:    v_mov_b32_e32 v1, 0x7fc00000251; GCN-NEXT:    v_cmp_nlt_f32_e32 vcc, 0, v0252; GCN-NEXT:    v_cndmask_b32_e64 v0, v1, 0, vcc253; GCN-NEXT:    ; return to shader part epilog254.entry:255  %tmp7 = fdiv afn float 1.000000e+00, %tmp6256  %tmp8 = fmul float 0.000000e+00, %tmp7257  %tmp9 = fmul reassoc nnan arcp contract float 0.000000e+00, %tmp8258  %.i188 = fadd nsz float %tmp9, 0.000000e+00259  %tmp10 = fcmp uge float %.i188, %tmp2260  %tmp11 = fneg float %.i188261  %.i092 = select i1 %tmp10, float %tmp2, float %tmp11262  %tmp12 = fcmp ule float %.i092, 0.000000e+00263  %.i198 = select i1 %tmp12, float 0.000000e+00, float 0x7FF8000000000000264  ret float %.i198265}266 267define double @v_fneg_add_f64(double %a, double %b) #0 {268; GCN-SAFE-LABEL: v_fneg_add_f64:269; GCN-SAFE:       ; %bb.0:270; GCN-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)271; GCN-SAFE-NEXT:    v_add_f64 v[0:1], v[0:1], v[2:3]272; GCN-SAFE-NEXT:    v_xor_b32_e32 v1, 0x80000000, v1273; GCN-SAFE-NEXT:    s_setpc_b64 s[30:31]274;275; GCN-NSZ-LABEL: v_fneg_add_f64:276; GCN-NSZ:       ; %bb.0:277; GCN-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)278; GCN-NSZ-NEXT:    v_add_f64 v[0:1], -v[0:1], -v[2:3]279; GCN-NSZ-NEXT:    s_setpc_b64 s[30:31]280  %add = fadd double %a, %b281  %fneg = fneg double %add282  ret double %fneg283}284 285define { double, double } @v_fneg_add_store_use_add_f64(double %a, double %b) #0 {286; GCN-LABEL: v_fneg_add_store_use_add_f64:287; GCN:       ; %bb.0:288; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)289; GCN-NEXT:    v_add_f64 v[2:3], v[0:1], v[2:3]290; GCN-NEXT:    v_xor_b32_e32 v1, 0x80000000, v3291; GCN-NEXT:    v_mov_b32_e32 v0, v2292; GCN-NEXT:    s_setpc_b64 s[30:31]293  %add = fadd double %a, %b294  %fneg = fneg double %add295  %insert.0 = insertvalue { double, double } poison, double %fneg, 0296  %insert.1 = insertvalue { double, double } %insert.0, double %add, 1297  ret { double, double } %insert.1298}299 300define { double, double } @v_fneg_add_multi_use_add_f64(double %a, double %b) #0 {301; SI-SAFE-LABEL: v_fneg_add_multi_use_add_f64:302; SI-SAFE:       ; %bb.0:303; SI-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)304; SI-SAFE-NEXT:    v_add_f64 v[0:1], v[0:1], v[2:3]305; SI-SAFE-NEXT:    v_xor_b32_e32 v4, 0x80000000, v1306; SI-SAFE-NEXT:    v_mul_f64 v[2:3], v[0:1], 4.0307; SI-SAFE-NEXT:    v_mov_b32_e32 v1, v4308; SI-SAFE-NEXT:    s_setpc_b64 s[30:31]309;310; GCN-NSZ-LABEL: v_fneg_add_multi_use_add_f64:311; GCN-NSZ:       ; %bb.0:312; GCN-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)313; GCN-NSZ-NEXT:    v_add_f64 v[0:1], -v[0:1], -v[2:3]314; GCN-NSZ-NEXT:    v_mul_f64 v[2:3], v[0:1], -4.0315; GCN-NSZ-NEXT:    s_setpc_b64 s[30:31]316;317; VI-SAFE-LABEL: v_fneg_add_multi_use_add_f64:318; VI-SAFE:       ; %bb.0:319; VI-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)320; VI-SAFE-NEXT:    v_add_f64 v[0:1], v[0:1], v[2:3]321; VI-SAFE-NEXT:    v_mul_f64 v[2:3], v[0:1], 4.0322; VI-SAFE-NEXT:    v_xor_b32_e32 v1, 0x80000000, v1323; VI-SAFE-NEXT:    s_setpc_b64 s[30:31]324  %add = fadd double %a, %b325  %fneg = fneg double %add326  %use1 = fmul double %add, 4.0327 328  %insert.0 = insertvalue { double, double } poison, double %fneg, 0329  %insert.1 = insertvalue { double, double } %insert.0, double %use1, 1330  ret { double, double } %insert.1331}332 333define double @v_fneg_add_fneg_x_f64(double %a, double %b) #0 {334; GCN-SAFE-LABEL: v_fneg_add_fneg_x_f64:335; GCN-SAFE:       ; %bb.0:336; GCN-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)337; GCN-SAFE-NEXT:    v_add_f64 v[0:1], v[2:3], -v[0:1]338; GCN-SAFE-NEXT:    v_xor_b32_e32 v1, 0x80000000, v1339; GCN-SAFE-NEXT:    s_setpc_b64 s[30:31]340;341; GCN-NSZ-LABEL: v_fneg_add_fneg_x_f64:342; GCN-NSZ:       ; %bb.0:343; GCN-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)344; GCN-NSZ-NEXT:    v_add_f64 v[0:1], v[0:1], -v[2:3]345; GCN-NSZ-NEXT:    s_setpc_b64 s[30:31]346  %fneg.a = fneg double %a347  %add = fadd double %fneg.a, %b348  %fneg = fneg double %add349  ret double %fneg350}351 352define double @v_fneg_add_x_fneg_f64(double %a, double %b) #0 {353; GCN-SAFE-LABEL: v_fneg_add_x_fneg_f64:354; GCN-SAFE:       ; %bb.0:355; GCN-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)356; GCN-SAFE-NEXT:    v_add_f64 v[0:1], v[0:1], -v[2:3]357; GCN-SAFE-NEXT:    v_xor_b32_e32 v1, 0x80000000, v1358; GCN-SAFE-NEXT:    s_setpc_b64 s[30:31]359;360; GCN-NSZ-LABEL: v_fneg_add_x_fneg_f64:361; GCN-NSZ:       ; %bb.0:362; GCN-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)363; GCN-NSZ-NEXT:    v_add_f64 v[0:1], v[2:3], -v[0:1]364; GCN-NSZ-NEXT:    s_setpc_b64 s[30:31]365  %fneg.b = fneg double %b366  %add = fadd double %a, %fneg.b367  %fneg = fneg double %add368  ret double %fneg369}370 371define double @v_fneg_add_fneg_fneg_f64(double %a, double %b) #0 {372; GCN-SAFE-LABEL: v_fneg_add_fneg_fneg_f64:373; GCN-SAFE:       ; %bb.0:374; GCN-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)375; GCN-SAFE-NEXT:    v_add_f64 v[0:1], -v[0:1], -v[2:3]376; GCN-SAFE-NEXT:    v_xor_b32_e32 v1, 0x80000000, v1377; GCN-SAFE-NEXT:    s_setpc_b64 s[30:31]378;379; GCN-NSZ-LABEL: v_fneg_add_fneg_fneg_f64:380; GCN-NSZ:       ; %bb.0:381; GCN-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)382; GCN-NSZ-NEXT:    v_add_f64 v[0:1], v[0:1], v[2:3]383; GCN-NSZ-NEXT:    s_setpc_b64 s[30:31]384  %fneg.a = fneg double %a385  %fneg.b = fneg double %b386  %add = fadd double %fneg.a, %fneg.b387  %fneg = fneg double %add388  ret double %fneg389}390 391define { double, double } @v_fneg_add_store_use_fneg_x_f64(double %a, double %b) #0 {392; SI-SAFE-LABEL: v_fneg_add_store_use_fneg_x_f64:393; SI-SAFE:       ; %bb.0:394; SI-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)395; SI-SAFE-NEXT:    v_mov_b32_e32 v5, v1396; SI-SAFE-NEXT:    v_mov_b32_e32 v4, v0397; SI-SAFE-NEXT:    v_add_f64 v[0:1], v[2:3], -v[4:5]398; SI-SAFE-NEXT:    v_xor_b32_e32 v3, 0x80000000, v5399; SI-SAFE-NEXT:    v_xor_b32_e32 v1, 0x80000000, v1400; SI-SAFE-NEXT:    v_mov_b32_e32 v2, v4401; SI-SAFE-NEXT:    s_setpc_b64 s[30:31]402;403; SI-NSZ-LABEL: v_fneg_add_store_use_fneg_x_f64:404; SI-NSZ:       ; %bb.0:405; SI-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)406; SI-NSZ-NEXT:    v_mov_b32_e32 v5, v1407; SI-NSZ-NEXT:    v_mov_b32_e32 v4, v0408; SI-NSZ-NEXT:    v_add_f64 v[0:1], v[4:5], -v[2:3]409; SI-NSZ-NEXT:    v_xor_b32_e32 v3, 0x80000000, v5410; SI-NSZ-NEXT:    v_mov_b32_e32 v2, v4411; SI-NSZ-NEXT:    s_setpc_b64 s[30:31]412;413; VI-SAFE-LABEL: v_fneg_add_store_use_fneg_x_f64:414; VI-SAFE:       ; %bb.0:415; VI-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)416; VI-SAFE-NEXT:    v_add_f64 v[4:5], v[2:3], -v[0:1]417; VI-SAFE-NEXT:    v_xor_b32_e32 v3, 0x80000000, v1418; VI-SAFE-NEXT:    v_mov_b32_e32 v2, v0419; VI-SAFE-NEXT:    v_xor_b32_e32 v1, 0x80000000, v5420; VI-SAFE-NEXT:    v_mov_b32_e32 v0, v4421; VI-SAFE-NEXT:    s_setpc_b64 s[30:31]422;423; VI-NSZ-LABEL: v_fneg_add_store_use_fneg_x_f64:424; VI-NSZ:       ; %bb.0:425; VI-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)426; VI-NSZ-NEXT:    v_add_f64 v[4:5], v[0:1], -v[2:3]427; VI-NSZ-NEXT:    v_xor_b32_e32 v3, 0x80000000, v1428; VI-NSZ-NEXT:    v_mov_b32_e32 v2, v0429; VI-NSZ-NEXT:    v_mov_b32_e32 v0, v4430; VI-NSZ-NEXT:    v_mov_b32_e32 v1, v5431; VI-NSZ-NEXT:    s_setpc_b64 s[30:31]432  %fneg.a = fneg double %a433  %add = fadd double %fneg.a, %b434  %fneg = fneg double %add435  %insert.0 = insertvalue { double, double } poison, double %fneg, 0436  %insert.1 = insertvalue { double, double } %insert.0, double %fneg.a, 1437  ret { double, double } %insert.1438}439 440define { double, double } @v_fneg_add_multi_use_fneg_x_f64(double %a, double %b, double %c) #0 {441; SI-SAFE-LABEL: v_fneg_add_multi_use_fneg_x_f64:442; SI-SAFE:       ; %bb.0:443; SI-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)444; SI-SAFE-NEXT:    v_add_f64 v[6:7], v[2:3], -v[0:1]445; SI-SAFE-NEXT:    v_mul_f64 v[2:3], -v[0:1], v[4:5]446; SI-SAFE-NEXT:    v_xor_b32_e32 v7, 0x80000000, v7447; SI-SAFE-NEXT:    v_mov_b32_e32 v0, v6448; SI-SAFE-NEXT:    v_mov_b32_e32 v1, v7449; SI-SAFE-NEXT:    s_setpc_b64 s[30:31]450;451; GCN-NSZ-LABEL: v_fneg_add_multi_use_fneg_x_f64:452; GCN-NSZ:       ; %bb.0:453; GCN-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)454; GCN-NSZ-NEXT:    v_add_f64 v[6:7], v[0:1], -v[2:3]455; GCN-NSZ-NEXT:    v_mul_f64 v[2:3], -v[0:1], v[4:5]456; GCN-NSZ-NEXT:    v_mov_b32_e32 v0, v6457; GCN-NSZ-NEXT:    v_mov_b32_e32 v1, v7458; GCN-NSZ-NEXT:    s_setpc_b64 s[30:31]459;460; VI-SAFE-LABEL: v_fneg_add_multi_use_fneg_x_f64:461; VI-SAFE:       ; %bb.0:462; VI-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)463; VI-SAFE-NEXT:    v_add_f64 v[6:7], v[2:3], -v[0:1]464; VI-SAFE-NEXT:    v_mul_f64 v[2:3], -v[0:1], v[4:5]465; VI-SAFE-NEXT:    v_xor_b32_e32 v1, 0x80000000, v7466; VI-SAFE-NEXT:    v_mov_b32_e32 v0, v6467; VI-SAFE-NEXT:    s_setpc_b64 s[30:31]468  %fneg.a = fneg double %a469  %add = fadd double %fneg.a, %b470  %fneg = fneg double %add471  %use1 = fmul double %fneg.a, %c472 473  %insert.0 = insertvalue { double, double } poison, double %fneg, 0474  %insert.1 = insertvalue { double, double } %insert.0, double %use1, 1475  ret { double, double } %insert.1476}477 478; This one asserted with -enable-no-signed-zeros-fp-math479define amdgpu_ps double @fneg_fadd_0_f64(double inreg %tmp2, double inreg %tmp6, <4 x i32> %arg) #0 {480; SI-SAFE-LABEL: fneg_fadd_0_f64:481; SI-SAFE:       ; %bb.0: ; %.entry482; SI-SAFE-NEXT:    v_div_scale_f64 v[0:1], s[4:5], s[2:3], s[2:3], 1.0483; SI-SAFE-NEXT:    v_rcp_f64_e32 v[2:3], v[0:1]484; SI-SAFE-NEXT:    v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0485; SI-SAFE-NEXT:    v_fma_f64 v[2:3], v[2:3], v[4:5], v[2:3]486; SI-SAFE-NEXT:    v_div_scale_f64 v[4:5], vcc, 1.0, s[2:3], 1.0487; SI-SAFE-NEXT:    v_fma_f64 v[6:7], -v[0:1], v[2:3], 1.0488; SI-SAFE-NEXT:    v_fma_f64 v[2:3], v[2:3], v[6:7], v[2:3]489; SI-SAFE-NEXT:    v_mul_f64 v[6:7], v[4:5], v[2:3]490; SI-SAFE-NEXT:    v_fma_f64 v[0:1], -v[0:1], v[6:7], v[4:5]491; SI-SAFE-NEXT:    v_div_fmas_f64 v[0:1], v[0:1], v[2:3], v[6:7]492; SI-SAFE-NEXT:    v_mov_b32_e32 v2, s1493; SI-SAFE-NEXT:    v_mov_b32_e32 v3, s0494; SI-SAFE-NEXT:    v_div_fixup_f64 v[0:1], v[0:1], s[2:3], 1.0495; SI-SAFE-NEXT:    v_mul_f64 v[0:1], v[0:1], 0496; SI-SAFE-NEXT:    v_add_f64 v[0:1], v[0:1], 0497; SI-SAFE-NEXT:    v_cmp_ngt_f64_e32 vcc, s[0:1], v[0:1]498; SI-SAFE-NEXT:    v_xor_b32_e32 v4, 0x80000000, v1499; SI-SAFE-NEXT:    v_cndmask_b32_e32 v1, v4, v2, vcc500; SI-SAFE-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc501; SI-SAFE-NEXT:    v_cmp_nlt_f64_e32 vcc, 0, v[0:1]502; SI-SAFE-NEXT:    s_and_b64 s[0:1], vcc, exec503; SI-SAFE-NEXT:    s_cselect_b32 s1, 0, 0x7ff80000504; SI-SAFE-NEXT:    s_mov_b32 s0, 0505; SI-SAFE-NEXT:    ; return to shader part epilog506;507; SI-NSZ-LABEL: fneg_fadd_0_f64:508; SI-NSZ:       ; %bb.0: ; %.entry509; SI-NSZ-NEXT:    v_div_scale_f64 v[0:1], s[4:5], s[2:3], s[2:3], 1.0510; SI-NSZ-NEXT:    v_rcp_f64_e32 v[2:3], v[0:1]511; SI-NSZ-NEXT:    v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0512; SI-NSZ-NEXT:    v_fma_f64 v[2:3], v[2:3], v[4:5], v[2:3]513; SI-NSZ-NEXT:    v_div_scale_f64 v[4:5], vcc, 1.0, s[2:3], 1.0514; SI-NSZ-NEXT:    v_fma_f64 v[6:7], -v[0:1], v[2:3], 1.0515; SI-NSZ-NEXT:    v_fma_f64 v[2:3], v[2:3], v[6:7], v[2:3]516; SI-NSZ-NEXT:    v_mul_f64 v[6:7], v[4:5], v[2:3]517; SI-NSZ-NEXT:    v_fma_f64 v[0:1], -v[0:1], v[6:7], v[4:5]518; SI-NSZ-NEXT:    v_div_fmas_f64 v[0:1], v[0:1], v[2:3], v[6:7]519; SI-NSZ-NEXT:    v_mov_b32_e32 v2, s1520; SI-NSZ-NEXT:    v_mov_b32_e32 v3, s0521; SI-NSZ-NEXT:    v_div_fixup_f64 v[0:1], v[0:1], s[2:3], 1.0522; SI-NSZ-NEXT:    s_mov_b32 s2, 0523; SI-NSZ-NEXT:    v_mul_f64 v[0:1], v[0:1], 0524; SI-NSZ-NEXT:    s_brev_b32 s3, 1525; SI-NSZ-NEXT:    v_fma_f64 v[0:1], v[0:1], s[2:3], s[2:3]526; SI-NSZ-NEXT:    v_cmp_nlt_f64_e64 vcc, -v[0:1], s[0:1]527; SI-NSZ-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc528; SI-NSZ-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc529; SI-NSZ-NEXT:    v_cmp_nlt_f64_e32 vcc, 0, v[0:1]530; SI-NSZ-NEXT:    s_and_b64 s[0:1], vcc, exec531; SI-NSZ-NEXT:    s_cselect_b32 s1, 0, 0x7ff80000532; SI-NSZ-NEXT:    s_mov_b32 s0, 0533; SI-NSZ-NEXT:    ; return to shader part epilog534;535; VI-SAFE-LABEL: fneg_fadd_0_f64:536; VI-SAFE:       ; %bb.0: ; %.entry537; VI-SAFE-NEXT:    v_div_scale_f64 v[0:1], s[4:5], s[2:3], s[2:3], 1.0538; VI-SAFE-NEXT:    v_rcp_f64_e32 v[2:3], v[0:1]539; VI-SAFE-NEXT:    v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0540; VI-SAFE-NEXT:    v_fma_f64 v[2:3], v[2:3], v[4:5], v[2:3]541; VI-SAFE-NEXT:    v_div_scale_f64 v[4:5], vcc, 1.0, s[2:3], 1.0542; VI-SAFE-NEXT:    v_fma_f64 v[6:7], -v[0:1], v[2:3], 1.0543; VI-SAFE-NEXT:    v_fma_f64 v[2:3], v[2:3], v[6:7], v[2:3]544; VI-SAFE-NEXT:    v_mul_f64 v[6:7], v[4:5], v[2:3]545; VI-SAFE-NEXT:    v_fma_f64 v[0:1], -v[0:1], v[6:7], v[4:5]546; VI-SAFE-NEXT:    v_mov_b32_e32 v4, s0547; VI-SAFE-NEXT:    v_div_fmas_f64 v[0:1], v[0:1], v[2:3], v[6:7]548; VI-SAFE-NEXT:    v_mov_b32_e32 v2, s1549; VI-SAFE-NEXT:    v_div_fixup_f64 v[0:1], v[0:1], s[2:3], 1.0550; VI-SAFE-NEXT:    v_mul_f64 v[0:1], v[0:1], 0551; VI-SAFE-NEXT:    v_add_f64 v[0:1], v[0:1], 0552; VI-SAFE-NEXT:    v_cmp_ngt_f64_e32 vcc, s[0:1], v[0:1]553; VI-SAFE-NEXT:    v_xor_b32_e32 v3, 0x80000000, v1554; VI-SAFE-NEXT:    v_cndmask_b32_e32 v1, v3, v2, vcc555; VI-SAFE-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc556; VI-SAFE-NEXT:    v_cmp_nlt_f64_e32 vcc, 0, v[0:1]557; VI-SAFE-NEXT:    s_and_b64 s[0:1], vcc, exec558; VI-SAFE-NEXT:    s_cselect_b32 s1, 0, 0x7ff80000559; VI-SAFE-NEXT:    s_mov_b32 s0, 0560; VI-SAFE-NEXT:    ; return to shader part epilog561;562; VI-NSZ-LABEL: fneg_fadd_0_f64:563; VI-NSZ:       ; %bb.0: ; %.entry564; VI-NSZ-NEXT:    v_div_scale_f64 v[0:1], s[4:5], s[2:3], s[2:3], 1.0565; VI-NSZ-NEXT:    v_rcp_f64_e32 v[2:3], v[0:1]566; VI-NSZ-NEXT:    v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0567; VI-NSZ-NEXT:    v_fma_f64 v[2:3], v[2:3], v[4:5], v[2:3]568; VI-NSZ-NEXT:    v_div_scale_f64 v[4:5], vcc, 1.0, s[2:3], 1.0569; VI-NSZ-NEXT:    v_fma_f64 v[6:7], -v[0:1], v[2:3], 1.0570; VI-NSZ-NEXT:    v_fma_f64 v[2:3], v[2:3], v[6:7], v[2:3]571; VI-NSZ-NEXT:    v_mul_f64 v[6:7], v[4:5], v[2:3]572; VI-NSZ-NEXT:    v_fma_f64 v[0:1], -v[0:1], v[6:7], v[4:5]573; VI-NSZ-NEXT:    v_div_fmas_f64 v[0:1], v[0:1], v[2:3], v[6:7]574; VI-NSZ-NEXT:    v_mov_b32_e32 v2, s1575; VI-NSZ-NEXT:    v_mov_b32_e32 v3, s0576; VI-NSZ-NEXT:    v_div_fixup_f64 v[0:1], v[0:1], s[2:3], 1.0577; VI-NSZ-NEXT:    s_mov_b32 s2, 0578; VI-NSZ-NEXT:    s_brev_b32 s3, 1579; VI-NSZ-NEXT:    v_mul_f64 v[0:1], v[0:1], 0580; VI-NSZ-NEXT:    v_fma_f64 v[0:1], v[0:1], s[2:3], s[2:3]581; VI-NSZ-NEXT:    v_cmp_nlt_f64_e64 vcc, -v[0:1], s[0:1]582; VI-NSZ-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc583; VI-NSZ-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc584; VI-NSZ-NEXT:    v_cmp_nlt_f64_e32 vcc, 0, v[0:1]585; VI-NSZ-NEXT:    s_and_b64 s[0:1], vcc, exec586; VI-NSZ-NEXT:    s_cselect_b32 s1, 0, 0x7ff80000587; VI-NSZ-NEXT:    s_mov_b32 s0, 0588; VI-NSZ-NEXT:    ; return to shader part epilog589.entry:590  %tmp7 = fdiv double 1.000000e+00, %tmp6591  %tmp8 = fmul double 0.000000e+00, %tmp7592  %tmp9 = fmul reassoc nnan arcp contract double 0.000000e+00, %tmp8593  %.i188 = fadd double %tmp9, 0.000000e+00594  %tmp10 = fcmp uge double %.i188, %tmp2595  %tmp11 = fneg double %.i188596  %.i092 = select i1 %tmp10, double %tmp2, double %tmp11597  %tmp12 = fcmp ule double %.i092, 0.000000e+00598  %.i198 = select i1 %tmp12, double 0.000000e+00, double 0x7FF8000000000000599  ret double %.i198600}601 602; This is a workaround because -enable-no-signed-zeros-fp-math does not set up603; function attribute unsafe-fp-math automatically. Combine with the previous test604; when that is done.605define amdgpu_ps double @fneg_fadd_0_nsz_f64(double inreg %tmp2, double inreg %tmp6, <4 x i32> %arg) #2 {606; SI-LABEL: fneg_fadd_0_nsz_f64:607; SI:       ; %bb.0: ; %.entry608; SI-NEXT:    v_rcp_f64_e32 v[0:1], s[2:3]609; SI-NEXT:    v_fma_f64 v[2:3], -s[2:3], v[0:1], 1.0610; SI-NEXT:    v_fma_f64 v[0:1], v[2:3], v[0:1], v[0:1]611; SI-NEXT:    v_fma_f64 v[2:3], -s[2:3], v[0:1], 1.0612; SI-NEXT:    v_fma_f64 v[0:1], v[2:3], v[0:1], v[0:1]613; SI-NEXT:    v_fma_f64 v[2:3], -s[2:3], v[0:1], 1.0614; SI-NEXT:    s_mov_b32 s2, 0615; SI-NEXT:    v_fma_f64 v[0:1], v[2:3], v[0:1], v[0:1]616; SI-NEXT:    s_brev_b32 s3, 1617; SI-NEXT:    v_mul_f64 v[0:1], v[0:1], s[2:3]618; SI-NEXT:    v_mov_b32_e32 v2, s1619; SI-NEXT:    v_cmp_nlt_f64_e64 vcc, -v[0:1], s[0:1]620; SI-NEXT:    v_mov_b32_e32 v3, s0621; SI-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc622; SI-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc623; SI-NEXT:    v_cmp_nlt_f64_e32 vcc, 0, v[0:1]624; SI-NEXT:    s_and_b64 s[0:1], vcc, exec625; SI-NEXT:    s_cselect_b32 s1, 0, 0x7ff80000626; SI-NEXT:    s_mov_b32 s0, 0627; SI-NEXT:    ; return to shader part epilog628;629; VI-LABEL: fneg_fadd_0_nsz_f64:630; VI:       ; %bb.0: ; %.entry631; VI-NEXT:    v_rcp_f64_e32 v[0:1], s[2:3]632; VI-NEXT:    v_fma_f64 v[2:3], -s[2:3], v[0:1], 1.0633; VI-NEXT:    v_fma_f64 v[0:1], v[2:3], v[0:1], v[0:1]634; VI-NEXT:    v_fma_f64 v[2:3], -s[2:3], v[0:1], 1.0635; VI-NEXT:    v_fma_f64 v[0:1], v[2:3], v[0:1], v[0:1]636; VI-NEXT:    v_fma_f64 v[2:3], -s[2:3], v[0:1], 1.0637; VI-NEXT:    s_mov_b32 s2, 0638; VI-NEXT:    s_brev_b32 s3, 1639; VI-NEXT:    v_fma_f64 v[0:1], v[2:3], v[0:1], v[0:1]640; VI-NEXT:    v_mov_b32_e32 v2, s1641; VI-NEXT:    v_mov_b32_e32 v3, s0642; VI-NEXT:    v_mul_f64 v[0:1], v[0:1], s[2:3]643; VI-NEXT:    v_cmp_nlt_f64_e64 vcc, -v[0:1], s[0:1]644; VI-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc645; VI-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc646; VI-NEXT:    v_cmp_nlt_f64_e32 vcc, 0, v[0:1]647; VI-NEXT:    s_and_b64 s[0:1], vcc, exec648; VI-NEXT:    s_cselect_b32 s1, 0, 0x7ff80000649; VI-NEXT:    s_mov_b32 s0, 0650; VI-NEXT:    ; return to shader part epilog651.entry:652  %tmp7 = fdiv afn double 1.000000e+00, %tmp6653  %tmp8 = fmul double 0.000000e+00, %tmp7654  %tmp9 = fmul reassoc nnan arcp contract double 0.000000e+00, %tmp8655  %.i188 = fadd nsz double %tmp9, 0.000000e+00656  %tmp10 = fcmp uge double %.i188, %tmp2657  %tmp11 = fneg double %.i188658  %.i092 = select i1 %tmp10, double %tmp2, double %tmp11659  %tmp12 = fcmp ule double %.i092, 0.000000e+00660  %.i198 = select i1 %tmp12, double 0.000000e+00, double 0x7FF8000000000000661  ret double %.i198662}663 664; --------------------------------------------------------------------------------665; fmul tests666; --------------------------------------------------------------------------------667 668define float @v_fneg_mul_f32(float %a, float %b) #0 {669; GCN-LABEL: v_fneg_mul_f32:670; GCN:       ; %bb.0:671; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)672; GCN-NEXT:    v_mul_f32_e64 v0, v0, -v1673; GCN-NEXT:    s_setpc_b64 s[30:31]674  %mul = fmul float %a, %b675  %fneg = fneg float %mul676  ret float %fneg677}678 679define { float, float } @v_fneg_mul_store_use_mul_f32(float %a, float %b) #0 {680; GCN-LABEL: v_fneg_mul_store_use_mul_f32:681; GCN:       ; %bb.0:682; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)683; GCN-NEXT:    v_mul_f32_e32 v1, v0, v1684; GCN-NEXT:    v_xor_b32_e32 v0, 0x80000000, v1685; GCN-NEXT:    s_setpc_b64 s[30:31]686  %mul = fmul float %a, %b687  %fneg = fneg float %mul688  %insert.0 = insertvalue { float, float } poison, float %fneg, 0689  %insert.1 = insertvalue { float, float } %insert.0, float %mul, 1690  ret { float, float } %insert.1691}692 693define { float, float } @v_fneg_mul_multi_use_mul_f32(float %a, float %b) #0 {694; GCN-LABEL: v_fneg_mul_multi_use_mul_f32:695; GCN:       ; %bb.0:696; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)697; GCN-NEXT:    v_mul_f32_e64 v0, v0, -v1698; GCN-NEXT:    v_mul_f32_e32 v1, -4.0, v0699; GCN-NEXT:    s_setpc_b64 s[30:31]700  %mul = fmul float %a, %b701  %fneg = fneg float %mul702  %use1 = fmul float %mul, 4.0703  %insert.0 = insertvalue { float, float } poison, float %fneg, 0704  %insert.1 = insertvalue { float, float } %insert.0, float %use1, 1705  ret { float, float } %insert.1706}707 708define float @v_fneg_mul_fneg_x_f32(float %a, float %b) #0 {709; GCN-LABEL: v_fneg_mul_fneg_x_f32:710; GCN:       ; %bb.0:711; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)712; GCN-NEXT:    v_mul_f32_e32 v0, v0, v1713; GCN-NEXT:    s_setpc_b64 s[30:31]714  %fneg.a = fneg float %a715  %mul = fmul float %fneg.a, %b716  %fneg = fneg float %mul717  ret float %fneg718}719 720define float @v_fneg_mul_x_fneg_f32(float %a, float %b) #0 {721; GCN-LABEL: v_fneg_mul_x_fneg_f32:722; GCN:       ; %bb.0:723; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)724; GCN-NEXT:    v_mul_f32_e32 v0, v0, v1725; GCN-NEXT:    s_setpc_b64 s[30:31]726  %fneg.b = fneg float %b727  %mul = fmul float %a, %fneg.b728  %fneg = fneg float %mul729  ret float %fneg730}731 732define float @v_fneg_mul_fneg_fneg_f32(float %a, float %b) #0 {733; GCN-LABEL: v_fneg_mul_fneg_fneg_f32:734; GCN:       ; %bb.0:735; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)736; GCN-NEXT:    v_mul_f32_e64 v0, v0, -v1737; GCN-NEXT:    s_setpc_b64 s[30:31]738  %fneg.a = fneg float %a739  %fneg.b = fneg float %b740  %mul = fmul float %fneg.a, %fneg.b741  %fneg = fneg float %mul742  ret float %fneg743}744 745define { float, float } @v_fneg_mul_store_use_fneg_x_f32(float %a, float %b) #0 {746; GCN-LABEL: v_fneg_mul_store_use_fneg_x_f32:747; GCN:       ; %bb.0:748; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)749; GCN-NEXT:    v_xor_b32_e32 v2, 0x80000000, v0750; GCN-NEXT:    v_mul_f32_e32 v0, v0, v1751; GCN-NEXT:    v_mov_b32_e32 v1, v2752; GCN-NEXT:    s_setpc_b64 s[30:31]753  %fneg.a = fneg float %a754  %mul = fmul float %fneg.a, %b755  %fneg = fneg float %mul756  %insert.0 = insertvalue { float, float } poison, float %fneg, 0757  %insert.1 = insertvalue { float, float } %insert.0, float %fneg.a, 1758  ret { float, float } %insert.1759}760 761define { float, float } @v_fneg_mul_multi_use_fneg_x_f32(float %a, float %b, float %c) #0 {762; GCN-LABEL: v_fneg_mul_multi_use_fneg_x_f32:763; GCN:       ; %bb.0:764; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)765; GCN-NEXT:    v_mul_f32_e32 v3, v0, v1766; GCN-NEXT:    v_mul_f32_e64 v1, -v0, v2767; GCN-NEXT:    v_mov_b32_e32 v0, v3768; GCN-NEXT:    s_setpc_b64 s[30:31]769  %fneg.a = fneg float %a770  %mul = fmul float %fneg.a, %b771  %fneg = fneg float %mul772  %use1 = fmul float %fneg.a, %c773  %insert.0 = insertvalue { float, float } poison, float %fneg, 0774  %insert.1 = insertvalue { float, float } %insert.0, float %use1, 1775  ret { float, float } %insert.1776}777 778; --------------------------------------------------------------------------------779; fminnum tests780; --------------------------------------------------------------------------------781 782define float @v_fneg_minnum_f32_ieee(float %a, float %b) #0 {783; GCN-LABEL: v_fneg_minnum_f32_ieee:784; GCN:       ; %bb.0:785; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)786; GCN-NEXT:    v_mul_f32_e32 v1, -1.0, v1787; GCN-NEXT:    v_mul_f32_e32 v0, -1.0, v0788; GCN-NEXT:    v_max_f32_e32 v0, v0, v1789; GCN-NEXT:    s_setpc_b64 s[30:31]790  %min = call float @llvm.minnum.f32(float %a, float %b)791  %fneg = fneg float %min792  ret float %fneg793}794 795define float @v_fneg_minnum_f32_no_ieee(float %a, float %b) #4 {796; GCN-LABEL: v_fneg_minnum_f32_no_ieee:797; GCN:       ; %bb.0:798; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)799; GCN-NEXT:    v_max_f32_e64 v0, -v0, -v1800; GCN-NEXT:    s_setpc_b64 s[30:31]801  %min = call float @llvm.minnum.f32(float %a, float %b)802  %fneg = fneg float %min803  ret float %fneg804}805 806define float @v_fneg_self_minnum_f32_ieee(float %a) #0 {807; GCN-LABEL: v_fneg_self_minnum_f32_ieee:808; GCN:       ; %bb.0:809; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)810; GCN-NEXT:    v_xor_b32_e32 v0, 0x80000000, v0811; GCN-NEXT:    s_setpc_b64 s[30:31]812  %min = call float @llvm.minnum.f32(float %a, float %a)813  %min.fneg = fneg float %min814  ret float %min.fneg815}816 817define float @v_fneg_self_minnum_f32_no_ieee(float %a) #4 {818; GCN-LABEL: v_fneg_self_minnum_f32_no_ieee:819; GCN:       ; %bb.0:820; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)821; GCN-NEXT:    v_xor_b32_e32 v0, 0x80000000, v0822; GCN-NEXT:    s_setpc_b64 s[30:31]823  %min = call float @llvm.minnum.f32(float %a, float %a)824  %min.fneg = fneg float %min825  ret float %min.fneg826}827 828define float @v_fneg_posk_minnum_f32_ieee(float %a) #0 {829; GCN-LABEL: v_fneg_posk_minnum_f32_ieee:830; GCN:       ; %bb.0:831; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)832; GCN-NEXT:    v_mul_f32_e32 v0, -1.0, v0833; GCN-NEXT:    v_max_f32_e32 v0, -4.0, v0834; GCN-NEXT:    s_setpc_b64 s[30:31]835  %min = call float @llvm.minnum.f32(float 4.0, float %a)836  %fneg = fneg float %min837  ret float %fneg838}839 840define float @v_fneg_posk_minnum_f32_no_ieee(float %a) #4 {841; GCN-LABEL: v_fneg_posk_minnum_f32_no_ieee:842; GCN:       ; %bb.0:843; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)844; GCN-NEXT:    v_max_f32_e64 v0, -v0, -4.0845; GCN-NEXT:    s_setpc_b64 s[30:31]846  %min = call float @llvm.minnum.f32(float 4.0, float %a)847  %fneg = fneg float %min848  ret float %fneg849}850 851define float @v_fneg_negk_minnum_f32_ieee(float %a) #0 {852; GCN-LABEL: v_fneg_negk_minnum_f32_ieee:853; GCN:       ; %bb.0:854; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)855; GCN-NEXT:    v_mul_f32_e32 v0, -1.0, v0856; GCN-NEXT:    v_max_f32_e32 v0, 4.0, v0857; GCN-NEXT:    s_setpc_b64 s[30:31]858  %min = call float @llvm.minnum.f32(float -4.0, float %a)859  %fneg = fneg float %min860  ret float %fneg861}862 863define float @v_fneg_negk_minnum_f32_no_ieee(float %a) #4 {864; GCN-LABEL: v_fneg_negk_minnum_f32_no_ieee:865; GCN:       ; %bb.0:866; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)867; GCN-NEXT:    v_max_f32_e64 v0, -v0, 4.0868; GCN-NEXT:    s_setpc_b64 s[30:31]869  %min = call float @llvm.minnum.f32(float -4.0, float %a)870  %fneg = fneg float %min871  ret float %fneg872}873 874define float @v_fneg_0_minnum_f32(float %a) #0 {875; GCN-LABEL: v_fneg_0_minnum_f32:876; GCN:       ; %bb.0:877; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)878; GCN-NEXT:    v_min_f32_e32 v0, 0, v0879; GCN-NEXT:    v_xor_b32_e32 v0, 0x80000000, v0880; GCN-NEXT:    s_setpc_b64 s[30:31]881  %min = call nnan float @llvm.minnum.f32(float 0.0, float %a)882  %fneg = fneg float %min883  ret float %fneg884}885 886define float @v_fneg_neg0_minnum_f32_ieee(float %a) #0 {887; GCN-LABEL: v_fneg_neg0_minnum_f32_ieee:888; GCN:       ; %bb.0:889; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)890; GCN-NEXT:    v_mul_f32_e32 v0, -1.0, v0891; GCN-NEXT:    v_max_f32_e32 v0, 0, v0892; GCN-NEXT:    s_setpc_b64 s[30:31]893  %min = call float @llvm.minnum.f32(float -0.0, float %a)894  %fneg = fneg float %min895  ret float %fneg896}897 898define float @v_fneg_inv2pi_minnum_f32(float %a) #0 {899; SI-LABEL: v_fneg_inv2pi_minnum_f32:900; SI:       ; %bb.0:901; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)902; SI-NEXT:    v_mul_f32_e32 v0, -1.0, v0903; SI-NEXT:    v_max_f32_e32 v0, 0xbe22f983, v0904; SI-NEXT:    s_setpc_b64 s[30:31]905;906; VI-LABEL: v_fneg_inv2pi_minnum_f32:907; VI:       ; %bb.0:908; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)909; VI-NEXT:    v_mul_f32_e32 v0, 1.0, v0910; VI-NEXT:    v_min_f32_e32 v0, 0.15915494, v0911; VI-NEXT:    v_xor_b32_e32 v0, 0x80000000, v0912; VI-NEXT:    s_setpc_b64 s[30:31]913  %min = call float @llvm.minnum.f32(float 0x3FC45F3060000000, float %a)914  %fneg = fneg float %min915  ret float %fneg916}917 918define float @v_fneg_neg_inv2pi_minnum_f32(float %a) #0 {919; SI-LABEL: v_fneg_neg_inv2pi_minnum_f32:920; SI:       ; %bb.0:921; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)922; SI-NEXT:    v_mul_f32_e32 v0, -1.0, v0923; SI-NEXT:    v_max_f32_e32 v0, 0x3e22f983, v0924; SI-NEXT:    s_setpc_b64 s[30:31]925;926; VI-LABEL: v_fneg_neg_inv2pi_minnum_f32:927; VI:       ; %bb.0:928; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)929; VI-NEXT:    v_mul_f32_e32 v0, -1.0, v0930; VI-NEXT:    v_max_f32_e32 v0, 0.15915494, v0931; VI-NEXT:    s_setpc_b64 s[30:31]932  %min = call float @llvm.minnum.f32(float 0xBFC45F3060000000, float %a)933  %fneg = fneg float %min934  ret float %fneg935}936 937define half @v_fneg_inv2pi_minnum_f16(half %a) #0 {938; SI-LABEL: v_fneg_inv2pi_minnum_f16:939; SI:       ; %bb.0:940; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)941; SI-NEXT:    v_cvt_f16_f32_e64 v0, -v0942; SI-NEXT:    v_cvt_f32_f16_e32 v0, v0943; SI-NEXT:    v_max_f32_e32 v0, 0xbe230000, v0944; SI-NEXT:    s_setpc_b64 s[30:31]945;946; VI-LABEL: v_fneg_inv2pi_minnum_f16:947; VI:       ; %bb.0:948; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)949; VI-NEXT:    v_max_f16_e32 v0, v0, v0950; VI-NEXT:    v_min_f16_e32 v0, 0.15915494, v0951; VI-NEXT:    v_xor_b32_e32 v0, 0x8000, v0952; VI-NEXT:    s_setpc_b64 s[30:31]953  %min = call half @llvm.minnum.f16(half 0xH3118, half %a)954  %fneg = fneg half %min955  ret half %fneg956}957 958define half @v_fneg_neg_inv2pi_minnum_f16(half %a) #0 {959; SI-LABEL: v_fneg_neg_inv2pi_minnum_f16:960; SI:       ; %bb.0:961; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)962; SI-NEXT:    v_cvt_f16_f32_e64 v0, -v0963; SI-NEXT:    v_cvt_f32_f16_e32 v0, v0964; SI-NEXT:    v_max_f32_e32 v0, 0x3e230000, v0965; SI-NEXT:    s_setpc_b64 s[30:31]966;967; VI-LABEL: v_fneg_neg_inv2pi_minnum_f16:968; VI:       ; %bb.0:969; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)970; VI-NEXT:    v_max_f16_e64 v0, -v0, -v0971; VI-NEXT:    v_max_f16_e32 v0, 0.15915494, v0972; VI-NEXT:    s_setpc_b64 s[30:31]973  %min = call half @llvm.minnum.f16(half 0xHB118, half %a)974  %fneg = fneg half %min975  ret half %fneg976}977 978define double @v_fneg_inv2pi_minnum_f64(double %a) #0 {979; SI-LABEL: v_fneg_inv2pi_minnum_f64:980; SI:       ; %bb.0:981; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)982; SI-NEXT:    v_max_f64 v[0:1], -v[0:1], -v[0:1]983; SI-NEXT:    s_mov_b32 s4, 0x6dc9c882984; SI-NEXT:    s_mov_b32 s5, 0xbfc45f30985; SI-NEXT:    v_max_f64 v[0:1], v[0:1], s[4:5]986; SI-NEXT:    s_setpc_b64 s[30:31]987;988; VI-LABEL: v_fneg_inv2pi_minnum_f64:989; VI:       ; %bb.0:990; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)991; VI-NEXT:    v_max_f64 v[0:1], v[0:1], v[0:1]992; VI-NEXT:    v_min_f64 v[0:1], v[0:1], 0.15915494309189532993; VI-NEXT:    v_xor_b32_e32 v1, 0x80000000, v1994; VI-NEXT:    s_setpc_b64 s[30:31]995  %min = call double @llvm.minnum.f64(double 0x3fc45f306dc9c882, double %a)996  %fneg = fneg double %min997  ret double %fneg998}999 1000define double @v_fneg_neg_inv2pi_minnum_f64(double %a) #0 {1001; SI-LABEL: v_fneg_neg_inv2pi_minnum_f64:1002; SI:       ; %bb.0:1003; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1004; SI-NEXT:    v_max_f64 v[0:1], -v[0:1], -v[0:1]1005; SI-NEXT:    s_mov_b32 s4, 0x6dc9c8821006; SI-NEXT:    s_mov_b32 s5, 0x3fc45f301007; SI-NEXT:    v_max_f64 v[0:1], v[0:1], s[4:5]1008; SI-NEXT:    s_setpc_b64 s[30:31]1009;1010; VI-LABEL: v_fneg_neg_inv2pi_minnum_f64:1011; VI:       ; %bb.0:1012; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1013; VI-NEXT:    v_max_f64 v[0:1], -v[0:1], -v[0:1]1014; VI-NEXT:    v_max_f64 v[0:1], v[0:1], 0.159154943091895321015; VI-NEXT:    s_setpc_b64 s[30:31]1016  %min = call double @llvm.minnum.f64(double 0xbfc45f306dc9c882, double %a)1017  %fneg = fneg double %min1018  ret double %fneg1019}1020 1021define float @v_fneg_neg0_minnum_f32_no_ieee(float %a) #4 {1022; GCN-LABEL: v_fneg_neg0_minnum_f32_no_ieee:1023; GCN:       ; %bb.0:1024; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1025; GCN-NEXT:    v_max_f32_e64 v0, -v0, 01026; GCN-NEXT:    s_setpc_b64 s[30:31]1027  %min = call float @llvm.minnum.f32(float -0.0, float %a)1028  %fneg = fneg float %min1029  ret float %fneg1030}1031 1032define float @v_fneg_0_minnum_foldable_use_f32_ieee(float %a, float %b) #0 {1033; GCN-LABEL: v_fneg_0_minnum_foldable_use_f32_ieee:1034; GCN:       ; %bb.0:1035; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1036; GCN-NEXT:    v_mul_f32_e32 v0, 1.0, v01037; GCN-NEXT:    v_min_f32_e32 v0, 0, v01038; GCN-NEXT:    v_mul_f32_e64 v0, -v0, v11039; GCN-NEXT:    s_setpc_b64 s[30:31]1040  %min = call float @llvm.minnum.f32(float 0.0, float %a)1041  %fneg = fneg float %min1042  %mul = fmul float %fneg, %b1043  ret float %mul1044}1045 1046define float @v_fneg_inv2pi_minnum_foldable_use_f32(float %a, float %b) #0 {1047; SI-LABEL: v_fneg_inv2pi_minnum_foldable_use_f32:1048; SI:       ; %bb.0:1049; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1050; SI-NEXT:    v_mul_f32_e32 v0, -1.0, v01051; SI-NEXT:    v_max_f32_e32 v0, 0xbe22f983, v01052; SI-NEXT:    v_mul_f32_e32 v0, v0, v11053; SI-NEXT:    s_setpc_b64 s[30:31]1054;1055; VI-LABEL: v_fneg_inv2pi_minnum_foldable_use_f32:1056; VI:       ; %bb.0:1057; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1058; VI-NEXT:    v_mul_f32_e32 v0, 1.0, v01059; VI-NEXT:    v_min_f32_e32 v0, 0.15915494, v01060; VI-NEXT:    v_mul_f32_e64 v0, -v0, v11061; VI-NEXT:    s_setpc_b64 s[30:31]1062  %min = call float @llvm.minnum.f32(float 0x3FC45F3060000000, float %a)1063  %fneg = fneg float %min1064  %mul = fmul float %fneg, %b1065  ret float %mul1066}1067 1068define float @v_fneg_0_minnum_foldable_use_f32_no_ieee(float %a, float %b) #4 {1069; GCN-LABEL: v_fneg_0_minnum_foldable_use_f32_no_ieee:1070; GCN:       ; %bb.0:1071; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1072; GCN-NEXT:    v_min_f32_e32 v0, 0, v01073; GCN-NEXT:    v_mul_f32_e64 v0, -v0, v11074; GCN-NEXT:    s_setpc_b64 s[30:31]1075  %min = call float @llvm.minnum.f32(float 0.0, float %a)1076  %fneg = fneg float %min1077  %mul = fmul float %fneg, %b1078  ret float %mul1079}1080 1081define { float, float } @v_fneg_minnum_multi_use_minnum_f32_ieee(float %a, float %b) #0 {1082; GCN-LABEL: v_fneg_minnum_multi_use_minnum_f32_ieee:1083; GCN:       ; %bb.0:1084; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1085; GCN-NEXT:    v_mul_f32_e32 v1, -1.0, v11086; GCN-NEXT:    v_mul_f32_e32 v0, -1.0, v01087; GCN-NEXT:    v_max_f32_e32 v0, v0, v11088; GCN-NEXT:    v_mul_f32_e32 v1, -4.0, v01089; GCN-NEXT:    s_setpc_b64 s[30:31]1090  %min = call float @llvm.minnum.f32(float %a, float %b)1091  %fneg = fneg float %min1092  %use1 = fmul float %min, 4.01093  %insert.0 = insertvalue { float, float } poison, float %fneg, 01094  %insert.1 = insertvalue { float, float } %insert.0, float %use1, 11095  ret { float, float } %insert.11096}1097 1098define <2 x float> @v_fneg_minnum_multi_use_minnum_f32_no_ieee(float %a, float %b) #4 {1099; GCN-LABEL: v_fneg_minnum_multi_use_minnum_f32_no_ieee:1100; GCN:       ; %bb.0:1101; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1102; GCN-NEXT:    v_max_f32_e64 v0, -v0, -v11103; GCN-NEXT:    v_mul_f32_e32 v1, -4.0, v01104; GCN-NEXT:    s_setpc_b64 s[30:31]1105  %min = call float @llvm.minnum.f32(float %a, float %b)1106  %fneg = fneg float %min1107  %use1 = fmul float %min, 4.01108  %ins0 = insertelement <2 x float> poison, float %fneg, i32 01109  %ins1 = insertelement <2 x float> %ins0, float %use1, i32 11110  ret <2 x float> %ins11111}1112 1113; --------------------------------------------------------------------------------1114; fmaxnum tests1115; --------------------------------------------------------------------------------1116 1117define float @v_fneg_maxnum_f32_ieee(float %a, float %b) #0 {1118; GCN-LABEL: v_fneg_maxnum_f32_ieee:1119; GCN:       ; %bb.0:1120; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1121; GCN-NEXT:    v_mul_f32_e32 v1, -1.0, v11122; GCN-NEXT:    v_mul_f32_e32 v0, -1.0, v01123; GCN-NEXT:    v_min_f32_e32 v0, v0, v11124; GCN-NEXT:    s_setpc_b64 s[30:31]1125  %max = call float @llvm.maxnum.f32(float %a, float %b)1126  %fneg = fneg float %max1127  ret float %fneg1128}1129 1130define float @v_fneg_maxnum_f32_no_ieee(float %a, float %b) #4 {1131; GCN-LABEL: v_fneg_maxnum_f32_no_ieee:1132; GCN:       ; %bb.0:1133; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1134; GCN-NEXT:    v_min_f32_e64 v0, -v0, -v11135; GCN-NEXT:    s_setpc_b64 s[30:31]1136  %max = call float @llvm.maxnum.f32(float %a, float %b)1137  %fneg = fneg float %max1138  ret float %fneg1139}1140 1141define float @v_fneg_self_maxnum_f32_ieee(float %a) #0 {1142; GCN-LABEL: v_fneg_self_maxnum_f32_ieee:1143; GCN:       ; %bb.0:1144; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1145; GCN-NEXT:    v_xor_b32_e32 v0, 0x80000000, v01146; GCN-NEXT:    s_setpc_b64 s[30:31]1147  %max = call float @llvm.maxnum.f32(float %a, float %a)1148  %max.fneg = fneg float %max1149  ret float %max.fneg1150}1151 1152define float @v_fneg_self_maxnum_f32_no_ieee(float %a) #4 {1153; GCN-LABEL: v_fneg_self_maxnum_f32_no_ieee:1154; GCN:       ; %bb.0:1155; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1156; GCN-NEXT:    v_xor_b32_e32 v0, 0x80000000, v01157; GCN-NEXT:    s_setpc_b64 s[30:31]1158  %max = call float @llvm.maxnum.f32(float %a, float %a)1159  %max.fneg = fneg float %max1160  ret float %max.fneg1161}1162 1163define float @v_fneg_posk_maxnum_f32_ieee(float %a) #0 {1164; GCN-LABEL: v_fneg_posk_maxnum_f32_ieee:1165; GCN:       ; %bb.0:1166; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1167; GCN-NEXT:    v_mul_f32_e32 v0, -1.0, v01168; GCN-NEXT:    v_min_f32_e32 v0, -4.0, v01169; GCN-NEXT:    s_setpc_b64 s[30:31]1170  %max = call float @llvm.maxnum.f32(float 4.0, float %a)1171  %fneg = fneg float %max1172  ret float %fneg1173}1174 1175define float @v_fneg_posk_maxnum_f32_no_ieee(float %a) #4 {1176; GCN-LABEL: v_fneg_posk_maxnum_f32_no_ieee:1177; GCN:       ; %bb.0:1178; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1179; GCN-NEXT:    v_min_f32_e64 v0, -v0, -4.01180; GCN-NEXT:    s_setpc_b64 s[30:31]1181  %max = call float @llvm.maxnum.f32(float 4.0, float %a)1182  %fneg = fneg float %max1183  ret float %fneg1184}1185 1186define float @v_fneg_negk_maxnum_f32_ieee(float %a) #0 {1187; GCN-LABEL: v_fneg_negk_maxnum_f32_ieee:1188; GCN:       ; %bb.0:1189; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1190; GCN-NEXT:    v_mul_f32_e32 v0, -1.0, v01191; GCN-NEXT:    v_min_f32_e32 v0, 4.0, v01192; GCN-NEXT:    s_setpc_b64 s[30:31]1193  %max = call float @llvm.maxnum.f32(float -4.0, float %a)1194  %fneg = fneg float %max1195  ret float %fneg1196}1197 1198define float @v_fneg_negk_maxnum_f32_no_ieee(float %a) #4 {1199; GCN-LABEL: v_fneg_negk_maxnum_f32_no_ieee:1200; GCN:       ; %bb.0:1201; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1202; GCN-NEXT:    v_min_f32_e64 v0, -v0, 4.01203; GCN-NEXT:    s_setpc_b64 s[30:31]1204  %max = call float @llvm.maxnum.f32(float -4.0, float %a)1205  %fneg = fneg float %max1206  ret float %fneg1207}1208 1209define float @v_fneg_0_maxnum_f32(float %a) #0 {1210; GCN-LABEL: v_fneg_0_maxnum_f32:1211; GCN:       ; %bb.0:1212; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1213; GCN-NEXT:    v_max_f32_e32 v0, 0, v01214; GCN-NEXT:    v_xor_b32_e32 v0, 0x80000000, v01215; GCN-NEXT:    s_setpc_b64 s[30:31]1216  %max = call nnan float @llvm.maxnum.f32(float 0.0, float %a)1217  %fneg = fneg float %max1218  ret float %fneg1219}1220 1221define float @v_fneg_neg0_maxnum_f32_ieee(float %a) #0 {1222; GCN-LABEL: v_fneg_neg0_maxnum_f32_ieee:1223; GCN:       ; %bb.0:1224; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1225; GCN-NEXT:    v_mul_f32_e32 v0, -1.0, v01226; GCN-NEXT:    v_min_f32_e32 v0, 0, v01227; GCN-NEXT:    s_setpc_b64 s[30:31]1228  %max = call float @llvm.maxnum.f32(float -0.0, float %a)1229  %fneg = fneg float %max1230  ret float %fneg1231}1232 1233define float @v_fneg_neg0_maxnum_f32_no_ieee(float %a) #4 {1234; GCN-LABEL: v_fneg_neg0_maxnum_f32_no_ieee:1235; GCN:       ; %bb.0:1236; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1237; GCN-NEXT:    v_min_f32_e64 v0, -v0, 01238; GCN-NEXT:    s_setpc_b64 s[30:31]1239  %max = call float @llvm.maxnum.f32(float -0.0, float %a)1240  %fneg = fneg float %max1241  ret float %fneg1242}1243 1244define float @v_fneg_0_maxnum_foldable_use_f32_ieee(float %a, float %b) #0 {1245; GCN-LABEL: v_fneg_0_maxnum_foldable_use_f32_ieee:1246; GCN:       ; %bb.0:1247; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1248; GCN-NEXT:    v_mul_f32_e32 v0, 1.0, v01249; GCN-NEXT:    v_max_f32_e32 v0, 0, v01250; GCN-NEXT:    v_mul_f32_e64 v0, -v0, v11251; GCN-NEXT:    s_setpc_b64 s[30:31]1252  %max = call float @llvm.maxnum.f32(float 0.0, float %a)1253  %fneg = fneg float %max1254  %mul = fmul float %fneg, %b1255  ret float %mul1256}1257 1258define float @v_fneg_0_maxnum_foldable_use_f32_no_ieee(float %a, float %b) #4 {1259; GCN-LABEL: v_fneg_0_maxnum_foldable_use_f32_no_ieee:1260; GCN:       ; %bb.0:1261; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1262; GCN-NEXT:    v_max_f32_e32 v0, 0, v01263; GCN-NEXT:    v_mul_f32_e64 v0, -v0, v11264; GCN-NEXT:    s_setpc_b64 s[30:31]1265  %max = call float @llvm.maxnum.f32(float 0.0, float %a)1266  %fneg = fneg float %max1267  %mul = fmul float %fneg, %b1268  ret float %mul1269}1270 1271define { float, float } @v_fneg_maxnum_multi_use_maxnum_f32_ieee(float %a, float %b) #0 {1272; GCN-LABEL: v_fneg_maxnum_multi_use_maxnum_f32_ieee:1273; GCN:       ; %bb.0:1274; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1275; GCN-NEXT:    v_mul_f32_e32 v1, -1.0, v11276; GCN-NEXT:    v_mul_f32_e32 v0, -1.0, v01277; GCN-NEXT:    v_min_f32_e32 v0, v0, v11278; GCN-NEXT:    v_mul_f32_e32 v1, -4.0, v01279; GCN-NEXT:    s_setpc_b64 s[30:31]1280  %max = call float @llvm.maxnum.f32(float %a, float %b)1281  %fneg = fneg float %max1282  %use1 = fmul float %max, 4.01283  %insert.0 = insertvalue { float, float } poison, float %fneg, 01284  %insert.1 = insertvalue { float, float } %insert.0, float %use1, 11285  ret { float, float } %insert.11286}1287 1288define <2 x float> @v_fneg_maxnum_multi_use_maxnum_f32_no_ieee(float %a, float %b) #4 {1289; GCN-LABEL: v_fneg_maxnum_multi_use_maxnum_f32_no_ieee:1290; GCN:       ; %bb.0:1291; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1292; GCN-NEXT:    v_min_f32_e64 v0, -v0, -v11293; GCN-NEXT:    v_mul_f32_e32 v1, -4.0, v01294; GCN-NEXT:    s_setpc_b64 s[30:31]1295  %max = call float @llvm.maxnum.f32(float %a, float %b)1296  %fneg = fneg float %max1297  %use1 = fmul float %max, 4.01298  %ins0 = insertelement <2 x float> poison, float %fneg, i32 01299  %ins1 = insertelement <2 x float> %ins0, float %use1, i32 11300  ret <2 x float> %ins11301}1302 1303; --------------------------------------------------------------------------------1304; fminimum tests1305; --------------------------------------------------------------------------------1306 1307define float @v_fneg_minimum_f32_ieee(float %a, float %b) #0 {1308; GCN-LABEL: v_fneg_minimum_f32_ieee:1309; GCN:       ; %bb.0:1310; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1311; GCN-NEXT:    v_max_f32_e64 v2, -v0, -v11312; GCN-NEXT:    v_mov_b32_e32 v3, 0x7fc000001313; GCN-NEXT:    v_cmp_o_f32_e64 vcc, -v0, -v11314; GCN-NEXT:    v_cndmask_b32_e32 v0, v3, v2, vcc1315; GCN-NEXT:    s_setpc_b64 s[30:31]1316  %min = call float @llvm.minimum.f32(float %a, float %b)1317  %fneg = fneg float %min1318  ret float %fneg1319}1320 1321define float @v_fneg_minimum_f32_no_ieee(float %a, float %b) #4 {1322; GCN-LABEL: v_fneg_minimum_f32_no_ieee:1323; GCN:       ; %bb.0:1324; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1325; GCN-NEXT:    v_max_f32_e64 v2, -v0, -v11326; GCN-NEXT:    v_mov_b32_e32 v3, 0x7fc000001327; GCN-NEXT:    v_cmp_o_f32_e64 vcc, -v0, -v11328; GCN-NEXT:    v_cndmask_b32_e32 v0, v3, v2, vcc1329; GCN-NEXT:    s_setpc_b64 s[30:31]1330  %min = call float @llvm.minimum.f32(float %a, float %b)1331  %fneg = fneg float %min1332  ret float %fneg1333}1334 1335define float @v_fneg_self_minimum_f32_ieee(float %a) #0 {1336; GCN-LABEL: v_fneg_self_minimum_f32_ieee:1337; GCN:       ; %bb.0:1338; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1339; GCN-NEXT:    v_xor_b32_e32 v0, 0x80000000, v01340; GCN-NEXT:    s_setpc_b64 s[30:31]1341  %min = call float @llvm.minimum.f32(float %a, float %a)1342  %min.fneg = fneg float %min1343  ret float %min.fneg1344}1345 1346define float @v_fneg_self_minimum_f32_no_ieee(float %a) #4 {1347; GCN-LABEL: v_fneg_self_minimum_f32_no_ieee:1348; GCN:       ; %bb.0:1349; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1350; GCN-NEXT:    v_xor_b32_e32 v0, 0x80000000, v01351; GCN-NEXT:    s_setpc_b64 s[30:31]1352  %min = call float @llvm.minimum.f32(float %a, float %a)1353  %min.fneg = fneg float %min1354  ret float %min.fneg1355}1356 1357define float @v_fneg_posk_minimum_f32_ieee(float %a) #0 {1358; GCN-LABEL: v_fneg_posk_minimum_f32_ieee:1359; GCN:       ; %bb.0:1360; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1361; GCN-NEXT:    v_max_f32_e64 v1, -v0, -4.01362; GCN-NEXT:    v_mov_b32_e32 v2, 0x7fc000001363; GCN-NEXT:    v_cmp_o_f32_e64 vcc, -v0, -v01364; GCN-NEXT:    v_cndmask_b32_e32 v0, v2, v1, vcc1365; GCN-NEXT:    s_setpc_b64 s[30:31]1366  %min = call float @llvm.minimum.f32(float 4.0, float %a)1367  %fneg = fneg float %min1368  ret float %fneg1369}1370 1371define float @v_fneg_posk_minimum_f32_no_ieee(float %a) #4 {1372; GCN-LABEL: v_fneg_posk_minimum_f32_no_ieee:1373; GCN:       ; %bb.0:1374; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1375; GCN-NEXT:    v_max_f32_e64 v1, -v0, -4.01376; GCN-NEXT:    v_mov_b32_e32 v2, 0x7fc000001377; GCN-NEXT:    v_cmp_o_f32_e64 vcc, -v0, -v01378; GCN-NEXT:    v_cndmask_b32_e32 v0, v2, v1, vcc1379; GCN-NEXT:    s_setpc_b64 s[30:31]1380  %min = call float @llvm.minimum.f32(float 4.0, float %a)1381  %fneg = fneg float %min1382  ret float %fneg1383}1384 1385define float @v_fneg_negk_minimum_f32_ieee(float %a) #0 {1386; GCN-LABEL: v_fneg_negk_minimum_f32_ieee:1387; GCN:       ; %bb.0:1388; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1389; GCN-NEXT:    v_max_f32_e64 v1, -v0, 4.01390; GCN-NEXT:    v_mov_b32_e32 v2, 0x7fc000001391; GCN-NEXT:    v_cmp_o_f32_e64 vcc, -v0, -v01392; GCN-NEXT:    v_cndmask_b32_e32 v0, v2, v1, vcc1393; GCN-NEXT:    s_setpc_b64 s[30:31]1394  %min = call float @llvm.minimum.f32(float -4.0, float %a)1395  %fneg = fneg float %min1396  ret float %fneg1397}1398 1399define float @v_fneg_negk_minimum_f32_no_ieee(float %a) #4 {1400; GCN-LABEL: v_fneg_negk_minimum_f32_no_ieee:1401; GCN:       ; %bb.0:1402; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1403; GCN-NEXT:    v_max_f32_e64 v1, -v0, 4.01404; GCN-NEXT:    v_mov_b32_e32 v2, 0x7fc000001405; GCN-NEXT:    v_cmp_o_f32_e64 vcc, -v0, -v01406; GCN-NEXT:    v_cndmask_b32_e32 v0, v2, v1, vcc1407; GCN-NEXT:    s_setpc_b64 s[30:31]1408  %min = call float @llvm.minimum.f32(float -4.0, float %a)1409  %fneg = fneg float %min1410  ret float %fneg1411}1412 1413define float @v_fneg_0_minimum_f32(float %a) #0 {1414; GCN-LABEL: v_fneg_0_minimum_f32:1415; GCN:       ; %bb.0:1416; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1417; GCN-NEXT:    v_min_f32_e32 v0, 0, v01418; GCN-NEXT:    v_xor_b32_e32 v0, 0x80000000, v01419; GCN-NEXT:    s_setpc_b64 s[30:31]1420  %min = call nnan float @llvm.minimum.f32(float 0.0, float %a)1421  %fneg = fneg float %min1422  ret float %fneg1423}1424 1425define float @v_fneg_neg0_minimum_f32_ieee(float %a) #0 {1426; GCN-LABEL: v_fneg_neg0_minimum_f32_ieee:1427; GCN:       ; %bb.0:1428; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1429; GCN-NEXT:    v_max_f32_e64 v1, -v0, 01430; GCN-NEXT:    v_mov_b32_e32 v2, 0x7fc000001431; GCN-NEXT:    v_cmp_o_f32_e64 vcc, -v0, -v01432; GCN-NEXT:    v_cndmask_b32_e32 v0, v2, v1, vcc1433; GCN-NEXT:    s_setpc_b64 s[30:31]1434  %min = call float @llvm.minimum.f32(float -0.0, float %a)1435  %fneg = fneg float %min1436  ret float %fneg1437}1438 1439define float @v_fneg_inv2pi_minimum_f32(float %a) #0 {1440; SI-LABEL: v_fneg_inv2pi_minimum_f32:1441; SI:       ; %bb.0:1442; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1443; SI-NEXT:    s_mov_b32 s4, 0xbe22f9831444; SI-NEXT:    v_max_f32_e64 v1, -v0, s41445; SI-NEXT:    v_mov_b32_e32 v2, 0x7fc000001446; SI-NEXT:    v_cmp_o_f32_e64 vcc, -v0, -v01447; SI-NEXT:    v_cndmask_b32_e32 v0, v2, v1, vcc1448; SI-NEXT:    s_setpc_b64 s[30:31]1449;1450; VI-LABEL: v_fneg_inv2pi_minimum_f32:1451; VI:       ; %bb.0:1452; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1453; VI-NEXT:    v_min_f32_e32 v1, 0.15915494, v01454; VI-NEXT:    v_mov_b32_e32 v2, 0x7fc000001455; VI-NEXT:    v_cmp_o_f32_e32 vcc, v0, v01456; VI-NEXT:    v_cndmask_b32_e32 v0, v2, v1, vcc1457; VI-NEXT:    v_xor_b32_e32 v0, 0x80000000, v01458; VI-NEXT:    s_setpc_b64 s[30:31]1459  %min = call float @llvm.minimum.f32(float 0x3FC45F3060000000, float %a)1460  %fneg = fneg float %min1461  ret float %fneg1462}1463 1464define float @v_fneg_neg_inv2pi_minimum_f32(float %a) #0 {1465; SI-LABEL: v_fneg_neg_inv2pi_minimum_f32:1466; SI:       ; %bb.0:1467; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1468; SI-NEXT:    s_mov_b32 s4, 0x3e22f9831469; SI-NEXT:    v_max_f32_e64 v1, -v0, s41470; SI-NEXT:    v_mov_b32_e32 v2, 0x7fc000001471; SI-NEXT:    v_cmp_o_f32_e64 vcc, -v0, -v01472; SI-NEXT:    v_cndmask_b32_e32 v0, v2, v1, vcc1473; SI-NEXT:    s_setpc_b64 s[30:31]1474;1475; VI-LABEL: v_fneg_neg_inv2pi_minimum_f32:1476; VI:       ; %bb.0:1477; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1478; VI-NEXT:    v_max_f32_e64 v1, -v0, 0.159154941479; VI-NEXT:    v_mov_b32_e32 v2, 0x7fc000001480; VI-NEXT:    v_cmp_o_f32_e64 vcc, -v0, -v01481; VI-NEXT:    v_cndmask_b32_e32 v0, v2, v1, vcc1482; VI-NEXT:    s_setpc_b64 s[30:31]1483  %min = call float @llvm.minimum.f32(float 0xBFC45F3060000000, float %a)1484  %fneg = fneg float %min1485  ret float %fneg1486}1487 1488define half @v_fneg_inv2pi_minimum_f16(half %a) #0 {1489; SI-LABEL: v_fneg_inv2pi_minimum_f16:1490; SI:       ; %bb.0:1491; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1492; SI-NEXT:    v_cvt_f16_f32_e64 v0, -v01493; SI-NEXT:    v_mov_b32_e32 v1, 0x7fc000001494; SI-NEXT:    v_cvt_f32_f16_e32 v0, v01495; SI-NEXT:    v_max_f32_e32 v2, 0xbe230000, v01496; SI-NEXT:    v_cmp_o_f32_e32 vcc, v0, v01497; SI-NEXT:    v_cndmask_b32_e32 v0, v1, v2, vcc1498; SI-NEXT:    s_setpc_b64 s[30:31]1499;1500; VI-LABEL: v_fneg_inv2pi_minimum_f16:1501; VI:       ; %bb.0:1502; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1503; VI-NEXT:    v_min_f16_e32 v1, 0.15915494, v01504; VI-NEXT:    v_mov_b32_e32 v2, 0x7e001505; VI-NEXT:    v_cmp_o_f16_e32 vcc, v0, v01506; VI-NEXT:    v_cndmask_b32_e32 v0, v2, v1, vcc1507; VI-NEXT:    v_xor_b32_e32 v0, 0x8000, v01508; VI-NEXT:    s_setpc_b64 s[30:31]1509  %min = call half @llvm.minimum.f16(half 0xH3118, half %a)1510  %fneg = fneg half %min1511  ret half %fneg1512}1513 1514define half @v_fneg_neg_inv2pi_minimum_f16(half %a) #0 {1515; SI-LABEL: v_fneg_neg_inv2pi_minimum_f16:1516; SI:       ; %bb.0:1517; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1518; SI-NEXT:    v_cvt_f16_f32_e64 v0, -v01519; SI-NEXT:    v_mov_b32_e32 v1, 0x7fc000001520; SI-NEXT:    v_cvt_f32_f16_e32 v0, v01521; SI-NEXT:    v_max_f32_e32 v2, 0x3e230000, v01522; SI-NEXT:    v_cmp_o_f32_e32 vcc, v0, v01523; SI-NEXT:    v_cndmask_b32_e32 v0, v1, v2, vcc1524; SI-NEXT:    s_setpc_b64 s[30:31]1525;1526; VI-LABEL: v_fneg_neg_inv2pi_minimum_f16:1527; VI:       ; %bb.0:1528; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1529; VI-NEXT:    v_max_f16_e64 v1, -v0, 0.159154941530; VI-NEXT:    v_mov_b32_e32 v2, 0x7e001531; VI-NEXT:    v_cmp_o_f16_e64 vcc, -v0, -v01532; VI-NEXT:    v_cndmask_b32_e32 v0, v2, v1, vcc1533; VI-NEXT:    s_setpc_b64 s[30:31]1534  %min = call half @llvm.minimum.f16(half 0xHB118, half %a)1535  %fneg = fneg half %min1536  ret half %fneg1537}1538 1539define double @v_fneg_inv2pi_minimum_f64(double %a) #0 {1540; SI-LABEL: v_fneg_inv2pi_minimum_f64:1541; SI:       ; %bb.0:1542; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1543; SI-NEXT:    s_mov_b32 s4, 0x6dc9c8821544; SI-NEXT:    s_mov_b32 s5, 0xbfc45f301545; SI-NEXT:    v_max_f64 v[2:3], -v[0:1], s[4:5]1546; SI-NEXT:    v_cmp_u_f64_e64 vcc, -v[0:1], -v[0:1]1547; SI-NEXT:    v_mov_b32_e32 v1, 0x7ff800001548; SI-NEXT:    v_cndmask_b32_e64 v0, v2, 0, vcc1549; SI-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc1550; SI-NEXT:    s_setpc_b64 s[30:31]1551;1552; VI-LABEL: v_fneg_inv2pi_minimum_f64:1553; VI:       ; %bb.0:1554; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1555; VI-NEXT:    v_min_f64 v[2:3], v[0:1], 0.159154943091895321556; VI-NEXT:    v_cmp_u_f64_e32 vcc, v[0:1], v[0:1]1557; VI-NEXT:    v_mov_b32_e32 v1, 0xfff800001558; VI-NEXT:    v_cndmask_b32_e64 v0, v2, 0, vcc1559; VI-NEXT:    v_cndmask_b32_e64 v1, -v3, v1, vcc1560; VI-NEXT:    s_setpc_b64 s[30:31]1561  %min = call double @llvm.minimum.f64(double 0x3fc45f306dc9c882, double %a)1562  %fneg = fneg double %min1563  ret double %fneg1564}1565 1566define double @v_fneg_neg_inv2pi_minimum_f64(double %a) #0 {1567; SI-LABEL: v_fneg_neg_inv2pi_minimum_f64:1568; SI:       ; %bb.0:1569; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1570; SI-NEXT:    s_mov_b32 s4, 0x6dc9c8821571; SI-NEXT:    s_mov_b32 s5, 0x3fc45f301572; SI-NEXT:    v_max_f64 v[2:3], -v[0:1], s[4:5]1573; SI-NEXT:    v_cmp_u_f64_e64 vcc, -v[0:1], -v[0:1]1574; SI-NEXT:    v_mov_b32_e32 v1, 0x7ff800001575; SI-NEXT:    v_cndmask_b32_e64 v0, v2, 0, vcc1576; SI-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc1577; SI-NEXT:    s_setpc_b64 s[30:31]1578;1579; VI-LABEL: v_fneg_neg_inv2pi_minimum_f64:1580; VI:       ; %bb.0:1581; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1582; VI-NEXT:    v_max_f64 v[2:3], -v[0:1], 0.159154943091895321583; VI-NEXT:    v_cmp_u_f64_e64 vcc, -v[0:1], -v[0:1]1584; VI-NEXT:    v_mov_b32_e32 v1, 0x7ff800001585; VI-NEXT:    v_cndmask_b32_e64 v0, v2, 0, vcc1586; VI-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc1587; VI-NEXT:    s_setpc_b64 s[30:31]1588  %min = call double @llvm.minimum.f64(double 0xbfc45f306dc9c882, double %a)1589  %fneg = fneg double %min1590  ret double %fneg1591}1592 1593define float @v_fneg_neg0_minimum_f32_no_ieee(float %a) #4 {1594; GCN-LABEL: v_fneg_neg0_minimum_f32_no_ieee:1595; GCN:       ; %bb.0:1596; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1597; GCN-NEXT:    v_max_f32_e64 v1, -v0, 01598; GCN-NEXT:    v_mov_b32_e32 v2, 0x7fc000001599; GCN-NEXT:    v_cmp_o_f32_e64 vcc, -v0, -v01600; GCN-NEXT:    v_cndmask_b32_e32 v0, v2, v1, vcc1601; GCN-NEXT:    s_setpc_b64 s[30:31]1602  %min = call float @llvm.minimum.f32(float -0.0, float %a)1603  %fneg = fneg float %min1604  ret float %fneg1605}1606 1607define float @v_fneg_0_minimum_foldable_use_f32_ieee(float %a, float %b) #0 {1608; GCN-LABEL: v_fneg_0_minimum_foldable_use_f32_ieee:1609; GCN:       ; %bb.0:1610; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1611; GCN-NEXT:    v_min_f32_e32 v2, 0, v01612; GCN-NEXT:    v_mov_b32_e32 v3, 0x7fc000001613; GCN-NEXT:    v_cmp_o_f32_e32 vcc, v0, v01614; GCN-NEXT:    v_cndmask_b32_e32 v0, v3, v2, vcc1615; GCN-NEXT:    v_mul_f32_e64 v0, -v0, v11616; GCN-NEXT:    s_setpc_b64 s[30:31]1617  %min = call float @llvm.minimum.f32(float 0.0, float %a)1618  %fneg = fneg float %min1619  %mul = fmul float %fneg, %b1620  ret float %mul1621}1622 1623define float @v_fneg_inv2pi_minimum_foldable_use_f32(float %a, float %b) #0 {1624; SI-LABEL: v_fneg_inv2pi_minimum_foldable_use_f32:1625; SI:       ; %bb.0:1626; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1627; SI-NEXT:    s_mov_b32 s4, 0xbe22f9831628; SI-NEXT:    v_max_f32_e64 v2, -v0, s41629; SI-NEXT:    v_mov_b32_e32 v3, 0x7fc000001630; SI-NEXT:    v_cmp_o_f32_e64 vcc, -v0, -v01631; SI-NEXT:    v_cndmask_b32_e32 v0, v3, v2, vcc1632; SI-NEXT:    v_mul_f32_e32 v0, v0, v11633; SI-NEXT:    s_setpc_b64 s[30:31]1634;1635; VI-LABEL: v_fneg_inv2pi_minimum_foldable_use_f32:1636; VI:       ; %bb.0:1637; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1638; VI-NEXT:    v_min_f32_e32 v2, 0.15915494, v01639; VI-NEXT:    v_mov_b32_e32 v3, 0x7fc000001640; VI-NEXT:    v_cmp_o_f32_e32 vcc, v0, v01641; VI-NEXT:    v_cndmask_b32_e32 v0, v3, v2, vcc1642; VI-NEXT:    v_mul_f32_e64 v0, -v0, v11643; VI-NEXT:    s_setpc_b64 s[30:31]1644  %min = call float @llvm.minimum.f32(float 0x3FC45F3060000000, float %a)1645  %fneg = fneg float %min1646  %mul = fmul float %fneg, %b1647  ret float %mul1648}1649 1650define float @v_fneg_0_minimum_foldable_use_f32_no_ieee(float %a, float %b) #4 {1651; GCN-LABEL: v_fneg_0_minimum_foldable_use_f32_no_ieee:1652; GCN:       ; %bb.0:1653; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1654; GCN-NEXT:    v_min_f32_e32 v2, 0, v01655; GCN-NEXT:    v_mov_b32_e32 v3, 0x7fc000001656; GCN-NEXT:    v_cmp_o_f32_e32 vcc, v0, v01657; GCN-NEXT:    v_cndmask_b32_e32 v0, v3, v2, vcc1658; GCN-NEXT:    v_mul_f32_e64 v0, -v0, v11659; GCN-NEXT:    s_setpc_b64 s[30:31]1660  %min = call float @llvm.minimum.f32(float 0.0, float %a)1661  %fneg = fneg float %min1662  %mul = fmul float %fneg, %b1663  ret float %mul1664}1665 1666define { float, float } @v_fneg_minimum_multi_use_minimum_f32_ieee(float %a, float %b) #0 {1667; GCN-LABEL: v_fneg_minimum_multi_use_minimum_f32_ieee:1668; GCN:       ; %bb.0:1669; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1670; GCN-NEXT:    v_max_f32_e64 v2, -v0, -v11671; GCN-NEXT:    v_mov_b32_e32 v3, 0x7fc000001672; GCN-NEXT:    v_cmp_o_f32_e64 vcc, -v0, -v11673; GCN-NEXT:    v_cndmask_b32_e32 v0, v3, v2, vcc1674; GCN-NEXT:    v_mul_f32_e32 v1, -4.0, v01675; GCN-NEXT:    s_setpc_b64 s[30:31]1676  %min = call float @llvm.minimum.f32(float %a, float %b)1677  %fneg = fneg float %min1678  %use1 = fmul float %min, 4.01679  %insert.0 = insertvalue { float, float } poison, float %fneg, 01680  %insert.1 = insertvalue { float, float } %insert.0, float %use1, 11681  ret { float, float } %insert.11682}1683 1684define <2 x float> @v_fneg_minimum_multi_use_minimum_f32_no_ieee(float %a, float %b) #4 {1685; GCN-LABEL: v_fneg_minimum_multi_use_minimum_f32_no_ieee:1686; GCN:       ; %bb.0:1687; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1688; GCN-NEXT:    v_max_f32_e64 v2, -v0, -v11689; GCN-NEXT:    v_mov_b32_e32 v3, 0x7fc000001690; GCN-NEXT:    v_cmp_o_f32_e64 vcc, -v0, -v11691; GCN-NEXT:    v_cndmask_b32_e32 v0, v3, v2, vcc1692; GCN-NEXT:    v_mul_f32_e32 v1, -4.0, v01693; GCN-NEXT:    s_setpc_b64 s[30:31]1694  %min = call float @llvm.minimum.f32(float %a, float %b)1695  %fneg = fneg float %min1696  %use1 = fmul float %min, 4.01697  %ins0 = insertelement <2 x float> poison, float %fneg, i32 01698  %ins1 = insertelement <2 x float> %ins0, float %use1, i32 11699  ret <2 x float> %ins11700}1701 1702; --------------------------------------------------------------------------------1703; fmaximum tests1704; --------------------------------------------------------------------------------1705 1706define float @v_fneg_maximum_f32_ieee(float %a, float %b) #0 {1707; GCN-LABEL: v_fneg_maximum_f32_ieee:1708; GCN:       ; %bb.0:1709; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1710; GCN-NEXT:    v_min_f32_e64 v2, -v0, -v11711; GCN-NEXT:    v_mov_b32_e32 v3, 0x7fc000001712; GCN-NEXT:    v_cmp_o_f32_e64 vcc, -v0, -v11713; GCN-NEXT:    v_cndmask_b32_e32 v0, v3, v2, vcc1714; GCN-NEXT:    s_setpc_b64 s[30:31]1715  %max = call float @llvm.maximum.f32(float %a, float %b)1716  %fneg = fneg float %max1717  ret float %fneg1718}1719 1720define float @v_fneg_maximum_f32_no_ieee(float %a, float %b) #4 {1721; GCN-LABEL: v_fneg_maximum_f32_no_ieee:1722; GCN:       ; %bb.0:1723; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1724; GCN-NEXT:    v_min_f32_e64 v2, -v0, -v11725; GCN-NEXT:    v_mov_b32_e32 v3, 0x7fc000001726; GCN-NEXT:    v_cmp_o_f32_e64 vcc, -v0, -v11727; GCN-NEXT:    v_cndmask_b32_e32 v0, v3, v2, vcc1728; GCN-NEXT:    s_setpc_b64 s[30:31]1729  %max = call float @llvm.maximum.f32(float %a, float %b)1730  %fneg = fneg float %max1731  ret float %fneg1732}1733 1734define float @v_fneg_self_maximum_f32_ieee(float %a) #0 {1735; GCN-LABEL: v_fneg_self_maximum_f32_ieee:1736; GCN:       ; %bb.0:1737; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1738; GCN-NEXT:    v_xor_b32_e32 v0, 0x80000000, v01739; GCN-NEXT:    s_setpc_b64 s[30:31]1740  %max = call float @llvm.maximum.f32(float %a, float %a)1741  %max.fneg = fneg float %max1742  ret float %max.fneg1743}1744 1745define float @v_fneg_self_maximum_f32_no_ieee(float %a) #4 {1746; GCN-LABEL: v_fneg_self_maximum_f32_no_ieee:1747; GCN:       ; %bb.0:1748; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1749; GCN-NEXT:    v_xor_b32_e32 v0, 0x80000000, v01750; GCN-NEXT:    s_setpc_b64 s[30:31]1751  %max = call float @llvm.maximum.f32(float %a, float %a)1752  %max.fneg = fneg float %max1753  ret float %max.fneg1754}1755 1756define float @v_fneg_posk_maximum_f32_ieee(float %a) #0 {1757; GCN-LABEL: v_fneg_posk_maximum_f32_ieee:1758; GCN:       ; %bb.0:1759; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1760; GCN-NEXT:    v_min_f32_e64 v1, -v0, -4.01761; GCN-NEXT:    v_mov_b32_e32 v2, 0x7fc000001762; GCN-NEXT:    v_cmp_o_f32_e64 vcc, -v0, -v01763; GCN-NEXT:    v_cndmask_b32_e32 v0, v2, v1, vcc1764; GCN-NEXT:    s_setpc_b64 s[30:31]1765  %max = call float @llvm.maximum.f32(float 4.0, float %a)1766  %fneg = fneg float %max1767  ret float %fneg1768}1769 1770define float @v_fneg_posk_maximum_f32_no_ieee(float %a) #4 {1771; GCN-LABEL: v_fneg_posk_maximum_f32_no_ieee:1772; GCN:       ; %bb.0:1773; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1774; GCN-NEXT:    v_min_f32_e64 v1, -v0, -4.01775; GCN-NEXT:    v_mov_b32_e32 v2, 0x7fc000001776; GCN-NEXT:    v_cmp_o_f32_e64 vcc, -v0, -v01777; GCN-NEXT:    v_cndmask_b32_e32 v0, v2, v1, vcc1778; GCN-NEXT:    s_setpc_b64 s[30:31]1779  %max = call float @llvm.maximum.f32(float 4.0, float %a)1780  %fneg = fneg float %max1781  ret float %fneg1782}1783 1784define float @v_fneg_negk_maximum_f32_ieee(float %a) #0 {1785; GCN-LABEL: v_fneg_negk_maximum_f32_ieee:1786; GCN:       ; %bb.0:1787; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1788; GCN-NEXT:    v_min_f32_e64 v1, -v0, 4.01789; GCN-NEXT:    v_mov_b32_e32 v2, 0x7fc000001790; GCN-NEXT:    v_cmp_o_f32_e64 vcc, -v0, -v01791; GCN-NEXT:    v_cndmask_b32_e32 v0, v2, v1, vcc1792; GCN-NEXT:    s_setpc_b64 s[30:31]1793  %max = call float @llvm.maximum.f32(float -4.0, float %a)1794  %fneg = fneg float %max1795  ret float %fneg1796}1797 1798define float @v_fneg_negk_maximum_f32_no_ieee(float %a) #4 {1799; GCN-LABEL: v_fneg_negk_maximum_f32_no_ieee:1800; GCN:       ; %bb.0:1801; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1802; GCN-NEXT:    v_min_f32_e64 v1, -v0, 4.01803; GCN-NEXT:    v_mov_b32_e32 v2, 0x7fc000001804; GCN-NEXT:    v_cmp_o_f32_e64 vcc, -v0, -v01805; GCN-NEXT:    v_cndmask_b32_e32 v0, v2, v1, vcc1806; GCN-NEXT:    s_setpc_b64 s[30:31]1807  %max = call float @llvm.maximum.f32(float -4.0, float %a)1808  %fneg = fneg float %max1809  ret float %fneg1810}1811 1812define float @v_fneg_0_maximum_f32(float %a) #0 {1813; GCN-LABEL: v_fneg_0_maximum_f32:1814; GCN:       ; %bb.0:1815; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1816; GCN-NEXT:    v_max_f32_e32 v0, 0, v01817; GCN-NEXT:    v_xor_b32_e32 v0, 0x80000000, v01818; GCN-NEXT:    s_setpc_b64 s[30:31]1819  %max = call nnan float @llvm.maximum.f32(float 0.0, float %a)1820  %fneg = fneg float %max1821  ret float %fneg1822}1823 1824define float @v_fneg_neg0_maximum_f32_ieee(float %a) #0 {1825; GCN-LABEL: v_fneg_neg0_maximum_f32_ieee:1826; GCN:       ; %bb.0:1827; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1828; GCN-NEXT:    v_min_f32_e64 v1, -v0, 01829; GCN-NEXT:    v_mov_b32_e32 v2, 0x7fc000001830; GCN-NEXT:    v_cmp_o_f32_e64 vcc, -v0, -v01831; GCN-NEXT:    v_cndmask_b32_e32 v0, v2, v1, vcc1832; GCN-NEXT:    s_setpc_b64 s[30:31]1833  %max = call float @llvm.maximum.f32(float -0.0, float %a)1834  %fneg = fneg float %max1835  ret float %fneg1836}1837 1838define float @v_fneg_neg0_maximum_f32_no_ieee(float %a) #4 {1839; GCN-LABEL: v_fneg_neg0_maximum_f32_no_ieee:1840; GCN:       ; %bb.0:1841; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1842; GCN-NEXT:    v_min_f32_e64 v1, -v0, 01843; GCN-NEXT:    v_mov_b32_e32 v2, 0x7fc000001844; GCN-NEXT:    v_cmp_o_f32_e64 vcc, -v0, -v01845; GCN-NEXT:    v_cndmask_b32_e32 v0, v2, v1, vcc1846; GCN-NEXT:    s_setpc_b64 s[30:31]1847  %max = call float @llvm.maximum.f32(float -0.0, float %a)1848  %fneg = fneg float %max1849  ret float %fneg1850}1851 1852define float @v_fneg_0_maximum_foldable_use_f32_ieee(float %a, float %b) #0 {1853; GCN-LABEL: v_fneg_0_maximum_foldable_use_f32_ieee:1854; GCN:       ; %bb.0:1855; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1856; GCN-NEXT:    v_max_f32_e32 v2, 0, v01857; GCN-NEXT:    v_mov_b32_e32 v3, 0x7fc000001858; GCN-NEXT:    v_cmp_o_f32_e32 vcc, v0, v01859; GCN-NEXT:    v_cndmask_b32_e32 v0, v3, v2, vcc1860; GCN-NEXT:    v_mul_f32_e64 v0, -v0, v11861; GCN-NEXT:    s_setpc_b64 s[30:31]1862  %max = call float @llvm.maximum.f32(float 0.0, float %a)1863  %fneg = fneg float %max1864  %mul = fmul float %fneg, %b1865  ret float %mul1866}1867 1868define float @v_fneg_0_maximum_foldable_use_f32_no_ieee(float %a, float %b) #4 {1869; GCN-LABEL: v_fneg_0_maximum_foldable_use_f32_no_ieee:1870; GCN:       ; %bb.0:1871; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1872; GCN-NEXT:    v_max_f32_e32 v2, 0, v01873; GCN-NEXT:    v_mov_b32_e32 v3, 0x7fc000001874; GCN-NEXT:    v_cmp_o_f32_e32 vcc, v0, v01875; GCN-NEXT:    v_cndmask_b32_e32 v0, v3, v2, vcc1876; GCN-NEXT:    v_mul_f32_e64 v0, -v0, v11877; GCN-NEXT:    s_setpc_b64 s[30:31]1878  %max = call float @llvm.maximum.f32(float 0.0, float %a)1879  %fneg = fneg float %max1880  %mul = fmul float %fneg, %b1881  ret float %mul1882}1883 1884define { float, float } @v_fneg_maximum_multi_use_maximum_f32_ieee(float %a, float %b) #0 {1885; GCN-LABEL: v_fneg_maximum_multi_use_maximum_f32_ieee:1886; GCN:       ; %bb.0:1887; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1888; GCN-NEXT:    v_min_f32_e64 v2, -v0, -v11889; GCN-NEXT:    v_mov_b32_e32 v3, 0x7fc000001890; GCN-NEXT:    v_cmp_o_f32_e64 vcc, -v0, -v11891; GCN-NEXT:    v_cndmask_b32_e32 v0, v3, v2, vcc1892; GCN-NEXT:    v_mul_f32_e32 v1, -4.0, v01893; GCN-NEXT:    s_setpc_b64 s[30:31]1894  %max = call float @llvm.maximum.f32(float %a, float %b)1895  %fneg = fneg float %max1896  %use1 = fmul float %max, 4.01897  %insert.0 = insertvalue { float, float } poison, float %fneg, 01898  %insert.1 = insertvalue { float, float } %insert.0, float %use1, 11899  ret { float, float } %insert.11900}1901 1902define <2 x float> @v_fneg_maximum_multi_use_maximum_f32_no_ieee(float %a, float %b) #4 {1903; GCN-LABEL: v_fneg_maximum_multi_use_maximum_f32_no_ieee:1904; GCN:       ; %bb.0:1905; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1906; GCN-NEXT:    v_min_f32_e64 v2, -v0, -v11907; GCN-NEXT:    v_mov_b32_e32 v3, 0x7fc000001908; GCN-NEXT:    v_cmp_o_f32_e64 vcc, -v0, -v11909; GCN-NEXT:    v_cndmask_b32_e32 v0, v3, v2, vcc1910; GCN-NEXT:    v_mul_f32_e32 v1, -4.0, v01911; GCN-NEXT:    s_setpc_b64 s[30:31]1912  %max = call float @llvm.maximum.f32(float %a, float %b)1913  %fneg = fneg float %max1914  %use1 = fmul float %max, 4.01915  %ins0 = insertelement <2 x float> poison, float %fneg, i32 01916  %ins1 = insertelement <2 x float> %ins0, float %use1, i32 11917  ret <2 x float> %ins11918}1919 1920; --------------------------------------------------------------------------------1921; fminimumnum tests1922; --------------------------------------------------------------------------------1923 1924define float @v_fneg_minimumnum_f32_ieee(float %a, float %b) #0 {1925; GCN-LABEL: v_fneg_minimumnum_f32_ieee:1926; GCN:       ; %bb.0:1927; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1928; GCN-NEXT:    v_mul_f32_e32 v1, -1.0, v11929; GCN-NEXT:    v_mul_f32_e32 v0, -1.0, v01930; GCN-NEXT:    v_max_f32_e32 v0, v0, v11931; GCN-NEXT:    s_setpc_b64 s[30:31]1932  %min = call float @llvm.minimumnum.f32(float %a, float %b)1933  %fneg = fneg float %min1934  ret float %fneg1935}1936 1937define float @v_fneg_minimumnum_f32_no_ieee(float %a, float %b) #4 {1938; GCN-LABEL: v_fneg_minimumnum_f32_no_ieee:1939; GCN:       ; %bb.0:1940; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1941; GCN-NEXT:    v_max_f32_e64 v0, -v0, -v11942; GCN-NEXT:    s_setpc_b64 s[30:31]1943  %min = call float @llvm.minimumnum.f32(float %a, float %b)1944  %fneg = fneg float %min1945  ret float %fneg1946}1947 1948define float @v_fneg_self_minimumnum_f32_ieee(float %a) #0 {1949; GCN-LABEL: v_fneg_self_minimumnum_f32_ieee:1950; GCN:       ; %bb.0:1951; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1952; GCN-NEXT:    v_xor_b32_e32 v0, 0x80000000, v01953; GCN-NEXT:    s_setpc_b64 s[30:31]1954  %min = call float @llvm.minimumnum.f32(float %a, float %a)1955  %min.fneg = fneg float %min1956  ret float %min.fneg1957}1958 1959define float @v_fneg_self_minimumnum_f32_no_ieee(float %a) #4 {1960; GCN-LABEL: v_fneg_self_minimumnum_f32_no_ieee:1961; GCN:       ; %bb.0:1962; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1963; GCN-NEXT:    v_xor_b32_e32 v0, 0x80000000, v01964; GCN-NEXT:    s_setpc_b64 s[30:31]1965  %min = call float @llvm.minimumnum.f32(float %a, float %a)1966  %min.fneg = fneg float %min1967  ret float %min.fneg1968}1969 1970define float @v_fneg_posk_minimumnum_f32_ieee(float %a) #0 {1971; GCN-LABEL: v_fneg_posk_minimumnum_f32_ieee:1972; GCN:       ; %bb.0:1973; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1974; GCN-NEXT:    v_mul_f32_e32 v0, -1.0, v01975; GCN-NEXT:    v_max_f32_e32 v0, -4.0, v01976; GCN-NEXT:    s_setpc_b64 s[30:31]1977  %min = call float @llvm.minimumnum.f32(float 4.0, float %a)1978  %fneg = fneg float %min1979  ret float %fneg1980}1981 1982define float @v_fneg_posk_minimumnum_f32_no_ieee(float %a) #4 {1983; GCN-LABEL: v_fneg_posk_minimumnum_f32_no_ieee:1984; GCN:       ; %bb.0:1985; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1986; GCN-NEXT:    v_max_f32_e64 v0, -v0, -4.01987; GCN-NEXT:    s_setpc_b64 s[30:31]1988  %min = call float @llvm.minimumnum.f32(float 4.0, float %a)1989  %fneg = fneg float %min1990  ret float %fneg1991}1992 1993define float @v_fneg_negk_minimumnum_f32_ieee(float %a) #0 {1994; GCN-LABEL: v_fneg_negk_minimumnum_f32_ieee:1995; GCN:       ; %bb.0:1996; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1997; GCN-NEXT:    v_mul_f32_e32 v0, -1.0, v01998; GCN-NEXT:    v_max_f32_e32 v0, 4.0, v01999; GCN-NEXT:    s_setpc_b64 s[30:31]2000  %min = call float @llvm.minimumnum.f32(float -4.0, float %a)2001  %fneg = fneg float %min2002  ret float %fneg2003}2004 2005define float @v_fneg_negk_minimumnum_f32_no_ieee(float %a) #4 {2006; GCN-LABEL: v_fneg_negk_minimumnum_f32_no_ieee:2007; GCN:       ; %bb.0:2008; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2009; GCN-NEXT:    v_max_f32_e64 v0, -v0, 4.02010; GCN-NEXT:    s_setpc_b64 s[30:31]2011  %min = call float @llvm.minimumnum.f32(float -4.0, float %a)2012  %fneg = fneg float %min2013  ret float %fneg2014}2015 2016define float @v_fneg_0_minimumnum_f32(float %a) #0 {2017; GCN-LABEL: v_fneg_0_minimumnum_f32:2018; GCN:       ; %bb.0:2019; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2020; GCN-NEXT:    v_min_f32_e32 v0, 0, v02021; GCN-NEXT:    v_xor_b32_e32 v0, 0x80000000, v02022; GCN-NEXT:    s_setpc_b64 s[30:31]2023  %min = call nnan float @llvm.minimumnum.f32(float 0.0, float %a)2024  %fneg = fneg float %min2025  ret float %fneg2026}2027 2028define float @v_fneg_neg0_minimumnum_f32_ieee(float %a) #0 {2029; GCN-LABEL: v_fneg_neg0_minimumnum_f32_ieee:2030; GCN:       ; %bb.0:2031; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2032; GCN-NEXT:    v_mul_f32_e32 v0, -1.0, v02033; GCN-NEXT:    v_max_f32_e32 v0, 0, v02034; GCN-NEXT:    s_setpc_b64 s[30:31]2035  %min = call float @llvm.minimumnum.f32(float -0.0, float %a)2036  %fneg = fneg float %min2037  ret float %fneg2038}2039 2040define float @v_fneg_inv2pi_minimumnum_f32(float %a) #0 {2041; SI-LABEL: v_fneg_inv2pi_minimumnum_f32:2042; SI:       ; %bb.0:2043; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2044; SI-NEXT:    v_mul_f32_e32 v0, -1.0, v02045; SI-NEXT:    v_max_f32_e32 v0, 0xbe22f983, v02046; SI-NEXT:    s_setpc_b64 s[30:31]2047;2048; VI-LABEL: v_fneg_inv2pi_minimumnum_f32:2049; VI:       ; %bb.0:2050; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2051; VI-NEXT:    v_mul_f32_e32 v0, 1.0, v02052; VI-NEXT:    v_min_f32_e32 v0, 0.15915494, v02053; VI-NEXT:    v_xor_b32_e32 v0, 0x80000000, v02054; VI-NEXT:    s_setpc_b64 s[30:31]2055  %min = call float @llvm.minimumnum.f32(float 0x3FC45F3060000000, float %a)2056  %fneg = fneg float %min2057  ret float %fneg2058}2059 2060define float @v_fneg_neg_inv2pi_minimumnum_f32(float %a) #0 {2061; SI-LABEL: v_fneg_neg_inv2pi_minimumnum_f32:2062; SI:       ; %bb.0:2063; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2064; SI-NEXT:    v_mul_f32_e32 v0, -1.0, v02065; SI-NEXT:    v_max_f32_e32 v0, 0x3e22f983, v02066; SI-NEXT:    s_setpc_b64 s[30:31]2067;2068; VI-LABEL: v_fneg_neg_inv2pi_minimumnum_f32:2069; VI:       ; %bb.0:2070; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2071; VI-NEXT:    v_mul_f32_e32 v0, -1.0, v02072; VI-NEXT:    v_max_f32_e32 v0, 0.15915494, v02073; VI-NEXT:    s_setpc_b64 s[30:31]2074  %min = call float @llvm.minimumnum.f32(float 0xBFC45F3060000000, float %a)2075  %fneg = fneg float %min2076  ret float %fneg2077}2078 2079define half @v_fneg_inv2pi_minimumnum_f16(half %a) #0 {2080; SI-LABEL: v_fneg_inv2pi_minimumnum_f16:2081; SI:       ; %bb.0:2082; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2083; SI-NEXT:    v_cvt_f16_f32_e64 v0, -v02084; SI-NEXT:    v_cvt_f32_f16_e32 v0, v02085; SI-NEXT:    v_max_f32_e32 v0, 0xbe230000, v02086; SI-NEXT:    s_setpc_b64 s[30:31]2087;2088; VI-LABEL: v_fneg_inv2pi_minimumnum_f16:2089; VI:       ; %bb.0:2090; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2091; VI-NEXT:    v_max_f16_e32 v0, v0, v02092; VI-NEXT:    v_min_f16_e32 v0, 0.15915494, v02093; VI-NEXT:    v_xor_b32_e32 v0, 0x8000, v02094; VI-NEXT:    s_setpc_b64 s[30:31]2095  %min = call half @llvm.minimumnum.f16(half 0xH3118, half %a)2096  %fneg = fneg half %min2097  ret half %fneg2098}2099 2100define half @v_fneg_neg_inv2pi_minimumnum_f16(half %a) #0 {2101; SI-LABEL: v_fneg_neg_inv2pi_minimumnum_f16:2102; SI:       ; %bb.0:2103; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2104; SI-NEXT:    v_cvt_f16_f32_e64 v0, -v02105; SI-NEXT:    v_cvt_f32_f16_e32 v0, v02106; SI-NEXT:    v_max_f32_e32 v0, 0x3e230000, v02107; SI-NEXT:    s_setpc_b64 s[30:31]2108;2109; VI-LABEL: v_fneg_neg_inv2pi_minimumnum_f16:2110; VI:       ; %bb.0:2111; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2112; VI-NEXT:    v_max_f16_e64 v0, -v0, -v02113; VI-NEXT:    v_max_f16_e32 v0, 0.15915494, v02114; VI-NEXT:    s_setpc_b64 s[30:31]2115  %min = call half @llvm.minimumnum.f16(half 0xHB118, half %a)2116  %fneg = fneg half %min2117  ret half %fneg2118}2119 2120define double @v_fneg_inv2pi_minimumnum_f64(double %a) #0 {2121; SI-LABEL: v_fneg_inv2pi_minimumnum_f64:2122; SI:       ; %bb.0:2123; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2124; SI-NEXT:    v_max_f64 v[0:1], -v[0:1], -v[0:1]2125; SI-NEXT:    s_mov_b32 s4, 0x6dc9c8822126; SI-NEXT:    s_mov_b32 s5, 0xbfc45f302127; SI-NEXT:    v_max_f64 v[0:1], v[0:1], s[4:5]2128; SI-NEXT:    s_setpc_b64 s[30:31]2129;2130; VI-LABEL: v_fneg_inv2pi_minimumnum_f64:2131; VI:       ; %bb.0:2132; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2133; VI-NEXT:    v_max_f64 v[0:1], v[0:1], v[0:1]2134; VI-NEXT:    v_min_f64 v[0:1], v[0:1], 0.159154943091895322135; VI-NEXT:    v_xor_b32_e32 v1, 0x80000000, v12136; VI-NEXT:    s_setpc_b64 s[30:31]2137  %min = call double @llvm.minimumnum.f64(double 0x3fc45f306dc9c882, double %a)2138  %fneg = fneg double %min2139  ret double %fneg2140}2141 2142define double @v_fneg_neg_inv2pi_minimumnum_f64(double %a) #0 {2143; SI-LABEL: v_fneg_neg_inv2pi_minimumnum_f64:2144; SI:       ; %bb.0:2145; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2146; SI-NEXT:    v_max_f64 v[0:1], -v[0:1], -v[0:1]2147; SI-NEXT:    s_mov_b32 s4, 0x6dc9c8822148; SI-NEXT:    s_mov_b32 s5, 0x3fc45f302149; SI-NEXT:    v_max_f64 v[0:1], v[0:1], s[4:5]2150; SI-NEXT:    s_setpc_b64 s[30:31]2151;2152; VI-LABEL: v_fneg_neg_inv2pi_minimumnum_f64:2153; VI:       ; %bb.0:2154; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2155; VI-NEXT:    v_max_f64 v[0:1], -v[0:1], -v[0:1]2156; VI-NEXT:    v_max_f64 v[0:1], v[0:1], 0.159154943091895322157; VI-NEXT:    s_setpc_b64 s[30:31]2158  %min = call double @llvm.minimumnum.f64(double 0xbfc45f306dc9c882, double %a)2159  %fneg = fneg double %min2160  ret double %fneg2161}2162 2163define float @v_fneg_neg0_minimumnum_f32_no_ieee(float %a) #4 {2164; GCN-LABEL: v_fneg_neg0_minimumnum_f32_no_ieee:2165; GCN:       ; %bb.0:2166; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2167; GCN-NEXT:    v_max_f32_e64 v0, -v0, 02168; GCN-NEXT:    s_setpc_b64 s[30:31]2169  %min = call float @llvm.minimumnum.f32(float -0.0, float %a)2170  %fneg = fneg float %min2171  ret float %fneg2172}2173 2174define float @v_fneg_0_minimumnum_foldable_use_f32_ieee(float %a, float %b) #0 {2175; GCN-LABEL: v_fneg_0_minimumnum_foldable_use_f32_ieee:2176; GCN:       ; %bb.0:2177; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2178; GCN-NEXT:    v_mul_f32_e32 v0, 1.0, v02179; GCN-NEXT:    v_min_f32_e32 v0, 0, v02180; GCN-NEXT:    v_mul_f32_e64 v0, -v0, v12181; GCN-NEXT:    s_setpc_b64 s[30:31]2182  %min = call float @llvm.minimumnum.f32(float 0.0, float %a)2183  %fneg = fneg float %min2184  %mul = fmul float %fneg, %b2185  ret float %mul2186}2187 2188define float @v_fneg_inv2pi_minimumnum_foldable_use_f32(float %a, float %b) #0 {2189; SI-LABEL: v_fneg_inv2pi_minimumnum_foldable_use_f32:2190; SI:       ; %bb.0:2191; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2192; SI-NEXT:    v_mul_f32_e32 v0, -1.0, v02193; SI-NEXT:    v_max_f32_e32 v0, 0xbe22f983, v02194; SI-NEXT:    v_mul_f32_e32 v0, v0, v12195; SI-NEXT:    s_setpc_b64 s[30:31]2196;2197; VI-LABEL: v_fneg_inv2pi_minimumnum_foldable_use_f32:2198; VI:       ; %bb.0:2199; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2200; VI-NEXT:    v_mul_f32_e32 v0, 1.0, v02201; VI-NEXT:    v_min_f32_e32 v0, 0.15915494, v02202; VI-NEXT:    v_mul_f32_e64 v0, -v0, v12203; VI-NEXT:    s_setpc_b64 s[30:31]2204  %min = call float @llvm.minimumnum.f32(float 0x3FC45F3060000000, float %a)2205  %fneg = fneg float %min2206  %mul = fmul float %fneg, %b2207  ret float %mul2208}2209 2210define float @v_fneg_0_minimumnum_foldable_use_f32_no_ieee(float %a, float %b) #4 {2211; GCN-LABEL: v_fneg_0_minimumnum_foldable_use_f32_no_ieee:2212; GCN:       ; %bb.0:2213; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2214; GCN-NEXT:    v_min_f32_e32 v0, 0, v02215; GCN-NEXT:    v_mul_f32_e64 v0, -v0, v12216; GCN-NEXT:    s_setpc_b64 s[30:31]2217  %min = call float @llvm.minimumnum.f32(float 0.0, float %a)2218  %fneg = fneg float %min2219  %mul = fmul float %fneg, %b2220  ret float %mul2221}2222 2223define { float, float } @v_fneg_minimumnum_multi_use_minimumnum_f32_ieee(float %a, float %b) #0 {2224; GCN-LABEL: v_fneg_minimumnum_multi_use_minimumnum_f32_ieee:2225; GCN:       ; %bb.0:2226; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2227; GCN-NEXT:    v_mul_f32_e32 v1, -1.0, v12228; GCN-NEXT:    v_mul_f32_e32 v0, -1.0, v02229; GCN-NEXT:    v_max_f32_e32 v0, v0, v12230; GCN-NEXT:    v_mul_f32_e32 v1, -4.0, v02231; GCN-NEXT:    s_setpc_b64 s[30:31]2232  %min = call float @llvm.minimumnum.f32(float %a, float %b)2233  %fneg = fneg float %min2234  %use1 = fmul float %min, 4.02235  %insert.0 = insertvalue { float, float } poison, float %fneg, 02236  %insert.1 = insertvalue { float, float } %insert.0, float %use1, 12237  ret { float, float } %insert.12238}2239 2240define <2 x float> @v_fneg_minimumnum_multi_use_minimumnum_f32_no_ieee(float %a, float %b) #4 {2241; GCN-LABEL: v_fneg_minimumnum_multi_use_minimumnum_f32_no_ieee:2242; GCN:       ; %bb.0:2243; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2244; GCN-NEXT:    v_max_f32_e64 v0, -v0, -v12245; GCN-NEXT:    v_mul_f32_e32 v1, -4.0, v02246; GCN-NEXT:    s_setpc_b64 s[30:31]2247  %min = call float @llvm.minimumnum.f32(float %a, float %b)2248  %fneg = fneg float %min2249  %use1 = fmul float %min, 4.02250  %ins0 = insertelement <2 x float> poison, float %fneg, i32 02251  %ins1 = insertelement <2 x float> %ins0, float %use1, i32 12252  ret <2 x float> %ins12253}2254 2255; --------------------------------------------------------------------------------2256; fmaximumnum tests2257; --------------------------------------------------------------------------------2258 2259define float @v_fneg_maximumnum_f32_ieee(float %a, float %b) #0 {2260; GCN-LABEL: v_fneg_maximumnum_f32_ieee:2261; GCN:       ; %bb.0:2262; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2263; GCN-NEXT:    v_mul_f32_e32 v1, -1.0, v12264; GCN-NEXT:    v_mul_f32_e32 v0, -1.0, v02265; GCN-NEXT:    v_min_f32_e32 v0, v0, v12266; GCN-NEXT:    s_setpc_b64 s[30:31]2267  %max = call float @llvm.maximumnum.f32(float %a, float %b)2268  %fneg = fneg float %max2269  ret float %fneg2270}2271 2272define float @v_fneg_maximumnum_f32_no_ieee(float %a, float %b) #4 {2273; GCN-LABEL: v_fneg_maximumnum_f32_no_ieee:2274; GCN:       ; %bb.0:2275; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2276; GCN-NEXT:    v_min_f32_e64 v0, -v0, -v12277; GCN-NEXT:    s_setpc_b64 s[30:31]2278  %max = call float @llvm.maximumnum.f32(float %a, float %b)2279  %fneg = fneg float %max2280  ret float %fneg2281}2282 2283define float @v_fneg_self_maximumnum_f32_ieee(float %a) #0 {2284; GCN-LABEL: v_fneg_self_maximumnum_f32_ieee:2285; GCN:       ; %bb.0:2286; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2287; GCN-NEXT:    v_xor_b32_e32 v0, 0x80000000, v02288; GCN-NEXT:    s_setpc_b64 s[30:31]2289  %max = call float @llvm.maximumnum.f32(float %a, float %a)2290  %max.fneg = fneg float %max2291  ret float %max.fneg2292}2293 2294define float @v_fneg_self_maximumnum_f32_no_ieee(float %a) #4 {2295; GCN-LABEL: v_fneg_self_maximumnum_f32_no_ieee:2296; GCN:       ; %bb.0:2297; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2298; GCN-NEXT:    v_xor_b32_e32 v0, 0x80000000, v02299; GCN-NEXT:    s_setpc_b64 s[30:31]2300  %max = call float @llvm.maximumnum.f32(float %a, float %a)2301  %max.fneg = fneg float %max2302  ret float %max.fneg2303}2304 2305define float @v_fneg_posk_maximumnum_f32_ieee(float %a) #0 {2306; GCN-LABEL: v_fneg_posk_maximumnum_f32_ieee:2307; GCN:       ; %bb.0:2308; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2309; GCN-NEXT:    v_mul_f32_e32 v0, -1.0, v02310; GCN-NEXT:    v_min_f32_e32 v0, -4.0, v02311; GCN-NEXT:    s_setpc_b64 s[30:31]2312  %max = call float @llvm.maximumnum.f32(float 4.0, float %a)2313  %fneg = fneg float %max2314  ret float %fneg2315}2316 2317define float @v_fneg_posk_maximumnum_f32_no_ieee(float %a) #4 {2318; GCN-LABEL: v_fneg_posk_maximumnum_f32_no_ieee:2319; GCN:       ; %bb.0:2320; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2321; GCN-NEXT:    v_min_f32_e64 v0, -v0, -4.02322; GCN-NEXT:    s_setpc_b64 s[30:31]2323  %max = call float @llvm.maximumnum.f32(float 4.0, float %a)2324  %fneg = fneg float %max2325  ret float %fneg2326}2327 2328define float @v_fneg_negk_maximumnum_f32_ieee(float %a) #0 {2329; GCN-LABEL: v_fneg_negk_maximumnum_f32_ieee:2330; GCN:       ; %bb.0:2331; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2332; GCN-NEXT:    v_mul_f32_e32 v0, -1.0, v02333; GCN-NEXT:    v_min_f32_e32 v0, 4.0, v02334; GCN-NEXT:    s_setpc_b64 s[30:31]2335  %max = call float @llvm.maximumnum.f32(float -4.0, float %a)2336  %fneg = fneg float %max2337  ret float %fneg2338}2339 2340define float @v_fneg_negk_maximumnum_f32_no_ieee(float %a) #4 {2341; GCN-LABEL: v_fneg_negk_maximumnum_f32_no_ieee:2342; GCN:       ; %bb.0:2343; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2344; GCN-NEXT:    v_min_f32_e64 v0, -v0, 4.02345; GCN-NEXT:    s_setpc_b64 s[30:31]2346  %max = call float @llvm.maximumnum.f32(float -4.0, float %a)2347  %fneg = fneg float %max2348  ret float %fneg2349}2350 2351define float @v_fneg_0_maximumnum_f32(float %a) #0 {2352; GCN-LABEL: v_fneg_0_maximumnum_f32:2353; GCN:       ; %bb.0:2354; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2355; GCN-NEXT:    v_max_f32_e32 v0, 0, v02356; GCN-NEXT:    v_xor_b32_e32 v0, 0x80000000, v02357; GCN-NEXT:    s_setpc_b64 s[30:31]2358  %max = call nnan float @llvm.maximumnum.f32(float 0.0, float %a)2359  %fneg = fneg float %max2360  ret float %fneg2361}2362 2363define float @v_fneg_neg0_maximumnum_f32_ieee(float %a) #0 {2364; GCN-LABEL: v_fneg_neg0_maximumnum_f32_ieee:2365; GCN:       ; %bb.0:2366; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2367; GCN-NEXT:    v_mul_f32_e32 v0, -1.0, v02368; GCN-NEXT:    v_min_f32_e32 v0, 0, v02369; GCN-NEXT:    s_setpc_b64 s[30:31]2370  %max = call float @llvm.maximumnum.f32(float -0.0, float %a)2371  %fneg = fneg float %max2372  ret float %fneg2373}2374 2375define float @v_fneg_neg0_maximumnum_f32_no_ieee(float %a) #4 {2376; GCN-LABEL: v_fneg_neg0_maximumnum_f32_no_ieee:2377; GCN:       ; %bb.0:2378; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2379; GCN-NEXT:    v_min_f32_e64 v0, -v0, 02380; GCN-NEXT:    s_setpc_b64 s[30:31]2381  %max = call float @llvm.maximumnum.f32(float -0.0, float %a)2382  %fneg = fneg float %max2383  ret float %fneg2384}2385 2386define float @v_fneg_0_maximumnum_foldable_use_f32_ieee(float %a, float %b) #0 {2387; GCN-LABEL: v_fneg_0_maximumnum_foldable_use_f32_ieee:2388; GCN:       ; %bb.0:2389; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2390; GCN-NEXT:    v_mul_f32_e32 v0, 1.0, v02391; GCN-NEXT:    v_max_f32_e32 v0, 0, v02392; GCN-NEXT:    v_mul_f32_e64 v0, -v0, v12393; GCN-NEXT:    s_setpc_b64 s[30:31]2394  %max = call float @llvm.maximumnum.f32(float 0.0, float %a)2395  %fneg = fneg float %max2396  %mul = fmul float %fneg, %b2397  ret float %mul2398}2399 2400define float @v_fneg_0_maximumnum_foldable_use_f32_no_ieee(float %a, float %b) #4 {2401; GCN-LABEL: v_fneg_0_maximumnum_foldable_use_f32_no_ieee:2402; GCN:       ; %bb.0:2403; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2404; GCN-NEXT:    v_max_f32_e32 v0, 0, v02405; GCN-NEXT:    v_mul_f32_e64 v0, -v0, v12406; GCN-NEXT:    s_setpc_b64 s[30:31]2407  %max = call float @llvm.maximumnum.f32(float 0.0, float %a)2408  %fneg = fneg float %max2409  %mul = fmul float %fneg, %b2410  ret float %mul2411}2412 2413define { float, float } @v_fneg_maximumnum_multi_use_maximumnum_f32_ieee(float %a, float %b) #0 {2414; GCN-LABEL: v_fneg_maximumnum_multi_use_maximumnum_f32_ieee:2415; GCN:       ; %bb.0:2416; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2417; GCN-NEXT:    v_mul_f32_e32 v1, -1.0, v12418; GCN-NEXT:    v_mul_f32_e32 v0, -1.0, v02419; GCN-NEXT:    v_min_f32_e32 v0, v0, v12420; GCN-NEXT:    v_mul_f32_e32 v1, -4.0, v02421; GCN-NEXT:    s_setpc_b64 s[30:31]2422  %max = call float @llvm.maximumnum.f32(float %a, float %b)2423  %fneg = fneg float %max2424  %use1 = fmul float %max, 4.02425  %insert.0 = insertvalue { float, float } poison, float %fneg, 02426  %insert.1 = insertvalue { float, float } %insert.0, float %use1, 12427  ret { float, float } %insert.12428}2429 2430define <2 x float> @v_fneg_maximumnum_multi_use_maximumnum_f32_no_ieee(float %a, float %b) #4 {2431; GCN-LABEL: v_fneg_maximumnum_multi_use_maximumnum_f32_no_ieee:2432; GCN:       ; %bb.0:2433; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2434; GCN-NEXT:    v_min_f32_e64 v0, -v0, -v12435; GCN-NEXT:    v_mul_f32_e32 v1, -4.0, v02436; GCN-NEXT:    s_setpc_b64 s[30:31]2437  %max = call float @llvm.maximumnum.f32(float %a, float %b)2438  %fneg = fneg float %max2439  %use1 = fmul float %max, 4.02440  %ins0 = insertelement <2 x float> poison, float %fneg, i32 02441  %ins1 = insertelement <2 x float> %ins0, float %use1, i32 12442  ret <2 x float> %ins12443}2444 2445; --------------------------------------------------------------------------------2446; fma tests2447; --------------------------------------------------------------------------------2448 2449define float @v_fneg_fma_f32(float %a, float %b, float %c) #0 {2450; GCN-SAFE-LABEL: v_fneg_fma_f32:2451; GCN-SAFE:       ; %bb.0:2452; GCN-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2453; GCN-SAFE-NEXT:    v_fma_f32 v0, v0, v1, v22454; GCN-SAFE-NEXT:    v_xor_b32_e32 v0, 0x80000000, v02455; GCN-SAFE-NEXT:    s_setpc_b64 s[30:31]2456;2457; GCN-NSZ-LABEL: v_fneg_fma_f32:2458; GCN-NSZ:       ; %bb.0:2459; GCN-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2460; GCN-NSZ-NEXT:    v_fma_f32 v0, v0, -v1, -v22461; GCN-NSZ-NEXT:    s_setpc_b64 s[30:31]2462  %fma = call float @llvm.fma.f32(float %a, float %b, float %c)2463  %fneg = fneg float %fma2464  ret float %fneg2465}2466 2467define { float, float } @v_fneg_fma_store_use_fma_f32(float %a, float %b, float %c) #0 {2468; GCN-LABEL: v_fneg_fma_store_use_fma_f32:2469; GCN:       ; %bb.0:2470; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2471; GCN-NEXT:    v_fma_f32 v1, v0, v1, v22472; GCN-NEXT:    v_xor_b32_e32 v0, 0x80000000, v12473; GCN-NEXT:    s_setpc_b64 s[30:31]2474  %fma = call float @llvm.fma.f32(float %a, float %b, float %c)2475  %fneg = fneg float %fma2476  %insert.0 = insertvalue { float, float } poison, float %fneg, 02477  %insert.1 = insertvalue { float, float } %insert.0, float %fma, 12478  ret { float, float } %insert.12479}2480 2481define { float, float } @v_fneg_fma_multi_use_fma_f32(float %a, float %b, float %c) #0 {2482; GCN-SAFE-LABEL: v_fneg_fma_multi_use_fma_f32:2483; GCN-SAFE:       ; %bb.0:2484; GCN-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2485; GCN-SAFE-NEXT:    v_fma_f32 v1, v0, v1, v22486; GCN-SAFE-NEXT:    v_xor_b32_e32 v0, 0x80000000, v12487; GCN-SAFE-NEXT:    v_mul_f32_e32 v1, 4.0, v12488; GCN-SAFE-NEXT:    s_setpc_b64 s[30:31]2489;2490; GCN-NSZ-LABEL: v_fneg_fma_multi_use_fma_f32:2491; GCN-NSZ:       ; %bb.0:2492; GCN-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2493; GCN-NSZ-NEXT:    v_fma_f32 v0, v0, -v1, -v22494; GCN-NSZ-NEXT:    v_mul_f32_e32 v1, -4.0, v02495; GCN-NSZ-NEXT:    s_setpc_b64 s[30:31]2496  %fma = call float @llvm.fma.f32(float %a, float %b, float %c)2497  %fneg = fneg float %fma2498  %use1 = fmul float %fma, 4.02499  %insert.0 = insertvalue { float, float } poison, float %fneg, 02500  %insert.1 = insertvalue { float, float } %insert.0, float %use1, 12501  ret { float, float } %insert.12502}2503 2504define float @v_fneg_fma_fneg_x_y_f32(float %a, float %b, float %c) #0 {2505; GCN-SAFE-LABEL: v_fneg_fma_fneg_x_y_f32:2506; GCN-SAFE:       ; %bb.0:2507; GCN-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2508; GCN-SAFE-NEXT:    v_fma_f32 v0, -v0, v1, v22509; GCN-SAFE-NEXT:    v_xor_b32_e32 v0, 0x80000000, v02510; GCN-SAFE-NEXT:    s_setpc_b64 s[30:31]2511;2512; GCN-NSZ-LABEL: v_fneg_fma_fneg_x_y_f32:2513; GCN-NSZ:       ; %bb.0:2514; GCN-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2515; GCN-NSZ-NEXT:    v_fma_f32 v0, v0, v1, -v22516; GCN-NSZ-NEXT:    s_setpc_b64 s[30:31]2517  %fneg.a = fneg float %a2518  %fma = call float @llvm.fma.f32(float %fneg.a, float %b, float %c)2519  %fneg = fneg float %fma2520  ret float %fneg2521}2522 2523define float @v_fneg_fma_x_fneg_y_f32(float %a, float %b, float %c) #0 {2524; GCN-SAFE-LABEL: v_fneg_fma_x_fneg_y_f32:2525; GCN-SAFE:       ; %bb.0:2526; GCN-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2527; GCN-SAFE-NEXT:    v_fma_f32 v0, v0, -v1, v22528; GCN-SAFE-NEXT:    v_xor_b32_e32 v0, 0x80000000, v02529; GCN-SAFE-NEXT:    s_setpc_b64 s[30:31]2530;2531; GCN-NSZ-LABEL: v_fneg_fma_x_fneg_y_f32:2532; GCN-NSZ:       ; %bb.0:2533; GCN-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2534; GCN-NSZ-NEXT:    v_fma_f32 v0, v0, v1, -v22535; GCN-NSZ-NEXT:    s_setpc_b64 s[30:31]2536  %fneg.b = fneg float %b2537  %fma = call float @llvm.fma.f32(float %a, float %fneg.b, float %c)2538  %fneg = fneg float %fma2539  ret float %fneg2540}2541 2542define float @v_fneg_fma_fneg_fneg_y_f32(float %a, float %b, float %c) #0 {2543; GCN-SAFE-LABEL: v_fneg_fma_fneg_fneg_y_f32:2544; GCN-SAFE:       ; %bb.0:2545; GCN-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2546; GCN-SAFE-NEXT:    v_fma_f32 v0, v0, v1, v22547; GCN-SAFE-NEXT:    v_xor_b32_e32 v0, 0x80000000, v02548; GCN-SAFE-NEXT:    s_setpc_b64 s[30:31]2549;2550; GCN-NSZ-LABEL: v_fneg_fma_fneg_fneg_y_f32:2551; GCN-NSZ:       ; %bb.0:2552; GCN-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2553; GCN-NSZ-NEXT:    v_fma_f32 v0, v0, -v1, -v22554; GCN-NSZ-NEXT:    s_setpc_b64 s[30:31]2555  %fneg.a = fneg float %a2556  %fneg.b = fneg float %b2557  %fma = call float @llvm.fma.f32(float %fneg.a, float %fneg.b, float %c)2558  %fneg = fneg float %fma2559  ret float %fneg2560}2561 2562define float @v_fneg_fma_fneg_x_fneg_f32(float %a, float %b, float %c) #0 {2563; GCN-SAFE-LABEL: v_fneg_fma_fneg_x_fneg_f32:2564; GCN-SAFE:       ; %bb.0:2565; GCN-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2566; GCN-SAFE-NEXT:    v_fma_f32 v0, -v0, v1, -v22567; GCN-SAFE-NEXT:    v_xor_b32_e32 v0, 0x80000000, v02568; GCN-SAFE-NEXT:    s_setpc_b64 s[30:31]2569;2570; GCN-NSZ-LABEL: v_fneg_fma_fneg_x_fneg_f32:2571; GCN-NSZ:       ; %bb.0:2572; GCN-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2573; GCN-NSZ-NEXT:    v_fma_f32 v0, v0, v1, v22574; GCN-NSZ-NEXT:    s_setpc_b64 s[30:31]2575  %fneg.a = fneg float %a2576  %fneg.c = fneg float %c2577  %fma = call float @llvm.fma.f32(float %fneg.a, float %b, float %fneg.c)2578  %fneg = fneg float %fma2579  ret float %fneg2580}2581 2582define float @v_fneg_fma_x_y_fneg_f32(float %a, float %b, float %c) #0 {2583; GCN-SAFE-LABEL: v_fneg_fma_x_y_fneg_f32:2584; GCN-SAFE:       ; %bb.0:2585; GCN-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2586; GCN-SAFE-NEXT:    v_fma_f32 v0, v0, v1, -v22587; GCN-SAFE-NEXT:    v_xor_b32_e32 v0, 0x80000000, v02588; GCN-SAFE-NEXT:    s_setpc_b64 s[30:31]2589;2590; GCN-NSZ-LABEL: v_fneg_fma_x_y_fneg_f32:2591; GCN-NSZ:       ; %bb.0:2592; GCN-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2593; GCN-NSZ-NEXT:    v_fma_f32 v0, v0, -v1, v22594; GCN-NSZ-NEXT:    s_setpc_b64 s[30:31]2595  %fneg.c = fneg float %c2596  %fma = call float @llvm.fma.f32(float %a, float %b, float %fneg.c)2597  %fneg = fneg float %fma2598  ret float %fneg2599}2600 2601define { float, float } @v_fneg_fma_store_use_fneg_x_y_f32(float %a, float %b, float %c) #0 {2602; GCN-SAFE-LABEL: v_fneg_fma_store_use_fneg_x_y_f32:2603; GCN-SAFE:       ; %bb.0:2604; GCN-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2605; GCN-SAFE-NEXT:    v_xor_b32_e32 v3, 0x80000000, v02606; GCN-SAFE-NEXT:    v_fma_f32 v0, -v0, v1, v22607; GCN-SAFE-NEXT:    v_xor_b32_e32 v0, 0x80000000, v02608; GCN-SAFE-NEXT:    v_mov_b32_e32 v1, v32609; GCN-SAFE-NEXT:    s_setpc_b64 s[30:31]2610;2611; GCN-NSZ-LABEL: v_fneg_fma_store_use_fneg_x_y_f32:2612; GCN-NSZ:       ; %bb.0:2613; GCN-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2614; GCN-NSZ-NEXT:    v_xor_b32_e32 v3, 0x80000000, v02615; GCN-NSZ-NEXT:    v_fma_f32 v0, v0, v1, -v22616; GCN-NSZ-NEXT:    v_mov_b32_e32 v1, v32617; GCN-NSZ-NEXT:    s_setpc_b64 s[30:31]2618  %fneg.a = fneg float %a2619  %fma = call float @llvm.fma.f32(float %fneg.a, float %b, float %c)2620  %fneg = fneg float %fma2621  %insert.0 = insertvalue { float, float } poison, float %fneg, 02622  %insert.1 = insertvalue { float, float } %insert.0, float %fneg.a, 12623  ret { float, float } %insert.12624}2625 2626define { float, float } @v_fneg_fma_multi_use_fneg_x_y_f32(float %a, float %b, float %c, float %d) #0 {2627; GCN-SAFE-LABEL: v_fneg_fma_multi_use_fneg_x_y_f32:2628; GCN-SAFE:       ; %bb.0:2629; GCN-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2630; GCN-SAFE-NEXT:    v_fma_f32 v1, -v0, v1, v22631; GCN-SAFE-NEXT:    v_xor_b32_e32 v2, 0x80000000, v12632; GCN-SAFE-NEXT:    v_mul_f32_e64 v1, -v0, v32633; GCN-SAFE-NEXT:    v_mov_b32_e32 v0, v22634; GCN-SAFE-NEXT:    s_setpc_b64 s[30:31]2635;2636; GCN-NSZ-LABEL: v_fneg_fma_multi_use_fneg_x_y_f32:2637; GCN-NSZ:       ; %bb.0:2638; GCN-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2639; GCN-NSZ-NEXT:    v_fma_f32 v2, v0, v1, -v22640; GCN-NSZ-NEXT:    v_mul_f32_e64 v1, -v0, v32641; GCN-NSZ-NEXT:    v_mov_b32_e32 v0, v22642; GCN-NSZ-NEXT:    s_setpc_b64 s[30:31]2643  %fneg.a = fneg float %a2644  %fma = call float @llvm.fma.f32(float %fneg.a, float %b, float %c)2645  %fneg = fneg float %fma2646  %use1 = fmul float %fneg.a, %d2647  %insert.0 = insertvalue { float, float } poison, float %fneg, 02648  %insert.1 = insertvalue { float, float } %insert.0, float %use1, 12649  ret { float, float } %insert.12650}2651 2652; --------------------------------------------------------------------------------2653; fmad tests2654; --------------------------------------------------------------------------------2655 2656define float @v_fneg_fmad_f32(float %a, float %b, float %c) #0 {2657; GCN-SAFE-LABEL: v_fneg_fmad_f32:2658; GCN-SAFE:       ; %bb.0:2659; GCN-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2660; GCN-SAFE-NEXT:    v_mac_f32_e32 v2, v0, v12661; GCN-SAFE-NEXT:    v_xor_b32_e32 v0, 0x80000000, v22662; GCN-SAFE-NEXT:    s_setpc_b64 s[30:31]2663;2664; GCN-NSZ-LABEL: v_fneg_fmad_f32:2665; GCN-NSZ:       ; %bb.0:2666; GCN-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2667; GCN-NSZ-NEXT:    v_mad_f32 v0, v0, -v1, -v22668; GCN-NSZ-NEXT:    s_setpc_b64 s[30:31]2669  %fma = call float @llvm.fmuladd.f32(float %a, float %b, float %c)2670  %fneg = fneg float %fma2671  ret float %fneg2672}2673 2674define <4 x float> @v_fneg_fmad_v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %c) #0 {2675; GCN-SAFE-LABEL: v_fneg_fmad_v4f32:2676; GCN-SAFE:       ; %bb.0:2677; GCN-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2678; GCN-SAFE-NEXT:    v_mac_f32_e32 v11, v3, v72679; GCN-SAFE-NEXT:    v_mac_f32_e32 v10, v2, v62680; GCN-SAFE-NEXT:    v_mac_f32_e32 v9, v1, v52681; GCN-SAFE-NEXT:    v_mac_f32_e32 v8, v0, v42682; GCN-SAFE-NEXT:    v_xor_b32_e32 v0, 0x80000000, v82683; GCN-SAFE-NEXT:    v_xor_b32_e32 v1, 0x80000000, v92684; GCN-SAFE-NEXT:    v_xor_b32_e32 v2, 0x80000000, v102685; GCN-SAFE-NEXT:    v_xor_b32_e32 v3, 0x80000000, v112686; GCN-SAFE-NEXT:    s_setpc_b64 s[30:31]2687;2688; GCN-NSZ-LABEL: v_fneg_fmad_v4f32:2689; GCN-NSZ:       ; %bb.0:2690; GCN-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2691; GCN-NSZ-NEXT:    v_mad_f32 v0, v0, -v4, -v82692; GCN-NSZ-NEXT:    v_mad_f32 v1, v1, -v5, -v92693; GCN-NSZ-NEXT:    v_mad_f32 v2, v2, -v6, -v102694; GCN-NSZ-NEXT:    v_mad_f32 v3, v3, -v7, -v112695; GCN-NSZ-NEXT:    s_setpc_b64 s[30:31]2696  %fma = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %c)2697  %fneg = fneg <4 x float> %fma2698  ret <4 x float> %fneg2699}2700 2701define { float, float } @v_fneg_fmad_multi_use_fmad_f32(float %a, float %b, float %c) #0 {2702; GCN-SAFE-LABEL: v_fneg_fmad_multi_use_fmad_f32:2703; GCN-SAFE:       ; %bb.0:2704; GCN-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2705; GCN-SAFE-NEXT:    v_mac_f32_e32 v2, v0, v12706; GCN-SAFE-NEXT:    v_xor_b32_e32 v0, 0x80000000, v22707; GCN-SAFE-NEXT:    v_mul_f32_e32 v1, 4.0, v22708; GCN-SAFE-NEXT:    s_setpc_b64 s[30:31]2709;2710; GCN-NSZ-LABEL: v_fneg_fmad_multi_use_fmad_f32:2711; GCN-NSZ:       ; %bb.0:2712; GCN-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2713; GCN-NSZ-NEXT:    v_mad_f32 v0, v0, -v1, -v22714; GCN-NSZ-NEXT:    v_mul_f32_e32 v1, -4.0, v02715; GCN-NSZ-NEXT:    s_setpc_b64 s[30:31]2716  %fma = call float @llvm.fmuladd.f32(float %a, float %b, float %c)2717  %fneg = fneg float %fma2718  %use1 = fmul float %fma, 4.02719  %insert.0 = insertvalue { float, float } poison, float %fneg, 02720  %insert.1 = insertvalue { float, float } %insert.0, float %use1, 12721  ret { float, float } %insert.12722}2723 2724; --------------------------------------------------------------------------------2725; fp_extend tests2726; --------------------------------------------------------------------------------2727 2728define double @v_fneg_fp_extend_f32_to_f64(float %a) #0 {2729; GCN-LABEL: v_fneg_fp_extend_f32_to_f64:2730; GCN:       ; %bb.0:2731; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2732; GCN-NEXT:    v_cvt_f64_f32_e64 v[0:1], -v02733; GCN-NEXT:    s_setpc_b64 s[30:31]2734  %fpext = fpext float %a to double2735  %fneg = fneg double %fpext2736  ret double %fneg2737}2738 2739define double @v_fneg_fp_extend_fneg_f32_to_f64(float %a) #0 {2740; GCN-LABEL: v_fneg_fp_extend_fneg_f32_to_f64:2741; GCN:       ; %bb.0:2742; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2743; GCN-NEXT:    v_cvt_f64_f32_e32 v[0:1], v02744; GCN-NEXT:    s_setpc_b64 s[30:31]2745  %fneg.a = fneg float %a2746  %fpext = fpext float %fneg.a to double2747  %fneg = fneg double %fpext2748  ret double %fneg2749}2750 2751define { double, float } @v_fneg_fp_extend_store_use_fneg_f32_to_f64(float %a) #0 {2752; GCN-LABEL: v_fneg_fp_extend_store_use_fneg_f32_to_f64:2753; GCN:       ; %bb.0:2754; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2755; GCN-NEXT:    v_mov_b32_e32 v2, v02756; GCN-NEXT:    v_cvt_f64_f32_e32 v[0:1], v22757; GCN-NEXT:    v_xor_b32_e32 v2, 0x80000000, v22758; GCN-NEXT:    s_setpc_b64 s[30:31]2759  %fneg.a = fneg float %a2760  %fpext = fpext float %fneg.a to double2761  %fneg = fneg double %fpext2762  %insert.0 = insertvalue { double, float } poison, double %fneg, 02763  %insert.1 = insertvalue { double, float } %insert.0, float %fneg.a, 12764  ret { double, float } %insert.12765}2766 2767define { double, double } @v_fneg_multi_use_fp_extend_fneg_f32_to_f64(float %a) #0 {2768; GCN-LABEL: v_fneg_multi_use_fp_extend_fneg_f32_to_f64:2769; GCN:       ; %bb.0:2770; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2771; GCN-NEXT:    v_cvt_f64_f32_e32 v[2:3], v02772; GCN-NEXT:    v_xor_b32_e32 v1, 0x80000000, v32773; GCN-NEXT:    v_mov_b32_e32 v0, v22774; GCN-NEXT:    s_setpc_b64 s[30:31]2775  %fpext = fpext float %a to double2776  %fneg = fneg double %fpext2777  %insert.0 = insertvalue { double, double } poison, double %fneg, 02778  %insert.1 = insertvalue { double, double } %insert.0, double %fpext, 12779  ret { double, double } %insert.12780}2781 2782define { double, double } @v_fneg_multi_foldable_use_fp_extend_fneg_f32_to_f64(float %a) #0 {2783; SI-LABEL: v_fneg_multi_foldable_use_fp_extend_fneg_f32_to_f64:2784; SI:       ; %bb.0:2785; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2786; SI-NEXT:    v_cvt_f64_f32_e32 v[0:1], v02787; SI-NEXT:    v_xor_b32_e32 v4, 0x80000000, v12788; SI-NEXT:    v_mul_f64 v[2:3], v[0:1], 4.02789; SI-NEXT:    v_mov_b32_e32 v1, v42790; SI-NEXT:    s_setpc_b64 s[30:31]2791;2792; VI-LABEL: v_fneg_multi_foldable_use_fp_extend_fneg_f32_to_f64:2793; VI:       ; %bb.0:2794; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2795; VI-NEXT:    v_cvt_f64_f32_e32 v[0:1], v02796; VI-NEXT:    v_mul_f64 v[2:3], v[0:1], 4.02797; VI-NEXT:    v_xor_b32_e32 v1, 0x80000000, v12798; VI-NEXT:    s_setpc_b64 s[30:31]2799  %fpext = fpext float %a to double2800  %fneg = fneg double %fpext2801  %mul = fmul double %fpext, 4.02802  %insert.0 = insertvalue { double, double } poison, double %fneg, 02803  %insert.1 = insertvalue { double, double } %insert.0, double %mul, 12804  ret { double, double } %insert.12805}2806 2807; FIXME: Source modifiers not folded for f16->f322808define { float, float } @v_fneg_multi_use_fp_extend_fneg_f16_to_f32(half %a) #0 {2809; SI-LABEL: v_fneg_multi_use_fp_extend_fneg_f16_to_f32:2810; SI:       ; %bb.0:2811; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2812; SI-NEXT:    v_mov_b32_e32 v1, v02813; SI-NEXT:    v_xor_b32_e32 v0, 0x80000000, v12814; SI-NEXT:    s_setpc_b64 s[30:31]2815;2816; VI-LABEL: v_fneg_multi_use_fp_extend_fneg_f16_to_f32:2817; VI:       ; %bb.0:2818; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2819; VI-NEXT:    v_cvt_f32_f16_e32 v1, v02820; VI-NEXT:    v_xor_b32_e32 v0, 0x80000000, v12821; VI-NEXT:    s_setpc_b64 s[30:31]2822  %fpext = fpext half %a to float2823  %fneg = fneg float %fpext2824  %insert.0 = insertvalue { float, float } poison, float %fneg, 02825  %insert.1 = insertvalue { float, float } %insert.0, float %fpext, 12826  ret { float, float } %insert.12827}2828 2829define { float, float } @v_fneg_multi_foldable_use_fp_extend_fneg_f16_to_f32(half %a) #0 {2830; SI-LABEL: v_fneg_multi_foldable_use_fp_extend_fneg_f16_to_f32:2831; SI:       ; %bb.0:2832; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2833; SI-NEXT:    v_xor_b32_e32 v2, 0x80000000, v02834; SI-NEXT:    v_mul_f32_e32 v1, 4.0, v02835; SI-NEXT:    v_mov_b32_e32 v0, v22836; SI-NEXT:    s_setpc_b64 s[30:31]2837;2838; VI-LABEL: v_fneg_multi_foldable_use_fp_extend_fneg_f16_to_f32:2839; VI:       ; %bb.0:2840; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2841; VI-NEXT:    v_cvt_f32_f16_e32 v1, v02842; VI-NEXT:    v_xor_b32_e32 v0, 0x80000000, v12843; VI-NEXT:    v_mul_f32_e32 v1, 4.0, v12844; VI-NEXT:    s_setpc_b64 s[30:31]2845  %fpext = fpext half %a to float2846  %fneg = fneg float %fpext2847  %mul = fmul float %fpext, 4.02848  %insert.0 = insertvalue { float, float } poison, float %fneg, 02849  %insert.1 = insertvalue { float, float } %insert.0, float %mul, 12850  ret { float, float } %insert.12851}2852 2853; --------------------------------------------------------------------------------2854; fp_round tests2855; --------------------------------------------------------------------------------2856 2857define float @v_fneg_fp_round_f64_to_f32(double %a) #0 {2858; GCN-LABEL: v_fneg_fp_round_f64_to_f32:2859; GCN:       ; %bb.0:2860; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2861; GCN-NEXT:    v_cvt_f32_f64_e64 v0, -v[0:1]2862; GCN-NEXT:    s_setpc_b64 s[30:31]2863  %fpround = fptrunc double %a to float2864  %fneg = fneg float %fpround2865  ret float %fneg2866}2867 2868define float @v_fneg_fp_round_fneg_f64_to_f32(double %a) #0 {2869; GCN-LABEL: v_fneg_fp_round_fneg_f64_to_f32:2870; GCN:       ; %bb.0:2871; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2872; GCN-NEXT:    v_cvt_f32_f64_e32 v0, v[0:1]2873; GCN-NEXT:    s_setpc_b64 s[30:31]2874  %fneg.a = fneg double %a2875  %fpround = fptrunc double %fneg.a to float2876  %fneg = fneg float %fpround2877  ret float %fneg2878}2879 2880define { float, double } @v_fneg_fp_round_store_use_fneg_f64_to_f32(double %a) #0 {2881; GCN-LABEL: v_fneg_fp_round_store_use_fneg_f64_to_f32:2882; GCN:       ; %bb.0:2883; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2884; GCN-NEXT:    v_cvt_f32_f64_e32 v3, v[0:1]2885; GCN-NEXT:    v_xor_b32_e32 v2, 0x80000000, v12886; GCN-NEXT:    v_mov_b32_e32 v1, v02887; GCN-NEXT:    v_mov_b32_e32 v0, v32888; GCN-NEXT:    s_setpc_b64 s[30:31]2889  %fneg.a = fneg double %a2890  %fpround = fptrunc double %fneg.a to float2891  %fneg = fneg float %fpround2892  %insert.0 = insertvalue { float, double } poison, float %fneg, 02893  %insert.1 = insertvalue { float, double } %insert.0, double %fneg.a, 12894  ret { float, double } %insert.12895}2896 2897define { float, double } @v_fneg_fp_round_multi_use_fneg_f64_to_f32(double %a, double %c) #0 {2898; SI-LABEL: v_fneg_fp_round_multi_use_fneg_f64_to_f32:2899; SI:       ; %bb.0:2900; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2901; SI-NEXT:    v_cvt_f32_f64_e32 v4, v[0:1]2902; SI-NEXT:    v_mul_f64 v[1:2], -v[0:1], v[2:3]2903; SI-NEXT:    v_mov_b32_e32 v0, v42904; SI-NEXT:    s_setpc_b64 s[30:31]2905;2906; VI-LABEL: v_fneg_fp_round_multi_use_fneg_f64_to_f32:2907; VI:       ; %bb.0:2908; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2909; VI-NEXT:    v_mul_f64 v[2:3], -v[0:1], v[2:3]2910; VI-NEXT:    v_cvt_f32_f64_e32 v0, v[0:1]2911; VI-NEXT:    v_mov_b32_e32 v1, v22912; VI-NEXT:    v_mov_b32_e32 v2, v32913; VI-NEXT:    s_setpc_b64 s[30:31]2914  %fneg.a = fneg double %a2915  %fpround = fptrunc double %fneg.a to float2916  %fneg = fneg float %fpround2917  %use1 = fmul double %fneg.a, %c2918  %insert.0 = insertvalue { float, double } poison, float %fneg, 02919  %insert.1 = insertvalue { float, double } %insert.0, double %use1, 12920  ret { float, double } %insert.12921}2922 2923define half @v_fneg_fp_round_f32_to_f16(float %a) #0 {2924; SI-LABEL: v_fneg_fp_round_f32_to_f16:2925; SI:       ; %bb.0:2926; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2927; SI-NEXT:    v_cvt_f16_f32_e64 v0, -v02928; SI-NEXT:    v_cvt_f32_f16_e32 v0, v02929; SI-NEXT:    s_setpc_b64 s[30:31]2930;2931; VI-LABEL: v_fneg_fp_round_f32_to_f16:2932; VI:       ; %bb.0:2933; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2934; VI-NEXT:    v_cvt_f16_f32_e64 v0, -v02935; VI-NEXT:    s_setpc_b64 s[30:31]2936  %fpround = fptrunc float %a to half2937  %fneg = fneg half %fpround2938  ret half %fneg2939}2940 2941define half @v_fneg_fp_round_fneg_f32_to_f16(float %a) #0 {2942; SI-LABEL: v_fneg_fp_round_fneg_f32_to_f16:2943; SI:       ; %bb.0:2944; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2945; SI-NEXT:    v_cvt_f16_f32_e32 v0, v02946; SI-NEXT:    v_cvt_f32_f16_e32 v0, v02947; SI-NEXT:    s_setpc_b64 s[30:31]2948;2949; VI-LABEL: v_fneg_fp_round_fneg_f32_to_f16:2950; VI:       ; %bb.0:2951; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2952; VI-NEXT:    v_cvt_f16_f32_e32 v0, v02953; VI-NEXT:    s_setpc_b64 s[30:31]2954  %fneg.a = fneg float %a2955  %fpround = fptrunc float %fneg.a to half2956  %fneg = fneg half %fpround2957  ret half %fneg2958}2959 2960define { float, float } @v_fneg_multi_use_fp_round_fneg_f64_to_f32(double %a) #0 {2961; GCN-LABEL: v_fneg_multi_use_fp_round_fneg_f64_to_f32:2962; GCN:       ; %bb.0:2963; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2964; GCN-NEXT:    v_cvt_f32_f64_e32 v1, v[0:1]2965; GCN-NEXT:    v_xor_b32_e32 v0, 0x80000000, v12966; GCN-NEXT:    s_setpc_b64 s[30:31]2967  %fpround = fptrunc double %a to float2968  %fneg = fneg float %fpround2969  %insert.0 = insertvalue { float, float } poison, float %fneg, 02970  %insert.1 = insertvalue { float, float } %insert.0, float %fpround, 12971  ret { float, float } %insert.12972}2973 2974define { half, float } @v_fneg_fp_round_store_use_fneg_f32_to_f16(float %a) #0 {2975; SI-LABEL: v_fneg_fp_round_store_use_fneg_f32_to_f16:2976; SI:       ; %bb.0:2977; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2978; SI-NEXT:    v_cvt_f16_f32_e32 v1, v02979; SI-NEXT:    v_cvt_f32_f16_e32 v2, v12980; SI-NEXT:    v_xor_b32_e32 v1, 0x80000000, v02981; SI-NEXT:    v_mov_b32_e32 v0, v22982; SI-NEXT:    s_setpc_b64 s[30:31]2983;2984; VI-LABEL: v_fneg_fp_round_store_use_fneg_f32_to_f16:2985; VI:       ; %bb.0:2986; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2987; VI-NEXT:    v_cvt_f16_f32_e32 v2, v02988; VI-NEXT:    v_xor_b32_e32 v1, 0x80000000, v02989; VI-NEXT:    v_mov_b32_e32 v0, v22990; VI-NEXT:    s_setpc_b64 s[30:31]2991  %fneg.a = fneg float %a2992  %fpround = fptrunc float %fneg.a to half2993  %fneg = fneg half %fpround2994  %insert.0 = insertvalue { half, float } poison, half %fneg, 02995  %insert.1 = insertvalue { half, float } %insert.0, float %fneg.a, 12996  ret { half, float } %insert.12997}2998 2999define { half, float } @v_fneg_fp_round_multi_use_fneg_f32_to_f16(float %a, float %c) #0 {3000; SI-LABEL: v_fneg_fp_round_multi_use_fneg_f32_to_f16:3001; SI:       ; %bb.0:3002; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3003; SI-NEXT:    v_cvt_f16_f32_e32 v2, v03004; SI-NEXT:    v_mul_f32_e64 v1, -v0, v13005; SI-NEXT:    v_cvt_f32_f16_e32 v2, v23006; SI-NEXT:    v_mov_b32_e32 v0, v23007; SI-NEXT:    s_setpc_b64 s[30:31]3008;3009; VI-LABEL: v_fneg_fp_round_multi_use_fneg_f32_to_f16:3010; VI:       ; %bb.0:3011; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3012; VI-NEXT:    v_cvt_f16_f32_e32 v2, v03013; VI-NEXT:    v_mul_f32_e64 v1, -v0, v13014; VI-NEXT:    v_mov_b32_e32 v0, v23015; VI-NEXT:    s_setpc_b64 s[30:31]3016  %fneg.a = fneg float %a3017  %fpround = fptrunc float %fneg.a to half3018  %fneg = fneg half %fpround3019  %use1 = fmul float %fneg.a, %c3020  %insert.0 = insertvalue { half, float } poison, half %fneg, 03021  %insert.1 = insertvalue { half, float } %insert.0, float %use1, 13022  ret { half, float } %insert.13023}3024 3025; --------------------------------------------------------------------------------3026; rcp tests3027; --------------------------------------------------------------------------------3028 3029define float @v_fneg_rcp_f32(float %a) #0 {3030; GCN-LABEL: v_fneg_rcp_f32:3031; GCN:       ; %bb.0:3032; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3033; GCN-NEXT:    v_rcp_f32_e64 v0, -v03034; GCN-NEXT:    s_setpc_b64 s[30:31]3035  %rcp = call float @llvm.amdgcn.rcp.f32(float %a)3036  %fneg = fneg float %rcp3037  ret float %fneg3038}3039 3040define float @v_fneg_rcp_fneg_f32(float %a) #0 {3041; GCN-LABEL: v_fneg_rcp_fneg_f32:3042; GCN:       ; %bb.0:3043; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3044; GCN-NEXT:    v_rcp_f32_e32 v0, v03045; GCN-NEXT:    s_setpc_b64 s[30:31]3046  %fneg.a = fneg float %a3047  %rcp = call float @llvm.amdgcn.rcp.f32(float %fneg.a)3048  %fneg = fneg float %rcp3049  ret float %fneg3050}3051 3052define void @v_fneg_rcp_store_use_fneg_f32(float %a, ptr addrspace(1) %ptr0, ptr addrspace(1) %ptr1) #0 {3053; GCN-LABEL: v_fneg_rcp_store_use_fneg_f32:3054; GCN:       ; %bb.0:3055; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3056; GCN-NEXT:    v_rcp_f32_e32 v5, v03057; GCN-NEXT:    v_xor_b32_e32 v0, 0x80000000, v03058; GCN-NEXT:    flat_store_dword v[1:2], v53059; GCN-NEXT:    flat_store_dword v[3:4], v03060; GCN-NEXT:    s_waitcnt vmcnt(0)3061; GCN-NEXT:    s_setpc_b64 s[30:31]3062  %fneg.a = fneg float %a3063  %rcp = call float @llvm.amdgcn.rcp.f32(float %fneg.a)3064  %fneg = fneg float %rcp3065  store float %fneg, ptr addrspace(1) %ptr03066  store float %fneg.a, ptr addrspace(1) %ptr13067  ret void3068}3069 3070define { float, float } @v_fneg_rcp_multi_use_fneg_f32(float %a, float %c) #0 {3071; GCN-LABEL: v_fneg_rcp_multi_use_fneg_f32:3072; GCN:       ; %bb.0:3073; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3074; GCN-NEXT:    v_rcp_f32_e32 v2, v03075; GCN-NEXT:    v_mul_f32_e64 v1, -v0, v13076; GCN-NEXT:    v_mov_b32_e32 v0, v23077; GCN-NEXT:    s_setpc_b64 s[30:31]3078  %fneg.a = fneg float %a3079  %rcp = call float @llvm.amdgcn.rcp.f32(float %fneg.a)3080  %fneg = fneg float %rcp3081  %use1 = fmul float %fneg.a, %c3082  %insert.0 = insertvalue { float, float } poison, float %fneg, 03083  %insert.1 = insertvalue { float, float } %insert.0, float %use1, 13084  ret { float, float } %insert.13085}3086 3087; Test getNegatedExpression works for rcp nodes3088define float @v_negated_rcp_f32(float %arg0, float %arg1) #1 {3089; GCN-LABEL: v_negated_rcp_f32:3090; GCN:       ; %bb.0:3091; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3092; GCN-NEXT:    v_fma_f32 v0, v0, v1, 2.03093; GCN-NEXT:    v_rcp_f32_e32 v0, v03094; GCN-NEXT:    v_add_f32_e32 v0, v1, v03095; GCN-NEXT:    s_setpc_b64 s[30:31]3096  %neg.arg0 = fneg float %arg03097  %fma = call nsz float @llvm.fma.f32(float %neg.arg0, float %arg1, float -2.0)3098  %rcp0 = call float @llvm.amdgcn.rcp.f32(float %fma)3099  %mul = fsub nsz float %arg1, %rcp03100  ret float %mul3101}3102 3103; --------------------------------------------------------------------------------3104; fmul_legacy tests3105; --------------------------------------------------------------------------------3106 3107define float @v_fneg_mul_legacy_f32(float %a, float %b) #0 {3108; GCN-LABEL: v_fneg_mul_legacy_f32:3109; GCN:       ; %bb.0:3110; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3111; GCN-NEXT:    v_mul_legacy_f32_e64 v0, v0, -v13112; GCN-NEXT:    s_setpc_b64 s[30:31]3113  %mul = call float @llvm.amdgcn.fmul.legacy(float %a, float %b)3114  %fneg = fneg float %mul3115  ret float %fneg3116}3117 3118define { float, float } @v_fneg_mul_legacy_store_use_mul_legacy_f32(float %a, float %b) #0 {3119; GCN-LABEL: v_fneg_mul_legacy_store_use_mul_legacy_f32:3120; GCN:       ; %bb.0:3121; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3122; GCN-NEXT:    v_mul_legacy_f32_e32 v1, v0, v13123; GCN-NEXT:    v_xor_b32_e32 v0, 0x80000000, v13124; GCN-NEXT:    s_setpc_b64 s[30:31]3125  %mul = call float @llvm.amdgcn.fmul.legacy(float %a, float %b)3126  %fneg = fneg float %mul3127  %insert.0 = insertvalue { float, float } poison, float %fneg, 03128  %insert.1 = insertvalue { float, float } %insert.0, float %mul, 13129  ret { float, float } %insert.13130}3131 3132define { float, float } @v_fneg_mul_legacy_multi_use_mul_legacy_f32(float %a, float %b) #0 {3133; GCN-LABEL: v_fneg_mul_legacy_multi_use_mul_legacy_f32:3134; GCN:       ; %bb.0:3135; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3136; GCN-NEXT:    v_mul_legacy_f32_e64 v0, v0, -v13137; GCN-NEXT:    v_mul_legacy_f32_e64 v1, -v0, 4.03138; GCN-NEXT:    s_setpc_b64 s[30:31]3139  %mul = call float @llvm.amdgcn.fmul.legacy(float %a, float %b)3140  %fneg = fneg float %mul3141  %use1 = call float @llvm.amdgcn.fmul.legacy(float %mul, float 4.0)3142  %insert.0 = insertvalue { float, float } poison, float %fneg, 03143  %insert.1 = insertvalue { float, float } %insert.0, float %use1, 13144  ret { float, float } %insert.13145}3146 3147define float @v_fneg_mul_legacy_fneg_x_f32(float %a, float %b) #0 {3148; GCN-LABEL: v_fneg_mul_legacy_fneg_x_f32:3149; GCN:       ; %bb.0:3150; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3151; GCN-NEXT:    v_mul_legacy_f32_e32 v0, v0, v13152; GCN-NEXT:    s_setpc_b64 s[30:31]3153  %fneg.a = fneg float %a3154  %mul = call float @llvm.amdgcn.fmul.legacy(float %fneg.a, float %b)3155  %fneg = fneg float %mul3156  ret float %fneg3157}3158 3159define float @v_fneg_mul_legacy_x_fneg_f32(float %a, float %b) #0 {3160; GCN-LABEL: v_fneg_mul_legacy_x_fneg_f32:3161; GCN:       ; %bb.0:3162; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3163; GCN-NEXT:    v_mul_legacy_f32_e32 v0, v0, v13164; GCN-NEXT:    s_setpc_b64 s[30:31]3165  %fneg.b = fneg float %b3166  %mul = call float @llvm.amdgcn.fmul.legacy(float %a, float %fneg.b)3167  %fneg = fneg float %mul3168  ret float %fneg3169}3170 3171define float @v_fneg_mul_legacy_fneg_fneg_f32(float %a, float %b) #0 {3172; GCN-LABEL: v_fneg_mul_legacy_fneg_fneg_f32:3173; GCN:       ; %bb.0:3174; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3175; GCN-NEXT:    v_mul_legacy_f32_e64 v0, v0, -v13176; GCN-NEXT:    s_setpc_b64 s[30:31]3177  %fneg.a = fneg float %a3178  %fneg.b = fneg float %b3179  %mul = call float @llvm.amdgcn.fmul.legacy(float %fneg.a, float %fneg.b)3180  %fneg = fneg float %mul3181  ret float %fneg3182}3183 3184define { float, float } @v_fneg_mul_legacy_store_use_fneg_x_f32(float %a, float %b) #0 {3185; GCN-LABEL: v_fneg_mul_legacy_store_use_fneg_x_f32:3186; GCN:       ; %bb.0:3187; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3188; GCN-NEXT:    v_xor_b32_e32 v2, 0x80000000, v03189; GCN-NEXT:    v_mul_legacy_f32_e32 v0, v0, v13190; GCN-NEXT:    v_mov_b32_e32 v1, v23191; GCN-NEXT:    s_setpc_b64 s[30:31]3192  %fneg.a = fneg float %a3193  %mul = call float @llvm.amdgcn.fmul.legacy(float %fneg.a, float %b)3194  %fneg = fneg float %mul3195 3196  %insert.0 = insertvalue { float, float } poison, float %fneg, 03197  %insert.1 = insertvalue { float, float } %insert.0, float %fneg.a, 13198  ret { float, float } %insert.13199}3200 3201define { float, float } @v_fneg_mul_legacy_multi_use_fneg_x_f32(float %a, float %b, float %c) #0 {3202; GCN-LABEL: v_fneg_mul_legacy_multi_use_fneg_x_f32:3203; GCN:       ; %bb.0:3204; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3205; GCN-NEXT:    v_mul_legacy_f32_e32 v3, v0, v13206; GCN-NEXT:    v_mul_legacy_f32_e64 v1, -v0, v23207; GCN-NEXT:    v_mov_b32_e32 v0, v33208; GCN-NEXT:    s_setpc_b64 s[30:31]3209  %fneg.a = fneg float %a3210  %mul = call float @llvm.amdgcn.fmul.legacy(float %fneg.a, float %b)3211  %fneg = fneg float %mul3212  %use1 = call float @llvm.amdgcn.fmul.legacy(float %fneg.a, float %c)3213  %insert.0 = insertvalue { float, float } poison, float %fneg, 03214  %insert.1 = insertvalue { float, float } %insert.0, float %use1, 13215  ret { float, float } %insert.13216}3217 3218; --------------------------------------------------------------------------------3219; sin tests3220; --------------------------------------------------------------------------------3221 3222define float @v_fneg_sin_f32(float %a) #0 {3223; GCN-LABEL: v_fneg_sin_f32:3224; GCN:       ; %bb.0:3225; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3226; GCN-NEXT:    v_mul_f32_e32 v0, 0xbe22f983, v03227; GCN-NEXT:    v_fract_f32_e32 v0, v03228; GCN-NEXT:    v_sin_f32_e32 v0, v03229; GCN-NEXT:    s_setpc_b64 s[30:31]3230  %sin = call float @llvm.sin.f32(float %a)3231  %fneg = fneg float %sin3232  ret float %fneg3233}3234 3235define float @v_fneg_amdgcn_sin_f32(float %a) #0 {3236; GCN-LABEL: v_fneg_amdgcn_sin_f32:3237; GCN:       ; %bb.0:3238; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3239; GCN-NEXT:    v_sin_f32_e64 v0, -v03240; GCN-NEXT:    s_setpc_b64 s[30:31]3241  %sin = call float @llvm.amdgcn.sin.f32(float %a)3242  %fneg = fneg float %sin3243  ret float %fneg3244}3245 3246; --------------------------------------------------------------------------------3247; ftrunc tests3248; --------------------------------------------------------------------------------3249 3250define float @v_fneg_trunc_f32(float %a) #0 {3251; GCN-LABEL: v_fneg_trunc_f32:3252; GCN:       ; %bb.0:3253; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3254; GCN-NEXT:    v_trunc_f32_e64 v0, -v03255; GCN-NEXT:    s_setpc_b64 s[30:31]3256  %trunc = call float @llvm.trunc.f32(float %a)3257  %fneg = fneg float %trunc3258  ret float %fneg3259}3260 3261; --------------------------------------------------------------------------------3262; fround tests3263; --------------------------------------------------------------------------------3264 3265define float @v_fneg_round_f32(float %a) #0 {3266; GCN-SAFE-LABEL: v_fneg_round_f32:3267; GCN-SAFE:       ; %bb.0:3268; GCN-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3269; GCN-SAFE-NEXT:    v_trunc_f32_e32 v1, v03270; GCN-SAFE-NEXT:    v_sub_f32_e32 v2, v0, v13271; GCN-SAFE-NEXT:    v_cmp_ge_f32_e64 s[4:5], |v2|, 0.53272; GCN-SAFE-NEXT:    v_cndmask_b32_e64 v2, 0, 1.0, s[4:5]3273; GCN-SAFE-NEXT:    s_brev_b32 s4, -23274; GCN-SAFE-NEXT:    v_bfi_b32 v0, s4, v2, v03275; GCN-SAFE-NEXT:    v_add_f32_e32 v0, v1, v03276; GCN-SAFE-NEXT:    v_xor_b32_e32 v0, 0x80000000, v03277; GCN-SAFE-NEXT:    s_setpc_b64 s[30:31]3278;3279; GCN-NSZ-LABEL: v_fneg_round_f32:3280; GCN-NSZ:       ; %bb.0:3281; GCN-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3282; GCN-NSZ-NEXT:    v_trunc_f32_e32 v1, v03283; GCN-NSZ-NEXT:    v_sub_f32_e32 v2, v0, v13284; GCN-NSZ-NEXT:    v_cmp_ge_f32_e64 s[4:5], |v2|, 0.53285; GCN-NSZ-NEXT:    v_cndmask_b32_e64 v2, 0, 1.0, s[4:5]3286; GCN-NSZ-NEXT:    s_brev_b32 s4, -23287; GCN-NSZ-NEXT:    v_bfi_b32 v0, s4, v2, v03288; GCN-NSZ-NEXT:    v_sub_f32_e64 v0, -v1, v03289; GCN-NSZ-NEXT:    s_setpc_b64 s[30:31]3290  %round = call float @llvm.round.f32(float %a)3291  %fneg = fneg float %round3292  ret float %fneg3293}3294 3295; --------------------------------------------------------------------------------3296; rint tests3297; --------------------------------------------------------------------------------3298 3299define float @v_fneg_rint_f32(float %a) #0 {3300; GCN-LABEL: v_fneg_rint_f32:3301; GCN:       ; %bb.0:3302; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3303; GCN-NEXT:    v_rndne_f32_e64 v0, -v03304; GCN-NEXT:    s_setpc_b64 s[30:31]3305  %rint = call float @llvm.rint.f32(float %a)3306  %fneg = fneg float %rint3307  ret float %fneg3308}3309 3310; --------------------------------------------------------------------------------3311; nearbyint tests3312; --------------------------------------------------------------------------------3313 3314define float @v_fneg_nearbyint_f32(float %a) #0 {3315; GCN-LABEL: v_fneg_nearbyint_f32:3316; GCN:       ; %bb.0:3317; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3318; GCN-NEXT:    v_rndne_f32_e64 v0, -v03319; GCN-NEXT:    s_setpc_b64 s[30:31]3320  %nearbyint = call float @llvm.nearbyint.f32(float %a)3321  %fneg = fneg float %nearbyint3322  ret float %fneg3323}3324 3325; --------------------------------------------------------------------------------3326; fcanonicalize tests3327; --------------------------------------------------------------------------------3328 3329define float @v_fneg_canonicalize_f32(float %a) #0 {3330; GCN-LABEL: v_fneg_canonicalize_f32:3331; GCN:       ; %bb.0:3332; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3333; GCN-NEXT:    v_mul_f32_e32 v0, -1.0, v03334; GCN-NEXT:    s_setpc_b64 s[30:31]3335  %trunc = call float @llvm.canonicalize.f32(float %a)3336  %fneg = fneg float %trunc3337  ret float %fneg3338}3339 3340; --------------------------------------------------------------------------------3341; arithmetic.fence tests3342; --------------------------------------------------------------------------------3343 3344define float @v_fneg_arithmetic_fence_f32(float %a) #0 {3345; GCN-LABEL: v_fneg_arithmetic_fence_f32:3346; GCN:       ; %bb.0:3347; GCN-NEXT:    ;ARITH_FENCE3348; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3349; GCN-NEXT:    v_xor_b32_e32 v0, 0x80000000, v03350; GCN-NEXT:    s_setpc_b64 s[30:31]3351  %fence = call float @llvm.arithmetic.fence.f32(float %a)3352  %fneg = fneg float %fence3353  ret float %fneg3354}3355 3356define float @v_fneg_arithmetic_fence_fmul_f32(float %a, float %b) #0 {3357; GCN-LABEL: v_fneg_arithmetic_fence_fmul_f32:3358; GCN:       ; %bb.0:3359; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3360; GCN-NEXT:    v_mul_f32_e32 v0, v0, v13361; GCN-NEXT:    ;ARITH_FENCE3362; GCN-NEXT:    v_xor_b32_e32 v0, 0x80000000, v03363; GCN-NEXT:    s_setpc_b64 s[30:31]3364  %mul = fmul float %a, %b3365  %fence = call float @llvm.arithmetic.fence.f32(float %mul)3366  %fneg = fneg float %fence3367  ret float %fneg3368}3369 3370; --------------------------------------------------------------------------------3371; vintrp tests3372; --------------------------------------------------------------------------------3373 3374define { float, float } @v_fneg_interp_p1_f32(float %a, float %b) #0 {3375; SI-LABEL: v_fneg_interp_p1_f32:3376; SI:       ; %bb.0:3377; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3378; SI-NEXT:    v_mul_f32_e64 v1, v0, -v13379; SI-NEXT:    s_mov_b32 m0, 03380; SI-NEXT:    v_interp_p1_f32 v0, v1, attr0.x3381; SI-NEXT:    v_interp_p1_f32 v1, v1, attr0.y3382; SI-NEXT:    s_setpc_b64 s[30:31]3383;3384; VI-LABEL: v_fneg_interp_p1_f32:3385; VI:       ; %bb.0:3386; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3387; VI-NEXT:    v_mul_f32_e64 v1, v0, -v13388; VI-NEXT:    s_mov_b32 m0, 03389; VI-NEXT:    v_interp_p1_f32_e32 v0, v1, attr0.x3390; VI-NEXT:    v_interp_p1_f32_e32 v1, v1, attr0.y3391; VI-NEXT:    s_setpc_b64 s[30:31]3392  %mul = fmul float %a, %b3393  %fneg = fneg float %mul3394  %intrp0 = call float @llvm.amdgcn.interp.p1(float %fneg, i32 0, i32 0, i32 0)3395  %intrp1 = call float @llvm.amdgcn.interp.p1(float %fneg, i32 1, i32 0, i32 0)3396  %insert.0 = insertvalue { float, float } poison, float %intrp0, 03397  %insert.1 = insertvalue { float, float } %insert.0, float %intrp1, 13398  ret { float, float } %insert.13399}3400 3401define { float, float } @v_fneg_interp_p2_f32(float %a, float %b) #0 {3402; SI-LABEL: v_fneg_interp_p2_f32:3403; SI:       ; %bb.0:3404; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3405; SI-NEXT:    v_mul_f32_e64 v2, v0, -v13406; SI-NEXT:    v_mov_b32_e32 v1, 4.03407; SI-NEXT:    v_mov_b32_e32 v0, 4.03408; SI-NEXT:    s_mov_b32 m0, 03409; SI-NEXT:    v_interp_p2_f32 v0, v2, attr0.x3410; SI-NEXT:    v_interp_p2_f32 v1, v2, attr0.y3411; SI-NEXT:    s_setpc_b64 s[30:31]3412;3413; VI-LABEL: v_fneg_interp_p2_f32:3414; VI:       ; %bb.0:3415; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3416; VI-NEXT:    v_mul_f32_e64 v2, v0, -v13417; VI-NEXT:    v_mov_b32_e32 v1, 4.03418; VI-NEXT:    v_mov_b32_e32 v0, 4.03419; VI-NEXT:    s_mov_b32 m0, 03420; VI-NEXT:    v_interp_p2_f32_e32 v0, v2, attr0.x3421; VI-NEXT:    v_interp_p2_f32_e32 v1, v2, attr0.y3422; VI-NEXT:    s_setpc_b64 s[30:31]3423  %mul = fmul float %a, %b3424  %fneg = fneg float %mul3425  %intrp0 = call float @llvm.amdgcn.interp.p2(float 4.0, float %fneg, i32 0, i32 0, i32 0)3426  %intrp1 = call float @llvm.amdgcn.interp.p2(float 4.0, float %fneg, i32 1, i32 0, i32 0)3427  %insert.0 = insertvalue { float, float } poison, float %intrp0, 03428  %insert.1 = insertvalue { float, float } %insert.0, float %intrp1, 13429  ret { float, float } %insert.13430}3431 3432; --------------------------------------------------------------------------------3433; CopyToReg tests3434; --------------------------------------------------------------------------------3435 3436define void @v_fneg_copytoreg_f32(ptr addrspace(1) %out, float %a, float %b, float %c, i32 %d) #0 {3437; SI-LABEL: v_fneg_copytoreg_f32:3438; SI:       ; %bb.0:3439; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3440; SI-NEXT:    v_and_b32_e32 v6, 0x3ff, v313441; SI-NEXT:    v_lshlrev_b32_e32 v6, 2, v63442; SI-NEXT:    v_add_i32_e32 v0, vcc, v0, v63443; SI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc3444; SI-NEXT:    v_mul_f32_e32 v2, v2, v33445; SI-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v53446; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc3447; SI-NEXT:    s_cbranch_execz .LBB192_23448; SI-NEXT:  ; %bb.1: ; %if3449; SI-NEXT:    v_mul_f32_e64 v3, -v2, v43450; SI-NEXT:    flat_store_dword v[0:1], v33451; SI-NEXT:    s_waitcnt vmcnt(0)3452; SI-NEXT:  .LBB192_2: ; %endif3453; SI-NEXT:    s_or_b64 exec, exec, s[4:5]3454; SI-NEXT:    flat_store_dword v[0:1], v23455; SI-NEXT:    s_waitcnt vmcnt(0)3456; SI-NEXT:    s_setpc_b64 s[30:31]3457;3458; VI-LABEL: v_fneg_copytoreg_f32:3459; VI:       ; %bb.0:3460; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3461; VI-NEXT:    v_and_b32_e32 v6, 0x3ff, v313462; VI-NEXT:    v_lshlrev_b32_e32 v6, 2, v63463; VI-NEXT:    v_add_u32_e32 v0, vcc, v0, v63464; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc3465; VI-NEXT:    v_mul_f32_e32 v2, v2, v33466; VI-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v53467; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc3468; VI-NEXT:    s_cbranch_execz .LBB192_23469; VI-NEXT:  ; %bb.1: ; %if3470; VI-NEXT:    v_mul_f32_e64 v3, -v2, v43471; VI-NEXT:    flat_store_dword v[0:1], v33472; VI-NEXT:    s_waitcnt vmcnt(0)3473; VI-NEXT:  .LBB192_2: ; %endif3474; VI-NEXT:    s_or_b64 exec, exec, s[4:5]3475; VI-NEXT:    flat_store_dword v[0:1], v23476; VI-NEXT:    s_waitcnt vmcnt(0)3477; VI-NEXT:    s_setpc_b64 s[30:31]3478  %tid = call i32 @llvm.amdgcn.workitem.id.x()3479  %tid.ext = sext i32 %tid to i643480  %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext3481  %mul = fmul float %a, %b3482  %fneg = fneg float %mul3483  %cmp0 = icmp eq i32 %d, 03484  br i1 %cmp0, label %if, label %endif3485 3486if:3487  %mul1 = fmul float %fneg, %c3488  store volatile float %mul1, ptr addrspace(1) %out.gep3489  br label %endif3490 3491endif:3492  store volatile float %mul, ptr addrspace(1) %out.gep3493  ret void3494}3495 3496; --------------------------------------------------------------------------------3497; inlineasm tests3498; --------------------------------------------------------------------------------3499 3500; Can't fold into use, so should fold into source3501define float @v_fneg_inlineasm_f32(float %a, float %b, float %c, i32 %d) #0 {3502; GCN-LABEL: v_fneg_inlineasm_f32:3503; GCN:       ; %bb.0:3504; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3505; GCN-NEXT:    v_mul_f32_e64 v0, v0, -v13506; GCN-NEXT:    ;;#ASMSTART3507; GCN-NEXT:    ; use v03508; GCN-NEXT:    ;;#ASMEND3509; GCN-NEXT:    s_setpc_b64 s[30:31]3510  %mul = fmul float %a, %b3511  %fneg = fneg float %mul3512  call void asm sideeffect "; use $0", "v"(float %fneg) #03513  ret float %fneg3514}3515 3516; --------------------------------------------------------------------------------3517; inlineasm tests3518; --------------------------------------------------------------------------------3519 3520; Can't fold into use, so should fold into source3521define float @v_fneg_inlineasm_multi_use_src_f32(ptr addrspace(1) %out, float %a, float %b, float %c, i32 %d) #0 {3522; GCN-LABEL: v_fneg_inlineasm_multi_use_src_f32:3523; GCN:       ; %bb.0:3524; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3525; GCN-NEXT:    v_mul_f32_e32 v0, v2, v33526; GCN-NEXT:    v_xor_b32_e32 v1, 0x80000000, v03527; GCN-NEXT:    ;;#ASMSTART3528; GCN-NEXT:    ; use v13529; GCN-NEXT:    ;;#ASMEND3530; GCN-NEXT:    s_setpc_b64 s[30:31]3531  %mul = fmul float %a, %b3532  %fneg = fneg float %mul3533  call void asm sideeffect "; use $0", "v"(float %fneg) #03534  ret float %mul3535}3536 3537; --------------------------------------------------------------------------------3538; code size regression tests3539; --------------------------------------------------------------------------------3540 3541; There are multiple users of the fneg that must use a VOP33542; instruction, so there is no penalty3543define { float, float } @multiuse_fneg_2_vop3_users_f32(float %a, float %b, float %c) #0 {3544; GCN-LABEL: multiuse_fneg_2_vop3_users_f32:3545; GCN:       ; %bb.0:3546; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3547; GCN-NEXT:    v_fma_f32 v3, -v0, v1, v23548; GCN-NEXT:    v_fma_f32 v1, -v0, v2, 2.03549; GCN-NEXT:    v_mov_b32_e32 v0, v33550; GCN-NEXT:    s_setpc_b64 s[30:31]3551  %fneg.a = fneg float %a3552  %fma0 = call float @llvm.fma.f32(float %fneg.a, float %b, float %c)3553  %fma1 = call float @llvm.fma.f32(float %fneg.a, float %c, float 2.0)3554  %insert.0 = insertvalue { float, float } poison, float %fma0, 03555  %insert.1 = insertvalue { float, float } %insert.0, float %fma1, 13556  ret { float, float } %insert.13557}3558 3559; There are multiple users, but both require using a larger encoding3560; for the modifier.3561define { float, float } @multiuse_fneg_2_vop2_users_f32(float %a, float %b, float %c) #0 {3562; GCN-LABEL: multiuse_fneg_2_vop2_users_f32:3563; GCN:       ; %bb.0:3564; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3565; GCN-NEXT:    v_mul_f32_e64 v3, -v0, v13566; GCN-NEXT:    v_mul_f32_e64 v1, -v0, v23567; GCN-NEXT:    v_mov_b32_e32 v0, v33568; GCN-NEXT:    s_setpc_b64 s[30:31]3569  %fneg.a = fneg float %a3570  %mul0 = fmul float %fneg.a, %b3571  %mul1 = fmul float %fneg.a, %c3572  %insert.0 = insertvalue { float, float } poison, float %mul0, 03573  %insert.1 = insertvalue { float, float } %insert.0, float %mul1, 13574  ret { float, float } %insert.13575}3576 3577; One user is VOP3 so has no cost to folding the modifier, the other does.3578define { float, float } @multiuse_fneg_vop2_vop3_users_f32(float %a, float %b, float %c) #0 {3579; GCN-LABEL: multiuse_fneg_vop2_vop3_users_f32:3580; GCN:       ; %bb.0:3581; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3582; GCN-NEXT:    v_fma_f32 v3, -v0, v1, 2.03583; GCN-NEXT:    v_mul_f32_e64 v1, -v0, v23584; GCN-NEXT:    v_mov_b32_e32 v0, v33585; GCN-NEXT:    s_setpc_b64 s[30:31]3586  %fneg.a = fneg float %a3587  %fma0 = call float @llvm.fma.f32(float %fneg.a, float %b, float 2.0)3588  %mul1 = fmul float %fneg.a, %c3589 3590  %insert.0 = insertvalue { float, float } poison, float %fma0, 03591  %insert.1 = insertvalue { float, float } %insert.0, float %mul1, 13592  ret { float, float } %insert.13593}3594 3595; The use of the fneg requires a code size increase, but folding into3596; the source does not3597define { float, float } @free_fold_src_code_size_cost_use_f32(ptr addrspace(1) %out, float %a, float %b, float %c, float %d) #0 {3598; GCN-SAFE-LABEL: free_fold_src_code_size_cost_use_f32:3599; GCN-SAFE:       ; %bb.0:3600; GCN-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3601; GCN-SAFE-NEXT:    v_fma_f32 v1, v2, v3, 2.03602; GCN-SAFE-NEXT:    v_mul_f32_e64 v0, -v1, v43603; GCN-SAFE-NEXT:    v_mul_f32_e64 v1, -v1, v53604; GCN-SAFE-NEXT:    s_setpc_b64 s[30:31]3605;3606; GCN-NSZ-LABEL: free_fold_src_code_size_cost_use_f32:3607; GCN-NSZ:       ; %bb.0:3608; GCN-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3609; GCN-NSZ-NEXT:    v_fma_f32 v1, v2, -v3, -2.03610; GCN-NSZ-NEXT:    v_mul_f32_e32 v0, v1, v43611; GCN-NSZ-NEXT:    v_mul_f32_e32 v1, v1, v53612; GCN-NSZ-NEXT:    s_setpc_b64 s[30:31]3613  %fma0 = call float @llvm.fma.f32(float %a, float %b, float 2.0)3614  %fneg.fma0 = fneg float %fma03615  %mul1 = fmul float %fneg.fma0, %c3616  %mul2 = fmul float %fneg.fma0, %d3617 3618  %insert.0 = insertvalue { float, float } poison, float %mul1, 03619  %insert.1 = insertvalue { float, float } %insert.0, float %mul2, 13620  ret { float, float } %insert.13621}3622 3623define { double, double } @free_fold_src_code_size_cost_use_f64(double %a, double %b, double %c, double %d) #0 {3624; GCN-LABEL: free_fold_src_code_size_cost_use_f64:3625; GCN:       ; %bb.0:3626; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3627; GCN-NEXT:    v_fma_f64 v[2:3], v[0:1], v[2:3], 2.03628; GCN-NEXT:    v_mul_f64 v[0:1], -v[2:3], v[4:5]3629; GCN-NEXT:    v_mul_f64 v[2:3], -v[2:3], v[6:7]3630; GCN-NEXT:    s_setpc_b64 s[30:31]3631  %fma0 = call double @llvm.fma.f64(double %a, double %b, double 2.0)3632  %fneg.fma0 = fneg double %fma03633  %mul1 = fmul double %fneg.fma0, %c3634  %mul2 = fmul double %fneg.fma0, %d3635 3636  %insert.0 = insertvalue { double, double } poison, double %mul1, 03637  %insert.1 = insertvalue { double, double } %insert.0, double %mul2, 13638  ret { double, double } %insert.13639}3640 3641; %trunc.a has one fneg use, but it requires a code size increase and3642; %the fneg can instead be folded for free into the fma.3643define float @one_use_cost_to_fold_into_src_f32(float %a, float %b, float %c, float %d) #0 {3644; GCN-LABEL: one_use_cost_to_fold_into_src_f32:3645; GCN:       ; %bb.0:3646; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3647; GCN-NEXT:    v_trunc_f32_e32 v0, v03648; GCN-NEXT:    v_fma_f32 v0, -v0, v1, v23649; GCN-NEXT:    s_setpc_b64 s[30:31]3650  %trunc.a = call float @llvm.trunc.f32(float %a)3651  %trunc.fneg.a = fneg float %trunc.a3652  %fma0 = call float @llvm.fma.f32(float %trunc.fneg.a, float %b, float %c)3653  ret float %fma03654}3655 3656define { float, float } @multi_use_cost_to_fold_into_src(float %a, float %b, float %c, float %d) #0 {3657; GCN-LABEL: multi_use_cost_to_fold_into_src:3658; GCN:       ; %bb.0:3659; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3660; GCN-NEXT:    v_trunc_f32_e32 v4, v03661; GCN-NEXT:    v_fma_f32 v0, -v4, v1, v23662; GCN-NEXT:    v_mul_f32_e32 v1, v4, v33663; GCN-NEXT:    s_setpc_b64 s[30:31]3664  %trunc.a = call float @llvm.trunc.f32(float %a)3665  %trunc.fneg.a = fneg float %trunc.a3666  %fma0 = call float @llvm.fma.f32(float %trunc.fneg.a, float %b, float %c)3667  %mul1 = fmul float %trunc.a, %d3668  %insert.0 = insertvalue { float, float } poison, float %fma0, 03669  %insert.1 = insertvalue { float, float } %insert.0, float %mul1, 13670  ret { float, float } %insert.13671}3672 3673; The AMDGPU combine to pull fneg into the FMA operands was being3674; undone by the generic combine to pull the fneg out of the fma if3675; !isFNegFree. We were reporting false for v2f32 even though it will3676; be split into f32 where it will be free.3677define <2 x float> @fneg_fma_fneg_dagcombine_loop(<2 x float> %arg, <2 x float> %arg1, <2 x float> %arg2) #0 {3678; GCN-LABEL: fneg_fma_fneg_dagcombine_loop:3679; GCN:       ; %bb.0: ; %bb3680; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3681; GCN-NEXT:    s_brev_b32 s4, 13682; GCN-NEXT:    v_fma_f32 v3, v3, -v5, s43683; GCN-NEXT:    v_fma_f32 v2, v2, -v4, s43684; GCN-NEXT:    v_sub_f32_e32 v1, v3, v13685; GCN-NEXT:    v_sub_f32_e32 v0, v2, v03686; GCN-NEXT:    v_mul_f32_e32 v0, v0, v43687; GCN-NEXT:    v_mul_f32_e32 v1, v1, v53688; GCN-NEXT:    s_setpc_b64 s[30:31]3689bb:3690  %i3 = call fast <2 x float> @llvm.fma.v2f32(<2 x float> %arg1, <2 x float> %arg2, <2 x float> zeroinitializer)3691  %i4 = fadd fast <2 x float> %i3, %arg3692  %i5 = fneg <2 x float> %i43693  %i6 = fmul fast <2 x float> %i5, %arg23694  ret <2 x float> %i63695}3696 3697; This expects denormal flushing, so can't turn this fmul into fneg3698; TODO: Keeping this as fmul saves encoding size3699define float @nnan_fmul_neg1_to_fneg(float %x, float %y) #0 {3700; GCN-LABEL: nnan_fmul_neg1_to_fneg:3701; GCN:       ; %bb.0:3702; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3703; GCN-NEXT:    v_mul_f32_e64 v0, -v0, v13704; GCN-NEXT:    s_setpc_b64 s[30:31]3705  %mul = fmul float %x, -1.03706  %add = fmul nnan float %mul, %y3707  ret float %add3708}3709 3710; It's legal to turn this fmul into an fneg since denormals are3711; preserved and we know an snan can't happen from the flag.3712define float @denormal_fmul_neg1_to_fneg(float %x, float %y) {3713; GCN-LABEL: denormal_fmul_neg1_to_fneg:3714; GCN:       ; %bb.0:3715; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3716; GCN-NEXT:    v_mul_f32_e64 v0, -v0, v13717; GCN-NEXT:    s_setpc_b64 s[30:31]3718  %mul = fmul nnan float %x, -1.03719  %add = fmul float %mul, %y3720  ret float %add3721}3722 3723; know the source can't be an snan3724define float @denorm_snan_fmul_neg1_to_fneg(float %x, float %y) {3725; GCN-LABEL: denorm_snan_fmul_neg1_to_fneg:3726; GCN:       ; %bb.0:3727; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3728; GCN-NEXT:    v_mul_f32_e64 v0, v0, -v03729; GCN-NEXT:    v_mul_f32_e32 v0, v0, v13730; GCN-NEXT:    s_setpc_b64 s[30:31]3731  %canonical = fmul float %x, %x3732  %mul = fmul float %canonical, -1.03733  %add = fmul float %mul, %y3734  ret float %add3735}3736 3737define float @flush_snan_fmul_neg1_to_fneg(float %x, float %y) #0 {3738; GCN-LABEL: flush_snan_fmul_neg1_to_fneg:3739; GCN:       ; %bb.0:3740; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3741; GCN-NEXT:    v_mul_f32_e32 v0, 1.0, v03742; GCN-NEXT:    v_mul_f32_e64 v0, -v0, v13743; GCN-NEXT:    s_setpc_b64 s[30:31]3744  %quiet = call float @llvm.canonicalize.f32(float %x)3745  %mul = fmul float %quiet, -1.03746  %add = fmul float %mul, %y3747  ret float %add3748}3749 3750define float @fadd_select_fneg_fneg_f32(i32 %arg0, float %x, float %y, float %z) {3751; GCN-LABEL: fadd_select_fneg_fneg_f32:3752; GCN:       ; %bb.0:3753; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3754; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v03755; GCN-NEXT:    v_cndmask_b32_e32 v0, v2, v1, vcc3756; GCN-NEXT:    v_sub_f32_e32 v0, v3, v03757; GCN-NEXT:    s_setpc_b64 s[30:31]3758  %cmp = icmp eq i32 %arg0, 03759  %neg.x = fneg float %x3760  %neg.y  = fneg float %y3761  %select = select i1 %cmp, float %neg.x, float %neg.y3762  %add = fadd float %select, %z3763  ret float %add3764}3765 3766define double @fadd_select_fneg_fneg_f64(i32 %arg0, double %x, double %y, double %z) {3767; GCN-LABEL: fadd_select_fneg_fneg_f64:3768; GCN:       ; %bb.0:3769; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3770; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v03771; GCN-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc3772; GCN-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc3773; GCN-NEXT:    v_add_f64 v[0:1], v[5:6], -v[1:2]3774; GCN-NEXT:    s_setpc_b64 s[30:31]3775  %cmp = icmp eq i32 %arg0, 03776  %neg.x = fneg double %x3777  %neg.y  = fneg double %y3778  %select = select i1 %cmp, double %neg.x, double %neg.y3779  %add = fadd double %select, %z3780  ret double %add3781}3782 3783define half @fadd_select_fneg_fneg_f16(i32 %arg0, half %x, half %y, half %z) {3784; SI-LABEL: fadd_select_fneg_fneg_f16:3785; SI:       ; %bb.0:3786; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3787; SI-NEXT:    v_cvt_f16_f32_e32 v1, v13788; SI-NEXT:    v_cvt_f16_f32_e32 v2, v23789; SI-NEXT:    v_cvt_f16_f32_e32 v3, v33790; SI-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v03791; SI-NEXT:    v_cvt_f32_f16_e32 v1, v13792; SI-NEXT:    v_cvt_f32_f16_e32 v2, v23793; SI-NEXT:    v_cvt_f32_f16_e32 v3, v33794; SI-NEXT:    v_cndmask_b32_e32 v0, v2, v1, vcc3795; SI-NEXT:    v_sub_f32_e32 v0, v3, v03796; SI-NEXT:    s_setpc_b64 s[30:31]3797;3798; VI-LABEL: fadd_select_fneg_fneg_f16:3799; VI:       ; %bb.0:3800; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3801; VI-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v03802; VI-NEXT:    v_cndmask_b32_e32 v0, v2, v1, vcc3803; VI-NEXT:    v_sub_f16_e32 v0, v3, v03804; VI-NEXT:    s_setpc_b64 s[30:31]3805  %cmp = icmp eq i32 %arg0, 03806  %neg.x = fneg half %x3807  %neg.y = fneg half %y3808  %select = select i1 %cmp, half %neg.x, half %neg.y3809  %add = fadd half %select, %z3810  ret half %add3811}3812 3813; FIXME: Terrible code for SI3814define <2 x half> @fadd_select_fneg_fneg_v2f16(i32 %arg0, <2 x half> %x, <2 x half> %y, <2 x half> %z) {3815; SI-LABEL: fadd_select_fneg_fneg_v2f16:3816; SI:       ; %bb.0:3817; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3818; SI-NEXT:    v_cvt_f16_f32_e32 v2, v23819; SI-NEXT:    v_cvt_f16_f32_e32 v1, v13820; SI-NEXT:    v_cvt_f16_f32_e32 v3, v33821; SI-NEXT:    v_cvt_f16_f32_e32 v5, v53822; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v23823; SI-NEXT:    v_or_b32_e32 v1, v1, v23824; SI-NEXT:    v_cvt_f16_f32_e32 v2, v43825; SI-NEXT:    v_cvt_f16_f32_e32 v4, v63826; SI-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v03827; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v23828; SI-NEXT:    v_or_b32_e32 v2, v3, v23829; SI-NEXT:    v_cndmask_b32_e32 v0, v2, v1, vcc3830; SI-NEXT:    v_lshrrev_b32_e32 v1, 16, v03831; SI-NEXT:    v_cvt_f32_f16_e32 v3, v43832; SI-NEXT:    v_cvt_f32_f16_e32 v4, v53833; SI-NEXT:    v_cvt_f32_f16_e32 v0, v03834; SI-NEXT:    v_cvt_f32_f16_e32 v1, v13835; SI-NEXT:    v_sub_f32_e32 v0, v4, v03836; SI-NEXT:    v_sub_f32_e32 v1, v3, v13837; SI-NEXT:    s_setpc_b64 s[30:31]3838;3839; VI-LABEL: fadd_select_fneg_fneg_v2f16:3840; VI:       ; %bb.0:3841; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3842; VI-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v03843; VI-NEXT:    v_cndmask_b32_e32 v0, v2, v1, vcc3844; VI-NEXT:    v_sub_f16_sdwa v1, v3, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_13845; VI-NEXT:    v_sub_f16_e32 v0, v3, v03846; VI-NEXT:    v_or_b32_e32 v0, v0, v13847; VI-NEXT:    s_setpc_b64 s[30:31]3848  %cmp = icmp eq i32 %arg0, 03849  %neg.x = fneg <2 x half> %x3850  %neg.y = fneg <2 x half> %y3851  %select = select i1 %cmp, <2 x half> %neg.x, <2 x half> %neg.y3852  %add = fadd <2 x half> %select, %z3853  ret <2 x half> %add3854}3855 3856; --------------------------------------------------------------------------------3857; select tests3858; --------------------------------------------------------------------------------3859 3860define amdgpu_kernel void @s_fneg_select_infloop_regression_f32(float %arg, i1 %arg1, ptr addrspace(1) %ptr) {3861; SI-LABEL: s_fneg_select_infloop_regression_f32:3862; SI:       ; %bb.0:3863; SI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x93864; SI-NEXT:    s_waitcnt lgkmcnt(0)3865; SI-NEXT:    s_bitcmp1_b32 s1, 03866; SI-NEXT:    v_mov_b32_e32 v0, s03867; SI-NEXT:    s_cselect_b64 s[0:1], -1, 03868; SI-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s[0:1]3869; SI-NEXT:    v_cndmask_b32_e64 v2, -v0, 0, s[0:1]3870; SI-NEXT:    v_mov_b32_e32 v0, s23871; SI-NEXT:    v_mov_b32_e32 v1, s33872; SI-NEXT:    flat_store_dword v[0:1], v23873; SI-NEXT:    s_endpgm3874;3875; VI-LABEL: s_fneg_select_infloop_regression_f32:3876; VI:       ; %bb.0:3877; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x243878; VI-NEXT:    s_waitcnt lgkmcnt(0)3879; VI-NEXT:    s_bitcmp1_b32 s1, 03880; VI-NEXT:    v_mov_b32_e32 v0, s03881; VI-NEXT:    s_cselect_b64 s[0:1], -1, 03882; VI-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s[0:1]3883; VI-NEXT:    v_cndmask_b32_e64 v2, -v0, 0, s[0:1]3884; VI-NEXT:    v_mov_b32_e32 v0, s23885; VI-NEXT:    v_mov_b32_e32 v1, s33886; VI-NEXT:    flat_store_dword v[0:1], v23887; VI-NEXT:    s_endpgm3888  %i = select i1 %arg1, float 0.0, float %arg3889  %i2 = fneg float %i3890  %i3 = select i1 %arg1, float 0.0, float %i23891  store float %i3, ptr addrspace(1) %ptr, align 43892  ret void3893}3894 3895define float @v_fneg_select_infloop_regression_f32(float %arg, i1 %arg1) {3896; GCN-LABEL: v_fneg_select_infloop_regression_f32:3897; GCN:       ; %bb.0:3898; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3899; GCN-NEXT:    v_and_b32_e32 v1, 1, v13900; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v13901; GCN-NEXT:    v_cndmask_b32_e64 v0, v0, 0, vcc3902; GCN-NEXT:    v_cndmask_b32_e64 v0, -v0, 0, vcc3903; GCN-NEXT:    s_setpc_b64 s[30:31]3904  %i = select i1 %arg1, float 0.0, float %arg3905  %i2 = fneg float %i3906  %i3 = select i1 %arg1, float 0.0, float %i23907  ret float %i33908}3909 3910define float @v_fneg_select_infloop_regression_f32_commute0(float %arg, i1 %arg1) {3911; GCN-LABEL: v_fneg_select_infloop_regression_f32_commute0:3912; GCN:       ; %bb.0:3913; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3914; GCN-NEXT:    v_and_b32_e32 v1, 1, v13915; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v13916; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc3917; GCN-NEXT:    v_cndmask_b32_e64 v0, -v0, 0, vcc3918; GCN-NEXT:    s_setpc_b64 s[30:31]3919  %i = select i1 %arg1, float %arg, float 0.03920  %i2 = fneg float %i3921  %i3 = select i1 %arg1, float 0.0, float %i23922  ret float %i33923}3924 3925define float @v_fneg_select_infloop_regression_f32_commute1(float %arg, i1 %arg1) {3926; GCN-LABEL: v_fneg_select_infloop_regression_f32_commute1:3927; GCN:       ; %bb.0:3928; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3929; GCN-NEXT:    v_and_b32_e32 v1, 1, v13930; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v13931; GCN-NEXT:    v_cndmask_b32_e64 v0, v0, 0, vcc3932; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, -v0, vcc3933; GCN-NEXT:    s_setpc_b64 s[30:31]3934  %i = select i1 %arg1, float 0.0, float %arg3935  %i2 = fneg float %i3936  %i3 = select i1 %arg1, float %i2, float 0.03937  ret float %i33938}3939 3940define float @v_fneg_select_infloop_regression_f32_commute2(float %arg, i1 %arg1) {3941; GCN-LABEL: v_fneg_select_infloop_regression_f32_commute2:3942; GCN:       ; %bb.0:3943; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3944; GCN-NEXT:    v_and_b32_e32 v1, 1, v13945; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v13946; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc3947; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, -v0, vcc3948; GCN-NEXT:    s_setpc_b64 s[30:31]3949  %i = select i1 %arg1, float %arg, float 0.03950  %i2 = fneg float %i3951  %i3 = select i1 %arg1, float %i2, float 0.03952  ret float %i33953}3954 3955; Check with an inline constant that's equally cheap to negate3956define float @v_fneg_select_infloop_regression_inline_imm_f32(float %arg, i1 %arg1) {3957; GCN-LABEL: v_fneg_select_infloop_regression_inline_imm_f32:3958; GCN:       ; %bb.0:3959; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3960; GCN-NEXT:    v_and_b32_e32 v1, 1, v13961; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v13962; GCN-NEXT:    v_cndmask_b32_e64 v0, v0, 2.0, vcc3963; GCN-NEXT:    v_cndmask_b32_e64 v0, -v0, 2.0, vcc3964; GCN-NEXT:    s_setpc_b64 s[30:31]3965  %i = select i1 %arg1, float 2.0, float %arg3966  %i2 = fneg float %i3967  %i3 = select i1 %arg1, float 2.0, float %i23968  ret float %i33969}3970 3971define float @v_fneg_select_infloop_regression_inline_imm_f32_commute0(float %arg, i1 %arg1) {3972; GCN-LABEL: v_fneg_select_infloop_regression_inline_imm_f32_commute0:3973; GCN:       ; %bb.0:3974; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3975; GCN-NEXT:    v_and_b32_e32 v1, 1, v13976; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v13977; GCN-NEXT:    v_cndmask_b32_e32 v0, 2.0, v0, vcc3978; GCN-NEXT:    v_cndmask_b32_e64 v0, -v0, 2.0, vcc3979; GCN-NEXT:    s_setpc_b64 s[30:31]3980  %i = select i1 %arg1, float %arg, float 2.03981  %i2 = fneg float %i3982  %i3 = select i1 %arg1, float 2.0, float %i23983  ret float %i33984}3985 3986define float @v_fneg_select_infloop_regression_inline_imm_f32_commute1(float %arg, i1 %arg1) {3987; GCN-LABEL: v_fneg_select_infloop_regression_inline_imm_f32_commute1:3988; GCN:       ; %bb.0:3989; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3990; GCN-NEXT:    v_and_b32_e32 v1, 1, v13991; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v13992; GCN-NEXT:    v_cndmask_b32_e64 v0, v0, 2.0, vcc3993; GCN-NEXT:    v_cndmask_b32_e64 v0, 2.0, -v0, vcc3994; GCN-NEXT:    s_setpc_b64 s[30:31]3995  %i = select i1 %arg1, float 2.0, float %arg3996  %i2 = fneg float %i3997  %i3 = select i1 %arg1, float %i2, float 2.03998  ret float %i33999}4000 4001define float @v_fneg_select_infloop_regression_inline_imm_f32_commute2(float %arg, i1 %arg1) {4002; GCN-LABEL: v_fneg_select_infloop_regression_inline_imm_f32_commute2:4003; GCN:       ; %bb.0:4004; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4005; GCN-NEXT:    v_and_b32_e32 v1, 1, v14006; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v14007; GCN-NEXT:    v_cndmask_b32_e32 v0, 2.0, v0, vcc4008; GCN-NEXT:    v_cndmask_b32_e64 v0, 2.0, -v0, vcc4009; GCN-NEXT:    s_setpc_b64 s[30:31]4010  %i = select i1 %arg1, float %arg, float 2.04011  %i2 = fneg float %i4012  %i3 = select i1 %arg1, float %i2, float 2.04013  ret float %i34014}4015 4016; Check with an inline constant that's equally cheap to negate4017define float @v_fneg_select_infloop_regression_neg_inline_imm_f32(float %arg, i1 %arg1) {4018; GCN-LABEL: v_fneg_select_infloop_regression_neg_inline_imm_f32:4019; GCN:       ; %bb.0:4020; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4021; GCN-NEXT:    v_and_b32_e32 v1, 1, v14022; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v14023; GCN-NEXT:    v_cndmask_b32_e64 v0, v0, -2.0, vcc4024; GCN-NEXT:    v_cndmask_b32_e64 v0, -v0, -2.0, vcc4025; GCN-NEXT:    s_setpc_b64 s[30:31]4026  %i = select i1 %arg1, float -2.0, float %arg4027  %i2 = fneg float %i4028  %i3 = select i1 %arg1, float -2.0, float %i24029  ret float %i34030}4031 4032define float @v_fneg_select_infloop_regression_neg_inline_imm_f32_commute0(float %arg, i1 %arg1) {4033; GCN-LABEL: v_fneg_select_infloop_regression_neg_inline_imm_f32_commute0:4034; GCN:       ; %bb.0:4035; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4036; GCN-NEXT:    v_and_b32_e32 v1, 1, v14037; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v14038; GCN-NEXT:    v_cndmask_b32_e32 v0, -2.0, v0, vcc4039; GCN-NEXT:    v_cndmask_b32_e64 v0, -v0, -2.0, vcc4040; GCN-NEXT:    s_setpc_b64 s[30:31]4041  %i = select i1 %arg1, float %arg, float -2.04042  %i2 = fneg float %i4043  %i3 = select i1 %arg1, float -2.0, float %i24044  ret float %i34045}4046 4047define float @v_fneg_select_infloop_regression_neg_inline_imm_f32_commute1(float %arg, i1 %arg1) {4048; GCN-LABEL: v_fneg_select_infloop_regression_neg_inline_imm_f32_commute1:4049; GCN:       ; %bb.0:4050; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4051; GCN-NEXT:    v_and_b32_e32 v1, 1, v14052; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v14053; GCN-NEXT:    v_cndmask_b32_e64 v0, v0, -2.0, vcc4054; GCN-NEXT:    v_cndmask_b32_e64 v0, -2.0, -v0, vcc4055; GCN-NEXT:    s_setpc_b64 s[30:31]4056  %i = select i1 %arg1, float -2.0, float %arg4057  %i2 = fneg float %i4058  %i3 = select i1 %arg1, float %i2, float -2.04059  ret float %i34060}4061 4062define float @v_fneg_select_infloop_regression_neg_inline_imm_f32_commute2(float %arg, i1 %arg1) {4063; GCN-LABEL: v_fneg_select_infloop_regression_neg_inline_imm_f32_commute2:4064; GCN:       ; %bb.0:4065; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4066; GCN-NEXT:    v_and_b32_e32 v1, 1, v14067; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v14068; GCN-NEXT:    v_cndmask_b32_e32 v0, -2.0, v0, vcc4069; GCN-NEXT:    v_cndmask_b32_e64 v0, -2.0, -v0, vcc4070; GCN-NEXT:    s_setpc_b64 s[30:31]4071  %i = select i1 %arg1, float %arg, float -2.04072  %i2 = fneg float %i4073  %i3 = select i1 %arg1, float %i2, float -2.04074  ret float %i34075}4076 4077define amdgpu_kernel void @s_fneg_select_infloop_regression_f64(double %arg, i1 %arg1, ptr addrspace(1) %ptr) {4078; SI-LABEL: s_fneg_select_infloop_regression_f64:4079; SI:       ; %bb.0:4080; SI-NEXT:    s_load_dword s6, s[4:5], 0xb4081; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x94082; SI-NEXT:    s_load_dwordx2 s[2:3], s[4:5], 0xd4083; SI-NEXT:    v_bfrev_b32_e32 v0, 14084; SI-NEXT:    s_waitcnt lgkmcnt(0)4085; SI-NEXT:    s_bitcmp1_b32 s6, 04086; SI-NEXT:    s_cselect_b64 s[4:5], -1, 04087; SI-NEXT:    v_mov_b32_e32 v1, s14088; SI-NEXT:    s_and_b64 s[6:7], s[4:5], exec4089; SI-NEXT:    v_cndmask_b32_e64 v0, -v1, v0, s[4:5]4090; SI-NEXT:    s_cselect_b32 s0, 0, s04091; SI-NEXT:    v_mov_b32_e32 v2, s24092; SI-NEXT:    v_cndmask_b32_e64 v1, v0, 0, s[4:5]4093; SI-NEXT:    v_mov_b32_e32 v0, s04094; SI-NEXT:    v_mov_b32_e32 v3, s34095; SI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]4096; SI-NEXT:    s_endpgm4097;4098; VI-LABEL: s_fneg_select_infloop_regression_f64:4099; VI:       ; %bb.0:4100; VI-NEXT:    s_load_dword s6, s[4:5], 0x2c4101; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x244102; VI-NEXT:    s_load_dwordx2 s[2:3], s[4:5], 0x344103; VI-NEXT:    v_bfrev_b32_e32 v0, 14104; VI-NEXT:    s_waitcnt lgkmcnt(0)4105; VI-NEXT:    s_bitcmp1_b32 s6, 04106; VI-NEXT:    s_cselect_b64 s[4:5], -1, 04107; VI-NEXT:    v_mov_b32_e32 v1, s14108; VI-NEXT:    s_and_b64 s[6:7], s[4:5], exec4109; VI-NEXT:    v_cndmask_b32_e64 v0, -v1, v0, s[4:5]4110; VI-NEXT:    s_cselect_b32 s0, 0, s04111; VI-NEXT:    v_mov_b32_e32 v2, s24112; VI-NEXT:    v_cndmask_b32_e64 v1, v0, 0, s[4:5]4113; VI-NEXT:    v_mov_b32_e32 v0, s04114; VI-NEXT:    v_mov_b32_e32 v3, s34115; VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]4116; VI-NEXT:    s_endpgm4117  %i = select i1 %arg1, double 0.0, double %arg4118  %i2 = fneg double %i4119  %i3 = select i1 %arg1, double 0.0, double %i24120  store double %i3, ptr addrspace(1) %ptr, align 44121  ret void4122}4123 4124define double @v_fneg_select_infloop_regression_f64(double %arg, i1 %arg1) {4125; GCN-LABEL: v_fneg_select_infloop_regression_f64:4126; GCN:       ; %bb.0:4127; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4128; GCN-NEXT:    v_and_b32_e32 v2, 1, v24129; GCN-NEXT:    v_bfrev_b32_e32 v3, 14130; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v24131; GCN-NEXT:    v_cndmask_b32_e64 v1, -v1, v3, vcc4132; GCN-NEXT:    v_cndmask_b32_e64 v0, v0, 0, vcc4133; GCN-NEXT:    v_cndmask_b32_e64 v1, v1, 0, vcc4134; GCN-NEXT:    s_setpc_b64 s[30:31]4135  %i = select i1 %arg1, double 0.0, double %arg4136  %i2 = fneg double %i4137  %i3 = select i1 %arg1, double 0.0, double %i24138  ret double %i34139}4140 4141define amdgpu_kernel void @s_fneg_select_infloop_regression_f16(half %arg, i1 %arg1, ptr addrspace(1) %ptr) {4142; SI-LABEL: s_fneg_select_infloop_regression_f16:4143; SI:       ; %bb.0:4144; SI-NEXT:    s_load_dword s2, s[4:5], 0x94145; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0xb4146; SI-NEXT:    s_waitcnt lgkmcnt(0)4147; SI-NEXT:    v_cvt_f32_f16_e32 v0, s24148; SI-NEXT:    s_bitcmp1_b32 s2, 164149; SI-NEXT:    s_cselect_b64 s[2:3], -1, 04150; SI-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s[2:3]4151; SI-NEXT:    v_cndmask_b32_e64 v0, -v0, 0, s[2:3]4152; SI-NEXT:    v_cvt_f16_f32_e32 v2, v04153; SI-NEXT:    v_mov_b32_e32 v0, s04154; SI-NEXT:    v_mov_b32_e32 v1, s14155; SI-NEXT:    flat_store_short v[0:1], v24156; SI-NEXT:    s_endpgm4157;4158; VI-LABEL: s_fneg_select_infloop_regression_f16:4159; VI:       ; %bb.0:4160; VI-NEXT:    s_load_dword s2, s[4:5], 0x244161; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x2c4162; VI-NEXT:    s_waitcnt lgkmcnt(0)4163; VI-NEXT:    s_bitcmp1_b32 s2, 164164; VI-NEXT:    v_mov_b32_e32 v0, s24165; VI-NEXT:    s_cselect_b64 s[2:3], -1, 04166; VI-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s[2:3]4167; VI-NEXT:    v_xor_b32_e32 v0, 0x8000, v04168; VI-NEXT:    v_cndmask_b32_e64 v2, v0, 0, s[2:3]4169; VI-NEXT:    v_mov_b32_e32 v0, s04170; VI-NEXT:    v_mov_b32_e32 v1, s14171; VI-NEXT:    flat_store_short v[0:1], v24172; VI-NEXT:    s_endpgm4173  %i = select i1 %arg1, half 0.0, half %arg4174  %i2 = fneg half %i4175  %i3 = select i1 %arg1, half 0.0, half %i24176  store half %i3, ptr addrspace(1) %ptr, align 44177  ret void4178}4179 4180define half @v_fneg_select_infloop_regression_f16(half %arg, i1 %arg1) {4181; SI-LABEL: v_fneg_select_infloop_regression_f16:4182; SI:       ; %bb.0:4183; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4184; SI-NEXT:    v_cvt_f16_f32_e32 v0, v04185; SI-NEXT:    v_and_b32_e32 v1, 1, v14186; SI-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v14187; SI-NEXT:    v_cvt_f32_f16_e32 v0, v04188; SI-NEXT:    v_cndmask_b32_e64 v0, v0, 0, vcc4189; SI-NEXT:    v_cndmask_b32_e64 v0, -v0, 0, vcc4190; SI-NEXT:    s_setpc_b64 s[30:31]4191;4192; VI-LABEL: v_fneg_select_infloop_regression_f16:4193; VI:       ; %bb.0:4194; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4195; VI-NEXT:    v_and_b32_e32 v1, 1, v14196; VI-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v14197; VI-NEXT:    v_cndmask_b32_e64 v0, v0, 0, vcc4198; VI-NEXT:    v_xor_b32_e32 v0, 0x8000, v04199; VI-NEXT:    v_cndmask_b32_e64 v0, v0, 0, vcc4200; VI-NEXT:    s_setpc_b64 s[30:31]4201  %i = select i1 %arg1, half 0.0, half %arg4202  %i2 = fneg half %i4203  %i3 = select i1 %arg1, half 0.0, half %i24204  ret half %i34205}4206 4207define amdgpu_kernel void @s_fneg_select_infloop_regression_v2f16(<2 x half> %arg, i1 %arg1, ptr addrspace(1) %ptr) {4208; SI-LABEL: s_fneg_select_infloop_regression_v2f16:4209; SI:       ; %bb.0:4210; SI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x94211; SI-NEXT:    s_waitcnt lgkmcnt(0)4212; SI-NEXT:    s_and_b32 s1, 1, s14213; SI-NEXT:    s_cselect_b32 s0, 0, s04214; SI-NEXT:    s_xor_b32 s0, s0, 0x800080004215; SI-NEXT:    s_cmp_eq_u32 s1, 14216; SI-NEXT:    s_cselect_b32 s0, 0, s04217; SI-NEXT:    v_mov_b32_e32 v0, s24218; SI-NEXT:    v_mov_b32_e32 v1, s34219; SI-NEXT:    v_mov_b32_e32 v2, s04220; SI-NEXT:    flat_store_dword v[0:1], v24221; SI-NEXT:    s_endpgm4222;4223; VI-LABEL: s_fneg_select_infloop_regression_v2f16:4224; VI:       ; %bb.0:4225; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x244226; VI-NEXT:    s_waitcnt lgkmcnt(0)4227; VI-NEXT:    s_and_b32 s1, 1, s14228; VI-NEXT:    s_cselect_b32 s0, 0, s04229; VI-NEXT:    s_xor_b32 s0, s0, 0x800080004230; VI-NEXT:    s_cmp_eq_u32 s1, 14231; VI-NEXT:    s_cselect_b32 s0, 0, s04232; VI-NEXT:    v_mov_b32_e32 v0, s24233; VI-NEXT:    v_mov_b32_e32 v1, s34234; VI-NEXT:    v_mov_b32_e32 v2, s04235; VI-NEXT:    flat_store_dword v[0:1], v24236; VI-NEXT:    s_endpgm4237  %i = select i1 %arg1, <2 x half> zeroinitializer, <2 x half> %arg4238  %i2 = fneg <2 x half> %i4239  %i3 = select i1 %arg1, <2 x half> zeroinitializer, <2 x half> %i24240  store <2 x half> %i3, ptr addrspace(1) %ptr, align 44241  ret void4242}4243 4244define <2 x half> @v_fneg_select_infloop_regression_v2f16(<2 x half> %arg, i1 %arg1) {4245; SI-LABEL: v_fneg_select_infloop_regression_v2f16:4246; SI:       ; %bb.0:4247; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4248; SI-NEXT:    v_cvt_f16_f32_e32 v1, v14249; SI-NEXT:    v_cvt_f16_f32_e32 v0, v04250; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v14251; SI-NEXT:    v_or_b32_e32 v0, v0, v14252; SI-NEXT:    v_and_b32_e32 v1, 1, v24253; SI-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v14254; SI-NEXT:    v_cndmask_b32_e64 v0, v0, 0, vcc4255; SI-NEXT:    v_xor_b32_e32 v0, 0x80008000, v04256; SI-NEXT:    v_cndmask_b32_e64 v1, v0, 0, vcc4257; SI-NEXT:    v_cvt_f32_f16_e32 v0, v14258; SI-NEXT:    v_lshrrev_b32_e32 v1, 16, v14259; SI-NEXT:    v_cvt_f32_f16_e32 v1, v14260; SI-NEXT:    s_setpc_b64 s[30:31]4261;4262; VI-LABEL: v_fneg_select_infloop_regression_v2f16:4263; VI:       ; %bb.0:4264; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4265; VI-NEXT:    v_and_b32_e32 v1, 1, v14266; VI-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v14267; VI-NEXT:    v_cndmask_b32_e64 v0, v0, 0, vcc4268; VI-NEXT:    v_xor_b32_e32 v0, 0x80008000, v04269; VI-NEXT:    v_cndmask_b32_e64 v0, v0, 0, vcc4270; VI-NEXT:    s_setpc_b64 s[30:31]4271  %i = select i1 %arg1, <2 x half> zeroinitializer, <2 x half> %arg4272  %i2 = fneg <2 x half> %i4273  %i3 = select i1 %arg1, <2 x half> zeroinitializer, <2 x half> %i24274  ret <2 x half> %i34275}4276 4277define amdgpu_kernel void @s_fneg_select_infloop_regression_v2f32(<2 x float> %arg, i1 %arg1, ptr addrspace(1) %ptr) {4278; SI-LABEL: s_fneg_select_infloop_regression_v2f32:4279; SI:       ; %bb.0:4280; SI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x94281; SI-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0xd4282; SI-NEXT:    v_bfrev_b32_e32 v0, 14283; SI-NEXT:    s_waitcnt lgkmcnt(0)4284; SI-NEXT:    s_bitcmp1_b32 s2, 04285; SI-NEXT:    v_mov_b32_e32 v1, s04286; SI-NEXT:    s_cselect_b64 s[2:3], -1, 04287; SI-NEXT:    v_cndmask_b32_e64 v2, -v1, v0, s[2:3]4288; SI-NEXT:    v_mov_b32_e32 v1, s14289; SI-NEXT:    v_cndmask_b32_e64 v0, -v1, v0, s[2:3]4290; SI-NEXT:    v_cndmask_b32_e64 v1, v0, 0, s[2:3]4291; SI-NEXT:    v_cndmask_b32_e64 v0, v2, 0, s[2:3]4292; SI-NEXT:    v_mov_b32_e32 v2, s44293; SI-NEXT:    v_mov_b32_e32 v3, s54294; SI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]4295; SI-NEXT:    s_endpgm4296;4297; VI-LABEL: s_fneg_select_infloop_regression_v2f32:4298; VI:       ; %bb.0:4299; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x244300; VI-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x344301; VI-NEXT:    v_bfrev_b32_e32 v0, 14302; VI-NEXT:    s_waitcnt lgkmcnt(0)4303; VI-NEXT:    s_bitcmp1_b32 s2, 04304; VI-NEXT:    v_mov_b32_e32 v1, s04305; VI-NEXT:    s_cselect_b64 s[2:3], -1, 04306; VI-NEXT:    v_cndmask_b32_e64 v2, -v1, v0, s[2:3]4307; VI-NEXT:    v_mov_b32_e32 v1, s14308; VI-NEXT:    v_cndmask_b32_e64 v0, -v1, v0, s[2:3]4309; VI-NEXT:    v_cndmask_b32_e64 v1, v0, 0, s[2:3]4310; VI-NEXT:    v_cndmask_b32_e64 v0, v2, 0, s[2:3]4311; VI-NEXT:    v_mov_b32_e32 v2, s44312; VI-NEXT:    v_mov_b32_e32 v3, s54313; VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]4314; VI-NEXT:    s_endpgm4315  %i = select i1 %arg1, <2 x float> zeroinitializer, <2 x float> %arg4316  %i2 = fneg <2 x float> %i4317  %i3 = select i1 %arg1, <2 x float> zeroinitializer, <2 x float> %i24318  store <2 x float> %i3, ptr addrspace(1) %ptr, align 44319  ret void4320}4321 4322define <2 x float> @v_fneg_select_infloop_regression_v2f32(<2 x float> %arg, i1 %arg1) {4323; GCN-LABEL: v_fneg_select_infloop_regression_v2f32:4324; GCN:       ; %bb.0:4325; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4326; GCN-NEXT:    v_and_b32_e32 v2, 1, v24327; GCN-NEXT:    v_bfrev_b32_e32 v3, 14328; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v24329; GCN-NEXT:    v_cndmask_b32_e64 v1, -v1, v3, vcc4330; GCN-NEXT:    v_cndmask_b32_e64 v0, -v0, v3, vcc4331; GCN-NEXT:    v_cndmask_b32_e64 v0, v0, 0, vcc4332; GCN-NEXT:    v_cndmask_b32_e64 v1, v1, 0, vcc4333; GCN-NEXT:    s_setpc_b64 s[30:31]4334  %i = select i1 %arg1, <2 x float> zeroinitializer, <2 x float> %arg4335  %i2 = fneg <2 x float> %i4336  %i3 = select i1 %arg1, <2 x float> zeroinitializer, <2 x float> %i24337  ret <2 x float> %i34338}4339 4340define amdgpu_kernel void @s_fabs_select_infloop_regression_f32(float %arg, i1 %arg1, ptr addrspace(1) %ptr) {4341; SI-LABEL: s_fabs_select_infloop_regression_f32:4342; SI:       ; %bb.0:4343; SI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x94344; SI-NEXT:    s_waitcnt lgkmcnt(0)4345; SI-NEXT:    s_bitcmp1_b32 s1, 04346; SI-NEXT:    v_mov_b32_e32 v0, s04347; SI-NEXT:    s_cselect_b64 s[0:1], -1, 04348; SI-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s[0:1]4349; SI-NEXT:    v_cndmask_b32_e64 v2, |v0|, 0, s[0:1]4350; SI-NEXT:    v_mov_b32_e32 v0, s24351; SI-NEXT:    v_mov_b32_e32 v1, s34352; SI-NEXT:    flat_store_dword v[0:1], v24353; SI-NEXT:    s_endpgm4354;4355; VI-LABEL: s_fabs_select_infloop_regression_f32:4356; VI:       ; %bb.0:4357; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x244358; VI-NEXT:    s_waitcnt lgkmcnt(0)4359; VI-NEXT:    s_bitcmp1_b32 s1, 04360; VI-NEXT:    v_mov_b32_e32 v0, s04361; VI-NEXT:    s_cselect_b64 s[0:1], -1, 04362; VI-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s[0:1]4363; VI-NEXT:    v_cndmask_b32_e64 v2, |v0|, 0, s[0:1]4364; VI-NEXT:    v_mov_b32_e32 v0, s24365; VI-NEXT:    v_mov_b32_e32 v1, s34366; VI-NEXT:    flat_store_dword v[0:1], v24367; VI-NEXT:    s_endpgm4368  %i = select i1 %arg1, float 0.0, float %arg4369  %i2 = call float @llvm.fabs.f32(float %i)4370  %i3 = select i1 %arg1, float 0.0, float %i24371  store float %i3, ptr addrspace(1) %ptr, align 44372  ret void4373}4374 4375define float @v_fabs_select_infloop_regression_f32(float %arg, i1 %arg1) {4376; GCN-LABEL: v_fabs_select_infloop_regression_f32:4377; GCN:       ; %bb.0:4378; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4379; GCN-NEXT:    v_and_b32_e32 v1, 1, v14380; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v14381; GCN-NEXT:    v_cndmask_b32_e64 v0, v0, 0, vcc4382; GCN-NEXT:    v_cndmask_b32_e64 v0, |v0|, 0, vcc4383; GCN-NEXT:    s_setpc_b64 s[30:31]4384  %i = select i1 %arg1, float 0.0, float %arg4385  %i2 = call float @llvm.fabs.f32(float %i)4386  %i3 = select i1 %arg1, float 0.0, float %i24387  ret float %i34388}4389 4390define amdgpu_kernel void @s_fneg_fabs_select_infloop_regression(float %arg, i1 %arg1, ptr addrspace(1) %ptr) {4391; SI-LABEL: s_fneg_fabs_select_infloop_regression:4392; SI:       ; %bb.0:4393; SI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x94394; SI-NEXT:    s_waitcnt lgkmcnt(0)4395; SI-NEXT:    s_bitcmp1_b32 s1, 04396; SI-NEXT:    v_mov_b32_e32 v0, s04397; SI-NEXT:    s_cselect_b64 s[0:1], -1, 04398; SI-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s[0:1]4399; SI-NEXT:    v_cndmask_b32_e64 v2, -|v0|, 0, s[0:1]4400; SI-NEXT:    v_mov_b32_e32 v0, s24401; SI-NEXT:    v_mov_b32_e32 v1, s34402; SI-NEXT:    flat_store_dword v[0:1], v24403; SI-NEXT:    s_endpgm4404;4405; VI-LABEL: s_fneg_fabs_select_infloop_regression:4406; VI:       ; %bb.0:4407; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x244408; VI-NEXT:    s_waitcnt lgkmcnt(0)4409; VI-NEXT:    s_bitcmp1_b32 s1, 04410; VI-NEXT:    v_mov_b32_e32 v0, s04411; VI-NEXT:    s_cselect_b64 s[0:1], -1, 04412; VI-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s[0:1]4413; VI-NEXT:    v_cndmask_b32_e64 v2, -|v0|, 0, s[0:1]4414; VI-NEXT:    v_mov_b32_e32 v0, s24415; VI-NEXT:    v_mov_b32_e32 v1, s34416; VI-NEXT:    flat_store_dword v[0:1], v24417; VI-NEXT:    s_endpgm4418  %i = select i1 %arg1, float 0.0, float %arg4419  %i2 = call float @llvm.fabs.f32(float %i)4420  %neg.i2 = fneg float %i24421  %i3 = select i1 %arg1, float 0.0, float %neg.i24422  store float %i3, ptr addrspace(1) %ptr, align 44423  ret void4424}4425 4426define float @v_fneg_fabs_select_infloop_regression(float %arg, i1 %arg1) {4427; GCN-LABEL: v_fneg_fabs_select_infloop_regression:4428; GCN:       ; %bb.0:4429; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4430; GCN-NEXT:    v_and_b32_e32 v1, 1, v14431; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v14432; GCN-NEXT:    v_cndmask_b32_e64 v0, v0, 0, vcc4433; GCN-NEXT:    v_cndmask_b32_e64 v0, -|v0|, 0, vcc4434; GCN-NEXT:    s_setpc_b64 s[30:31]4435  %i = select i1 %arg1, float 0.0, float %arg4436  %i2 = call float @llvm.fabs.f32(float %i)4437  %neg.i2 = fneg float %i24438  %i3 = select i1 %arg1, float 0.0, float %neg.i24439  ret float %i34440}4441 4442define float @v_fmul_0_fsub_0_safe_infloop_regression(float %arg) {4443; GCN-SAFE-LABEL: v_fmul_0_fsub_0_safe_infloop_regression:4444; GCN-SAFE:       ; %bb.0: ; %bb4445; GCN-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4446; GCN-SAFE-NEXT:    v_mul_f32_e32 v0, 0, v04447; GCN-SAFE-NEXT:    v_sub_f32_e32 v0, 0, v04448; GCN-SAFE-NEXT:    s_setpc_b64 s[30:31]4449;4450; SI-NSZ-LABEL: v_fmul_0_fsub_0_safe_infloop_regression:4451; SI-NSZ:       ; %bb.0: ; %bb4452; SI-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4453; SI-NSZ-NEXT:    s_brev_b32 s4, 14454; SI-NSZ-NEXT:    v_fma_f32 v0, v0, s4, 04455; SI-NSZ-NEXT:    s_setpc_b64 s[30:31]4456; FIXME: utils/update_llc_test_checks.py will generate redundant VI4457; labels, remove them, they will cause test failure.4458bb:4459  %i = fmul float %arg, 0.04460  %i1 = fsub float 0.0, %i4461  ret float %i14462}4463 4464define float @v_fmul_0_fsub_0_nsz_infloop_regression(float %arg) {4465; GCN-LABEL: v_fmul_0_fsub_0_nsz_infloop_regression:4466; GCN:       ; %bb.0: ; %bb4467; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4468; GCN-NEXT:    v_mul_f32_e32 v0, 0x80000000, v04469; GCN-NEXT:    s_setpc_b64 s[30:31]4470bb:4471  %i = fmul float %arg, 0.04472  %i1 = fsub nsz float 0.0, %i4473  ret float %i14474}4475 4476declare i32 @llvm.amdgcn.workitem.id.x() #14477declare float @llvm.fma.f32(float, float, float) #14478declare <2 x float> @llvm.fma.v2f32(<2 x float>, <2 x float>, <2 x float>)4479declare float @llvm.fmuladd.f32(float, float, float) #14480declare <4 x float> @llvm.fmuladd.v4f32(<4 x float>, <4 x float>, <4 x float>) #14481declare float @llvm.fabs.f32(float) #14482declare float @llvm.sin.f32(float) #14483declare float @llvm.trunc.f32(float) #14484declare float @llvm.round.f32(float) #14485declare float @llvm.rint.f32(float) #14486declare float @llvm.nearbyint.f32(float) #14487declare float @llvm.roundeven.f32(float) #14488declare float @llvm.canonicalize.f32(float) #14489declare float @llvm.arithmetic.fence.f32(float) #14490declare float @llvm.minnum.f32(float, float) #14491declare float @llvm.maxnum.f32(float, float) #14492declare double @llvm.minnum.f64(double, double) #14493declare double @llvm.fma.f64(double, double, double) #14494 4495declare float @llvm.amdgcn.sin.f32(float) #14496declare float @llvm.amdgcn.rcp.f32(float) #14497declare float @llvm.amdgcn.rcp.legacy(float) #14498declare float @llvm.amdgcn.fmul.legacy(float, float) #14499declare float @llvm.amdgcn.interp.p1(float, i32, i32, i32) #04500declare float @llvm.amdgcn.interp.p2(float, float, i32, i32, i32) #04501 4502declare half @llvm.fma.f16(half, half, half) #14503declare <2 x half> @llvm.fma.v2f16(<2 x half>, <2 x half>, <2 x half>)4504declare half @llvm.fmuladd.f16(half, half, half) #14505declare <4 x half> @llvm.fmuladd.v4f16(<4 x half>, <4 x half>, <4 x half>) #14506declare half @llvm.sin.f16(half) #14507declare half @llvm.trunc.f16(half) #14508declare half @llvm.round.f16(half) #14509declare half @llvm.rint.f16(half) #14510declare half @llvm.nearbyint.f16(half) #14511declare half @llvm.canonicalize.f16(half) #14512declare half @llvm.minnum.f16(half, half) #14513declare half @llvm.maxnum.f16(half, half) #14514declare half @llvm.amdgcn.sin.f16(half) #14515declare half @llvm.amdgcn.rcp.f16(half) #14516 4517attributes #0 = { nounwind "denormal-fp-math-f32"="preserve-sign,preserve-sign" }4518attributes #1 = { nounwind readnone }4519attributes #2 = { nounwind }4520attributes #3 = { nounwind "no-signed-zeros-fp-math"="true" }4521attributes #4 = { nounwind "amdgpu-ieee"="false" "denormal-fp-math-f32"="preserve-sign,preserve-sign" }4522