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1; RUN: llc -mtriple=amdgcn -stop-after=amdgpu-isel < %s | FileCheck -check-prefixes=GCN,SI %s2; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -stop-after=amdgpu-isel < %s | FileCheck -check-prefixes=GCN,FP16 %s3; RUN: llc -mtriple=amdgcn -enable-new-pm -stop-after=amdgpu-isel < %s | FileCheck -check-prefixes=GCN,SI %s4; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -enable-new-pm -stop-after=amdgpu-isel < %s | FileCheck -check-prefixes=GCN,FP16 %s5 6 7define amdgpu_kernel void @divergent_fneg_f32(ptr addrspace(1) %out, ptr addrspace(1) %in) {8; GCN-LABEL: name: divergent_fneg_f329; GCN-LABEL: bb.0 (%ir-block.0)10; GCN: %[[REG:[0-9]+]]:sreg_32 = S_MOV_B32 -214748364811; GCN: V_XOR_B32_e64 killed %[[REG]]12 13 %tid = call i32 @llvm.amdgcn.workitem.id.x()14 %tid.ext = sext i32 %tid to i6415 %in.gep = getelementptr inbounds float, ptr addrspace(1) %in, i64 %tid.ext16 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext17 %val = load volatile float, ptr addrspace(1) %in.gep18 %fneg = fneg float %val19 store float %fneg, ptr addrspace(1) %out.gep20 ret void21}22 23define amdgpu_kernel void @uniform_fneg_f32(ptr addrspace(1) %out, ptr addrspace(1) %in, i64 %idx) {24; GCN-LABEL: name: uniform_fneg_f3225; GCN-LABEL: bb.0 (%ir-block.0)26; GCN: %[[REG:[0-9]+]]:sreg_32 = S_MOV_B32 -214748364827; GCN: S_XOR_B32 killed %{{[0-9]+}}, killed %[[REG]]28 29 %in.gep = getelementptr inbounds float, ptr addrspace(1) %in, i64 %idx30 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %idx31 %val = load volatile float, ptr addrspace(1) %in.gep32 %fneg = fneg float %val33 store float %fneg, ptr addrspace(1) %out.gep34 ret void35}36 37define amdgpu_kernel void @divergent_fabs_f32(ptr addrspace(1) %out, ptr addrspace(1) %in) {38; GCN-LABEL: name: divergent_fabs_f3239; GCN-LABEL: bb.0 (%ir-block.0)40; GCN: %[[REG:[0-9]+]]:sreg_32 = S_MOV_B32 214748364741; GCN: V_AND_B32_e64 killed %[[REG]]42 43 %tid = call i32 @llvm.amdgcn.workitem.id.x()44 %tid.ext = sext i32 %tid to i6445 %in.gep = getelementptr inbounds float, ptr addrspace(1) %in, i64 %tid.ext46 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext47 %val = load volatile float, ptr addrspace(1) %in.gep48 %fabs = call float @llvm.fabs.f32(float %val)49 store float %fabs, ptr addrspace(1) %out.gep50 ret void51}52 53define amdgpu_kernel void @uniform_fabs_f32(ptr addrspace(1) %out, ptr addrspace(1) %in, i64 %idx) {54; GCN-LABEL: name: uniform_fabs_f3255; GCN-LABEL: bb.0 (%ir-block.0)56; GCN: %[[REG:[0-9]+]]:sreg_32 = S_MOV_B32 214748364757; GCN: S_AND_B32 killed %{{[0-9]+}}, killed %[[REG]]58 59 %in.gep = getelementptr inbounds float, ptr addrspace(1) %in, i64 %idx60 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %idx61 %val = load volatile float, ptr addrspace(1) %in.gep62 %fabs = call float @llvm.fabs.f32(float %val)63 store float %fabs, ptr addrspace(1) %out.gep64 ret void65}66 67define amdgpu_kernel void @divergent_fneg_fabs_f32(ptr addrspace(1) %out, ptr addrspace(1) %in) {68; GCN-LABEL: name: divergent_fneg_fabs_f3269; GCN-LABEL: bb.0 (%ir-block.0)70; GCN: %[[REG:[0-9]+]]:sreg_32 = S_MOV_B32 -214748364871; GCN: V_OR_B32_e64 killed %[[REG]]72 73 %tid = call i32 @llvm.amdgcn.workitem.id.x()74 %tid.ext = sext i32 %tid to i6475 %in.gep = getelementptr inbounds float, ptr addrspace(1) %in, i64 %tid.ext76 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext77 %val = load volatile float, ptr addrspace(1) %in.gep78 %fabs = call float @llvm.fabs.f32(float %val)79 %fneg = fneg float %fabs80 store float %fneg, ptr addrspace(1) %out.gep81 ret void82}83 84define amdgpu_kernel void @uniform_fneg_fabs_f32(ptr addrspace(1) %out, ptr addrspace(1) %in, i64 %idx) {85; GCN-LABEL: name: uniform_fneg_fabs_f3286; GCN-LABEL: bb.0 (%ir-block.0)87; GCN: %[[REG:[0-9]+]]:sreg_32 = S_MOV_B32 -214748364888; GCN: S_OR_B32 killed %{{[0-9]+}}, killed %[[REG]]89 90 %in.gep = getelementptr inbounds float, ptr addrspace(1) %in, i64 %idx91 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %idx92 %val = load volatile float, ptr addrspace(1) %in.gep93 %fabs = call float @llvm.fabs.f32(float %val)94 %fneg = fneg float %fabs95 store float %fneg, ptr addrspace(1) %out.gep96 ret void97}98 99 100define amdgpu_kernel void @divergent_fabs_f16(ptr addrspace(1) %in, ptr addrspace(1) %out) {101; GCN-LABEL: name: divergent_fabs_f16102; GCN-LABEL: bb.0 (%ir-block.0)103; FP16: %[[REG:[0-9]+]]:sreg_32 = S_MOV_B32 32767104; FP16: V_AND_B32_e64 killed %[[REG]]105 106 %tid = call i32 @llvm.amdgcn.workitem.id.x()107 %tid.ext = sext i32 %tid to i64108 %in.gep = getelementptr inbounds half, ptr addrspace(1) %in, i64 %tid.ext109 %val = load volatile half, ptr addrspace(1) %in.gep110 %fabs = call half @llvm.fabs.f16(half %val)111 store half %fabs, ptr addrspace(1) %out112 ret void113}114 115define amdgpu_kernel void @uniform_fabs_f16(ptr addrspace(1) %in, ptr addrspace(1) %out, i64 %idx) {116; GCN-LABEL: name: uniform_fabs_f16117; GCN-LABEL: bb.0 (%ir-block.0)118; GCN: %[[REG:[0-9]+]]:sreg_32 = S_MOV_B32 32767119; GCN: S_AND_B32 killed %{{[0-9]+}}, killed %[[REG]]120 121 %in.gep = getelementptr inbounds half, ptr addrspace(1) %in, i64 %idx122 %val = load volatile half, ptr addrspace(1) %in.gep123 %fabs = call half @llvm.fabs.f16(half %val)124 store half %fabs, ptr addrspace(1) %out125 ret void126}127 128define amdgpu_kernel void @divergent_fneg_f16(ptr addrspace(1) %in, ptr addrspace(1) %out) {129; GCN-LABEL: name: divergent_fneg_f16130; GCN-LABEL: bb.0 (%ir-block.0)131; FP16: %[[REG:[0-9]+]]:sreg_32 = S_MOV_B32 32768132; FP16: V_XOR_B32_e64 killed %[[REG]]133 134 %tid = call i32 @llvm.amdgcn.workitem.id.x()135 %tid.ext = sext i32 %tid to i64136 %in.gep = getelementptr inbounds half, ptr addrspace(1) %in, i64 %tid.ext137 %val = load volatile half, ptr addrspace(1) %in.gep138 %fneg = fneg half %val139 store half %fneg, ptr addrspace(1) %out140 ret void141}142 143define amdgpu_kernel void @uniform_fneg_f16(ptr addrspace(1) %in, ptr addrspace(1) %out, i64 %idx) {144; GCN-LABEL: name: uniform_fneg_f16145; GCN-LABEL: bb.0 (%ir-block.0)146; GCN: %[[REG:[0-9]+]]:sreg_32 = S_MOV_B32 32768147; GCN: S_XOR_B32 killed %{{[0-9]+}}, killed %[[REG]]148 149 %in.gep = getelementptr inbounds half, ptr addrspace(1) %in, i64 %idx150 %val = load volatile half, ptr addrspace(1) %in.gep151 %fneg = fneg half %val152 store half %fneg, ptr addrspace(1) %out153 ret void154}155 156define amdgpu_kernel void @divergent_fneg_fabs_f16(ptr addrspace(1) %in, ptr addrspace(1) %out) {157; GCN-LABEL: name: divergent_fneg_fabs_f16158; GCN-LABEL: bb.0 (%ir-block.0)159; FP16: %[[REG:[0-9]+]]:sreg_32 = S_MOV_B32 32768160; FP16: V_OR_B32_e64 killed %[[REG]]161 162 %tid = call i32 @llvm.amdgcn.workitem.id.x()163 %tid.ext = sext i32 %tid to i64164 %in.gep = getelementptr inbounds half, ptr addrspace(1) %in, i64 %tid.ext165 %val = load volatile half, ptr addrspace(1) %in.gep166 %fabs = call half @llvm.fabs.f16(half %val)167 %fneg = fneg half %fabs168 store half %fneg, ptr addrspace(1) %out169 ret void170}171 172define amdgpu_kernel void @uniform_fneg_fabs_f16(ptr addrspace(1) %in, ptr addrspace(1) %out, i64 %idx) {173; GCN-LABEL: name: uniform_fneg_fabs_f16174; GCN-LABEL: bb.0 (%ir-block.0)175; GCN: %[[REG:[0-9]+]]:sreg_32 = S_MOV_B32 32768176; GCN: S_OR_B32 killed %{{[0-9]+}}, killed %[[REG]]177 178 %in.gep = getelementptr inbounds half, ptr addrspace(1) %in, i64 %idx179 %val = load volatile half, ptr addrspace(1) %in.gep180 %fabs = call half @llvm.fabs.f16(half %val)181 %fneg = fneg half %fabs182 store half %fneg, ptr addrspace(1) %out183 ret void184}185 186define amdgpu_kernel void @divergent_fneg_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %in) {187; GCN-LABEL: name: divergent_fneg_v2f16188; GCN-LABEL: bb.0 (%ir-block.0)189; FP16: %[[REG:[0-9]+]]:sreg_32 = S_MOV_B32 -2147450880190; FP16: V_XOR_B32_e64 killed %[[REG]]191 192 %tid = call i32 @llvm.amdgcn.workitem.id.x()193 %gep.in = getelementptr inbounds <2 x half>, ptr addrspace(1) %in, i32 %tid194 %gep.out = getelementptr inbounds <2 x half>, ptr addrspace(1) %in, i32 %tid195 %val = load <2 x half>, ptr addrspace(1) %gep.in, align 2196 %fneg = fneg <2 x half> %val197 store <2 x half> %fneg, ptr addrspace(1) %gep.out198 ret void199}200 201define amdgpu_kernel void @uniform_fneg_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %in, i32 %idx) {202; GCN-LABEL: name: uniform_fneg_v2f16203; GCN-LABEL: bb.0 (%ir-block.0)204; GCN: %[[REG:[0-9]+]]:sreg_32 = S_MOV_B32 -2147450880205; GCN: S_XOR_B32 killed %{{[0-9]+}}, killed %[[REG]]206 207 %gep.in = getelementptr inbounds <2 x half>, ptr addrspace(1) %in, i32 %idx208 %gep.out = getelementptr inbounds <2 x half>, ptr addrspace(1) %in, i32 %idx209 %val = load <2 x half>, ptr addrspace(1) %gep.in, align 2210 %fneg = fneg <2 x half> %val211 store <2 x half> %fneg, ptr addrspace(1) %gep.out212 ret void213}214 215define amdgpu_kernel void @divergent_fabs_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %in) {216; GCN-LABEL: name: divergent_fabs_v2f16217; GCN-LABEL: bb.0 (%ir-block.0)218; FP16: %[[REG:[0-9]+]]:sreg_32 = S_MOV_B32 2147450879219; FP16: V_AND_B32_e64 killed %[[REG]]220 221 %tid = call i32 @llvm.amdgcn.workitem.id.x()222 %gep.in = getelementptr inbounds <2 x half>, ptr addrspace(1) %in, i32 %tid223 %gep.out = getelementptr inbounds <2 x half>, ptr addrspace(1) %in, i32 %tid224 %val = load <2 x half>, ptr addrspace(1) %gep.in, align 2225 %fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %val)226 store <2 x half> %fabs, ptr addrspace(1) %gep.out227 ret void228}229 230define amdgpu_kernel void @uniform_fabs_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %in, i32 %idx) {231; GCN-LABEL: name: uniform_fabs_v2f16232; GCN-LABEL: bb.0 (%ir-block.0)233; GCN: %[[REG:[0-9]+]]:sreg_32 = S_MOV_B32 2147450879234; GCN: S_AND_B32 killed %{{[0-9]+}}, killed %[[REG]]235 236 %gep.in = getelementptr inbounds <2 x half>, ptr addrspace(1) %in, i32 %idx237 %gep.out = getelementptr inbounds <2 x half>, ptr addrspace(1) %in, i32 %idx238 %val = load <2 x half>, ptr addrspace(1) %gep.in, align 2239 %fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %val)240 store <2 x half> %fabs, ptr addrspace(1) %gep.out241 ret void242}243 244define amdgpu_kernel void @divergent_fneg_fabs_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %in) {245; GCN-LABEL: name: divergent_fneg_fabs_v2f16246; GCN-LABEL: bb.0 (%ir-block.0)247; FP16: %[[REG:[0-9]+]]:sreg_32 = S_MOV_B32 -2147450880248; FP16: V_OR_B32_e64 killed %[[REG]]249 250 %tid = call i32 @llvm.amdgcn.workitem.id.x()251 %gep.in = getelementptr inbounds <2 x half>, ptr addrspace(1) %in, i32 %tid252 %gep.out = getelementptr inbounds <2 x half>, ptr addrspace(1) %in, i32 %tid253 %val = load <2 x half>, ptr addrspace(1) %gep.in, align 2254 %fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %val)255 %fneg = fneg <2 x half> %fabs256 store <2 x half> %fneg, ptr addrspace(1) %gep.out257 ret void258}259 260define amdgpu_kernel void @uniform_fneg_fabs_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %in, i32 %idx) {261; GCN-LABEL: name: uniform_fneg_fabs_v2f16262; GCN-LABEL: bb.0 (%ir-block.0)263; GCN: %[[REG:[0-9]+]]:sreg_32 = S_MOV_B32 -2147450880264; GCN: S_OR_B32 killed %{{[0-9]+}}, killed %[[REG]]265 266 %gep.in = getelementptr inbounds <2 x half>, ptr addrspace(1) %in, i32 %idx267 %gep.out = getelementptr inbounds <2 x half>, ptr addrspace(1) %in, i32 %idx268 %val = load <2 x half>, ptr addrspace(1) %gep.in, align 2269 %fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %val)270 %fneg = fneg <2 x half> %fabs271 store <2 x half> %fneg, ptr addrspace(1) %gep.out272 ret void273}274 275define amdgpu_kernel void @divergent_fneg_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %in) {276; GCN-LABEL: name: divergent_fneg_v2f32277; GCN-LABEL: bb.0 (%ir-block.0)278; GCN: %[[REG:[0-9]+]]:sreg_32 = S_MOV_B32 -2147483648279; GCN: V_XOR_B32_e64 %[[REG]]280; GCN: V_XOR_B32_e64 %[[REG]]281 282 %tid = call i32 @llvm.amdgcn.workitem.id.x()283 %gep.in = getelementptr inbounds <2 x float>, ptr addrspace(1) %in, i32 %tid284 %gep.out = getelementptr inbounds <2 x float>, ptr addrspace(1) %in, i32 %tid285 %val = load <2 x float>, ptr addrspace(1) %gep.in, align 4286 %fneg = fneg <2 x float> %val287 store <2 x float> %fneg, ptr addrspace(1) %gep.out288 ret void289}290 291define amdgpu_kernel void @uniform_fneg_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %in, i32 %idx) {292; GCN-LABEL: name: uniform_fneg_v2f32293; GCN-LABEL: bb.0 (%ir-block.0)294; GCN: %[[REG:[0-9]+]]:sreg_32 = S_MOV_B32 -2147483648295; GCN: S_XOR_B32 killed %{{[0-9]+}}, %[[REG]]296; GCN: S_XOR_B32 killed %{{[0-9]+}}, %[[REG]]297 298 %gep.in = getelementptr inbounds <2 x float>, ptr addrspace(1) %in, i32 %idx299 %gep.out = getelementptr inbounds <2 x float>, ptr addrspace(1) %in, i32 %idx300 %val = load <2 x float>, ptr addrspace(1) %gep.in, align 4301 %fneg = fneg <2 x float> %val302 store <2 x float> %fneg, ptr addrspace(1) %gep.out303 ret void304}305 306define amdgpu_kernel void @divergent_fabs_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %in) {307; GCN-LABEL: name: divergent_fabs_v2f32308; GCN-LABEL: bb.0 (%ir-block.0)309; GCN: %[[REG:[0-9]+]]:sreg_32 = S_MOV_B32 2147483647310; GCN: V_AND_B32_e64 %[[REG]]311; GCN: V_AND_B32_e64 %[[REG]]312 313 %tid = call i32 @llvm.amdgcn.workitem.id.x()314 %gep.in = getelementptr inbounds <2 x float>, ptr addrspace(1) %in, i32 %tid315 %gep.out = getelementptr inbounds <2 x float>, ptr addrspace(1) %in, i32 %tid316 %val = load <2 x float>, ptr addrspace(1) %gep.in, align 4317 %fabs = call <2 x float> @llvm.fabs.v2f32(<2 x float> %val)318 store <2 x float> %fabs, ptr addrspace(1) %gep.out319 ret void320}321 322define amdgpu_kernel void @uniform_fabs_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %in, i32 %idx) {323; GCN-LABEL: name: uniform_fabs_v2f32324; GCN-LABEL: bb.0 (%ir-block.0)325; GCN: %[[REG:[0-9]+]]:sreg_32 = S_MOV_B32 2147483647326; GCN: S_AND_B32 killed %{{[0-9]+}}, %[[REG]]327; GCN: S_AND_B32 killed %{{[0-9]+}}, %[[REG]]328 329 %gep.in = getelementptr inbounds <2 x float>, ptr addrspace(1) %in, i32 %idx330 %gep.out = getelementptr inbounds <2 x float>, ptr addrspace(1) %in, i32 %idx331 %val = load <2 x float>, ptr addrspace(1) %gep.in, align 4332 %fabs = call <2 x float> @llvm.fabs.v2f32(<2 x float> %val)333 store <2 x float> %fabs, ptr addrspace(1) %gep.out334 ret void335}336 337define amdgpu_kernel void @divergent_fneg_fabs_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %in) {338; GCN-LABEL: name: divergent_fneg_fabs_v2f32339; GCN-LABEL: bb.0 (%ir-block.0)340; GCN: %[[REG:[0-9]+]]:sreg_32 = S_MOV_B32 -2147483648341; GCN: V_OR_B32_e64 %[[REG]]342; GCN: V_OR_B32_e64 %[[REG]]343 344 %tid = call i32 @llvm.amdgcn.workitem.id.x()345 %gep.in = getelementptr inbounds <2 x float>, ptr addrspace(1) %in, i32 %tid346 %gep.out = getelementptr inbounds <2 x float>, ptr addrspace(1) %in, i32 %tid347 %val = load <2 x float>, ptr addrspace(1) %gep.in, align 4348 %fabs = call <2 x float> @llvm.fabs.v2f32(<2 x float> %val)349 %fneg = fneg <2 x float> %fabs350 store <2 x float> %fneg, ptr addrspace(1) %gep.out351 ret void352}353 354define amdgpu_kernel void @uniform_fneg_fabs_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %in, i32 %idx) {355; GCN-LABEL: name: uniform_fneg_fabs_v2f32356; GCN-LABEL: bb.0 (%ir-block.0)357; GCN: %[[REG:[0-9]+]]:sreg_32 = S_MOV_B32 -2147483648358; GCN: S_OR_B32 killed %{{[0-9]+}}, %[[REG]]359; GCN: S_OR_B32 killed %{{[0-9]+}}, %[[REG]]360 361 %gep.in = getelementptr inbounds <2 x float>, ptr addrspace(1) %in, i32 %idx362 %gep.out = getelementptr inbounds <2 x float>, ptr addrspace(1) %in, i32 %idx363 %val = load <2 x float>, ptr addrspace(1) %gep.in, align 4364 %fabs = call <2 x float> @llvm.fabs.v2f32(<2 x float> %val)365 %fneg = fneg <2 x float> %fabs366 store <2 x float> %fneg, ptr addrspace(1) %gep.out367 ret void368}369 370define amdgpu_kernel void @divergent_fneg_f64(ptr addrspace(1) %out, ptr addrspace(1) %in) {371; GCN-LABEL: name: divergent_fneg_f64372; GCN-LABEL: bb.0 (%ir-block.0)373; SI: %[[VREG64:[0-9]+]]:vreg_64 = BUFFER_LOAD_DWORDX2_ADDR64374; FP16: %[[VREG64:[0-9]+]]:vreg_64 = GLOBAL_LOAD_DWORDX2_SADDR375; GCN: %[[HI32:[0-9]+]]:vgpr_32 = COPY %[[VREG64]].sub1376; GCN: %[[SREG_MASK:[0-9]+]]:sreg_32 = S_MOV_B32 -2147483648377; GCN: %[[XOR:[0-9]+]]:vgpr_32 = V_XOR_B32_e64 killed %[[SREG_MASK]], killed %[[HI32]]378; GCN: %[[LO32:[0-9]+]]:vgpr_32 = COPY %[[VREG64]].sub0379; GCN: REG_SEQUENCE killed %[[LO32]], %subreg.sub0, killed %[[XOR]], %subreg.sub1380 381 382 %tid = call i32 @llvm.amdgcn.workitem.id.x()383 %tid.ext = sext i32 %tid to i64384 %in.gep = getelementptr inbounds double, ptr addrspace(1) %in, i64 %tid.ext385 %out.gep = getelementptr inbounds double, ptr addrspace(1) %out, i64 %tid.ext386 %val = load volatile double, ptr addrspace(1) %in.gep387 %fneg = fneg double %val388 store double %fneg, ptr addrspace(1) %out.gep389 ret void390}391 392define amdgpu_kernel void @uniform_fneg_f64(ptr addrspace(1) %out, ptr addrspace(1) %in, i64 %idx) {393; GCN-LABEL: name: uniform_fneg_f64394; GCN-LABEL: bb.0 (%ir-block.0)395; SI: %[[VREG64:[0-9]+]]:vreg_64 = BUFFER_LOAD_DWORDX2_ADDR64396; FP16: %[[VREG64:[0-9]+]]:vreg_64 = GLOBAL_LOAD_DWORDX2_SADDR397; GCN: %[[LO32:[0-9]+]]:sreg_32 = COPY %[[VREG64]].sub0398; GCN: %[[HI32:[0-9]+]]:sreg_32 = COPY %[[VREG64]].sub1399; GCN: %[[SREG_MASK:[0-9]+]]:sreg_32 = S_MOV_B32 -2147483648400; GCN: %[[XOR:[0-9]+]]:sreg_32 = S_XOR_B32 killed %[[HI32]], killed %[[SREG_MASK]]401; GCN: %[[XOR_COPY:[0-9]+]]:sreg_32 = COPY killed %[[XOR]]402; GCN: REG_SEQUENCE killed %[[LO32]], %subreg.sub0, killed %[[XOR_COPY]], %subreg.sub1403 404 %in.gep = getelementptr inbounds double, ptr addrspace(1) %in, i64 %idx405 %out.gep = getelementptr inbounds double, ptr addrspace(1) %out, i64 %idx406 %val = load volatile double, ptr addrspace(1) %in.gep407 %fneg = fneg double %val408 store double %fneg, ptr addrspace(1) %out.gep409 ret void410}411 412define amdgpu_kernel void @divergent_fabs_f64(ptr addrspace(1) %out, ptr addrspace(1) %in) {413; GCN-LABEL: name: divergent_fabs_f64414; GCN-LABEL: bb.0 (%ir-block.0)415; SI: %[[VREG64:[0-9]+]]:vreg_64 = BUFFER_LOAD_DWORDX2_ADDR64416; FP16: %[[VREG64:[0-9]+]]:vreg_64 = GLOBAL_LOAD_DWORDX2_SADDR417; GCN: %[[HI32:[0-9]+]]:vgpr_32 = COPY %[[VREG64]].sub1418; GCN: %[[SREG_MASK:[0-9]+]]:sreg_32 = S_MOV_B32 2147483647419; GCN: %[[AND:[0-9]+]]:vgpr_32 = V_AND_B32_e64 killed %[[SREG_MASK]], killed %[[HI32]]420; GCN: %[[LO32:[0-9]+]]:vgpr_32 = COPY %[[VREG64]].sub0421; GCN: REG_SEQUENCE killed %[[LO32]], %subreg.sub0, killed %[[AND]], %subreg.sub1422 423 424 %tid = call i32 @llvm.amdgcn.workitem.id.x()425 %tid.ext = sext i32 %tid to i64426 %in.gep = getelementptr inbounds double, ptr addrspace(1) %in, i64 %tid.ext427 %out.gep = getelementptr inbounds double, ptr addrspace(1) %out, i64 %tid.ext428 %val = load volatile double, ptr addrspace(1) %in.gep429 %fabs = call double @llvm.fabs.f64(double %val)430 store double %fabs, ptr addrspace(1) %out.gep431 ret void432}433 434define amdgpu_kernel void @uniform_fabs_f64(ptr addrspace(1) %out, ptr addrspace(1) %in, i64 %idx) {435; GCN-LABEL: name: uniform_fabs_f64436; GCN-LABEL: bb.0 (%ir-block.0)437; SI: %[[VREG64:[0-9]+]]:vreg_64 = BUFFER_LOAD_DWORDX2_ADDR64438; FP16: %[[VREG64:[0-9]+]]:vreg_64 = GLOBAL_LOAD_DWORDX2_SADDR439; GCN: %[[LO32:[0-9]+]]:sreg_32 = COPY %[[VREG64]].sub0440; GCN: %[[HI32:[0-9]+]]:sreg_32 = COPY %[[VREG64]].sub1441; GCN: %[[SREG_MASK:[0-9]+]]:sreg_32 = S_MOV_B32 2147483647442; GCN: %[[AND:[0-9]+]]:sreg_32 = S_AND_B32 killed %[[HI32]], killed %[[SREG_MASK]]443; GCN: %[[AND_COPY:[0-9]+]]:sreg_32 = COPY killed %[[AND]]444; GCN: REG_SEQUENCE killed %[[LO32]], %subreg.sub0, killed %[[AND_COPY]], %subreg.sub1445 446 447 %in.gep = getelementptr inbounds double, ptr addrspace(1) %in, i64 %idx448 %out.gep = getelementptr inbounds double, ptr addrspace(1) %out, i64 %idx449 %val = load volatile double, ptr addrspace(1) %in.gep450 %fabs = call double @llvm.fabs.f64(double %val)451 store double %fabs, ptr addrspace(1) %out.gep452 ret void453}454 455define amdgpu_kernel void @divergent_fneg_fabs_f64(ptr addrspace(1) %out, ptr addrspace(1) %in) {456; GCN-LABEL: name: divergent_fneg_fabs_f64457; GCN-LABEL: bb.0 (%ir-block.0)458; SI: %[[VREG64:[0-9]+]]:vreg_64 = BUFFER_LOAD_DWORDX2_ADDR64459; FP16: %[[VREG64:[0-9]+]]:vreg_64 = GLOBAL_LOAD_DWORDX2_SADDR460; GCN: %[[HI32:[0-9]+]]:vgpr_32 = COPY %[[VREG64]].sub1461; GCN: %[[SREG_MASK:[0-9]+]]:sreg_32 = S_MOV_B32 -2147483648462; GCN: %[[OR:[0-9]+]]:vgpr_32 = V_OR_B32_e64 killed %[[SREG_MASK]], killed %[[HI32]]463; GCN: %[[LO32:[0-9]+]]:vgpr_32 = COPY %[[VREG64]].sub0464; GCN: REG_SEQUENCE killed %[[LO32]], %subreg.sub0, killed %[[OR]], %subreg.sub1465 466 467 %tid = call i32 @llvm.amdgcn.workitem.id.x()468 %tid.ext = sext i32 %tid to i64469 %in.gep = getelementptr inbounds double, ptr addrspace(1) %in, i64 %tid.ext470 %out.gep = getelementptr inbounds double, ptr addrspace(1) %out, i64 %tid.ext471 %val = load volatile double, ptr addrspace(1) %in.gep472 %fabs = call double @llvm.fabs.f64(double %val)473 %fneg = fneg double %fabs474 store double %fneg, ptr addrspace(1) %out.gep475 ret void476}477 478define amdgpu_kernel void @uniform_fneg_fabs_f64(ptr addrspace(1) %out, ptr addrspace(1) %in, i64 %idx) {479; GCN-LABEL: name: uniform_fneg_fabs_f64480; GCN-LABEL: bb.0 (%ir-block.0)481; SI: %[[VREG64:[0-9]+]]:vreg_64 = BUFFER_LOAD_DWORDX2_ADDR64482; FP16: %[[VREG64:[0-9]+]]:vreg_64 = GLOBAL_LOAD_DWORDX2_SADDR483; GCN: %[[LO32:[0-9]+]]:sreg_32 = COPY %[[VREG64]].sub0484; GCN: %[[HI32:[0-9]+]]:sreg_32 = COPY %[[VREG64]].sub1485; GCN: %[[SREG_MASK:[0-9]+]]:sreg_32 = S_MOV_B32 -2147483648486; GCN: %[[OR:[0-9]+]]:sreg_32 = S_OR_B32 killed %[[HI32]], killed %[[SREG_MASK]]487; GCN: %[[OR_COPY:[0-9]+]]:sreg_32 = COPY killed %[[OR]]488; GCN: REG_SEQUENCE killed %[[LO32]], %subreg.sub0, killed %[[OR_COPY]], %subreg.sub1489 490 491 %in.gep = getelementptr inbounds double, ptr addrspace(1) %in, i64 %idx492 %out.gep = getelementptr inbounds double, ptr addrspace(1) %out, i64 %idx493 %val = load volatile double, ptr addrspace(1) %in.gep494 %fabs = call double @llvm.fabs.f64(double %val)495 %fneg = fneg double %fabs496 store double %fneg, ptr addrspace(1) %out.gep497 ret void498}499 500declare float @llvm.fabs.f32(float)501declare half @llvm.fabs.f16(half)502declare double @llvm.fabs.f64(double)503declare <2 x half> @llvm.fabs.v2f16(<2 x half>)504declare <2 x float> @llvm.fabs.v2f32(<2 x float>)505 506declare i32 @llvm.amdgcn.workitem.id.x()507