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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -march=amdgcn < %s | FileCheck -check-prefixes=SI,GCN %s3; RUN: llc -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=VI,GCN %s4 5define amdgpu_kernel void @fneg_fabs_fadd_f64(ptr addrspace(1) %out, double %x, double %y) {6; SI-LABEL: fneg_fabs_fadd_f64:7; SI: ; %bb.0:8; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x99; SI-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0xd10; SI-NEXT: s_mov_b32 s7, 0xf00011; SI-NEXT: s_mov_b32 s6, -112; SI-NEXT: s_waitcnt lgkmcnt(0)13; SI-NEXT: s_mov_b32 s4, s014; SI-NEXT: s_mov_b32 s5, s115; SI-NEXT: v_mov_b32_e32 v0, s216; SI-NEXT: v_mov_b32_e32 v1, s317; SI-NEXT: v_add_f64 v[0:1], s[8:9], -|v[0:1]|18; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 019; SI-NEXT: s_endpgm20;21; VI-LABEL: fneg_fabs_fadd_f64:22; VI: ; %bb.0:23; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2424; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x3425; VI-NEXT: s_waitcnt lgkmcnt(0)26; VI-NEXT: v_mov_b32_e32 v0, s227; VI-NEXT: v_mov_b32_e32 v1, s328; VI-NEXT: v_add_f64 v[0:1], s[4:5], -|v[0:1]|29; VI-NEXT: v_mov_b32_e32 v2, s030; VI-NEXT: v_mov_b32_e32 v3, s131; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]32; VI-NEXT: s_endpgm33 %fabs = call double @llvm.fabs.f64(double %x)34 %fsub = fsub double -0.000000e+00, %fabs35 %fadd = fadd double %y, %fsub36 store double %fadd, ptr addrspace(1) %out, align 837 ret void38}39 40define amdgpu_kernel void @v_fneg_fabs_fadd_f64(ptr addrspace(1) %out, ptr addrspace(1) %xptr, ptr addrspace(1) %yptr) {41; SI-LABEL: v_fneg_fabs_fadd_f64:42; SI: ; %bb.0:43; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x944; SI-NEXT: s_waitcnt lgkmcnt(0)45; SI-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x046; SI-NEXT: s_mov_b32 s3, 0xf00047; SI-NEXT: s_mov_b32 s2, -148; SI-NEXT: s_waitcnt lgkmcnt(0)49; SI-NEXT: v_add_f64 v[0:1], s[4:5], -|s[4:5]|50; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 051; SI-NEXT: s_endpgm52;53; VI-LABEL: v_fneg_fabs_fadd_f64:54; VI: ; %bb.0:55; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2456; VI-NEXT: s_waitcnt lgkmcnt(0)57; VI-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x058; VI-NEXT: v_mov_b32_e32 v2, s059; VI-NEXT: v_mov_b32_e32 v3, s160; VI-NEXT: s_waitcnt lgkmcnt(0)61; VI-NEXT: v_add_f64 v[0:1], s[2:3], -|s[2:3]|62; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]63; VI-NEXT: s_endpgm64 %x = load double, ptr addrspace(1) %xptr, align 865 %y = load double, ptr addrspace(1) %xptr, align 866 %fabs = call double @llvm.fabs.f64(double %x)67 %fsub = fsub double -0.000000e+00, %fabs68 %fadd = fadd double %y, %fsub69 store double %fadd, ptr addrspace(1) %out, align 870 ret void71}72 73define amdgpu_kernel void @fneg_fabs_fmul_f64(ptr addrspace(1) %out, double %x, double %y) {74; SI-LABEL: fneg_fabs_fmul_f64:75; SI: ; %bb.0:76; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x977; SI-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0xd78; SI-NEXT: s_mov_b32 s7, 0xf00079; SI-NEXT: s_mov_b32 s6, -180; SI-NEXT: s_waitcnt lgkmcnt(0)81; SI-NEXT: s_mov_b32 s4, s082; SI-NEXT: s_mov_b32 s5, s183; SI-NEXT: v_mov_b32_e32 v0, s284; SI-NEXT: v_mov_b32_e32 v1, s385; SI-NEXT: v_mul_f64 v[0:1], s[8:9], -|v[0:1]|86; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 087; SI-NEXT: s_endpgm88;89; VI-LABEL: fneg_fabs_fmul_f64:90; VI: ; %bb.0:91; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2492; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x3493; VI-NEXT: s_waitcnt lgkmcnt(0)94; VI-NEXT: v_mov_b32_e32 v0, s295; VI-NEXT: v_mov_b32_e32 v1, s396; VI-NEXT: v_mul_f64 v[0:1], s[4:5], -|v[0:1]|97; VI-NEXT: v_mov_b32_e32 v2, s098; VI-NEXT: v_mov_b32_e32 v3, s199; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]100; VI-NEXT: s_endpgm101 %fabs = call double @llvm.fabs.f64(double %x)102 %fsub = fsub double -0.000000e+00, %fabs103 %fmul = fmul double %y, %fsub104 store double %fmul, ptr addrspace(1) %out, align 8105 ret void106}107 108define amdgpu_kernel void @fneg_fabs_free_f64(ptr addrspace(1) %out, i64 %in) {109; SI-LABEL: fneg_fabs_free_f64:110; SI: ; %bb.0:111; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9112; SI-NEXT: s_mov_b32 s7, 0xf000113; SI-NEXT: s_waitcnt lgkmcnt(0)114; SI-NEXT: s_bitset1_b32 s3, 31115; SI-NEXT: s_mov_b32 s6, -1116; SI-NEXT: s_mov_b32 s4, s0117; SI-NEXT: s_mov_b32 s5, s1118; SI-NEXT: v_mov_b32_e32 v0, s2119; SI-NEXT: v_mov_b32_e32 v1, s3120; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0121; SI-NEXT: s_endpgm122;123; VI-LABEL: fneg_fabs_free_f64:124; VI: ; %bb.0:125; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24126; VI-NEXT: s_waitcnt lgkmcnt(0)127; VI-NEXT: v_mov_b32_e32 v0, s0128; VI-NEXT: s_or_b32 s0, s3, 0x80000000129; VI-NEXT: v_mov_b32_e32 v1, s1130; VI-NEXT: v_mov_b32_e32 v2, s2131; VI-NEXT: v_mov_b32_e32 v3, s0132; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]133; VI-NEXT: s_endpgm134 %bc = bitcast i64 %in to double135 %fabs = call double @llvm.fabs.f64(double %bc)136 %fsub = fsub double -0.000000e+00, %fabs137 store double %fsub, ptr addrspace(1) %out138 ret void139}140 141define amdgpu_kernel void @fneg_fabs_fn_free_f64(ptr addrspace(1) %out, i64 %in) {142; SI-LABEL: fneg_fabs_fn_free_f64:143; SI: ; %bb.0:144; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9145; SI-NEXT: s_mov_b32 s7, 0xf000146; SI-NEXT: s_waitcnt lgkmcnt(0)147; SI-NEXT: s_bitset1_b32 s3, 31148; SI-NEXT: s_mov_b32 s6, -1149; SI-NEXT: s_mov_b32 s4, s0150; SI-NEXT: s_mov_b32 s5, s1151; SI-NEXT: v_mov_b32_e32 v0, s2152; SI-NEXT: v_mov_b32_e32 v1, s3153; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0154; SI-NEXT: s_endpgm155;156; VI-LABEL: fneg_fabs_fn_free_f64:157; VI: ; %bb.0:158; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24159; VI-NEXT: s_waitcnt lgkmcnt(0)160; VI-NEXT: v_mov_b32_e32 v0, s0161; VI-NEXT: s_or_b32 s0, s3, 0x80000000162; VI-NEXT: v_mov_b32_e32 v1, s1163; VI-NEXT: v_mov_b32_e32 v2, s2164; VI-NEXT: v_mov_b32_e32 v3, s0165; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]166; VI-NEXT: s_endpgm167 %bc = bitcast i64 %in to double168 %fabs = call double @fabs(double %bc)169 %fsub = fsub double -0.000000e+00, %fabs170 store double %fsub, ptr addrspace(1) %out171 ret void172}173 174define amdgpu_kernel void @fneg_fabs_f64(ptr addrspace(1) %out, [8 x i32], double %in) {175; SI-LABEL: fneg_fabs_f64:176; SI: ; %bb.0:177; SI-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x13178; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9179; SI-NEXT: s_mov_b32 s3, 0xf000180; SI-NEXT: s_waitcnt lgkmcnt(0)181; SI-NEXT: s_or_b32 s4, s7, 0x80000000182; SI-NEXT: s_mov_b32 s2, -1183; SI-NEXT: v_mov_b32_e32 v0, s6184; SI-NEXT: v_mov_b32_e32 v1, s4185; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0186; SI-NEXT: s_endpgm187;188; VI-LABEL: fneg_fabs_f64:189; VI: ; %bb.0:190; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x4c191; VI-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24192; VI-NEXT: s_waitcnt lgkmcnt(0)193; VI-NEXT: s_bitset1_b32 s1, 31194; VI-NEXT: v_mov_b32_e32 v2, s2195; VI-NEXT: v_mov_b32_e32 v0, s0196; VI-NEXT: v_mov_b32_e32 v1, s1197; VI-NEXT: v_mov_b32_e32 v3, s3198; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]199; VI-NEXT: s_endpgm200 %fabs = call double @llvm.fabs.f64(double %in)201 %fsub = fsub double -0.000000e+00, %fabs202 store double %fsub, ptr addrspace(1) %out, align 8203 ret void204}205 206define amdgpu_kernel void @fneg_fabs_v2f64(ptr addrspace(1) %out, <2 x double> %in) {207; SI-LABEL: fneg_fabs_v2f64:208; SI: ; %bb.0:209; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xd210; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9211; SI-NEXT: s_mov_b32 s7, 0xf000212; SI-NEXT: s_waitcnt lgkmcnt(0)213; SI-NEXT: s_bitset1_b32 s3, 31214; SI-NEXT: s_bitset1_b32 s1, 31215; SI-NEXT: s_mov_b32 s6, -1216; SI-NEXT: v_mov_b32_e32 v0, s0217; SI-NEXT: v_mov_b32_e32 v2, s2218; SI-NEXT: v_mov_b32_e32 v1, s1219; SI-NEXT: v_mov_b32_e32 v3, s3220; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0221; SI-NEXT: s_endpgm222;223; VI-LABEL: fneg_fabs_v2f64:224; VI: ; %bb.0:225; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34226; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24227; VI-NEXT: s_waitcnt lgkmcnt(0)228; VI-NEXT: s_bitset1_b32 s3, 31229; VI-NEXT: s_bitset1_b32 s1, 31230; VI-NEXT: v_mov_b32_e32 v4, s4231; VI-NEXT: v_mov_b32_e32 v0, s0232; VI-NEXT: v_mov_b32_e32 v2, s2233; VI-NEXT: v_mov_b32_e32 v1, s1234; VI-NEXT: v_mov_b32_e32 v3, s3235; VI-NEXT: v_mov_b32_e32 v5, s5236; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]237; VI-NEXT: s_endpgm238 %fabs = call <2 x double> @llvm.fabs.v2f64(<2 x double> %in)239 %fsub = fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %fabs240 store <2 x double> %fsub, ptr addrspace(1) %out241 ret void242}243 244define amdgpu_kernel void @fneg_fabs_v4f64(ptr addrspace(1) %out, <4 x double> %in) {245; SI-LABEL: fneg_fabs_v4f64:246; SI: ; %bb.0:247; SI-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x11248; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9249; SI-NEXT: s_mov_b32 s3, 0xf000250; SI-NEXT: s_mov_b32 s2, -1251; SI-NEXT: s_waitcnt lgkmcnt(0)252; SI-NEXT: s_or_b32 s4, s11, 0x80000000253; SI-NEXT: s_or_b32 s5, s15, 0x80000000254; SI-NEXT: s_or_b32 s6, s13, 0x80000000255; SI-NEXT: s_or_b32 s7, s9, 0x80000000256; SI-NEXT: v_mov_b32_e32 v0, s12257; SI-NEXT: v_mov_b32_e32 v2, s14258; SI-NEXT: v_mov_b32_e32 v4, s8259; SI-NEXT: v_mov_b32_e32 v6, s10260; SI-NEXT: v_mov_b32_e32 v1, s6261; SI-NEXT: v_mov_b32_e32 v3, s5262; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:16263; SI-NEXT: v_mov_b32_e32 v5, s7264; SI-NEXT: v_mov_b32_e32 v7, s4265; SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0266; SI-NEXT: s_endpgm267;268; VI-LABEL: fneg_fabs_v4f64:269; VI: ; %bb.0:270; VI-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x44271; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24272; VI-NEXT: s_waitcnt lgkmcnt(0)273; VI-NEXT: s_or_b32 s4, s11, 0x80000000274; VI-NEXT: s_or_b32 s5, s9, 0x80000000275; VI-NEXT: s_or_b32 s2, s15, 0x80000000276; VI-NEXT: s_or_b32 s3, s13, 0x80000000277; VI-NEXT: v_mov_b32_e32 v3, s2278; VI-NEXT: s_add_u32 s2, s0, 16279; VI-NEXT: v_mov_b32_e32 v1, s3280; VI-NEXT: s_addc_u32 s3, s1, 0281; VI-NEXT: v_mov_b32_e32 v5, s3282; VI-NEXT: v_mov_b32_e32 v0, s12283; VI-NEXT: v_mov_b32_e32 v2, s14284; VI-NEXT: v_mov_b32_e32 v4, s2285; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]286; VI-NEXT: v_mov_b32_e32 v5, s1287; VI-NEXT: v_mov_b32_e32 v0, s8288; VI-NEXT: v_mov_b32_e32 v1, s5289; VI-NEXT: v_mov_b32_e32 v2, s10290; VI-NEXT: v_mov_b32_e32 v3, s4291; VI-NEXT: v_mov_b32_e32 v4, s0292; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]293; VI-NEXT: s_endpgm294 %fabs = call <4 x double> @llvm.fabs.v4f64(<4 x double> %in)295 %fsub = fsub <4 x double> <double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00>, %fabs296 store <4 x double> %fsub, ptr addrspace(1) %out297 ret void298}299 300declare double @fabs(double) readnone301declare double @llvm.fabs.f64(double) readnone302declare <2 x double> @llvm.fabs.v2f64(<2 x double>) readnone303declare <4 x double> @llvm.fabs.v4f64(<4 x double>) readnone304;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:305; GCN: {{.*}}306