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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn < %s | FileCheck --check-prefixes=SI,FUNC %s3; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga < %s | FileCheck --check-prefixes=VI,FUNC %s4 5define amdgpu_kernel void @fneg_fabsf_fadd_f32(ptr addrspace(1) %out, float %x, float %y) {6; SI-LABEL: fneg_fabsf_fadd_f32:7; SI: ; %bb.0:8; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x99; SI-NEXT: s_mov_b32 s7, 0xf00010; SI-NEXT: s_mov_b32 s6, -111; SI-NEXT: s_waitcnt lgkmcnt(0)12; SI-NEXT: s_mov_b32 s4, s013; SI-NEXT: s_mov_b32 s5, s114; SI-NEXT: v_mov_b32_e32 v0, s215; SI-NEXT: v_sub_f32_e64 v0, s3, |v0|16; SI-NEXT: buffer_store_dword v0, off, s[4:7], 017; SI-NEXT: s_endpgm18;19; VI-LABEL: fneg_fabsf_fadd_f32:20; VI: ; %bb.0:21; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2422; VI-NEXT: s_waitcnt lgkmcnt(0)23; VI-NEXT: v_mov_b32_e32 v0, s224; VI-NEXT: v_sub_f32_e64 v2, s3, |v0|25; VI-NEXT: v_mov_b32_e32 v0, s026; VI-NEXT: v_mov_b32_e32 v1, s127; VI-NEXT: flat_store_dword v[0:1], v228; VI-NEXT: s_endpgm29 %fabs = call float @llvm.fabs.f32(float %x)30 %fsub = fsub float -0.000000e+00, %fabs31 %fadd = fadd float %y, %fsub32 store float %fadd, ptr addrspace(1) %out, align 433 ret void34}35 36define amdgpu_kernel void @fneg_fabsf_fmul_f32(ptr addrspace(1) %out, float %x, float %y) {37; SI-LABEL: fneg_fabsf_fmul_f32:38; SI: ; %bb.0:39; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x940; SI-NEXT: s_mov_b32 s7, 0xf00041; SI-NEXT: s_mov_b32 s6, -142; SI-NEXT: s_waitcnt lgkmcnt(0)43; SI-NEXT: s_mov_b32 s4, s044; SI-NEXT: s_mov_b32 s5, s145; SI-NEXT: v_mov_b32_e32 v0, s246; SI-NEXT: v_mul_f32_e64 v0, s3, -|v0|47; SI-NEXT: buffer_store_dword v0, off, s[4:7], 048; SI-NEXT: s_endpgm49;50; VI-LABEL: fneg_fabsf_fmul_f32:51; VI: ; %bb.0:52; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2453; VI-NEXT: s_waitcnt lgkmcnt(0)54; VI-NEXT: v_mov_b32_e32 v0, s255; VI-NEXT: v_mul_f32_e64 v2, s3, -|v0|56; VI-NEXT: v_mov_b32_e32 v0, s057; VI-NEXT: v_mov_b32_e32 v1, s158; VI-NEXT: flat_store_dword v[0:1], v259; VI-NEXT: s_endpgm60 %fabs = call float @llvm.fabs.f32(float %x)61 %fsub = fsub float -0.000000e+00, %fabs62 %fmul = fmul float %y, %fsub63 store float %fmul, ptr addrspace(1) %out, align 464 ret void65}66 67define amdgpu_kernel void @fneg_fabsf_free_f32(ptr addrspace(1) %out, i32 %in) {68; SI-LABEL: fneg_fabsf_free_f32:69; SI: ; %bb.0:70; SI-NEXT: s_load_dword s2, s[4:5], 0xb71; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x972; SI-NEXT: s_mov_b32 s3, 0xf00073; SI-NEXT: s_waitcnt lgkmcnt(0)74; SI-NEXT: s_or_b32 s4, s2, 0x8000000075; SI-NEXT: s_mov_b32 s2, -176; SI-NEXT: v_mov_b32_e32 v0, s477; SI-NEXT: buffer_store_dword v0, off, s[0:3], 078; SI-NEXT: s_endpgm79;80; VI-LABEL: fneg_fabsf_free_f32:81; VI: ; %bb.0:82; VI-NEXT: s_load_dword s2, s[4:5], 0x2c83; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2484; VI-NEXT: s_waitcnt lgkmcnt(0)85; VI-NEXT: s_bitset1_b32 s2, 3186; VI-NEXT: v_mov_b32_e32 v0, s087; VI-NEXT: v_mov_b32_e32 v1, s188; VI-NEXT: v_mov_b32_e32 v2, s289; VI-NEXT: flat_store_dword v[0:1], v290; VI-NEXT: s_endpgm91 %bc = bitcast i32 %in to float92 %fabs = call float @llvm.fabs.f32(float %bc)93 %fsub = fsub float -0.000000e+00, %fabs94 store float %fsub, ptr addrspace(1) %out95 ret void96}97 98define amdgpu_kernel void @fneg_fabsf_fn_free_f32(ptr addrspace(1) %out, i32 %in) {99; SI-LABEL: fneg_fabsf_fn_free_f32:100; SI: ; %bb.0:101; SI-NEXT: s_load_dword s2, s[4:5], 0xb102; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9103; SI-NEXT: s_mov_b32 s3, 0xf000104; SI-NEXT: s_waitcnt lgkmcnt(0)105; SI-NEXT: s_or_b32 s4, s2, 0x80000000106; SI-NEXT: s_mov_b32 s2, -1107; SI-NEXT: v_mov_b32_e32 v0, s4108; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0109; SI-NEXT: s_endpgm110;111; VI-LABEL: fneg_fabsf_fn_free_f32:112; VI: ; %bb.0:113; VI-NEXT: s_load_dword s2, s[4:5], 0x2c114; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24115; VI-NEXT: s_waitcnt lgkmcnt(0)116; VI-NEXT: s_bitset1_b32 s2, 31117; VI-NEXT: v_mov_b32_e32 v0, s0118; VI-NEXT: v_mov_b32_e32 v1, s1119; VI-NEXT: v_mov_b32_e32 v2, s2120; VI-NEXT: flat_store_dword v[0:1], v2121; VI-NEXT: s_endpgm122 %bc = bitcast i32 %in to float123 %fabs = call float @fabsf(float %bc)124 %fsub = fsub float -0.000000e+00, %fabs125 store float %fsub, ptr addrspace(1) %out126 ret void127}128 129define amdgpu_kernel void @fneg_fabsf_f32(ptr addrspace(1) %out, float %in) {130; SI-LABEL: fneg_fabsf_f32:131; SI: ; %bb.0:132; SI-NEXT: s_load_dword s2, s[4:5], 0xb133; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9134; SI-NEXT: s_mov_b32 s3, 0xf000135; SI-NEXT: s_waitcnt lgkmcnt(0)136; SI-NEXT: s_or_b32 s4, s2, 0x80000000137; SI-NEXT: s_mov_b32 s2, -1138; SI-NEXT: v_mov_b32_e32 v0, s4139; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0140; SI-NEXT: s_endpgm141;142; VI-LABEL: fneg_fabsf_f32:143; VI: ; %bb.0:144; VI-NEXT: s_load_dword s2, s[4:5], 0x2c145; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24146; VI-NEXT: s_waitcnt lgkmcnt(0)147; VI-NEXT: s_bitset1_b32 s2, 31148; VI-NEXT: v_mov_b32_e32 v0, s0149; VI-NEXT: v_mov_b32_e32 v1, s1150; VI-NEXT: v_mov_b32_e32 v2, s2151; VI-NEXT: flat_store_dword v[0:1], v2152; VI-NEXT: s_endpgm153 %fabs = call float @llvm.fabs.f32(float %in)154 %fsub = fsub float -0.000000e+00, %fabs155 store float %fsub, ptr addrspace(1) %out, align 4156 ret void157}158 159define amdgpu_kernel void @v_fneg_fabsf_f32(ptr addrspace(1) %out, ptr addrspace(1) %in) {160; SI-LABEL: v_fneg_fabsf_f32:161; SI: ; %bb.0:162; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9163; SI-NEXT: s_mov_b32 s7, 0xf000164; SI-NEXT: s_mov_b32 s6, -1165; SI-NEXT: s_mov_b32 s10, s6166; SI-NEXT: s_mov_b32 s11, s7167; SI-NEXT: s_waitcnt lgkmcnt(0)168; SI-NEXT: s_mov_b32 s8, s2169; SI-NEXT: s_mov_b32 s9, s3170; SI-NEXT: buffer_load_dword v0, off, s[8:11], 0171; SI-NEXT: s_mov_b32 s4, s0172; SI-NEXT: s_mov_b32 s5, s1173; SI-NEXT: s_waitcnt vmcnt(0)174; SI-NEXT: v_or_b32_e32 v0, 0x80000000, v0175; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0176; SI-NEXT: s_endpgm177;178; VI-LABEL: v_fneg_fabsf_f32:179; VI: ; %bb.0:180; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24181; VI-NEXT: s_waitcnt lgkmcnt(0)182; VI-NEXT: v_mov_b32_e32 v0, s2183; VI-NEXT: v_mov_b32_e32 v1, s3184; VI-NEXT: flat_load_dword v2, v[0:1]185; VI-NEXT: v_mov_b32_e32 v0, s0186; VI-NEXT: v_mov_b32_e32 v1, s1187; VI-NEXT: s_waitcnt vmcnt(0)188; VI-NEXT: v_or_b32_e32 v2, 0x80000000, v2189; VI-NEXT: flat_store_dword v[0:1], v2190; VI-NEXT: s_endpgm191 %val = load float, ptr addrspace(1) %in, align 4192 %fabs = call float @llvm.fabs.f32(float %val)193 %fsub = fsub float -0.000000e+00, %fabs194 store float %fsub, ptr addrspace(1) %out, align 4195 ret void196}197 198define amdgpu_kernel void @fneg_fabsf_v2f32(ptr addrspace(1) %out, <2 x float> %in) {199; SI-LABEL: fneg_fabsf_v2f32:200; SI: ; %bb.0:201; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9202; SI-NEXT: s_waitcnt lgkmcnt(0)203; SI-NEXT: s_mov_b64 s[4:5], s[2:3]204; SI-NEXT: s_mov_b32 s3, 0xf000205; SI-NEXT: s_bitset1_b32 s5, 31206; SI-NEXT: s_bitset1_b32 s4, 31207; SI-NEXT: s_mov_b32 s2, -1208; SI-NEXT: v_mov_b32_e32 v0, s4209; SI-NEXT: v_mov_b32_e32 v1, s5210; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0211; SI-NEXT: s_endpgm212;213; VI-LABEL: fneg_fabsf_v2f32:214; VI: ; %bb.0:215; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24216; VI-NEXT: s_waitcnt lgkmcnt(0)217; VI-NEXT: s_bitset1_b32 s3, 31218; VI-NEXT: s_bitset1_b32 s2, 31219; VI-NEXT: v_mov_b32_e32 v3, s1220; VI-NEXT: v_mov_b32_e32 v0, s2221; VI-NEXT: v_mov_b32_e32 v1, s3222; VI-NEXT: v_mov_b32_e32 v2, s0223; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]224; VI-NEXT: s_endpgm225 %fabs = call <2 x float> @llvm.fabs.v2f32(<2 x float> %in)226 %fsub = fsub <2 x float> <float -0.000000e+00, float -0.000000e+00>, %fabs227 store <2 x float> %fsub, ptr addrspace(1) %out228 ret void229}230 231define amdgpu_kernel void @fneg_fabsf_v4f32(ptr addrspace(1) %out, <4 x float> %in) {232; SI-LABEL: fneg_fabsf_v4f32:233; SI: ; %bb.0:234; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xd235; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9236; SI-NEXT: s_mov_b32 s7, 0xf000237; SI-NEXT: s_waitcnt lgkmcnt(0)238; SI-NEXT: s_bitset1_b32 s3, 31239; SI-NEXT: s_bitset1_b32 s2, 31240; SI-NEXT: s_bitset1_b32 s1, 31241; SI-NEXT: s_bitset1_b32 s0, 31242; SI-NEXT: s_mov_b32 s6, -1243; SI-NEXT: v_mov_b32_e32 v0, s0244; SI-NEXT: v_mov_b32_e32 v1, s1245; SI-NEXT: v_mov_b32_e32 v2, s2246; SI-NEXT: v_mov_b32_e32 v3, s3247; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0248; SI-NEXT: s_endpgm249;250; VI-LABEL: fneg_fabsf_v4f32:251; VI: ; %bb.0:252; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34253; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24254; VI-NEXT: s_waitcnt lgkmcnt(0)255; VI-NEXT: s_bitset1_b32 s3, 31256; VI-NEXT: s_bitset1_b32 s2, 31257; VI-NEXT: s_bitset1_b32 s1, 31258; VI-NEXT: s_bitset1_b32 s0, 31259; VI-NEXT: v_mov_b32_e32 v4, s4260; VI-NEXT: v_mov_b32_e32 v0, s0261; VI-NEXT: v_mov_b32_e32 v1, s1262; VI-NEXT: v_mov_b32_e32 v2, s2263; VI-NEXT: v_mov_b32_e32 v3, s3264; VI-NEXT: v_mov_b32_e32 v5, s5265; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]266; VI-NEXT: s_endpgm267 %fabs = call <4 x float> @llvm.fabs.v4f32(<4 x float> %in)268 %fsub = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %fabs269 store <4 x float> %fsub, ptr addrspace(1) %out270 ret void271}272 273declare float @fabsf(float) readnone274declare float @llvm.fabs.f32(float) readnone275declare <2 x float> @llvm.fabs.v2f32(<2 x float>) readnone276declare <4 x float> @llvm.fabs.v4f32(<4 x float>) readnone277 278;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:279; FUNC: {{.*}}280