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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 < %s | FileCheck -check-prefixes=GCN,GFX7 %s3; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9 %s4; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s5; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s6 7define i32 @fneg_xor_select_i32(i1 %cond, i32 %arg0, i32 %arg1) {8; GCN-LABEL: fneg_xor_select_i32:9; GCN: ; %bb.0:10; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)11; GCN-NEXT: v_and_b32_e32 v0, 1, v012; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v013; GCN-NEXT: v_cndmask_b32_e64 v0, -v2, -v1, vcc14; GCN-NEXT: s_setpc_b64 s[30:31]15;16; GFX11-LABEL: fneg_xor_select_i32:17; GFX11: ; %bb.0:18; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)19; GFX11-NEXT: v_and_b32_e32 v0, 1, v020; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)21; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v022; GFX11-NEXT: v_cndmask_b32_e64 v0, -v2, -v1, vcc_lo23; GFX11-NEXT: s_setpc_b64 s[30:31]24 %select = select i1 %cond, i32 %arg0, i32 %arg125 %fneg = xor i32 %select, -214748364826 ret i32 %fneg27}28 29define <2 x i32> @fneg_xor_select_v2i32(<2 x i1> %cond, <2 x i32> %arg0, <2 x i32> %arg1) {30; GCN-LABEL: fneg_xor_select_v2i32:31; GCN: ; %bb.0:32; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)33; GCN-NEXT: v_and_b32_e32 v0, 1, v034; GCN-NEXT: v_and_b32_e32 v1, 1, v135; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v036; GCN-NEXT: v_cndmask_b32_e64 v0, -v4, -v2, vcc37; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v138; GCN-NEXT: v_cndmask_b32_e64 v1, -v5, -v3, vcc39; GCN-NEXT: s_setpc_b64 s[30:31]40;41; GFX11-TRUE16-LABEL: fneg_xor_select_v2i32:42; GFX11-TRUE16: ; %bb.0:43; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)44; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 1, v0.l45; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 1, v1.l46; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)47; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.l48; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, -v4, -v2, vcc_lo49; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v1.l50; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, -v5, -v3, vcc_lo51; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]52;53; GFX11-FAKE16-LABEL: fneg_xor_select_v2i32:54; GFX11-FAKE16: ; %bb.0:55; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)56; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 1, v057; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 1, v158; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)59; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v060; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, -v4, -v2, vcc_lo61; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v162; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, -v5, -v3, vcc_lo63; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]64 %select = select <2 x i1> %cond, <2 x i32> %arg0, <2 x i32> %arg165 %fneg = xor <2 x i32> %select, <i32 -2147483648, i32 -2147483648>66 ret <2 x i32> %fneg67}68 69define i32 @fneg_xor_select_i32_multi_use(i1 %cond, i32 %arg0, i32 %arg1, ptr addrspace(1) %ptr) {70; GFX7-LABEL: fneg_xor_select_i32_multi_use:71; GFX7: ; %bb.0:72; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)73; GFX7-NEXT: v_and_b32_e32 v0, 1, v074; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v075; GFX7-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc76; GFX7-NEXT: flat_store_dword v[3:4], v077; GFX7-NEXT: v_xor_b32_e32 v0, 0x80000000, v078; GFX7-NEXT: s_waitcnt vmcnt(0)79; GFX7-NEXT: s_setpc_b64 s[30:31]80;81; GFX9-LABEL: fneg_xor_select_i32_multi_use:82; GFX9: ; %bb.0:83; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)84; GFX9-NEXT: v_and_b32_e32 v0, 1, v085; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v086; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc87; GFX9-NEXT: global_store_dword v[3:4], v0, off88; GFX9-NEXT: v_xor_b32_e32 v0, 0x80000000, v089; GFX9-NEXT: s_waitcnt vmcnt(0)90; GFX9-NEXT: s_setpc_b64 s[30:31]91;92; GFX11-LABEL: fneg_xor_select_i32_multi_use:93; GFX11: ; %bb.0:94; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)95; GFX11-NEXT: v_and_b32_e32 v0, 1, v096; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)97; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v098; GFX11-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc_lo99; GFX11-NEXT: v_xor_b32_e32 v0, 0x80000000, v1100; GFX11-NEXT: global_store_b32 v[3:4], v1, off101; GFX11-NEXT: s_setpc_b64 s[30:31]102 %select = select i1 %cond, i32 %arg0, i32 %arg1103 store i32 %select, ptr addrspace(1) %ptr104 %fneg = xor i32 %select, -2147483648105 ret i32 %fneg106}107 108define i64 @fneg_xor_select_i64(i1 %cond, i64 %arg0, i64 %arg1) {109; GCN-LABEL: fneg_xor_select_i64:110; GCN: ; %bb.0:111; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)112; GCN-NEXT: v_and_b32_e32 v0, 1, v0113; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0114; GCN-NEXT: v_cndmask_b32_e32 v0, v3, v1, vcc115; GCN-NEXT: v_cndmask_b32_e64 v1, -v4, -v2, vcc116; GCN-NEXT: s_setpc_b64 s[30:31]117;118; GFX11-LABEL: fneg_xor_select_i64:119; GFX11: ; %bb.0:120; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)121; GFX11-NEXT: v_and_b32_e32 v0, 1, v0122; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)123; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0124; GFX11-NEXT: v_cndmask_b32_e32 v0, v3, v1, vcc_lo125; GFX11-NEXT: v_cndmask_b32_e64 v1, -v4, -v2, vcc_lo126; GFX11-NEXT: s_setpc_b64 s[30:31]127 %select = select i1 %cond, i64 %arg0, i64 %arg1128 %fneg = xor i64 %select, 9223372036854775808129 ret i64 %fneg130}131 132define <2 x i64> @fneg_xor_select_v2i64(<2 x i1> %cond, <2 x i64> %arg0, <2 x i64> %arg1) {133; GCN-LABEL: fneg_xor_select_v2i64:134; GCN: ; %bb.0:135; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)136; GCN-NEXT: v_and_b32_e32 v1, 1, v1137; GCN-NEXT: v_and_b32_e32 v0, 1, v0138; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0139; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v1140; GCN-NEXT: v_cndmask_b32_e32 v0, v6, v2, vcc141; GCN-NEXT: v_cndmask_b32_e64 v2, v8, v4, s[4:5]142; GCN-NEXT: v_cndmask_b32_e64 v1, -v7, -v3, vcc143; GCN-NEXT: v_cndmask_b32_e64 v3, -v9, -v5, s[4:5]144; GCN-NEXT: s_setpc_b64 s[30:31]145;146; GFX11-TRUE16-LABEL: fneg_xor_select_v2i64:147; GFX11-TRUE16: ; %bb.0:148; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)149; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 1, v0.l150; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 1, v1.l151; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)152; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.l153; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 1, v0.h154; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v6, v2, vcc_lo155; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)156; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v2, v8, v4, s0157; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, -v7, -v3, vcc_lo158; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v3, -v9, -v5, s0159; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]160;161; GFX11-FAKE16-LABEL: fneg_xor_select_v2i64:162; GFX11-FAKE16: ; %bb.0:163; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)164; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 1, v0165; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)166; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0167; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v0, v6, v2 :: v_dual_and_b32 v1, 1, v1168; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e64 s0, 1, v1169; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, -v7, -v3, vcc_lo170; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)171; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, v8, v4, s0172; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, -v9, -v5, s0173; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]174 %select = select <2 x i1> %cond, <2 x i64> %arg0, <2 x i64> %arg1175 %fneg = xor <2 x i64> %select, <i64 9223372036854775808, i64 9223372036854775808>176 ret <2 x i64> %fneg177}178 179define i16 @fneg_xor_select_i16(i1 %cond, i16 %arg0, i16 %arg1) {180; GCN-LABEL: fneg_xor_select_i16:181; GCN: ; %bb.0:182; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)183; GCN-NEXT: v_and_b32_e32 v0, 1, v0184; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0185; GCN-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc186; GCN-NEXT: v_xor_b32_e32 v0, 0xffff8000, v0187; GCN-NEXT: s_setpc_b64 s[30:31]188;189; GFX11-TRUE16-LABEL: fneg_xor_select_i16:190; GFX11-TRUE16: ; %bb.0:191; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)192; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 1, v0193; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)194; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0195; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v1.l, vcc_lo196; GFX11-TRUE16-NEXT: v_xor_b16 v0.l, 0x8000, v0.l197; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]198;199; GFX11-FAKE16-LABEL: fneg_xor_select_i16:200; GFX11-FAKE16: ; %bb.0:201; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)202; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 1, v0203; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)204; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0205; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc_lo206; GFX11-FAKE16-NEXT: v_xor_b32_e32 v0, 0xffff8000, v0207; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]208 %select = select i1 %cond, i16 %arg0, i16 %arg1209 %fneg = xor i16 %select, -32768210 ret i16 %fneg211}212 213define <2 x i16> @fneg_xor_select_v2i16(<2 x i1> %cond, <2 x i16> %arg0, <2 x i16> %arg1) {214; GFX7-LABEL: fneg_xor_select_v2i16:215; GFX7: ; %bb.0:216; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)217; GFX7-NEXT: v_and_b32_e32 v0, 1, v0218; GFX7-NEXT: v_and_b32_e32 v1, 1, v1219; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0220; GFX7-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc221; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v1222; GFX7-NEXT: v_cndmask_b32_e32 v1, v5, v3, vcc223; GFX7-NEXT: v_xor_b32_e32 v1, 0x8000, v1224; GFX7-NEXT: v_xor_b32_e32 v0, 0x8000, v0225; GFX7-NEXT: v_lshlrev_b32_e32 v2, 16, v1226; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0227; GFX7-NEXT: v_or_b32_e32 v0, v0, v2228; GFX7-NEXT: v_and_b32_e32 v1, 0xffff, v1229; GFX7-NEXT: s_setpc_b64 s[30:31]230;231; GFX9-LABEL: fneg_xor_select_v2i16:232; GFX9: ; %bb.0:233; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)234; GFX9-NEXT: v_and_b32_e32 v1, 1, v1235; GFX9-NEXT: v_and_b32_e32 v0, 1, v0236; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v1237; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v0238; GFX9-NEXT: v_cndmask_b32_e64 v0, v3, v2, s[4:5]239; GFX9-NEXT: v_cndmask_b32_sdwa v1, v3, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1240; GFX9-NEXT: s_mov_b32 s4, 0x5040100241; GFX9-NEXT: v_perm_b32 v0, v1, v0, s4242; GFX9-NEXT: v_xor_b32_e32 v0, 0x80008000, v0243; GFX9-NEXT: s_setpc_b64 s[30:31]244;245; GFX11-TRUE16-LABEL: fneg_xor_select_v2i16:246; GFX11-TRUE16: ; %bb.0:247; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)248; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 1, v0.l249; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 1, v1.l250; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)251; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.l252; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 1, v0.h253; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v3.l, v2.l, vcc_lo254; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)255; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v3.h, v2.h, s0256; GFX11-TRUE16-NEXT: v_xor_b32_e32 v0, 0x80008000, v0257; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]258;259; GFX11-FAKE16-LABEL: fneg_xor_select_v2i16:260; GFX11-FAKE16: ; %bb.0:261; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)262; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 1, v0263; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2264; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v3265; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)266; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0267; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v0, v3, v2 :: v_dual_and_b32 v1, 1, v1268; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1269; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)270; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v5, v4, vcc_lo271; GFX11-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100272; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)273; GFX11-FAKE16-NEXT: v_xor_b32_e32 v0, 0x80008000, v0274; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]275 %select = select <2 x i1> %cond, <2 x i16> %arg0, <2 x i16> %arg1276 %fneg = xor <2 x i16> %select, <i16 -32768, i16 -32768>277 ret <2 x i16> %fneg278}279 280define i16 @fneg_xor_select_i16_multi_use(i1 %cond, i16 %arg0, i16 %arg1, ptr addrspace(1) %ptr) {281; GFX7-LABEL: fneg_xor_select_i16_multi_use:282; GFX7: ; %bb.0:283; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)284; GFX7-NEXT: v_and_b32_e32 v0, 1, v0285; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0286; GFX7-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc287; GFX7-NEXT: flat_store_short v[3:4], v0288; GFX7-NEXT: v_xor_b32_e32 v0, 0xffff8000, v0289; GFX7-NEXT: s_waitcnt vmcnt(0)290; GFX7-NEXT: s_setpc_b64 s[30:31]291;292; GFX9-LABEL: fneg_xor_select_i16_multi_use:293; GFX9: ; %bb.0:294; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)295; GFX9-NEXT: v_and_b32_e32 v0, 1, v0296; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0297; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc298; GFX9-NEXT: global_store_short v[3:4], v0, off299; GFX9-NEXT: v_xor_b32_e32 v0, 0xffff8000, v0300; GFX9-NEXT: s_waitcnt vmcnt(0)301; GFX9-NEXT: s_setpc_b64 s[30:31]302;303; GFX11-TRUE16-LABEL: fneg_xor_select_i16_multi_use:304; GFX11-TRUE16: ; %bb.0:305; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)306; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 1, v0307; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)308; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0309; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.l, v1.l, vcc_lo310; GFX11-TRUE16-NEXT: v_xor_b16 v0.l, 0x8000, v0.h311; GFX11-TRUE16-NEXT: global_store_d16_hi_b16 v[3:4], v0, off312; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]313;314; GFX11-FAKE16-LABEL: fneg_xor_select_i16_multi_use:315; GFX11-FAKE16: ; %bb.0:316; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)317; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 1, v0318; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)319; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0320; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc_lo321; GFX11-FAKE16-NEXT: v_xor_b32_e32 v0, 0xffff8000, v1322; GFX11-FAKE16-NEXT: global_store_b16 v[3:4], v1, off323; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]324 %select = select i1 %cond, i16 %arg0, i16 %arg1325 store i16 %select, ptr addrspace(1) %ptr326 %fneg = xor i16 %select, -32768327 ret i16 %fneg328}329 330define i64 @fneg_xor_select_i64_multi_user(i1 %cond, i64 %arg0, i64 %arg1, ptr addrspace(1) %ptr) {331; GFX7-LABEL: fneg_xor_select_i64_multi_user:332; GFX7: ; %bb.0:333; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)334; GFX7-NEXT: v_and_b32_e32 v0, 1, v0335; GFX7-NEXT: v_mov_b32_e32 v7, v1336; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0337; GFX7-NEXT: v_cndmask_b32_e32 v1, v4, v2, vcc338; GFX7-NEXT: v_cndmask_b32_e32 v0, v3, v7, vcc339; GFX7-NEXT: flat_store_dwordx2 v[5:6], v[0:1]340; GFX7-NEXT: v_cndmask_b32_e64 v1, -v4, -v2, vcc341; GFX7-NEXT: s_waitcnt vmcnt(0)342; GFX7-NEXT: s_setpc_b64 s[30:31]343;344; GFX9-LABEL: fneg_xor_select_i64_multi_user:345; GFX9: ; %bb.0:346; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)347; GFX9-NEXT: v_and_b32_e32 v0, 1, v0348; GFX9-NEXT: v_mov_b32_e32 v7, v1349; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0350; GFX9-NEXT: v_cndmask_b32_e32 v1, v4, v2, vcc351; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v7, vcc352; GFX9-NEXT: global_store_dwordx2 v[5:6], v[0:1], off353; GFX9-NEXT: v_cndmask_b32_e64 v1, -v4, -v2, vcc354; GFX9-NEXT: s_waitcnt vmcnt(0)355; GFX9-NEXT: s_setpc_b64 s[30:31]356;357; GFX11-LABEL: fneg_xor_select_i64_multi_user:358; GFX11: ; %bb.0:359; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)360; GFX11-NEXT: v_dual_mov_b32 v7, v1 :: v_dual_and_b32 v0, 1, v0361; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)362; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0363; GFX11-NEXT: v_dual_cndmask_b32 v1, v4, v2 :: v_dual_cndmask_b32 v0, v3, v7364; GFX11-NEXT: v_cndmask_b32_e64 v2, -v4, -v2, vcc_lo365; GFX11-NEXT: global_store_b64 v[5:6], v[0:1], off366; GFX11-NEXT: v_mov_b32_e32 v1, v2367; GFX11-NEXT: s_setpc_b64 s[30:31]368 %select = select i1 %cond, i64 %arg0, i64 %arg1369 store i64 %select, ptr addrspace(1) %ptr370 %fneg = xor i64 %select, 9223372036854775808371 ret i64 %fneg372}373 374define i32 @select_fneg_xor_select_i32(i1 %cond0, i1 %cond1, i32 %arg0, i32 %arg1) {375; GCN-LABEL: select_fneg_xor_select_i32:376; GCN: ; %bb.0:377; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)378; GCN-NEXT: v_and_b32_e32 v0, 1, v0379; GCN-NEXT: v_and_b32_e32 v1, 1, v1380; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0381; GCN-NEXT: v_cndmask_b32_e64 v0, -v2, v3, vcc382; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v1383; GCN-NEXT: v_cndmask_b32_e64 v0, v0, -v0, vcc384; GCN-NEXT: s_setpc_b64 s[30:31]385;386; GFX11-LABEL: select_fneg_xor_select_i32:387; GFX11: ; %bb.0:388; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)389; GFX11-NEXT: v_and_b32_e32 v0, 1, v0390; GFX11-NEXT: v_and_b32_e32 v1, 1, v1391; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)392; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0393; GFX11-NEXT: v_cndmask_b32_e64 v0, -v2, v3, vcc_lo394; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1395; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)396; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, -v0, vcc_lo397; GFX11-NEXT: s_setpc_b64 s[30:31]398 %fneg0 = xor i32 %arg0, -2147483648399 %select0 = select i1 %cond0, i32 %arg1, i32 %fneg0400 %fneg1 = xor i32 %select0, -2147483648401 %select1 = select i1 %cond1, i32 %fneg1, i32 %select0402 ret i32 %select1403}404 405define float @select_fneg_select_f32(i1 %cond0, i1 %cond1, float %arg0, float %arg1) {406; GCN-LABEL: select_fneg_select_f32:407; GCN: ; %bb.0:408; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)409; GCN-NEXT: v_and_b32_e32 v0, 1, v0410; GCN-NEXT: v_and_b32_e32 v1, 1, v1411; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0412; GCN-NEXT: v_cndmask_b32_e64 v0, -v2, v3, vcc413; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v1414; GCN-NEXT: v_cndmask_b32_e64 v0, v0, -v0, vcc415; GCN-NEXT: s_setpc_b64 s[30:31]416;417; GFX11-LABEL: select_fneg_select_f32:418; GFX11: ; %bb.0:419; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)420; GFX11-NEXT: v_and_b32_e32 v0, 1, v0421; GFX11-NEXT: v_and_b32_e32 v1, 1, v1422; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)423; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0424; GFX11-NEXT: v_cndmask_b32_e64 v0, -v2, v3, vcc_lo425; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1426; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)427; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, -v0, vcc_lo428; GFX11-NEXT: s_setpc_b64 s[30:31]429 %fneg0 = fneg float %arg0430 %select0 = select i1 %cond0, float %arg1, float %fneg0431 %fneg1 = fneg float %select0432 %select1 = select i1 %cond1, float %fneg1, float %select0433 ret float %select1434}435 436define double @fneg_xor_select_f64(i1 %cond, double %arg0, double %arg1) {437; GCN-LABEL: fneg_xor_select_f64:438; GCN: ; %bb.0:439; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)440; GCN-NEXT: v_and_b32_e32 v0, 1, v0441; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0442; GCN-NEXT: v_cndmask_b32_e32 v0, v3, v1, vcc443; GCN-NEXT: v_cndmask_b32_e64 v1, -v4, -v2, vcc444; GCN-NEXT: s_setpc_b64 s[30:31]445;446; GFX11-LABEL: fneg_xor_select_f64:447; GFX11: ; %bb.0:448; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)449; GFX11-NEXT: v_and_b32_e32 v0, 1, v0450; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)451; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0452; GFX11-NEXT: v_cndmask_b32_e32 v0, v3, v1, vcc_lo453; GFX11-NEXT: v_cndmask_b32_e64 v1, -v4, -v2, vcc_lo454; GFX11-NEXT: s_setpc_b64 s[30:31]455 %select = select i1 %cond, double %arg0, double %arg1456 %fneg = fneg double %select457 ret double %fneg458}459 460define double @fneg_xor_select_f64_multi_user(i1 %cond, double %arg0, double %arg1, ptr addrspace(1) %ptr) {461; GFX7-LABEL: fneg_xor_select_f64_multi_user:462; GFX7: ; %bb.0:463; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)464; GFX7-NEXT: v_and_b32_e32 v0, 1, v0465; GFX7-NEXT: v_mov_b32_e32 v7, v1466; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0467; GFX7-NEXT: v_cndmask_b32_e32 v1, v4, v2, vcc468; GFX7-NEXT: v_cndmask_b32_e32 v0, v3, v7, vcc469; GFX7-NEXT: flat_store_dwordx2 v[5:6], v[0:1]470; GFX7-NEXT: v_xor_b32_e32 v1, 0x80000000, v1471; GFX7-NEXT: s_waitcnt vmcnt(0)472; GFX7-NEXT: s_setpc_b64 s[30:31]473;474; GFX9-LABEL: fneg_xor_select_f64_multi_user:475; GFX9: ; %bb.0:476; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)477; GFX9-NEXT: v_and_b32_e32 v0, 1, v0478; GFX9-NEXT: v_mov_b32_e32 v7, v1479; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0480; GFX9-NEXT: v_cndmask_b32_e32 v1, v4, v2, vcc481; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v7, vcc482; GFX9-NEXT: global_store_dwordx2 v[5:6], v[0:1], off483; GFX9-NEXT: v_xor_b32_e32 v1, 0x80000000, v1484; GFX9-NEXT: s_waitcnt vmcnt(0)485; GFX9-NEXT: s_setpc_b64 s[30:31]486;487; GFX11-LABEL: fneg_xor_select_f64_multi_user:488; GFX11: ; %bb.0:489; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)490; GFX11-NEXT: v_dual_mov_b32 v7, v1 :: v_dual_and_b32 v0, 1, v0491; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)492; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0493; GFX11-NEXT: v_dual_cndmask_b32 v1, v4, v2 :: v_dual_cndmask_b32 v0, v3, v7494; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)495; GFX11-NEXT: v_xor_b32_e32 v2, 0x80000000, v1496; GFX11-NEXT: global_store_b64 v[5:6], v[0:1], off497; GFX11-NEXT: v_mov_b32_e32 v1, v2498; GFX11-NEXT: s_setpc_b64 s[30:31]499 %select = select i1 %cond, double %arg0, double %arg1500 store double %select, ptr addrspace(1) %ptr501 %fneg = fneg double %select502 ret double %fneg503}504 505define double @fneg_xor_select_i64_user_with_srcmods(i1 %cond, i64 %arg0, i64 %arg1) {506; GCN-LABEL: fneg_xor_select_i64_user_with_srcmods:507; GCN: ; %bb.0:508; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)509; GCN-NEXT: v_and_b32_e32 v0, 1, v0510; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0511; GCN-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc512; GCN-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc513; GCN-NEXT: v_add_f64 v[0:1], -v[1:2], 2.0514; GCN-NEXT: s_setpc_b64 s[30:31]515;516; GFX11-LABEL: fneg_xor_select_i64_user_with_srcmods:517; GFX11: ; %bb.0:518; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)519; GFX11-NEXT: v_and_b32_e32 v0, 1, v0520; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)521; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0522; GFX11-NEXT: v_dual_cndmask_b32 v2, v4, v2 :: v_dual_cndmask_b32 v1, v3, v1523; GFX11-NEXT: v_add_f64 v[0:1], -v[1:2], 2.0524; GFX11-NEXT: s_setpc_b64 s[30:31]525 %select = select i1 %cond, i64 %arg0, i64 %arg1526 %fneg = xor i64 %select, 9223372036854775808527 %cast = bitcast i64 %fneg to double528 %add = fadd double %cast, 2.0529 ret double %add530}531 532define double @select_fneg_select_fneg_f64(i1 %cond0, i1 %cond1, double %arg0, double %arg1) {533; GCN-LABEL: select_fneg_select_fneg_f64:534; GCN: ; %bb.0:535; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)536; GCN-NEXT: v_and_b32_e32 v0, 1, v0537; GCN-NEXT: v_xor_b32_e32 v3, 0x80000000, v3538; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0539; GCN-NEXT: v_and_b32_e32 v1, 1, v1540; GCN-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc541; GCN-NEXT: v_cndmask_b32_e32 v2, v3, v5, vcc542; GCN-NEXT: v_xor_b32_e32 v3, 0x80000000, v2543; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v1544; GCN-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc545; GCN-NEXT: s_setpc_b64 s[30:31]546;547; GFX11-LABEL: select_fneg_select_fneg_f64:548; GFX11: ; %bb.0:549; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)550; GFX11-NEXT: v_and_b32_e32 v0, 1, v0551; GFX11-NEXT: v_xor_b32_e32 v3, 0x80000000, v3552; GFX11-NEXT: v_and_b32_e32 v1, 1, v1553; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)554; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0555; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc_lo556; GFX11-NEXT: v_cndmask_b32_e32 v2, v3, v5, vcc_lo557; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)558; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1559; GFX11-NEXT: v_xor_b32_e32 v3, 0x80000000, v2560; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)561; GFX11-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo562; GFX11-NEXT: s_setpc_b64 s[30:31]563 %fneg0 = fneg double %arg0564 %select0 = select i1 %cond0, double %arg1, double %fneg0565 %fneg1 = fneg double %select0566 %select1 = select i1 %cond1, double %fneg1, double %select0567 ret double %select1568}569 570define i64 @select_fneg_xor_select_i64(i1 %cond0, i1 %cond1, i64 %arg0, i64 %arg1) {571; GCN-LABEL: select_fneg_xor_select_i64:572; GCN: ; %bb.0:573; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)574; GCN-NEXT: v_and_b32_e32 v0, 1, v0575; GCN-NEXT: v_and_b32_e32 v1, 1, v1576; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0577; GCN-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc578; GCN-NEXT: v_cndmask_b32_e64 v2, -v3, v5, vcc579; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v1580; GCN-NEXT: v_cndmask_b32_e64 v1, v2, -v2, vcc581; GCN-NEXT: s_setpc_b64 s[30:31]582;583; GFX11-LABEL: select_fneg_xor_select_i64:584; GFX11: ; %bb.0:585; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)586; GFX11-NEXT: v_and_b32_e32 v0, 1, v0587; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)588; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0589; GFX11-NEXT: v_dual_cndmask_b32 v0, v2, v4 :: v_dual_and_b32 v1, 1, v1590; GFX11-NEXT: v_cndmask_b32_e64 v2, -v3, v5, vcc_lo591; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1592; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)593; GFX11-NEXT: v_cndmask_b32_e64 v1, v2, -v2, vcc_lo594; GFX11-NEXT: s_setpc_b64 s[30:31]595 %fneg0 = xor i64 %arg0, 9223372036854775808596 %select0 = select i1 %cond0, i64 %arg1, i64 %fneg0597 %fneg1 = xor i64 %select0, 9223372036854775808598 %select1 = select i1 %cond1, i64 %fneg1, i64 %select0599 ret i64 %select1600}601 602define half @select_fneg_select_f16(i1 %cond0, i1 %cond1, half %arg0, half %arg1) {603; GFX7-LABEL: select_fneg_select_f16:604; GFX7: ; %bb.0:605; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)606; GFX7-NEXT: v_cvt_f16_f32_e32 v3, v3607; GFX7-NEXT: v_cvt_f16_f32_e64 v2, -v2608; GFX7-NEXT: v_and_b32_e32 v0, 1, v0609; GFX7-NEXT: v_and_b32_e32 v1, 1, v1610; GFX7-NEXT: v_cvt_f32_f16_e32 v3, v3611; GFX7-NEXT: v_cvt_f32_f16_e32 v2, v2612; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0613; GFX7-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc614; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v1615; GFX7-NEXT: v_cndmask_b32_e64 v0, v0, -v0, vcc616; GFX7-NEXT: s_setpc_b64 s[30:31]617;618; GFX9-LABEL: select_fneg_select_f16:619; GFX9: ; %bb.0:620; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)621; GFX9-NEXT: v_and_b32_e32 v0, 1, v0622; GFX9-NEXT: v_xor_b32_e32 v2, 0x8000, v2623; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0624; GFX9-NEXT: v_and_b32_e32 v1, 1, v1625; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc626; GFX9-NEXT: v_xor_b32_e32 v2, 0x8000, v0627; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v1628; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc629; GFX9-NEXT: s_setpc_b64 s[30:31]630;631; GFX11-TRUE16-LABEL: select_fneg_select_f16:632; GFX11-TRUE16: ; %bb.0:633; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)634; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 1, v0635; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 1, v1636; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)637; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0638; GFX11-TRUE16-NEXT: v_xor_b16 v0.l, 0x8000, v2.l639; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v3.l, vcc_lo640; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)641; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1642; GFX11-TRUE16-NEXT: v_xor_b16 v0.h, 0x8000, v0.l643; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)644; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v0.h, vcc_lo645; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]646;647; GFX11-FAKE16-LABEL: select_fneg_select_f16:648; GFX11-FAKE16: ; %bb.0:649; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)650; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 1, v0651; GFX11-FAKE16-NEXT: v_xor_b32_e32 v2, 0x8000, v2652; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 1, v1653; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)654; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0655; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc_lo656; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)657; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1658; GFX11-FAKE16-NEXT: v_xor_b32_e32 v2, 0x8000, v0659; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)660; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo661; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]662 %fneg0 = fneg half %arg0663 %select0 = select i1 %cond0, half %arg1, half %fneg0664 %fneg1 = fneg half %select0665 %select1 = select i1 %cond1, half %fneg1, half %select0666 ret half %select1667}668 669define i16 @select_fneg_xor_select_i16(i1 %cond0, i1 %cond1, i16 %arg0, i16 %arg1) {670; GCN-LABEL: select_fneg_xor_select_i16:671; GCN: ; %bb.0:672; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)673; GCN-NEXT: v_and_b32_e32 v0, 1, v0674; GCN-NEXT: v_xor_b32_e32 v2, 0xffff8000, v2675; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0676; GCN-NEXT: v_and_b32_e32 v1, 1, v1677; GCN-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc678; GCN-NEXT: v_xor_b32_e32 v2, 0xffff8000, v0679; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v1680; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc681; GCN-NEXT: s_setpc_b64 s[30:31]682;683; GFX11-TRUE16-LABEL: select_fneg_xor_select_i16:684; GFX11-TRUE16: ; %bb.0:685; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)686; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 1, v0687; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 1, v1688; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)689; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0690; GFX11-TRUE16-NEXT: v_xor_b16 v0.l, 0x8000, v2.l691; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v3.l, vcc_lo692; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)693; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1694; GFX11-TRUE16-NEXT: v_xor_b16 v0.h, 0x8000, v0.l695; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)696; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v0.h, vcc_lo697; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]698;699; GFX11-FAKE16-LABEL: select_fneg_xor_select_i16:700; GFX11-FAKE16: ; %bb.0:701; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)702; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 1, v0703; GFX11-FAKE16-NEXT: v_xor_b32_e32 v2, 0xffff8000, v2704; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 1, v1705; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)706; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0707; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc_lo708; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)709; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1710; GFX11-FAKE16-NEXT: v_xor_b32_e32 v2, 0xffff8000, v0711; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)712; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo713; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]714 %fneg0 = xor i16 %arg0, -32768715 %select0 = select i1 %cond0, i16 %arg1, i16 %fneg0716 %fneg1 = xor i16 %select0, -32768717 %select1 = select i1 %cond1, i16 %fneg1, i16 %select0718 ret i16 %select1719}720 721define <2 x half> @select_fneg_select_v2f16(<2 x i1> %cond0, <2 x i1> %cond1, <2 x half> %arg0, <2 x half> %arg1) {722; GFX7-LABEL: select_fneg_select_v2f16:723; GFX7: ; %bb.0:724; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)725; GFX7-NEXT: v_cvt_f16_f32_e32 v5, v5726; GFX7-NEXT: v_cvt_f16_f32_e32 v4, v4727; GFX7-NEXT: v_cvt_f16_f32_e32 v6, v6728; GFX7-NEXT: v_cvt_f16_f32_e32 v7, v7729; GFX7-NEXT: v_lshlrev_b32_e32 v5, 16, v5730; GFX7-NEXT: v_or_b32_e32 v4, v4, v5731; GFX7-NEXT: v_xor_b32_e32 v4, 0x80008000, v4732; GFX7-NEXT: v_cvt_f32_f16_e32 v5, v6733; GFX7-NEXT: v_cvt_f32_f16_e32 v6, v7734; GFX7-NEXT: v_lshrrev_b32_e32 v7, 16, v4735; GFX7-NEXT: v_cvt_f32_f16_e32 v7, v7736; GFX7-NEXT: v_cvt_f32_f16_e32 v4, v4737; GFX7-NEXT: v_and_b32_e32 v1, 1, v1738; GFX7-NEXT: v_and_b32_e32 v0, 1, v0739; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v1740; GFX7-NEXT: v_cndmask_b32_e32 v1, v7, v6, vcc741; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0742; GFX7-NEXT: v_cvt_f16_f32_e32 v6, v1743; GFX7-NEXT: v_cndmask_b32_e32 v0, v4, v5, vcc744; GFX7-NEXT: v_cvt_f16_f32_e32 v4, v0745; GFX7-NEXT: v_and_b32_e32 v2, 1, v2746; GFX7-NEXT: v_lshlrev_b32_e32 v5, 16, v6747; GFX7-NEXT: v_and_b32_e32 v3, 1, v3748; GFX7-NEXT: v_or_b32_e32 v4, v4, v5749; GFX7-NEXT: v_xor_b32_e32 v4, 0x80008000, v4750; GFX7-NEXT: v_cvt_f32_f16_e32 v5, v4751; GFX7-NEXT: v_lshrrev_b32_e32 v4, 16, v4752; GFX7-NEXT: v_cvt_f32_f16_e32 v4, v4753; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v2754; GFX7-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc755; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v3756; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc757; GFX7-NEXT: s_setpc_b64 s[30:31]758;759; GFX9-LABEL: select_fneg_select_v2f16:760; GFX9: ; %bb.0:761; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)762; GFX9-NEXT: v_and_b32_e32 v1, 1, v1763; GFX9-NEXT: v_and_b32_e32 v3, 1, v3764; GFX9-NEXT: v_and_b32_e32 v0, 1, v0765; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v1766; GFX9-NEXT: v_xor_b32_e32 v1, 0x80008000, v4767; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v3768; GFX9-NEXT: v_cndmask_b32_sdwa v3, v1, v5, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1769; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0770; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v5, vcc771; GFX9-NEXT: s_mov_b32 s6, 0x5040100772; GFX9-NEXT: v_perm_b32 v1, v3, v0, s6773; GFX9-NEXT: v_and_b32_e32 v2, 1, v2774; GFX9-NEXT: v_xor_b32_e32 v1, 0x80008000, v1775; GFX9-NEXT: s_mov_b64 vcc, s[4:5]776; GFX9-NEXT: v_cndmask_b32_sdwa v3, v3, v1, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1777; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v2778; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc779; GFX9-NEXT: v_perm_b32 v0, v3, v0, s6780; GFX9-NEXT: s_setpc_b64 s[30:31]781;782; GFX11-TRUE16-LABEL: select_fneg_select_v2f16:783; GFX11-TRUE16: ; %bb.0:784; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)785; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 1, v1.l786; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 1, v0.l787; GFX11-TRUE16-NEXT: v_xor_b32_e32 v1, 0x80008000, v4788; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)789; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.h790; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 1, v0.l791; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 1, v3.l792; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 1, v2.l793; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v1.h, v5.h, vcc_lo794; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)795; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v5.l, s0796; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.l797; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)798; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 1, v0.h799; GFX11-TRUE16-NEXT: v_xor_b32_e32 v2, 0x80008000, v1800; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)801; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v1.h, v2.h, vcc_lo802; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v2.l, s0803; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]804;805; GFX11-FAKE16-LABEL: select_fneg_select_v2f16:806; GFX11-FAKE16: ; %bb.0:807; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)808; GFX11-FAKE16-NEXT: v_xor_b32_e32 v4, 0x80008000, v4809; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v5810; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 1, v3811; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)812; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v4813; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 1, v0814; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0815; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v4, v5, vcc_lo816; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 1, v1817; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)818; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1819; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v7, v6, vcc_lo820; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v3821; GFX11-FAKE16-NEXT: v_perm_b32 v4, v1, v0, 0x5040100822; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)823; GFX11-FAKE16-NEXT: v_xor_b32_e32 v4, 0x80008000, v4824; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v4825; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)826; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v1, v5 :: v_dual_and_b32 v2, 1, v2827; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v2828; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc_lo829; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)830; GFX11-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100831; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]832 %fneg0 = fneg <2 x half> %arg0833 %select0 = select <2 x i1> %cond0, <2 x half> %arg1, <2 x half> %fneg0834 %fneg1 = fneg <2 x half> %select0835 %select1 = select <2 x i1> %cond1, <2 x half> %fneg1, <2 x half> %select0836 ret <2 x half> %select1837}838 839define <2 x i16> @select_fneg_xor_select_v2i16(<2 x i1> %cond0, <2 x i1> %cond1, <2 x i16> %arg0, <2 x i16> %arg1) {840; GFX7-LABEL: select_fneg_xor_select_v2i16:841; GFX7: ; %bb.0:842; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)843; GFX7-NEXT: v_and_b32_e32 v1, 1, v1844; GFX7-NEXT: v_and_b32_e32 v0, 1, v0845; GFX7-NEXT: v_xor_b32_e32 v5, 0xffff8000, v5846; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v1847; GFX7-NEXT: v_and_b32_e32 v3, 1, v3848; GFX7-NEXT: v_xor_b32_e32 v4, 0xffff8000, v4849; GFX7-NEXT: v_cndmask_b32_e32 v1, v5, v7, vcc850; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0851; GFX7-NEXT: v_and_b32_e32 v2, 1, v2852; GFX7-NEXT: v_cndmask_b32_e32 v0, v4, v6, vcc853; GFX7-NEXT: v_xor_b32_e32 v5, 0x8000, v1854; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v3855; GFX7-NEXT: v_xor_b32_e32 v4, 0x8000, v0856; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc857; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v2858; GFX7-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc859; GFX7-NEXT: v_lshlrev_b32_e32 v3, 16, v1860; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0861; GFX7-NEXT: v_or_b32_e32 v0, v0, v3862; GFX7-NEXT: v_and_b32_e32 v1, 0xffff, v1863; GFX7-NEXT: s_setpc_b64 s[30:31]864;865; GFX9-LABEL: select_fneg_xor_select_v2i16:866; GFX9: ; %bb.0:867; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)868; GFX9-NEXT: v_and_b32_e32 v1, 1, v1869; GFX9-NEXT: v_and_b32_e32 v3, 1, v3870; GFX9-NEXT: v_and_b32_e32 v0, 1, v0871; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v1872; GFX9-NEXT: v_xor_b32_e32 v1, 0x80008000, v4873; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v3874; GFX9-NEXT: v_cndmask_b32_sdwa v3, v1, v5, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1875; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0876; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v5, vcc877; GFX9-NEXT: s_mov_b32 s6, 0x5040100878; GFX9-NEXT: v_perm_b32 v1, v3, v0, s6879; GFX9-NEXT: v_and_b32_e32 v2, 1, v2880; GFX9-NEXT: v_xor_b32_e32 v1, 0x80008000, v1881; GFX9-NEXT: s_mov_b64 vcc, s[4:5]882; GFX9-NEXT: v_cndmask_b32_sdwa v3, v3, v1, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1883; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v2884; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc885; GFX9-NEXT: v_perm_b32 v0, v3, v0, s6886; GFX9-NEXT: s_setpc_b64 s[30:31]887;888; GFX11-TRUE16-LABEL: select_fneg_xor_select_v2i16:889; GFX11-TRUE16: ; %bb.0:890; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)891; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 1, v1.l892; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 1, v0.l893; GFX11-TRUE16-NEXT: v_xor_b32_e32 v1, 0x80008000, v4894; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)895; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.h896; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 1, v0.l897; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 1, v3.l898; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 1, v2.l899; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v1.h, v5.h, vcc_lo900; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)901; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v5.l, s0902; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.l903; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)904; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 1, v0.h905; GFX11-TRUE16-NEXT: v_xor_b32_e32 v2, 0x80008000, v1906; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)907; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v1.h, v2.h, vcc_lo908; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v2.l, s0909; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]910;911; GFX11-FAKE16-LABEL: select_fneg_xor_select_v2i16:912; GFX11-FAKE16: ; %bb.0:913; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)914; GFX11-FAKE16-NEXT: v_xor_b32_e32 v4, 0x80008000, v4915; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v5916; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 1, v3917; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)918; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v4919; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 1, v0920; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0921; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v4, v5, vcc_lo922; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 1, v1923; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)924; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1925; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v7, v6, vcc_lo926; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v3927; GFX11-FAKE16-NEXT: v_perm_b32 v4, v1, v0, 0x5040100928; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)929; GFX11-FAKE16-NEXT: v_xor_b32_e32 v4, 0x80008000, v4930; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v4931; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)932; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v1, v5 :: v_dual_and_b32 v2, 1, v2933; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v2934; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc_lo935; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)936; GFX11-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100937; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]938 %fneg0 = xor <2 x i16> %arg0, <i16 -32768, i16 -32768>939 %select0 = select <2 x i1> %cond0, <2 x i16> %arg1, <2 x i16> %fneg0940 %fneg1 = xor <2 x i16> %select0, <i16 -32768, i16 -32768>941 %select1 = select <2 x i1> %cond1, <2 x i16> %fneg1, <2 x i16> %select0942 ret <2 x i16> %select1943}944 945; pattern that appeared in rocm-device-libs to manually operate on the946; sign bit of the high half of a double947define double @cospiD_pattern0(i32 %arg, double %arg1, double %arg2) {948; GCN-LABEL: cospiD_pattern0:949; GCN: ; %bb.0:950; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)951; GCN-NEXT: v_and_b32_e32 v5, 1, v0952; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v5953; GCN-NEXT: v_cndmask_b32_e32 v3, v1, v3, vcc954; GCN-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc955; GCN-NEXT: v_bfrev_b32_e32 v2, 1956; GCN-NEXT: v_cmp_lt_i32_e32 vcc, 1, v0957; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc958; GCN-NEXT: v_xor_b32_e32 v1, v1, v0959; GCN-NEXT: v_mov_b32_e32 v0, v3960; GCN-NEXT: s_setpc_b64 s[30:31]961;962; GFX11-LABEL: cospiD_pattern0:963; GFX11: ; %bb.0:964; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)965; GFX11-NEXT: v_and_b32_e32 v5, 1, v0966; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)967; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v5968; GFX11-NEXT: v_cndmask_b32_e32 v3, v1, v3, vcc_lo969; GFX11-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc_lo970; GFX11-NEXT: v_cmp_lt_i32_e32 vcc_lo, 1, v0971; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 0x80000000, vcc_lo972; GFX11-NEXT: v_xor_b32_e32 v1, v1, v0973; GFX11-NEXT: v_mov_b32_e32 v0, v3974; GFX11-NEXT: s_setpc_b64 s[30:31]975 %i = and i32 %arg, 1976 %i3 = icmp eq i32 %i, 0977 %i4 = select i1 %i3, double %arg2, double %arg1978 %i5 = bitcast double %i4 to <2 x i32>979 %i6 = icmp sgt i32 %arg, 1980 %i7 = select i1 %i6, i32 -2147483648, i32 0981 %i8 = extractelement <2 x i32> %i5, i64 1982 %i9 = xor i32 %i8, %i7983 %i10 = insertelement <2 x i32> %i5, i32 %i9, i64 1984 %i11 = bitcast <2 x i32> %i10 to double985 ret double %i11986}987 988define double @cospiD_pattern1(i32 %arg, double %arg1, double %arg2) {989; GCN-LABEL: cospiD_pattern1:990; GCN: ; %bb.0:991; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)992; GCN-NEXT: v_and_b32_e32 v5, 1, v0993; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v5994; GCN-NEXT: v_cndmask_b32_e32 v3, v1, v3, vcc995; GCN-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc996; GCN-NEXT: v_xor_b32_e32 v2, 0x80000000, v1997; GCN-NEXT: v_cmp_lt_i32_e32 vcc, 1, v0998; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc999; GCN-NEXT: v_mov_b32_e32 v0, v31000; GCN-NEXT: s_setpc_b64 s[30:31]1001;1002; GFX11-LABEL: cospiD_pattern1:1003; GFX11: ; %bb.0:1004; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1005; GFX11-NEXT: v_and_b32_e32 v5, 1, v01006; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)1007; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v51008; GFX11-NEXT: v_cndmask_b32_e32 v3, v1, v3, vcc_lo1009; GFX11-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc_lo1010; GFX11-NEXT: v_cmp_lt_i32_e32 vcc_lo, 1, v01011; GFX11-NEXT: v_mov_b32_e32 v0, v31012; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)1013; GFX11-NEXT: v_xor_b32_e32 v2, 0x80000000, v11014; GFX11-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo1015; GFX11-NEXT: s_setpc_b64 s[30:31]1016 %i = and i32 %arg, 11017 %i3 = icmp eq i32 %i, 01018 %i4 = select i1 %i3, double %arg2, double %arg11019 %i5 = icmp sgt i32 %arg, 11020 %i6 = fneg double %i41021 %i7 = select i1 %i5, double %i6, double %i41022 ret double %i71023}1024 1025; artifical example, scaled to operation on 16-bit halves of a float.1026define float @cospiD_pattern0_half(i16 %arg, float %arg1, float %arg2) {1027; GFX7-LABEL: cospiD_pattern0_half:1028; GFX7: ; %bb.0:1029; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1030; GFX7-NEXT: v_bfe_i32 v3, v0, 0, 161031; GFX7-NEXT: v_and_b32_e32 v0, 1, v01032; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 0, v01033; GFX7-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc1034; GFX7-NEXT: v_mov_b32_e32 v2, 0xffff80001035; GFX7-NEXT: v_cmp_lt_i32_e32 vcc, 1, v31036; GFX7-NEXT: v_and_b32_e32 v1, 0xffff, v01037; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v01038; GFX7-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc1039; GFX7-NEXT: v_xor_b32_e32 v0, v0, v21040; GFX7-NEXT: v_lshlrev_b32_e32 v0, 16, v01041; GFX7-NEXT: v_or_b32_e32 v0, v1, v01042; GFX7-NEXT: s_setpc_b64 s[30:31]1043;1044; GFX9-LABEL: cospiD_pattern0_half:1045; GFX9: ; %bb.0:1046; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1047; GFX9-NEXT: v_and_b32_e32 v3, 1, v01048; GFX9-NEXT: v_cmp_eq_u16_e32 vcc, 0, v31049; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc1050; GFX9-NEXT: v_mov_b32_e32 v2, 0xffff80001051; GFX9-NEXT: v_cmp_lt_i16_e32 vcc, 1, v01052; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc1053; GFX9-NEXT: v_xor_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1054; GFX9-NEXT: s_mov_b32 s4, 0x50401001055; GFX9-NEXT: v_perm_b32 v0, v0, v1, s41056; GFX9-NEXT: s_setpc_b64 s[30:31]1057;1058; GFX11-TRUE16-LABEL: cospiD_pattern0_half:1059; GFX11-TRUE16: ; %bb.0:1060; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1061; GFX11-TRUE16-NEXT: v_and_b16 v0.h, v0.l, 11062; GFX11-TRUE16-NEXT: v_cmp_lt_i16_e32 vcc_lo, 1, v0.l1063; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)1064; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v0.h1065; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, v1, v2, s01066; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, 0, 0x8000, vcc_lo1067; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)1068; GFX11-TRUE16-NEXT: v_xor_b16 v0.h, v0.h, v1.l1069; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]1070;1071; GFX11-FAKE16-LABEL: cospiD_pattern0_half:1072; GFX11-FAKE16: ; %bb.0:1073; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1074; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 1, v01075; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)1076; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v31077; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo1078; GFX11-FAKE16-NEXT: v_cmp_lt_i16_e32 vcc_lo, 1, v01079; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v11080; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 0xffff8000, vcc_lo1081; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1082; GFX11-FAKE16-NEXT: v_xor_b32_e32 v0, v2, v01083; GFX11-FAKE16-NEXT: v_perm_b32 v0, v0, v1, 0x50401001084; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]1085 %i = and i16 %arg, 11086 %i3 = icmp eq i16 %i, 01087 %i4 = select i1 %i3, float %arg2, float %arg11088 %i5 = bitcast float %i4 to <2 x i16>1089 %i6 = icmp sgt i16 %arg, 11090 %i7 = select i1 %i6, i16 -32768, i16 01091 %i8 = extractelement <2 x i16> %i5, i64 11092 %i9 = xor i16 %i8, %i71093 %i10 = insertelement <2 x i16> %i5, i16 %i9, i64 11094 %i11 = bitcast <2 x i16> %i10 to float1095 ret float %i111096}1097 1098define float @cospiD_pattern1_half(i16 %arg, float %arg1, float %arg2) {1099; GFX7-LABEL: cospiD_pattern1_half:1100; GFX7: ; %bb.0:1101; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1102; GFX7-NEXT: v_bfe_i32 v3, v0, 0, 161103; GFX7-NEXT: v_and_b32_e32 v0, 1, v01104; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 0, v01105; GFX7-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc1106; GFX7-NEXT: v_cmp_lt_i32_e32 vcc, 1, v31107; GFX7-NEXT: v_cndmask_b32_e64 v0, v0, -v0, vcc1108; GFX7-NEXT: s_setpc_b64 s[30:31]1109;1110; GFX9-LABEL: cospiD_pattern1_half:1111; GFX9: ; %bb.0:1112; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1113; GFX9-NEXT: v_and_b32_e32 v3, 1, v01114; GFX9-NEXT: v_cmp_eq_u16_e32 vcc, 0, v31115; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc1116; GFX9-NEXT: v_cmp_lt_i16_e32 vcc, 1, v01117; GFX9-NEXT: v_cndmask_b32_e64 v0, v1, -v1, vcc1118; GFX9-NEXT: s_setpc_b64 s[30:31]1119;1120; GFX11-TRUE16-LABEL: cospiD_pattern1_half:1121; GFX11-TRUE16: ; %bb.0:1122; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1123; GFX11-TRUE16-NEXT: v_and_b16 v0.h, v0.l, 11124; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)1125; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0.h1126; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo1127; GFX11-TRUE16-NEXT: v_cmp_lt_i16_e32 vcc_lo, 1, v0.l1128; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, v1, -v1, vcc_lo1129; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]1130;1131; GFX11-FAKE16-LABEL: cospiD_pattern1_half:1132; GFX11-FAKE16: ; %bb.0:1133; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1134; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 1, v01135; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)1136; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v31137; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo1138; GFX11-FAKE16-NEXT: v_cmp_lt_i16_e32 vcc_lo, 1, v01139; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, v1, -v1, vcc_lo1140; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]1141 %i = and i16 %arg, 11142 %i3 = icmp eq i16 %i, 01143 %i4 = select i1 %i3, float %arg2, float %arg11144 %i5 = icmp sgt i16 %arg, 11145 %i6 = fneg float %i41146 %i7 = select i1 %i5, float %i6, float %i41147 ret float %i71148}1149 1150define double @fneg_f64_bitcast_vector_i64_to_f64(i64 %arg) {1151; GCN-LABEL: fneg_f64_bitcast_vector_i64_to_f64:1152; GCN: ; %bb.0:1153; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1154; GCN-NEXT: v_xor_b32_e32 v1, 0x80000000, v11155; GCN-NEXT: s_setpc_b64 s[30:31]1156;1157; GFX11-LABEL: fneg_f64_bitcast_vector_i64_to_f64:1158; GFX11: ; %bb.0:1159; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1160; GFX11-NEXT: v_xor_b32_e32 v1, 0x80000000, v11161; GFX11-NEXT: s_setpc_b64 s[30:31]1162 %bitcast = bitcast i64 %arg to double1163 %fneg = fneg double %bitcast1164 ret double %fneg1165}1166 1167define double @fneg_f64_bitcast_vector_v2i32_to_f64(<2 x i32> %arg) {1168; GCN-LABEL: fneg_f64_bitcast_vector_v2i32_to_f64:1169; GCN: ; %bb.0:1170; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1171; GCN-NEXT: v_xor_b32_e32 v1, 0x80000000, v11172; GCN-NEXT: s_setpc_b64 s[30:31]1173;1174; GFX11-LABEL: fneg_f64_bitcast_vector_v2i32_to_f64:1175; GFX11: ; %bb.0:1176; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1177; GFX11-NEXT: v_xor_b32_e32 v1, 0x80000000, v11178; GFX11-NEXT: s_setpc_b64 s[30:31]1179 %bitcast = bitcast <2 x i32> %arg to double1180 %fneg = fneg double %bitcast1181 ret double %fneg1182}1183 1184define double @fneg_f64_bitcast_vector_v2f32_to_f64(<2 x float> %arg) {1185; GCN-LABEL: fneg_f64_bitcast_vector_v2f32_to_f64:1186; GCN: ; %bb.0:1187; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1188; GCN-NEXT: v_xor_b32_e32 v1, 0x80000000, v11189; GCN-NEXT: s_setpc_b64 s[30:31]1190;1191; GFX11-LABEL: fneg_f64_bitcast_vector_v2f32_to_f64:1192; GFX11: ; %bb.0:1193; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1194; GFX11-NEXT: v_xor_b32_e32 v1, 0x80000000, v11195; GFX11-NEXT: s_setpc_b64 s[30:31]1196 %bitcast = bitcast <2 x float> %arg to double1197 %fneg = fneg double %bitcast1198 ret double %fneg1199}1200 1201define double @fneg_f64_bitcast_vector_v4i16_to_f64(<4 x i16> %arg) {1202; GFX7-LABEL: fneg_f64_bitcast_vector_v4i16_to_f64:1203; GFX7: ; %bb.0:1204; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1205; GFX7-NEXT: v_lshlrev_b32_e32 v3, 16, v31206; GFX7-NEXT: v_and_b32_e32 v2, 0xffff, v21207; GFX7-NEXT: v_or_b32_e32 v2, v2, v31208; GFX7-NEXT: v_lshlrev_b32_e32 v1, 16, v11209; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v01210; GFX7-NEXT: v_or_b32_e32 v0, v0, v11211; GFX7-NEXT: v_xor_b32_e32 v1, 0x80000000, v21212; GFX7-NEXT: s_setpc_b64 s[30:31]1213;1214; GFX9-LABEL: fneg_f64_bitcast_vector_v4i16_to_f64:1215; GFX9: ; %bb.0:1216; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1217; GFX9-NEXT: v_xor_b32_e32 v1, 0x80000000, v11218; GFX9-NEXT: s_setpc_b64 s[30:31]1219;1220; GFX11-LABEL: fneg_f64_bitcast_vector_v4i16_to_f64:1221; GFX11: ; %bb.0:1222; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1223; GFX11-NEXT: v_xor_b32_e32 v1, 0x80000000, v11224; GFX11-NEXT: s_setpc_b64 s[30:31]1225 %bitcast = bitcast <4 x i16> %arg to double1226 %fneg = fneg double %bitcast1227 ret double %fneg1228}1229 1230define double @fneg_f64_bitcast_vector_v4f16_to_f64(<4 x half> %arg) {1231; GFX7-LABEL: fneg_f64_bitcast_vector_v4f16_to_f64:1232; GFX7: ; %bb.0:1233; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1234; GFX7-NEXT: v_cvt_f16_f32_e32 v3, v31235; GFX7-NEXT: v_cvt_f16_f32_e32 v2, v21236; GFX7-NEXT: v_cvt_f16_f32_e32 v1, v11237; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v01238; GFX7-NEXT: v_lshlrev_b32_e32 v3, 16, v31239; GFX7-NEXT: v_or_b32_e32 v2, v2, v31240; GFX7-NEXT: v_lshlrev_b32_e32 v1, 16, v11241; GFX7-NEXT: v_or_b32_e32 v0, v0, v11242; GFX7-NEXT: v_xor_b32_e32 v1, 0x80000000, v21243; GFX7-NEXT: s_setpc_b64 s[30:31]1244;1245; GFX9-LABEL: fneg_f64_bitcast_vector_v4f16_to_f64:1246; GFX9: ; %bb.0:1247; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1248; GFX9-NEXT: v_xor_b32_e32 v1, 0x80000000, v11249; GFX9-NEXT: s_setpc_b64 s[30:31]1250;1251; GFX11-LABEL: fneg_f64_bitcast_vector_v4f16_to_f64:1252; GFX11: ; %bb.0:1253; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1254; GFX11-NEXT: v_xor_b32_e32 v1, 0x80000000, v11255; GFX11-NEXT: s_setpc_b64 s[30:31]1256 %bitcast = bitcast <4 x half> %arg to double1257 %fneg = fneg double %bitcast1258 ret double %fneg1259}1260 1261define double @fneg_f64_bitcast_build_vector_v2i32_to_f64(i32 %elt0, i32 %elt1) {1262; GCN-LABEL: fneg_f64_bitcast_build_vector_v2i32_to_f64:1263; GCN: ; %bb.0:1264; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1265; GCN-NEXT: v_xor_b32_e32 v1, 0x80000000, v11266; GCN-NEXT: s_setpc_b64 s[30:31]1267;1268; GFX11-LABEL: fneg_f64_bitcast_build_vector_v2i32_to_f64:1269; GFX11: ; %bb.0:1270; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1271; GFX11-NEXT: v_xor_b32_e32 v1, 0x80000000, v11272; GFX11-NEXT: s_setpc_b64 s[30:31]1273 %insert.0 = insertelement <2 x i32> poison, i32 %elt0, i32 01274 %insert.1 = insertelement <2 x i32> %insert.0, i32 %elt1, i32 11275 %bitcast = bitcast <2 x i32> %insert.1 to double1276 %fneg = fneg double %bitcast1277 ret double %fneg1278}1279 1280define double @fneg_f64_bitcast_build_vector_v2f32_to_f64(float %elt0, float %elt1) {1281; GCN-LABEL: fneg_f64_bitcast_build_vector_v2f32_to_f64:1282; GCN: ; %bb.0:1283; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1284; GCN-NEXT: v_xor_b32_e32 v1, 0x80000000, v11285; GCN-NEXT: s_setpc_b64 s[30:31]1286;1287; GFX11-LABEL: fneg_f64_bitcast_build_vector_v2f32_to_f64:1288; GFX11: ; %bb.0:1289; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1290; GFX11-NEXT: v_xor_b32_e32 v1, 0x80000000, v11291; GFX11-NEXT: s_setpc_b64 s[30:31]1292 %insert.0 = insertelement <2 x float> poison, float %elt0, i32 01293 %insert.1 = insertelement <2 x float> %insert.0, float %elt1, i32 11294 %bitcast = bitcast <2 x float> %insert.1 to double1295 %fneg = fneg double %bitcast1296 ret double %fneg1297}1298 1299define double @fneg_f64_bitcast_build_vector_v4i16_to_f64(i16 %elt0, i16 %elt1, i16 %elt2, i16 %elt3) {1300; GFX7-LABEL: fneg_f64_bitcast_build_vector_v4i16_to_f64:1301; GFX7: ; %bb.0:1302; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1303; GFX7-NEXT: v_lshlrev_b32_e32 v3, 16, v31304; GFX7-NEXT: v_and_b32_e32 v2, 0xffff, v21305; GFX7-NEXT: v_or_b32_e32 v2, v2, v31306; GFX7-NEXT: v_lshlrev_b32_e32 v1, 16, v11307; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v01308; GFX7-NEXT: v_or_b32_e32 v0, v0, v11309; GFX7-NEXT: v_xor_b32_e32 v1, 0x80000000, v21310; GFX7-NEXT: s_setpc_b64 s[30:31]1311;1312; GFX9-LABEL: fneg_f64_bitcast_build_vector_v4i16_to_f64:1313; GFX9: ; %bb.0:1314; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1315; GFX9-NEXT: s_mov_b32 s4, 0x50401001316; GFX9-NEXT: v_perm_b32 v2, v3, v2, s41317; GFX9-NEXT: v_perm_b32 v0, v1, v0, s41318; GFX9-NEXT: v_xor_b32_e32 v1, 0x80000000, v21319; GFX9-NEXT: s_setpc_b64 s[30:31]1320;1321; GFX11-TRUE16-LABEL: fneg_f64_bitcast_build_vector_v4i16_to_f64:1322; GFX11-TRUE16: ; %bb.0:1323; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1324; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v3.l1325; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l1326; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)1327; GFX11-TRUE16-NEXT: v_xor_b32_e32 v1, 0x80000000, v21328; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]1329;1330; GFX11-FAKE16-LABEL: fneg_f64_bitcast_build_vector_v4i16_to_f64:1331; GFX11-FAKE16: ; %bb.0:1332; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1333; GFX11-FAKE16-NEXT: v_perm_b32 v2, v3, v2, 0x50401001334; GFX11-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x50401001335; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)1336; GFX11-FAKE16-NEXT: v_xor_b32_e32 v1, 0x80000000, v21337; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]1338 %insert.0 = insertelement <4 x i16> poison, i16 %elt0, i32 01339 %insert.1 = insertelement <4 x i16> %insert.0, i16 %elt1, i32 11340 %insert.2 = insertelement <4 x i16> %insert.1, i16 %elt2, i32 21341 %insert.3 = insertelement <4 x i16> %insert.2, i16 %elt3, i32 31342 %bitcast = bitcast <4 x i16> %insert.3 to double1343 %fneg = fneg double %bitcast1344 ret double %fneg1345}1346 1347define double @fneg_f64_bitcast_build_vector_v4f16_to_f64(half %elt0, half %elt1, half %elt2, half %elt3) {1348; GFX7-LABEL: fneg_f64_bitcast_build_vector_v4f16_to_f64:1349; GFX7: ; %bb.0:1350; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1351; GFX7-NEXT: v_cvt_f16_f32_e32 v3, v31352; GFX7-NEXT: v_cvt_f16_f32_e32 v2, v21353; GFX7-NEXT: v_cvt_f16_f32_e32 v1, v11354; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v01355; GFX7-NEXT: v_lshlrev_b32_e32 v3, 16, v31356; GFX7-NEXT: v_or_b32_e32 v2, v2, v31357; GFX7-NEXT: v_lshlrev_b32_e32 v1, 16, v11358; GFX7-NEXT: v_or_b32_e32 v0, v0, v11359; GFX7-NEXT: v_xor_b32_e32 v1, 0x80000000, v21360; GFX7-NEXT: s_setpc_b64 s[30:31]1361;1362; GFX9-LABEL: fneg_f64_bitcast_build_vector_v4f16_to_f64:1363; GFX9: ; %bb.0:1364; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1365; GFX9-NEXT: s_mov_b32 s4, 0x50401001366; GFX9-NEXT: v_perm_b32 v2, v3, v2, s41367; GFX9-NEXT: v_perm_b32 v0, v1, v0, s41368; GFX9-NEXT: v_xor_b32_e32 v1, 0x80000000, v21369; GFX9-NEXT: s_setpc_b64 s[30:31]1370;1371; GFX11-TRUE16-LABEL: fneg_f64_bitcast_build_vector_v4f16_to_f64:1372; GFX11-TRUE16: ; %bb.0:1373; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1374; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v3.l1375; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l1376; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)1377; GFX11-TRUE16-NEXT: v_xor_b32_e32 v1, 0x80000000, v21378; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]1379;1380; GFX11-FAKE16-LABEL: fneg_f64_bitcast_build_vector_v4f16_to_f64:1381; GFX11-FAKE16: ; %bb.0:1382; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1383; GFX11-FAKE16-NEXT: v_perm_b32 v2, v3, v2, 0x50401001384; GFX11-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x50401001385; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)1386; GFX11-FAKE16-NEXT: v_xor_b32_e32 v1, 0x80000000, v21387; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]1388 %insert.0 = insertelement <4 x half> poison, half %elt0, i32 01389 %insert.1 = insertelement <4 x half> %insert.0, half %elt1, i32 11390 %insert.2 = insertelement <4 x half> %insert.1, half %elt2, i32 21391 %insert.3 = insertelement <4 x half> %insert.2, half %elt3, i32 31392 %bitcast = bitcast <4 x half> %insert.3 to double1393 %fneg = fneg double %bitcast1394 ret double %fneg1395}1396 1397define double @fneg_f64_bitcast_build_vector_v4bf16_to_f64(bfloat %elt0, bfloat %elt1, bfloat %elt2, bfloat %elt3) {1398; GFX7-LABEL: fneg_f64_bitcast_build_vector_v4bf16_to_f64:1399; GFX7: ; %bb.0:1400; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1401; GFX7-NEXT: v_mul_f32_e32 v3, 1.0, v31402; GFX7-NEXT: v_mul_f32_e32 v1, 1.0, v11403; GFX7-NEXT: v_lshrrev_b32_e32 v3, 16, v31404; GFX7-NEXT: v_mul_f32_e32 v2, 1.0, v21405; GFX7-NEXT: v_lshrrev_b32_e32 v1, 16, v11406; GFX7-NEXT: v_mul_f32_e32 v0, 1.0, v01407; GFX7-NEXT: v_alignbit_b32 v2, v3, v2, 161408; GFX7-NEXT: v_alignbit_b32 v0, v1, v0, 161409; GFX7-NEXT: v_xor_b32_e32 v1, 0x80000000, v21410; GFX7-NEXT: s_setpc_b64 s[30:31]1411;1412; GFX9-LABEL: fneg_f64_bitcast_build_vector_v4bf16_to_f64:1413; GFX9: ; %bb.0:1414; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1415; GFX9-NEXT: s_mov_b32 s4, 0x50401001416; GFX9-NEXT: v_perm_b32 v2, v3, v2, s41417; GFX9-NEXT: v_perm_b32 v0, v1, v0, s41418; GFX9-NEXT: v_xor_b32_e32 v1, 0x80000000, v21419; GFX9-NEXT: s_setpc_b64 s[30:31]1420;1421; GFX11-TRUE16-LABEL: fneg_f64_bitcast_build_vector_v4bf16_to_f64:1422; GFX11-TRUE16: ; %bb.0:1423; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1424; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v3.l1425; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l1426; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)1427; GFX11-TRUE16-NEXT: v_xor_b32_e32 v1, 0x80000000, v21428; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]1429;1430; GFX11-FAKE16-LABEL: fneg_f64_bitcast_build_vector_v4bf16_to_f64:1431; GFX11-FAKE16: ; %bb.0:1432; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1433; GFX11-FAKE16-NEXT: v_perm_b32 v2, v3, v2, 0x50401001434; GFX11-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x50401001435; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)1436; GFX11-FAKE16-NEXT: v_xor_b32_e32 v1, 0x80000000, v21437; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]1438 %insert.0 = insertelement <4 x bfloat> poison, bfloat %elt0, i32 01439 %insert.1 = insertelement <4 x bfloat> %insert.0, bfloat %elt1, i32 11440 %insert.2 = insertelement <4 x bfloat> %insert.1, bfloat %elt2, i32 21441 %insert.3 = insertelement <4 x bfloat> %insert.2, bfloat %elt3, i32 31442 %bitcast = bitcast <4 x bfloat> %insert.3 to double1443 %fneg = fneg double %bitcast1444 ret double %fneg1445}1446 1447define double @fneg_f64_bitcast_build_vector_v2i32_to_f64_modifier_user(i32 %elt0, i32 %elt1, double %fp.val) {1448; GCN-LABEL: fneg_f64_bitcast_build_vector_v2i32_to_f64_modifier_user:1449; GCN: ; %bb.0:1450; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1451; GCN-NEXT: v_mul_f64 v[0:1], -v[0:1], v[2:3]1452; GCN-NEXT: s_setpc_b64 s[30:31]1453;1454; GFX11-LABEL: fneg_f64_bitcast_build_vector_v2i32_to_f64_modifier_user:1455; GFX11: ; %bb.0:1456; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1457; GFX11-NEXT: v_mul_f64 v[0:1], -v[0:1], v[2:3]1458; GFX11-NEXT: s_setpc_b64 s[30:31]1459 %insert.0 = insertelement <2 x i32> poison, i32 %elt0, i32 01460 %insert.1 = insertelement <2 x i32> %insert.0, i32 %elt1, i32 11461 %bitcast = bitcast <2 x i32> %insert.1 to double1462 %fneg = fneg double %bitcast1463 %fmul = fmul double %fneg, %fp.val1464 ret double %fmul1465}1466 1467define { double, double } @fneg_f64_bitcast_build_vector_v2i32_to_f64_multi_modifier_user(i32 %elt0, i32 %elt1, double %fp.val0, double %fp.val1) {1468; GCN-LABEL: fneg_f64_bitcast_build_vector_v2i32_to_f64_multi_modifier_user:1469; GCN: ; %bb.0:1470; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1471; GCN-NEXT: v_mul_f64 v[6:7], -v[0:1], v[2:3]1472; GCN-NEXT: v_mul_f64 v[2:3], v[4:5], -v[0:1]1473; GCN-NEXT: v_mov_b32_e32 v0, v61474; GCN-NEXT: v_mov_b32_e32 v1, v71475; GCN-NEXT: s_setpc_b64 s[30:31]1476;1477; GFX11-LABEL: fneg_f64_bitcast_build_vector_v2i32_to_f64_multi_modifier_user:1478; GFX11: ; %bb.0:1479; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1480; GFX11-NEXT: v_mul_f64 v[6:7], -v[0:1], v[2:3]1481; GFX11-NEXT: v_mul_f64 v[2:3], v[4:5], -v[0:1]1482; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)1483; GFX11-NEXT: v_dual_mov_b32 v0, v6 :: v_dual_mov_b32 v1, v71484; GFX11-NEXT: s_setpc_b64 s[30:31]1485 %insert.0 = insertelement <2 x i32> poison, i32 %elt0, i32 01486 %insert.1 = insertelement <2 x i32> %insert.0, i32 %elt1, i32 11487 %bitcast = bitcast <2 x i32> %insert.1 to double1488 %fneg = fneg double %bitcast1489 %fmul0 = fmul double %fneg, %fp.val01490 %fmul1 = fmul double %fp.val1, %fneg1491 %ret.0 = insertvalue { double, double } poison, double %fmul0, 01492 %ret.1 = insertvalue { double, double } %ret.0, double %fmul1, 11493 ret { double, double } %ret.11494}1495 1496define double @fneg_f64_bitcast_build_vector_v2i32_to_f64_modifier_user_integer_neg_source(i32 %elt0, i32 %elt1, double %fp.val) {1497; GCN-LABEL: fneg_f64_bitcast_build_vector_v2i32_to_f64_modifier_user_integer_neg_source:1498; GCN: ; %bb.0:1499; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1500; GCN-NEXT: v_xor_b32_e32 v1, 0x80000000, v11501; GCN-NEXT: v_mul_f64 v[0:1], -v[0:1], v[2:3]1502; GCN-NEXT: s_setpc_b64 s[30:31]1503;1504; GFX11-LABEL: fneg_f64_bitcast_build_vector_v2i32_to_f64_modifier_user_integer_neg_source:1505; GFX11: ; %bb.0:1506; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1507; GFX11-NEXT: v_xor_b32_e32 v1, 0x80000000, v11508; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)1509; GFX11-NEXT: v_mul_f64 v[0:1], -v[0:1], v[2:3]1510; GFX11-NEXT: s_setpc_b64 s[30:31]1511 %neg.elt1 = xor i32 %elt1, -21474836481512 %insert.0 = insertelement <2 x i32> poison, i32 %elt0, i32 01513 %insert.1 = insertelement <2 x i32> %insert.0, i32 %neg.elt1, i32 11514 %bitcast = bitcast <2 x i32> %insert.1 to double1515 %fneg = fneg double %bitcast1516 %fmul = fmul double %fneg, %fp.val1517 ret double %fmul1518}1519 1520define double @fneg_f64_bitcast_build_vector_v2f32_foldable_sources_to_f64(float %elt0, float %elt1) {1521; GCN-LABEL: fneg_f64_bitcast_build_vector_v2f32_foldable_sources_to_f64:1522; GCN: ; %bb.0:1523; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1524; GCN-NEXT: v_sub_f32_e32 v1, -2.0, v11525; GCN-NEXT: s_setpc_b64 s[30:31]1526;1527; GFX11-LABEL: fneg_f64_bitcast_build_vector_v2f32_foldable_sources_to_f64:1528; GFX11: ; %bb.0:1529; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1530; GFX11-NEXT: v_sub_f32_e32 v1, -2.0, v11531; GFX11-NEXT: s_setpc_b64 s[30:31]1532 %fadd = fadd nsz nnan float %elt1, 2.01533 %insert.0 = insertelement <2 x float> poison, float %elt0, i32 01534 %insert.1 = insertelement <2 x float> %insert.0, float %fadd, i32 11535 %bitcast = bitcast <2 x float> %insert.1 to double1536 %fneg = fneg double %bitcast1537 ret double %fneg1538}1539 1540define double @fneg_f64_bitcast_build_vector_v2f32_to_f64_bitcast_source_user(float %elt0, float %elt1, ptr addrspace(1) %ptr) {1541; GFX7-LABEL: fneg_f64_bitcast_build_vector_v2f32_to_f64_bitcast_source_user:1542; GFX7: ; %bb.0:1543; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1544; GFX7-NEXT: flat_store_dwordx2 v[2:3], v[0:1]1545; GFX7-NEXT: v_xor_b32_e32 v1, 0x80000000, v11546; GFX7-NEXT: s_waitcnt vmcnt(0)1547; GFX7-NEXT: s_setpc_b64 s[30:31]1548;1549; GFX9-LABEL: fneg_f64_bitcast_build_vector_v2f32_to_f64_bitcast_source_user:1550; GFX9: ; %bb.0:1551; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1552; GFX9-NEXT: global_store_dwordx2 v[2:3], v[0:1], off1553; GFX9-NEXT: v_xor_b32_e32 v1, 0x80000000, v11554; GFX9-NEXT: s_waitcnt vmcnt(0)1555; GFX9-NEXT: s_setpc_b64 s[30:31]1556;1557; GFX11-LABEL: fneg_f64_bitcast_build_vector_v2f32_to_f64_bitcast_source_user:1558; GFX11: ; %bb.0:1559; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1560; GFX11-NEXT: v_xor_b32_e32 v4, 0x80000000, v11561; GFX11-NEXT: global_store_b64 v[2:3], v[0:1], off1562; GFX11-NEXT: v_mov_b32_e32 v1, v41563; GFX11-NEXT: s_setpc_b64 s[30:31]1564 %insert.0 = insertelement <2 x float> poison, float %elt0, i32 01565 %insert.1 = insertelement <2 x float> %insert.0, float %elt1, i32 11566 store <2 x float> %insert.1, ptr addrspace(1) %ptr1567 %bitcast = bitcast <2 x float> %insert.1 to double1568 %fneg = fneg double %bitcast1569 ret double %fneg1570}1571 1572define { double, <2 x float> } @fneg_f64_bitcast_build_vector_v2f32_to_f64_bitcast_source_foldable_user(float %elt0, float %elt1, <2 x float> %arg.v2f32) {1573; GCN-LABEL: fneg_f64_bitcast_build_vector_v2f32_to_f64_bitcast_source_foldable_user:1574; GCN: ; %bb.0:1575; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1576; GCN-NEXT: v_add_f32_e32 v2, v0, v21577; GCN-NEXT: v_add_f32_e32 v3, v1, v31578; GCN-NEXT: v_xor_b32_e32 v1, 0x80000000, v11579; GCN-NEXT: s_setpc_b64 s[30:31]1580;1581; GFX11-LABEL: fneg_f64_bitcast_build_vector_v2f32_to_f64_bitcast_source_foldable_user:1582; GFX11: ; %bb.0:1583; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1584; GFX11-NEXT: v_xor_b32_e32 v4, 0x80000000, v11585; GFX11-NEXT: v_dual_add_f32 v2, v0, v2 :: v_dual_add_f32 v3, v1, v31586; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)1587; GFX11-NEXT: v_mov_b32_e32 v1, v41588; GFX11-NEXT: s_setpc_b64 s[30:31]1589 %insert.0 = insertelement <2 x float> poison, float %elt0, i32 01590 %insert.1 = insertelement <2 x float> %insert.0, float %elt1, i32 11591 %other.bitcast.source.user = fadd <2 x float> %insert.1, %arg.v2f321592 %bitcast = bitcast <2 x float> %insert.1 to double1593 %fneg = fneg double %bitcast1594 %ret.0 = insertvalue { double, <2 x float> } poison, double %fneg, 01595 %ret.1 = insertvalue { double, <2 x float> } %ret.0, <2 x float> %other.bitcast.source.user, 11596 ret { double, <2 x float> } %ret.11597}1598 1599define { double, double } @fneg_f64_bitcast_build_vector_v2f32_to_f64_bitcast_user(float %elt0, float %elt1) {1600; GCN-LABEL: fneg_f64_bitcast_build_vector_v2f32_to_f64_bitcast_user:1601; GCN: ; %bb.0:1602; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1603; GCN-NEXT: v_mov_b32_e32 v3, v11604; GCN-NEXT: v_xor_b32_e32 v1, 0x80000000, v31605; GCN-NEXT: v_mov_b32_e32 v2, v01606; GCN-NEXT: s_setpc_b64 s[30:31]1607;1608; GFX11-LABEL: fneg_f64_bitcast_build_vector_v2f32_to_f64_bitcast_user:1609; GFX11: ; %bb.0:1610; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1611; GFX11-NEXT: v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v01612; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)1613; GFX11-NEXT: v_xor_b32_e32 v1, 0x80000000, v31614; GFX11-NEXT: s_setpc_b64 s[30:31]1615 %insert.0 = insertelement <2 x float> poison, float %elt0, i32 01616 %insert.1 = insertelement <2 x float> %insert.0, float %elt1, i32 11617 %bitcast = bitcast <2 x float> %insert.1 to double1618 %fneg = fneg double %bitcast1619 %ret.0 = insertvalue { double, double } poison, double %fneg, 01620 %ret.1 = insertvalue { double, double } %ret.0, double %bitcast, 11621 ret { double, double } %ret.11622}1623 1624define { double, double } @fneg_f64_bitcast_build_vector_v2f32_to_f64_bitcast_foldable_user(float %elt0, float %elt1, double %arg.f64) {1625; GCN-LABEL: fneg_f64_bitcast_build_vector_v2f32_to_f64_bitcast_foldable_user:1626; GCN: ; %bb.0:1627; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1628; GCN-NEXT: v_add_f64 v[2:3], v[0:1], v[2:3]1629; GCN-NEXT: v_xor_b32_e32 v1, 0x80000000, v11630; GCN-NEXT: s_setpc_b64 s[30:31]1631;1632; GFX11-LABEL: fneg_f64_bitcast_build_vector_v2f32_to_f64_bitcast_foldable_user:1633; GFX11: ; %bb.0:1634; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1635; GFX11-NEXT: v_add_f64 v[2:3], v[0:1], v[2:3]1636; GFX11-NEXT: v_xor_b32_e32 v1, 0x80000000, v11637; GFX11-NEXT: s_setpc_b64 s[30:31]1638 %insert.0 = insertelement <2 x float> poison, float %elt0, i32 01639 %insert.1 = insertelement <2 x float> %insert.0, float %elt1, i32 11640 %bitcast = bitcast <2 x float> %insert.1 to double1641 %other.bitcast.user = fadd double %bitcast, %arg.f641642 %fneg = fneg double %bitcast1643 %ret.0 = insertvalue { double, double } poison, double %fneg, 01644 %ret.1 = insertvalue { double, double } %ret.0, double %other.bitcast.user, 11645 ret { double, double } %ret.11646}1647 1648; Check for correct bitcasting back when there are multiple uses1649define amdgpu_kernel void @multiple_uses_fneg_select_f64(double %x, double %y, i1 %z, ptr addrspace(1) %dst) {1650; GFX7-LABEL: multiple_uses_fneg_select_f64:1651; GFX7: ; %bb.0:1652; GFX7-NEXT: s_load_dword s6, s[8:9], 0x41653; GFX7-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x01654; GFX7-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x61655; GFX7-NEXT: s_add_i32 s12, s12, s171656; GFX7-NEXT: s_lshr_b32 flat_scratch_hi, s12, 81657; GFX7-NEXT: s_waitcnt lgkmcnt(0)1658; GFX7-NEXT: s_bitcmp1_b32 s6, 01659; GFX7-NEXT: s_cselect_b64 vcc, -1, 01660; GFX7-NEXT: s_and_b64 s[6:7], vcc, exec1661; GFX7-NEXT: v_mov_b32_e32 v0, s31662; GFX7-NEXT: v_mov_b32_e32 v1, s11663; GFX7-NEXT: s_cselect_b32 s1, s1, s31664; GFX7-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc1665; GFX7-NEXT: s_cselect_b32 s0, s0, s21666; GFX7-NEXT: v_mov_b32_e32 v1, s11667; GFX7-NEXT: v_mov_b32_e32 v2, s41668; GFX7-NEXT: s_mov_b32 flat_scratch_lo, s131669; GFX7-NEXT: v_cndmask_b32_e64 v1, v1, -v0, vcc1670; GFX7-NEXT: v_mov_b32_e32 v0, s01671; GFX7-NEXT: v_mov_b32_e32 v3, s51672; GFX7-NEXT: flat_store_dwordx2 v[2:3], v[0:1]1673; GFX7-NEXT: s_endpgm1674;1675; GFX9-LABEL: multiple_uses_fneg_select_f64:1676; GFX9: ; %bb.0:1677; GFX9-NEXT: s_load_dword s6, s[8:9], 0x101678; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x01679; GFX9-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x181680; GFX9-NEXT: v_mov_b32_e32 v2, 01681; GFX9-NEXT: s_waitcnt lgkmcnt(0)1682; GFX9-NEXT: s_bitcmp1_b32 s6, 01683; GFX9-NEXT: s_cselect_b64 vcc, -1, 01684; GFX9-NEXT: s_and_b64 s[6:7], vcc, exec1685; GFX9-NEXT: v_mov_b32_e32 v0, s31686; GFX9-NEXT: v_mov_b32_e32 v1, s11687; GFX9-NEXT: s_cselect_b32 s1, s1, s31688; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc1689; GFX9-NEXT: s_cselect_b32 s0, s0, s21690; GFX9-NEXT: v_mov_b32_e32 v1, s11691; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, -v0, vcc1692; GFX9-NEXT: v_mov_b32_e32 v0, s01693; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[4:5]1694; GFX9-NEXT: s_endpgm1695;1696; GFX11-LABEL: multiple_uses_fneg_select_f64:1697; GFX11: ; %bb.0:1698; GFX11-NEXT: s_clause 0x21699; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x01700; GFX11-NEXT: s_load_b32 s6, s[4:5], 0x101701; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x181702; GFX11-NEXT: v_mov_b32_e32 v2, 01703; GFX11-NEXT: s_waitcnt lgkmcnt(0)1704; GFX11-NEXT: v_mov_b32_e32 v0, s11705; GFX11-NEXT: s_bitcmp1_b32 s6, 01706; GFX11-NEXT: s_cselect_b32 vcc_lo, -1, 01707; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)1708; GFX11-NEXT: v_cndmask_b32_e32 v0, s3, v0, vcc_lo1709; GFX11-NEXT: s_and_b32 s6, vcc_lo, exec_lo1710; GFX11-NEXT: s_cselect_b32 s1, s1, s31711; GFX11-NEXT: s_cselect_b32 s0, s0, s21712; GFX11-NEXT: v_cndmask_b32_e64 v1, s1, -v0, vcc_lo1713; GFX11-NEXT: v_mov_b32_e32 v0, s01714; GFX11-NEXT: global_store_b64 v2, v[0:1], s[4:5]1715; GFX11-NEXT: s_endpgm1716 %a = select i1 %z, double %x, double %y1717 %b = fneg double %a1718 %c = select i1 %z, double %a, double %b1719 %d = fneg double %c1720 store double %d, ptr addrspace(1) %dst1721 ret void1722}1723 1724define amdgpu_kernel void @fnge_select_f32_multi_use_regression(float %.i2369) {1725; GCN-LABEL: fnge_select_f32_multi_use_regression:1726; GCN: ; %bb.0: ; %.entry1727; GCN-NEXT: s_load_dword s0, s[8:9], 0x01728; GCN-NEXT: s_waitcnt lgkmcnt(0)1729; GCN-NEXT: v_cmp_nlt_f32_e64 s[0:1], s0, 01730; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]1731; GCN-NEXT: v_cmp_nge_f32_e32 vcc, 0, v01732; GCN-NEXT: v_cndmask_b32_e32 v1, 0, v0, vcc1733; GCN-NEXT: v_mul_f32_e64 v0, -v0, v11734; GCN-NEXT: v_cmp_le_f32_e32 vcc, 0, v01735; GCN-NEXT: s_and_b64 vcc, exec, vcc1736; GCN-NEXT: s_endpgm1737;1738; GFX11-LABEL: fnge_select_f32_multi_use_regression:1739; GFX11: ; %bb.0: ; %.entry1740; GFX11-NEXT: s_load_b32 s0, s[4:5], 0x01741; GFX11-NEXT: s_waitcnt lgkmcnt(0)1742; GFX11-NEXT: v_cmp_nlt_f32_e64 s0, s0, 01743; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1744; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s01745; GFX11-NEXT: v_cmp_nge_f32_e32 vcc_lo, 0, v01746; GFX11-NEXT: v_cndmask_b32_e32 v1, 0, v0, vcc_lo1747; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1748; GFX11-NEXT: v_mul_f32_e64 v0, -v0, v11749; GFX11-NEXT: v_cmp_le_f32_e32 vcc_lo, 0, v01750; GFX11-NEXT: s_and_b32 vcc_lo, exec_lo, vcc_lo1751; GFX11-NEXT: s_endpgm1752.entry:1753 %i = fcmp uge float %.i2369, 0.000000e+001754 %.i2379 = select i1 %i, i32 1, i32 01755 %.i0436 = bitcast i32 %.i2379 to float1756 %.i0440 = fneg float %.i04361757 %i1 = fcmp ugt float %.i0436, 0.000000e+001758 %.i2495 = select i1 %i1, i32 %.i2379, i32 01759 %.i0552 = bitcast i32 %.i2495 to float1760 %.i0592 = fmul float %.i0440, %.i05521761 %.i0721 = fcmp oge float %.i0592, 0.000000e+001762 br i1 %.i0721, label %bb5, label %bb1763 1764bb: ; preds = %.entry1765 %i2 = call <2 x i32> @llvm.amdgcn.s.buffer.load.v2i32(<4 x i32> zeroinitializer, i32 1, i32 0)1766 %i3 = shufflevector <2 x i32> %i2, <2 x i32> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>1767 %i4 = bitcast <4 x i32> %i3 to <4 x float>1768 %.i0753 = extractelement <4 x float> %i4, i64 01769 br label %bb51770 1771bb5: ; preds = %bb, %.entry1772 ret void1773}1774 1775 1776declare <2 x i32> @llvm.amdgcn.s.buffer.load.v2i32(<4 x i32>, i32, i32 immarg) #01777 1778attributes #0 = { nocallback nofree nosync nounwind willreturn memory(none) }1779