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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s3; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI %s4; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX11,GFX11-TRUE16 %s5; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX11,GFX11-FAKE16 %s6; RUN: not --crash llc -mtriple=r600 -mcpu=redwood < %s 2>&1 | FileCheck -check-prefix=R600-ERR %s7 8; R600-ERR: LLVM ERROR: unsupported library call operation9 10define amdgpu_kernel void @s_fneg_f32(ptr addrspace(1) %out, float %in) {11; SI-LABEL: s_fneg_f32:12; SI: ; %bb.0:13; SI-NEXT: s_load_dword s6, s[4:5], 0xb14; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x915; SI-NEXT: s_mov_b32 s3, 0xf00016; SI-NEXT: s_mov_b32 s2, -117; SI-NEXT: s_waitcnt lgkmcnt(0)18; SI-NEXT: s_xor_b32 s4, s6, 0x8000000019; SI-NEXT: v_mov_b32_e32 v0, s420; SI-NEXT: buffer_store_dword v0, off, s[0:3], 021; SI-NEXT: s_endpgm22;23; VI-LABEL: s_fneg_f32:24; VI: ; %bb.0:25; VI-NEXT: s_load_dword s2, s[4:5], 0x2c26; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2427; VI-NEXT: s_waitcnt lgkmcnt(0)28; VI-NEXT: s_xor_b32 s2, s2, 0x8000000029; VI-NEXT: v_mov_b32_e32 v0, s030; VI-NEXT: v_mov_b32_e32 v1, s131; VI-NEXT: v_mov_b32_e32 v2, s232; VI-NEXT: flat_store_dword v[0:1], v233; VI-NEXT: s_endpgm34;35; GFX11-LABEL: s_fneg_f32:36; GFX11: ; %bb.0:37; GFX11-NEXT: s_clause 0x138; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c39; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x2440; GFX11-NEXT: s_waitcnt lgkmcnt(0)41; GFX11-NEXT: s_xor_b32 s2, s2, 0x8000000042; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)43; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s244; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]45; GFX11-NEXT: s_endpgm46 %fneg = fsub float -0.000000e+00, %in47 store float %fneg, ptr addrspace(1) %out48 ret void49}50 51define amdgpu_kernel void @s_fneg_v2f32(ptr addrspace(1) nocapture %out, <2 x float> %in) {52; SI-LABEL: s_fneg_v2f32:53; SI: ; %bb.0:54; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x955; SI-NEXT: s_waitcnt lgkmcnt(0)56; SI-NEXT: s_mov_b64 s[4:5], s[2:3]57; SI-NEXT: s_xor_b32 s5, s5, 0x8000000058; SI-NEXT: s_xor_b32 s4, s4, 0x8000000059; SI-NEXT: s_mov_b32 s3, 0xf00060; SI-NEXT: s_mov_b32 s2, -161; SI-NEXT: v_mov_b32_e32 v0, s462; SI-NEXT: v_mov_b32_e32 v1, s563; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 064; SI-NEXT: s_endpgm65;66; VI-LABEL: s_fneg_v2f32:67; VI: ; %bb.0:68; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2469; VI-NEXT: s_waitcnt lgkmcnt(0)70; VI-NEXT: s_xor_b32 s3, s3, 0x8000000071; VI-NEXT: s_xor_b32 s2, s2, 0x8000000072; VI-NEXT: v_mov_b32_e32 v3, s173; VI-NEXT: v_mov_b32_e32 v0, s274; VI-NEXT: v_mov_b32_e32 v1, s375; VI-NEXT: v_mov_b32_e32 v2, s076; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]77; VI-NEXT: s_endpgm78;79; GFX11-LABEL: s_fneg_v2f32:80; GFX11: ; %bb.0:81; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x2482; GFX11-NEXT: s_waitcnt lgkmcnt(0)83; GFX11-NEXT: s_xor_b32 s2, s2, 0x8000000084; GFX11-NEXT: s_xor_b32 s3, s3, 0x8000000085; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)86; GFX11-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s387; GFX11-NEXT: v_mov_b32_e32 v0, s288; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]89; GFX11-NEXT: s_endpgm90 %fneg = fsub <2 x float> <float -0.000000e+00, float -0.000000e+00>, %in91 store <2 x float> %fneg, ptr addrspace(1) %out92 ret void93}94 95define amdgpu_kernel void @s_fneg_v4f32(ptr addrspace(1) nocapture %out, <4 x float> %in) {96; SI-LABEL: s_fneg_v4f32:97; SI: ; %bb.0:98; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xd99; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9100; SI-NEXT: s_mov_b32 s7, 0xf000101; SI-NEXT: s_mov_b32 s6, -1102; SI-NEXT: s_waitcnt lgkmcnt(0)103; SI-NEXT: s_xor_b32 s3, s3, 0x80000000104; SI-NEXT: s_xor_b32 s2, s2, 0x80000000105; SI-NEXT: s_xor_b32 s1, s1, 0x80000000106; SI-NEXT: s_xor_b32 s0, s0, 0x80000000107; SI-NEXT: v_mov_b32_e32 v0, s0108; SI-NEXT: v_mov_b32_e32 v1, s1109; SI-NEXT: v_mov_b32_e32 v2, s2110; SI-NEXT: v_mov_b32_e32 v3, s3111; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0112; SI-NEXT: s_endpgm113;114; VI-LABEL: s_fneg_v4f32:115; VI: ; %bb.0:116; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34117; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24118; VI-NEXT: s_waitcnt lgkmcnt(0)119; VI-NEXT: s_xor_b32 s3, s3, 0x80000000120; VI-NEXT: s_xor_b32 s2, s2, 0x80000000121; VI-NEXT: s_xor_b32 s1, s1, 0x80000000122; VI-NEXT: s_xor_b32 s0, s0, 0x80000000123; VI-NEXT: v_mov_b32_e32 v4, s4124; VI-NEXT: v_mov_b32_e32 v0, s0125; VI-NEXT: v_mov_b32_e32 v1, s1126; VI-NEXT: v_mov_b32_e32 v2, s2127; VI-NEXT: v_mov_b32_e32 v3, s3128; VI-NEXT: v_mov_b32_e32 v5, s5129; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]130; VI-NEXT: s_endpgm131;132; GFX11-LABEL: s_fneg_v4f32:133; GFX11: ; %bb.0:134; GFX11-NEXT: s_clause 0x1135; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x34136; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x24137; GFX11-NEXT: s_waitcnt lgkmcnt(0)138; GFX11-NEXT: s_xor_b32 s3, s3, 0x80000000139; GFX11-NEXT: s_xor_b32 s2, s2, 0x80000000140; GFX11-NEXT: s_xor_b32 s0, s0, 0x80000000141; GFX11-NEXT: s_xor_b32 s1, s1, 0x80000000142; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)143; GFX11-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v1, s1144; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s3145; GFX11-NEXT: v_mov_b32_e32 v2, s2146; GFX11-NEXT: global_store_b128 v4, v[0:3], s[4:5]147; GFX11-NEXT: s_endpgm148 %fneg = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %in149 store <4 x float> %fneg, ptr addrspace(1) %out150 ret void151}152 153define amdgpu_kernel void @fsub0_f32(ptr addrspace(1) %out, i32 %in) {154; SI-LABEL: fsub0_f32:155; SI: ; %bb.0:156; SI-NEXT: s_load_dword s6, s[4:5], 0xb157; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9158; SI-NEXT: s_mov_b32 s3, 0xf000159; SI-NEXT: s_mov_b32 s2, -1160; SI-NEXT: s_waitcnt lgkmcnt(0)161; SI-NEXT: v_sub_f32_e64 v0, 0, s6162; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0163; SI-NEXT: s_endpgm164;165; VI-LABEL: fsub0_f32:166; VI: ; %bb.0:167; VI-NEXT: s_load_dword s2, s[4:5], 0x2c168; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24169; VI-NEXT: s_waitcnt lgkmcnt(0)170; VI-NEXT: v_sub_f32_e64 v2, 0, s2171; VI-NEXT: v_mov_b32_e32 v0, s0172; VI-NEXT: v_mov_b32_e32 v1, s1173; VI-NEXT: flat_store_dword v[0:1], v2174; VI-NEXT: s_endpgm175;176; GFX11-LABEL: fsub0_f32:177; GFX11: ; %bb.0:178; GFX11-NEXT: s_clause 0x1179; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c180; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24181; GFX11-NEXT: v_mov_b32_e32 v0, 0182; GFX11-NEXT: s_waitcnt lgkmcnt(0)183; GFX11-NEXT: v_sub_f32_e64 v1, 0, s2184; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]185; GFX11-NEXT: s_endpgm186 %bc = bitcast i32 %in to float187 %fsub = fsub float 0.0, %bc188 store float %fsub, ptr addrspace(1) %out189 ret void190}191 192define amdgpu_kernel void @fneg_free_f32(ptr addrspace(1) %out, i32 %in) {193; SI-LABEL: fneg_free_f32:194; SI: ; %bb.0:195; SI-NEXT: s_load_dword s6, s[4:5], 0xb196; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9197; SI-NEXT: s_mov_b32 s3, 0xf000198; SI-NEXT: s_mov_b32 s2, -1199; SI-NEXT: s_waitcnt lgkmcnt(0)200; SI-NEXT: s_xor_b32 s4, s6, 0x80000000201; SI-NEXT: v_mov_b32_e32 v0, s4202; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0203; SI-NEXT: s_endpgm204;205; VI-LABEL: fneg_free_f32:206; VI: ; %bb.0:207; VI-NEXT: s_load_dword s2, s[4:5], 0x2c208; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24209; VI-NEXT: s_waitcnt lgkmcnt(0)210; VI-NEXT: s_xor_b32 s2, s2, 0x80000000211; VI-NEXT: v_mov_b32_e32 v0, s0212; VI-NEXT: v_mov_b32_e32 v1, s1213; VI-NEXT: v_mov_b32_e32 v2, s2214; VI-NEXT: flat_store_dword v[0:1], v2215; VI-NEXT: s_endpgm216;217; GFX11-LABEL: fneg_free_f32:218; GFX11: ; %bb.0:219; GFX11-NEXT: s_clause 0x1220; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c221; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24222; GFX11-NEXT: s_waitcnt lgkmcnt(0)223; GFX11-NEXT: s_xor_b32 s2, s2, 0x80000000224; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)225; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2226; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]227; GFX11-NEXT: s_endpgm228 %bc = bitcast i32 %in to float229 %fsub = fsub float -0.0, %bc230 store float %fsub, ptr addrspace(1) %out231 ret void232}233 234define amdgpu_kernel void @fneg_fold_f32(ptr addrspace(1) %out, float %in) {235; SI-LABEL: fneg_fold_f32:236; SI: ; %bb.0:237; SI-NEXT: s_load_dword s6, s[4:5], 0xb238; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9239; SI-NEXT: s_mov_b32 s3, 0xf000240; SI-NEXT: s_mov_b32 s2, -1241; SI-NEXT: s_waitcnt lgkmcnt(0)242; SI-NEXT: v_mul_f32_e64 v0, -s6, s6243; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0244; SI-NEXT: s_endpgm245;246; VI-LABEL: fneg_fold_f32:247; VI: ; %bb.0:248; VI-NEXT: s_load_dword s2, s[4:5], 0x2c249; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24250; VI-NEXT: s_waitcnt lgkmcnt(0)251; VI-NEXT: v_mul_f32_e64 v2, -s2, s2252; VI-NEXT: v_mov_b32_e32 v0, s0253; VI-NEXT: v_mov_b32_e32 v1, s1254; VI-NEXT: flat_store_dword v[0:1], v2255; VI-NEXT: s_endpgm256;257; GFX11-LABEL: fneg_fold_f32:258; GFX11: ; %bb.0:259; GFX11-NEXT: s_clause 0x1260; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c261; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24262; GFX11-NEXT: v_mov_b32_e32 v0, 0263; GFX11-NEXT: s_waitcnt lgkmcnt(0)264; GFX11-NEXT: v_mul_f32_e64 v1, -s2, s2265; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]266; GFX11-NEXT: s_endpgm267 %fsub = fsub float -0.0, %in268 %fmul = fmul float %fsub, %in269 store float %fmul, ptr addrspace(1) %out270 ret void271}272 273; Make sure we turn some integer operations back into fabs274define amdgpu_kernel void @bitpreserve_fneg_f32(ptr addrspace(1) %out, float %in) {275; SI-LABEL: bitpreserve_fneg_f32:276; SI: ; %bb.0:277; SI-NEXT: s_load_dword s6, s[4:5], 0xb278; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9279; SI-NEXT: s_mov_b32 s3, 0xf000280; SI-NEXT: s_mov_b32 s2, -1281; SI-NEXT: s_waitcnt lgkmcnt(0)282; SI-NEXT: v_mul_f32_e64 v0, s6, -4.0283; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0284; SI-NEXT: s_endpgm285;286; VI-LABEL: bitpreserve_fneg_f32:287; VI: ; %bb.0:288; VI-NEXT: s_load_dword s2, s[4:5], 0x2c289; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24290; VI-NEXT: s_waitcnt lgkmcnt(0)291; VI-NEXT: v_mul_f32_e64 v2, s2, -4.0292; VI-NEXT: v_mov_b32_e32 v0, s0293; VI-NEXT: v_mov_b32_e32 v1, s1294; VI-NEXT: flat_store_dword v[0:1], v2295; VI-NEXT: s_endpgm296;297; GFX11-LABEL: bitpreserve_fneg_f32:298; GFX11: ; %bb.0:299; GFX11-NEXT: s_clause 0x1300; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c301; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24302; GFX11-NEXT: v_mov_b32_e32 v0, 0303; GFX11-NEXT: s_waitcnt lgkmcnt(0)304; GFX11-NEXT: v_mul_f32_e64 v1, s2, -4.0305; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]306; GFX11-NEXT: s_endpgm307 %in.bc = bitcast float %in to i32308 %int.abs = xor i32 %in.bc, 2147483648309 %bc = bitcast i32 %int.abs to float310 %fadd = fmul float %bc, 4.0311 store float %fadd, ptr addrspace(1) %out312 ret void313}314 315define amdgpu_kernel void @s_fneg_i32(ptr addrspace(1) %out, i32 %in) {316; SI-LABEL: s_fneg_i32:317; SI: ; %bb.0:318; SI-NEXT: s_load_dword s6, s[4:5], 0xb319; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9320; SI-NEXT: s_mov_b32 s3, 0xf000321; SI-NEXT: s_mov_b32 s2, -1322; SI-NEXT: s_waitcnt lgkmcnt(0)323; SI-NEXT: s_xor_b32 s4, s6, 0x80000000324; SI-NEXT: v_mov_b32_e32 v0, s4325; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0326; SI-NEXT: s_endpgm327;328; VI-LABEL: s_fneg_i32:329; VI: ; %bb.0:330; VI-NEXT: s_load_dword s2, s[4:5], 0x2c331; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24332; VI-NEXT: s_waitcnt lgkmcnt(0)333; VI-NEXT: s_xor_b32 s2, s2, 0x80000000334; VI-NEXT: v_mov_b32_e32 v0, s0335; VI-NEXT: v_mov_b32_e32 v1, s1336; VI-NEXT: v_mov_b32_e32 v2, s2337; VI-NEXT: flat_store_dword v[0:1], v2338; VI-NEXT: s_endpgm339;340; GFX11-LABEL: s_fneg_i32:341; GFX11: ; %bb.0:342; GFX11-NEXT: s_clause 0x1343; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c344; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24345; GFX11-NEXT: s_waitcnt lgkmcnt(0)346; GFX11-NEXT: s_xor_b32 s2, s2, 0x80000000347; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)348; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2349; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]350; GFX11-NEXT: s_endpgm351 %fneg = xor i32 %in, -2147483648352 store i32 %fneg, ptr addrspace(1) %out353 ret void354}355 356define i32 @v_fneg_i32(i32 %in) {357; GCN-LABEL: v_fneg_i32:358; GCN: ; %bb.0:359; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)360; GCN-NEXT: v_xor_b32_e32 v0, 0x80000000, v0361; GCN-NEXT: s_setpc_b64 s[30:31]362 %fneg = xor i32 %in, -2147483648363 ret i32 %fneg364}365 366define amdgpu_kernel void @s_fneg_i32_fp_use(ptr addrspace(1) %out, i32 %in) {367; SI-LABEL: s_fneg_i32_fp_use:368; SI: ; %bb.0:369; SI-NEXT: s_load_dword s6, s[4:5], 0xb370; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9371; SI-NEXT: s_mov_b32 s3, 0xf000372; SI-NEXT: s_mov_b32 s2, -1373; SI-NEXT: s_waitcnt lgkmcnt(0)374; SI-NEXT: v_sub_f32_e64 v0, 2.0, s6375; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0376; SI-NEXT: s_endpgm377;378; VI-LABEL: s_fneg_i32_fp_use:379; VI: ; %bb.0:380; VI-NEXT: s_load_dword s2, s[4:5], 0x2c381; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24382; VI-NEXT: s_waitcnt lgkmcnt(0)383; VI-NEXT: v_sub_f32_e64 v2, 2.0, s2384; VI-NEXT: v_mov_b32_e32 v0, s0385; VI-NEXT: v_mov_b32_e32 v1, s1386; VI-NEXT: flat_store_dword v[0:1], v2387; VI-NEXT: s_endpgm388;389; GFX11-LABEL: s_fneg_i32_fp_use:390; GFX11: ; %bb.0:391; GFX11-NEXT: s_clause 0x1392; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c393; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24394; GFX11-NEXT: v_mov_b32_e32 v0, 0395; GFX11-NEXT: s_waitcnt lgkmcnt(0)396; GFX11-NEXT: v_sub_f32_e64 v1, 2.0, s2397; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]398; GFX11-NEXT: s_endpgm399 %fneg = xor i32 %in, -2147483648400 %bitcast = bitcast i32 %fneg to float401 %fadd = fadd float %bitcast, 2.0402 store float %fadd, ptr addrspace(1) %out403 ret void404}405 406define float @v_fneg_i32_fp_use(i32 %in) {407; GCN-LABEL: v_fneg_i32_fp_use:408; GCN: ; %bb.0:409; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)410; GCN-NEXT: v_sub_f32_e32 v0, 2.0, v0411; GCN-NEXT: s_setpc_b64 s[30:31]412 %fneg = xor i32 %in, -2147483648413 %bitcast = bitcast i32 %fneg to float414 %fadd = fadd float %bitcast, 2.0415 ret float %fadd416}417 418define amdgpu_kernel void @s_fneg_i64(ptr addrspace(1) %out, i64 %in) {419; SI-LABEL: s_fneg_i64:420; SI: ; %bb.0:421; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9422; SI-NEXT: s_mov_b32 s7, 0xf000423; SI-NEXT: s_mov_b32 s6, -1424; SI-NEXT: s_waitcnt lgkmcnt(0)425; SI-NEXT: s_mov_b32 s4, s0426; SI-NEXT: s_xor_b32 s0, s3, 0x80000000427; SI-NEXT: s_mov_b32 s5, s1428; SI-NEXT: v_mov_b32_e32 v0, s2429; SI-NEXT: v_mov_b32_e32 v1, s0430; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0431; SI-NEXT: s_endpgm432;433; VI-LABEL: s_fneg_i64:434; VI: ; %bb.0:435; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24436; VI-NEXT: s_waitcnt lgkmcnt(0)437; VI-NEXT: v_mov_b32_e32 v0, s0438; VI-NEXT: s_xor_b32 s0, s3, 0x80000000439; VI-NEXT: v_mov_b32_e32 v1, s1440; VI-NEXT: v_mov_b32_e32 v2, s2441; VI-NEXT: v_mov_b32_e32 v3, s0442; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]443; VI-NEXT: s_endpgm444;445; GFX11-LABEL: s_fneg_i64:446; GFX11: ; %bb.0:447; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24448; GFX11-NEXT: s_waitcnt lgkmcnt(0)449; GFX11-NEXT: s_xor_b32 s3, s3, 0x80000000450; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)451; GFX11-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s3452; GFX11-NEXT: v_mov_b32_e32 v0, s2453; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]454; GFX11-NEXT: s_endpgm455 %fneg = xor i64 %in, -9223372036854775808456 store i64 %fneg, ptr addrspace(1) %out457 ret void458}459 460define i64 @v_fneg_i64(i64 %in) {461; GCN-LABEL: v_fneg_i64:462; GCN: ; %bb.0:463; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)464; GCN-NEXT: v_xor_b32_e32 v1, 0x80000000, v1465; GCN-NEXT: s_setpc_b64 s[30:31]466 %fneg = xor i64 %in, -9223372036854775808467 ret i64 %fneg468}469 470define amdgpu_kernel void @s_fneg_i64_fp_use(ptr addrspace(1) %out, i64 %in) {471; SI-LABEL: s_fneg_i64_fp_use:472; SI: ; %bb.0:473; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9474; SI-NEXT: s_mov_b32 s7, 0xf000475; SI-NEXT: s_mov_b32 s6, -1476; SI-NEXT: s_waitcnt lgkmcnt(0)477; SI-NEXT: v_add_f64 v[0:1], -s[2:3], 2.0478; SI-NEXT: s_mov_b32 s4, s0479; SI-NEXT: s_mov_b32 s5, s1480; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0481; SI-NEXT: s_endpgm482;483; VI-LABEL: s_fneg_i64_fp_use:484; VI: ; %bb.0:485; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24486; VI-NEXT: s_waitcnt lgkmcnt(0)487; VI-NEXT: v_add_f64 v[0:1], -s[2:3], 2.0488; VI-NEXT: v_mov_b32_e32 v2, s0489; VI-NEXT: v_mov_b32_e32 v3, s1490; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]491; VI-NEXT: s_endpgm492;493; GFX11-LABEL: s_fneg_i64_fp_use:494; GFX11: ; %bb.0:495; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24496; GFX11-NEXT: v_mov_b32_e32 v2, 0497; GFX11-NEXT: s_waitcnt lgkmcnt(0)498; GFX11-NEXT: v_add_f64 v[0:1], -s[2:3], 2.0499; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]500; GFX11-NEXT: s_endpgm501 %fneg = xor i64 %in, -9223372036854775808502 %bitcast = bitcast i64 %fneg to double503 %fadd = fadd double %bitcast, 2.0504 store double %fadd, ptr addrspace(1) %out505 ret void506}507 508define double @v_fneg_i64_fp_use(i64 %in) {509; GCN-LABEL: v_fneg_i64_fp_use:510; GCN: ; %bb.0:511; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)512; GCN-NEXT: v_add_f64 v[0:1], -v[0:1], 2.0513; GCN-NEXT: s_setpc_b64 s[30:31]514 %fneg = xor i64 %in, -9223372036854775808515 %bitcast = bitcast i64 %fneg to double516 %fadd = fadd double %bitcast, 2.0517 ret double %fadd518}519 520define i16 @v_fneg_i16(i16 %in) {521; SI-LABEL: v_fneg_i16:522; SI: ; %bb.0:523; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)524; SI-NEXT: v_xor_b32_e32 v0, 0xffff8000, v0525; SI-NEXT: s_setpc_b64 s[30:31]526;527; VI-LABEL: v_fneg_i16:528; VI: ; %bb.0:529; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)530; VI-NEXT: v_xor_b32_e32 v0, 0xffff8000, v0531; VI-NEXT: s_setpc_b64 s[30:31]532;533; GFX11-TRUE16-LABEL: v_fneg_i16:534; GFX11-TRUE16: ; %bb.0:535; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)536; GFX11-TRUE16-NEXT: v_xor_b16 v0.l, 0x8000, v0.l537; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]538;539; GFX11-FAKE16-LABEL: v_fneg_i16:540; GFX11-FAKE16: ; %bb.0:541; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)542; GFX11-FAKE16-NEXT: v_xor_b32_e32 v0, 0xffff8000, v0543; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]544 %fneg = xor i16 %in, -32768545 ret i16 %fneg546}547 548define amdgpu_kernel void @s_fneg_i16_fp_use(ptr addrspace(1) %out, i16 %in) {549; SI-LABEL: s_fneg_i16_fp_use:550; SI: ; %bb.0:551; SI-NEXT: s_load_dword s0, s[4:5], 0xb552; SI-NEXT: s_mov_b32 s3, 0xf000553; SI-NEXT: s_mov_b32 s2, -1554; SI-NEXT: s_waitcnt lgkmcnt(0)555; SI-NEXT: v_cvt_f32_f16_e32 v0, s0556; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9557; SI-NEXT: v_sub_f32_e32 v0, 2.0, v0558; SI-NEXT: v_cvt_f16_f32_e32 v0, v0559; SI-NEXT: s_waitcnt lgkmcnt(0)560; SI-NEXT: buffer_store_short v0, off, s[0:3], 0561; SI-NEXT: s_endpgm562;563; VI-LABEL: s_fneg_i16_fp_use:564; VI: ; %bb.0:565; VI-NEXT: s_load_dword s2, s[4:5], 0x2c566; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24567; VI-NEXT: s_waitcnt lgkmcnt(0)568; VI-NEXT: v_sub_f16_e64 v2, 2.0, s2569; VI-NEXT: v_mov_b32_e32 v0, s0570; VI-NEXT: v_mov_b32_e32 v1, s1571; VI-NEXT: flat_store_short v[0:1], v2572; VI-NEXT: s_endpgm573;574; GFX11-TRUE16-LABEL: s_fneg_i16_fp_use:575; GFX11-TRUE16: ; %bb.0:576; GFX11-TRUE16-NEXT: s_clause 0x1577; GFX11-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x2c578; GFX11-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24579; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0580; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)581; GFX11-TRUE16-NEXT: v_sub_f16_e64 v0.l, 2.0, s2582; GFX11-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]583; GFX11-TRUE16-NEXT: s_endpgm584;585; GFX11-FAKE16-LABEL: s_fneg_i16_fp_use:586; GFX11-FAKE16: ; %bb.0:587; GFX11-FAKE16-NEXT: s_clause 0x1588; GFX11-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x2c589; GFX11-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24590; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, 0591; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)592; GFX11-FAKE16-NEXT: v_sub_f16_e64 v1, 2.0, s2593; GFX11-FAKE16-NEXT: global_store_b16 v0, v1, s[0:1]594; GFX11-FAKE16-NEXT: s_endpgm595 %fneg = xor i16 %in, -32768596 %bitcast = bitcast i16 %fneg to half597 %fadd = fadd half %bitcast, 2.0598 store half %fadd, ptr addrspace(1) %out599 ret void600}601 602define half @v_fneg_i16_fp_use(i16 %in) {603; SI-LABEL: v_fneg_i16_fp_use:604; SI: ; %bb.0:605; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)606; SI-NEXT: v_cvt_f32_f16_e32 v0, v0607; SI-NEXT: v_sub_f32_e32 v0, 2.0, v0608; SI-NEXT: s_setpc_b64 s[30:31]609;610; VI-LABEL: v_fneg_i16_fp_use:611; VI: ; %bb.0:612; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)613; VI-NEXT: v_sub_f16_e32 v0, 2.0, v0614; VI-NEXT: s_setpc_b64 s[30:31]615;616; GFX11-TRUE16-LABEL: v_fneg_i16_fp_use:617; GFX11-TRUE16: ; %bb.0:618; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)619; GFX11-TRUE16-NEXT: v_sub_f16_e32 v0.l, 2.0, v0.l620; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]621;622; GFX11-FAKE16-LABEL: v_fneg_i16_fp_use:623; GFX11-FAKE16: ; %bb.0:624; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)625; GFX11-FAKE16-NEXT: v_sub_f16_e32 v0, 2.0, v0626; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]627 %fneg = xor i16 %in, -32768628 %bitcast = bitcast i16 %fneg to half629 %fadd = fadd half %bitcast, 2.0630 ret half %fadd631}632 633define amdgpu_kernel void @s_fneg_v2i16(ptr addrspace(1) %out, i32 %arg) {634; SI-LABEL: s_fneg_v2i16:635; SI: ; %bb.0:636; SI-NEXT: s_load_dword s6, s[4:5], 0xb637; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9638; SI-NEXT: s_mov_b32 s3, 0xf000639; SI-NEXT: s_mov_b32 s2, -1640; SI-NEXT: s_waitcnt lgkmcnt(0)641; SI-NEXT: s_xor_b32 s4, s6, 0x80008000642; SI-NEXT: v_mov_b32_e32 v0, s4643; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0644; SI-NEXT: s_endpgm645;646; VI-LABEL: s_fneg_v2i16:647; VI: ; %bb.0:648; VI-NEXT: s_load_dword s2, s[4:5], 0x2c649; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24650; VI-NEXT: s_waitcnt lgkmcnt(0)651; VI-NEXT: s_xor_b32 s2, s2, 0x80008000652; VI-NEXT: v_mov_b32_e32 v0, s0653; VI-NEXT: v_mov_b32_e32 v1, s1654; VI-NEXT: v_mov_b32_e32 v2, s2655; VI-NEXT: flat_store_dword v[0:1], v2656; VI-NEXT: s_endpgm657;658; GFX11-LABEL: s_fneg_v2i16:659; GFX11: ; %bb.0:660; GFX11-NEXT: s_clause 0x1661; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c662; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24663; GFX11-NEXT: s_waitcnt lgkmcnt(0)664; GFX11-NEXT: s_xor_b32 s2, s2, 0x80008000665; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)666; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2667; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]668; GFX11-NEXT: s_endpgm669 %in = bitcast i32 %arg to <2 x i16>670 %fneg = xor <2 x i16> %in, <i16 -32768, i16 -32768>671 store <2 x i16> %fneg, ptr addrspace(1) %out672 ret void673}674 675define <2 x i16> @v_fneg_v2i16(<2 x i16> %in) {676; SI-LABEL: v_fneg_v2i16:677; SI: ; %bb.0:678; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)679; SI-NEXT: v_xor_b32_e32 v1, 0x8000, v1680; SI-NEXT: v_xor_b32_e32 v0, 0x8000, v0681; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v1682; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0683; SI-NEXT: v_or_b32_e32 v0, v0, v2684; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1685; SI-NEXT: s_setpc_b64 s[30:31]686;687; VI-LABEL: v_fneg_v2i16:688; VI: ; %bb.0:689; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)690; VI-NEXT: v_xor_b32_e32 v0, 0x80008000, v0691; VI-NEXT: s_setpc_b64 s[30:31]692;693; GFX11-LABEL: v_fneg_v2i16:694; GFX11: ; %bb.0:695; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)696; GFX11-NEXT: v_xor_b32_e32 v0, 0x80008000, v0697; GFX11-NEXT: s_setpc_b64 s[30:31]698 %fneg = xor <2 x i16> %in, <i16 -32768, i16 -32768>699 ret <2 x i16> %fneg700}701 702define amdgpu_kernel void @s_fneg_v2i16_fp_use(ptr addrspace(1) %out, i32 %arg) {703; SI-LABEL: s_fneg_v2i16_fp_use:704; SI: ; %bb.0:705; SI-NEXT: s_load_dword s0, s[4:5], 0xb706; SI-NEXT: s_mov_b32 s3, 0xf000707; SI-NEXT: s_mov_b32 s2, -1708; SI-NEXT: s_waitcnt lgkmcnt(0)709; SI-NEXT: s_lshr_b32 s1, s0, 16710; SI-NEXT: v_cvt_f32_f16_e32 v0, s1711; SI-NEXT: v_cvt_f32_f16_e32 v1, s0712; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9713; SI-NEXT: v_sub_f32_e32 v0, 2.0, v0714; SI-NEXT: v_cvt_f16_f32_e32 v0, v0715; SI-NEXT: v_sub_f32_e32 v1, 2.0, v1716; SI-NEXT: v_cvt_f16_f32_e32 v1, v1717; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0718; SI-NEXT: v_or_b32_e32 v0, v1, v0719; SI-NEXT: s_waitcnt lgkmcnt(0)720; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0721; SI-NEXT: s_endpgm722;723; VI-LABEL: s_fneg_v2i16_fp_use:724; VI: ; %bb.0:725; VI-NEXT: s_load_dword s2, s[4:5], 0x2c726; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24727; VI-NEXT: v_mov_b32_e32 v0, 0x4000728; VI-NEXT: s_waitcnt lgkmcnt(0)729; VI-NEXT: s_lshr_b32 s3, s2, 16730; VI-NEXT: v_mov_b32_e32 v2, s3731; VI-NEXT: v_sub_f16_e64 v1, 2.0, s2732; VI-NEXT: v_sub_f16_sdwa v0, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD733; VI-NEXT: v_or_b32_e32 v2, v1, v0734; VI-NEXT: v_mov_b32_e32 v0, s0735; VI-NEXT: v_mov_b32_e32 v1, s1736; VI-NEXT: flat_store_dword v[0:1], v2737; VI-NEXT: s_endpgm738;739; GFX11-LABEL: s_fneg_v2i16_fp_use:740; GFX11: ; %bb.0:741; GFX11-NEXT: s_clause 0x1742; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c743; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24744; GFX11-NEXT: v_mov_b32_e32 v0, 0745; GFX11-NEXT: s_waitcnt lgkmcnt(0)746; GFX11-NEXT: v_pk_add_f16 v1, s2, 2.0 op_sel_hi:[1,0] neg_lo:[1,0] neg_hi:[1,0]747; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]748; GFX11-NEXT: s_endpgm749 %in = bitcast i32 %arg to <2 x i16>750 %fneg = xor <2 x i16> %in, <i16 -32768, i16 -32768>751 %bitcast = bitcast <2 x i16> %fneg to <2 x half>752 %fadd = fadd <2 x half> %bitcast, <half 2.0, half 2.0>753 store <2 x half> %fadd, ptr addrspace(1) %out754 ret void755}756 757define <2 x half> @v_fneg_v2i16_fp_use(i32 %arg) {758; SI-LABEL: v_fneg_v2i16_fp_use:759; SI: ; %bb.0:760; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)761; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v0762; SI-NEXT: v_cvt_f32_f16_e32 v0, v0763; SI-NEXT: v_cvt_f32_f16_e32 v1, v1764; SI-NEXT: v_sub_f32_e32 v0, 2.0, v0765; SI-NEXT: v_sub_f32_e32 v1, 2.0, v1766; SI-NEXT: s_setpc_b64 s[30:31]767;768; VI-LABEL: v_fneg_v2i16_fp_use:769; VI: ; %bb.0:770; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)771; VI-NEXT: v_mov_b32_e32 v1, 0x4000772; VI-NEXT: v_sub_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1773; VI-NEXT: v_sub_f16_e32 v0, 2.0, v0774; VI-NEXT: v_or_b32_e32 v0, v0, v1775; VI-NEXT: s_setpc_b64 s[30:31]776;777; GFX11-LABEL: v_fneg_v2i16_fp_use:778; GFX11: ; %bb.0:779; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)780; GFX11-NEXT: v_pk_add_f16 v0, v0, 2.0 op_sel_hi:[1,0] neg_lo:[1,0] neg_hi:[1,0]781; GFX11-NEXT: s_setpc_b64 s[30:31]782 %in = bitcast i32 %arg to <2 x i16>783 %fneg = xor <2 x i16> %in, <i16 -32768, i16 -32768>784 %bitcast = bitcast <2 x i16> %fneg to <2 x half>785 %fadd = fadd <2 x half> %bitcast, <half 2.0, half 2.0>786 ret <2 x half> %fadd787}788