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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 < %s | FileCheck %s3 4define float @fma_from_freeze_mul_add_left(float %x, float %y) {5; CHECK-LABEL: fma_from_freeze_mul_add_left:6; CHECK: ; %bb.0:7; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8; CHECK-NEXT: v_fma_f32 v0, v0, v1, 1.09; CHECK-NEXT: s_setpc_b64 s[30:31]10 %mul = fmul contract float %x, %y11 %mul.fr = freeze float %mul12 %add = fadd contract float %mul.fr, 1.000000e+0013 ret float %add14}15 16define float @fma_from_freeze_mul_add_left_with_nnan(float %x, float %y) {17; CHECK-LABEL: fma_from_freeze_mul_add_left_with_nnan:18; CHECK: ; %bb.0:19; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)20; CHECK-NEXT: v_fma_f32 v0, v0, v1, 1.021; CHECK-NEXT: s_setpc_b64 s[30:31]22 %mul = fmul nnan contract afn float %x, %y23 %mul.fr = freeze float %mul24 %add = fadd nnan contract float %mul.fr, 1.000000e+0025 ret float %add26}27 28define float @fma_from_freeze_mul_add_right(float %x, float %y) {29; CHECK-LABEL: fma_from_freeze_mul_add_right:30; CHECK: ; %bb.0:31; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)32; CHECK-NEXT: v_fma_f32 v0, v0, v1, 1.033; CHECK-NEXT: s_setpc_b64 s[30:31]34 %mul = fmul contract float %x, %y35 %mul.fr = freeze float %mul36 %add = fadd contract float 1.000000e+00, %mul.fr37 ret float %add38}39 40define float @fma_from_freeze_mul_add_right_with_nnan(float %x, float %y) {41; CHECK-LABEL: fma_from_freeze_mul_add_right_with_nnan:42; CHECK: ; %bb.0:43; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)44; CHECK-NEXT: v_fma_f32 v0, v0, v1, 1.045; CHECK-NEXT: s_setpc_b64 s[30:31]46 %mul = fmul nnan contract float %x, %y47 %mul.fr = freeze float %mul48 %add = fadd nnan contract float 1.000000e+00, %mul.fr49 ret float %add50}51 52define float @fma_from_freeze_mul_sub_left(float %x, float %y) {53; CHECK-LABEL: fma_from_freeze_mul_sub_left:54; CHECK: ; %bb.0:55; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)56; CHECK-NEXT: v_fma_f32 v0, v0, v1, -1.057; CHECK-NEXT: s_setpc_b64 s[30:31]58 %mul = fmul contract float %x, %y59 %mul.fr = freeze float %mul60 %sub = fsub contract float %mul.fr, 1.000000e+0061 ret float %sub62}63 64define float @fma_from_freeze_mul_sub_left_with_nnan(float %x, float %y) {65; CHECK-LABEL: fma_from_freeze_mul_sub_left_with_nnan:66; CHECK: ; %bb.0:67; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)68; CHECK-NEXT: v_fma_f32 v0, v0, v1, -1.069; CHECK-NEXT: s_setpc_b64 s[30:31]70 %mul = fmul nnan contract float %x, %y71 %mul.fr = freeze float %mul72 %sub = fsub nnan contract float %mul.fr, 1.000000e+0073 ret float %sub74}75 76define float @fma_from_freeze_mul_sub_right(float %x, float %y) {77; CHECK-LABEL: fma_from_freeze_mul_sub_right:78; CHECK: ; %bb.0:79; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)80; CHECK-NEXT: v_fma_f32 v0, -v0, v1, 1.081; CHECK-NEXT: s_setpc_b64 s[30:31]82 %mul = fmul contract float %x, %y83 %mul.fr = freeze float %mul84 %sub = fsub contract float 1.000000e+00, %mul.fr85 ret float %sub86}87 88define float @fma_from_freeze_mul_sub_right_with_nnan(float %x, float %y) {89; CHECK-LABEL: fma_from_freeze_mul_sub_right_with_nnan:90; CHECK: ; %bb.0:91; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)92; CHECK-NEXT: v_fma_f32 v0, -v0, v1, 1.093; CHECK-NEXT: s_setpc_b64 s[30:31]94 %mul = fmul nnan contract float %x, %y95 %mul.fr = freeze float %mul96 %sub = fsub nnan contract float 1.000000e+00, %mul.fr97 ret float %sub98}99 100define float @fma_freeze_sink_multiple_maybe_poison_nnan_add(float %x, float %y) {101; CHECK-LABEL: fma_freeze_sink_multiple_maybe_poison_nnan_add:102; CHECK: ; %bb.0:103; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)104; CHECK-NEXT: v_dual_subrev_f32 v0, 1.0, v0 :: v_dual_add_f32 v1, 1.0, v1105; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1)106; CHECK-NEXT: v_fma_f32 v0, v0, v1, 1.0107; CHECK-NEXT: s_setpc_b64 s[30:31]108 %fsub_x = fsub nnan contract float %x, 1.000000e+00109 %fadd_y = fadd nnan contract float %y, 1.000000e+00110 %mul = fmul nnan contract float %fsub_x, %fadd_y111 %mul.fr = freeze float %mul112 %add = fadd nnan contract float %mul.fr, 1.000000e+00113 ret float %add114}115 116define float @fma_freeze_sink_multiple_maybe_poison_nnan_sub(float %x, float %y) {117; CHECK-LABEL: fma_freeze_sink_multiple_maybe_poison_nnan_sub:118; CHECK: ; %bb.0:119; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)120; CHECK-NEXT: v_dual_add_f32 v0, 1.0, v0 :: v_dual_add_f32 v1, -1.0, v1121; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1)122; CHECK-NEXT: v_fma_f32 v0, v0, v1, -1.0123; CHECK-NEXT: s_setpc_b64 s[30:31]124 %fadd_x = fadd nnan contract float %x, 1.000000e+00125 %fsub_y = fsub nnan contract float %y, 1.000000e+00126 %mul = fmul nnan contract float %fadd_x, %fsub_y127 %mul.fr = freeze float %mul128 %sub = fsub nnan contract float %mul.fr, 1.000000e+00129 ret float %sub130}131