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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -run-pass si-fold-operands,dead-mi-elimination %s -o - | FileCheck -check-prefix=GCN %s3 4---5 6name: shrink_scalar_imm_vgpr_v_add_i32_e64_no_carry_out_use7tracksRegLiveness: true8 9body: |10 bb.0:11 ; GCN-LABEL: name: shrink_scalar_imm_vgpr_v_add_i32_e64_no_carry_out_use12 ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 1234513 ; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF14 ; GCN-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def $vcc, implicit $exec15 ; GCN-NEXT: S_ENDPGM 0, implicit [[V_ADD_CO_U32_e32_]]16 %0:sreg_32_xm0 = S_MOV_B32 1234517 %1:vgpr_32 = IMPLICIT_DEF18 %2:vgpr_32, %3:sreg_64 = V_ADD_CO_U32_e64 %0, %1, 0, implicit $exec19 S_ENDPGM 0, implicit %220 21...22 23---24 25name: shrink_vgpr_scalar_imm_v_add_i32_e64_no_carry_out_use26tracksRegLiveness: true27 28body: |29 bb.0:30 ; GCN-LABEL: name: shrink_vgpr_scalar_imm_v_add_i32_e64_no_carry_out_use31 ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF32 ; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 1234533 ; GCN-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def $vcc, implicit $exec34 ; GCN-NEXT: S_ENDPGM 0, implicit [[V_ADD_CO_U32_e32_]]35 %0:vgpr_32 = IMPLICIT_DEF36 %1:sreg_32_xm0 = S_MOV_B32 1234537 %2:vgpr_32, %3:sreg_64 = V_ADD_CO_U32_e64 %0, %1, 0, implicit $exec38 S_ENDPGM 0, implicit %239 40...41---42 43name: shrink_scalar_imm_vgpr_v_add_i32_e64_carry_out_use44tracksRegLiveness: true45 46body: |47 bb.0:48 ; GCN-LABEL: name: shrink_scalar_imm_vgpr_v_add_i32_e64_carry_out_use49 ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 1234550 ; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF51 ; GCN-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def $vcc, implicit $exec52 ; GCN-NEXT: S_ENDPGM 0, implicit [[V_ADD_CO_U32_e32_]]53 %0:sreg_32_xm0 = S_MOV_B32 1234554 %1:vgpr_32 = IMPLICIT_DEF55 %2:vgpr_32, %3:sreg_64 = V_ADD_CO_U32_e64 %0, %1, 0, implicit $exec56 S_ENDPGM 0, implicit %257 58...59---60 61# This does not shrink because it would violate the constant bus62# restriction. to have an SGPR input and an immediate, so a copy would63# be required.64 65name: shrink_vector_imm_sgpr_v_add_i32_e64_no_carry_out_use66tracksRegLiveness: true67 68body: |69 bb.0:70 ; GCN-LABEL: name: shrink_vector_imm_sgpr_v_add_i32_e64_no_carry_out_use71 ; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 12345, implicit $exec72 ; GCN-NEXT: [[DEF:%[0-9]+]]:sreg_32_xm0 = IMPLICIT_DEF73 ; GCN-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64 = V_ADD_CO_U32_e64 [[DEF]], [[V_MOV_B32_e32_]], 0, implicit $exec74 ; GCN-NEXT: S_ENDPGM 0, implicit [[V_ADD_CO_U32_e64_]]75 %0:vgpr_32 = V_MOV_B32_e32 12345, implicit $exec76 %1:sreg_32_xm0 = IMPLICIT_DEF77 %2:vgpr_32, %3:sreg_64 = V_ADD_CO_U32_e64 %0, %1, 0, implicit $exec78 S_ENDPGM 0, implicit %279 80...81 82---83 84name: shrink_sgpr_vector_imm_v_add_i32_e64_no_carry_out_use85tracksRegLiveness: true86 87body: |88 bb.0:89 ; GCN-LABEL: name: shrink_sgpr_vector_imm_v_add_i32_e64_no_carry_out_use90 ; GCN: [[DEF:%[0-9]+]]:sreg_32_xm0 = IMPLICIT_DEF91 ; GCN-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 12345, implicit $exec92 ; GCN-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64 = V_ADD_CO_U32_e64 [[V_MOV_B32_e32_]], [[DEF]], 0, implicit $exec93 ; GCN-NEXT: S_ENDPGM 0, implicit [[V_ADD_CO_U32_e64_]]94 %0:sreg_32_xm0 = IMPLICIT_DEF95 %1:vgpr_32 = V_MOV_B32_e32 12345, implicit $exec96 %2:vgpr_32, %3:sreg_64 = V_ADD_CO_U32_e64 %0, %1, 0, implicit $exec97 S_ENDPGM 0, implicit %298 99...100 101---102 103name: shrink_scalar_imm_vgpr_v_add_i32_e64_live_vcc_use104tracksRegLiveness: true105 106body: |107 bb.0:108 ; GCN-LABEL: name: shrink_scalar_imm_vgpr_v_add_i32_e64_live_vcc_use109 ; GCN: $vcc = S_MOV_B64 -1110 ; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345111 ; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF112 ; GCN-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64 = V_ADD_CO_U32_e64 [[S_MOV_B32_]], [[DEF]], 0, implicit $exec113 ; GCN-NEXT: S_ENDPGM 0, implicit [[V_ADD_CO_U32_e64_]], implicit $vcc114 $vcc = S_MOV_B64 -1115 %0:sreg_32_xm0 = S_MOV_B32 12345116 %1:vgpr_32 = IMPLICIT_DEF117 %2:vgpr_32, %3:sreg_64 = V_ADD_CO_U32_e64 %0, %1, 0, implicit $exec118 S_ENDPGM 0, implicit %2, implicit $vcc119 120...121 122---123 124name: shrink_scalar_imm_vgpr_v_add_i32_e64_liveout_vcc_use125tracksRegLiveness: true126 127body: |128 ; GCN-LABEL: name: shrink_scalar_imm_vgpr_v_add_i32_e64_liveout_vcc_use129 ; GCN: bb.0:130 ; GCN-NEXT: successors: %bb.1(0x80000000)131 ; GCN-NEXT: {{ $}}132 ; GCN-NEXT: $vcc = S_MOV_B64 -1133 ; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345134 ; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF135 ; GCN-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64 = V_ADD_CO_U32_e64 [[S_MOV_B32_]], [[DEF]], 0, implicit $exec136 ; GCN-NEXT: {{ $}}137 ; GCN-NEXT: bb.1:138 ; GCN-NEXT: liveins: $vcc139 ; GCN-NEXT: {{ $}}140 ; GCN-NEXT: S_ENDPGM 0, implicit [[V_ADD_CO_U32_e64_]], implicit $vcc141 bb.0:142 successors: %bb.1143 $vcc = S_MOV_B64 -1144 %0:sreg_32_xm0 = S_MOV_B32 12345145 %1:vgpr_32 = IMPLICIT_DEF146 %2:vgpr_32, %3:sreg_64 = V_ADD_CO_U32_e64 %0, %1, 0, implicit $exec147 148 bb.1:149 liveins: $vcc150 S_ENDPGM 0, implicit %2, implicit $vcc151 152...153---154 155name: shrink_scalar_imm_vgpr_v_add_i32_e64_liveout_vcc_lo_use156tracksRegLiveness: true157 158body: |159 ; GCN-LABEL: name: shrink_scalar_imm_vgpr_v_add_i32_e64_liveout_vcc_lo_use160 ; GCN: bb.0:161 ; GCN-NEXT: successors: %bb.1(0x80000000)162 ; GCN-NEXT: {{ $}}163 ; GCN-NEXT: $vcc = S_MOV_B64 -1164 ; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345165 ; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF166 ; GCN-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64 = V_ADD_CO_U32_e64 [[S_MOV_B32_]], [[DEF]], 0, implicit $exec167 ; GCN-NEXT: {{ $}}168 ; GCN-NEXT: bb.1:169 ; GCN-NEXT: liveins: $vcc_lo170 ; GCN-NEXT: {{ $}}171 ; GCN-NEXT: S_ENDPGM 0, implicit [[V_ADD_CO_U32_e64_]], implicit $vcc_lo172 bb.0:173 successors: %bb.1174 $vcc = S_MOV_B64 -1175 %0:sreg_32_xm0 = S_MOV_B32 12345176 %1:vgpr_32 = IMPLICIT_DEF177 %2:vgpr_32, %3:sreg_64 = V_ADD_CO_U32_e64 %0, %1, 0, implicit $exec178 179 bb.1:180 liveins: $vcc_lo181 S_ENDPGM 0, implicit %2, implicit $vcc_lo182 183...184---185 186# This is not OK to clobber because vcc_lo has a livein use.187 188name: shrink_scalar_imm_vgpr_v_add_i32_e64_livein_vcc189tracksRegLiveness: true190 191body: |192 ; GCN-LABEL: name: shrink_scalar_imm_vgpr_v_add_i32_e64_livein_vcc193 ; GCN: bb.0:194 ; GCN-NEXT: successors: %bb.1(0x80000000)195 ; GCN-NEXT: {{ $}}196 ; GCN-NEXT: $vcc = S_MOV_B64 -1197 ; GCN-NEXT: {{ $}}198 ; GCN-NEXT: bb.1:199 ; GCN-NEXT: liveins: $vcc200 ; GCN-NEXT: {{ $}}201 ; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345202 ; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF203 ; GCN-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64 = V_ADD_CO_U32_e64 [[S_MOV_B32_]], [[DEF]], 0, implicit $exec204 ; GCN-NEXT: S_ENDPGM 0, implicit [[V_ADD_CO_U32_e64_]], implicit $vcc_lo205 bb.0:206 successors: %bb.1207 $vcc = S_MOV_B64 -1208 209 bb.1:210 liveins: $vcc211 %0:sreg_32_xm0 = S_MOV_B32 12345212 %1:vgpr_32 = IMPLICIT_DEF213 %2:vgpr_32, %3:sreg_64 = V_ADD_CO_U32_e64 %0, %1, 0, implicit $exec214 S_ENDPGM 0, implicit %2, implicit $vcc_lo215 216...217---218 219name: shrink_scalar_imm_vgpr_v_add_i32_e64_livein_vcc_hi220tracksRegLiveness: true221 222body: |223 ; GCN-LABEL: name: shrink_scalar_imm_vgpr_v_add_i32_e64_livein_vcc_hi224 ; GCN: bb.0:225 ; GCN-NEXT: successors: %bb.1(0x80000000)226 ; GCN-NEXT: {{ $}}227 ; GCN-NEXT: $vcc_hi = S_MOV_B32 -1228 ; GCN-NEXT: {{ $}}229 ; GCN-NEXT: bb.1:230 ; GCN-NEXT: successors: %bb.2(0x80000000)231 ; GCN-NEXT: liveins: $vcc_hi232 ; GCN-NEXT: {{ $}}233 ; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345234 ; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF235 ; GCN-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64 = V_ADD_CO_U32_e64 [[S_MOV_B32_]], [[DEF]], 0, implicit $exec236 ; GCN-NEXT: {{ $}}237 ; GCN-NEXT: bb.2:238 ; GCN-NEXT: liveins: $vcc_hi239 ; GCN-NEXT: {{ $}}240 ; GCN-NEXT: S_ENDPGM 0, implicit [[V_ADD_CO_U32_e64_]], implicit $vcc_hi241 bb.0:242 successors: %bb.1243 $vcc_hi = S_MOV_B32 -1244 245 bb.1:246 liveins: $vcc_hi247 %0:sreg_32_xm0 = S_MOV_B32 12345248 %1:vgpr_32 = IMPLICIT_DEF249 %2:vgpr_32, %3:sreg_64 = V_ADD_CO_U32_e64 %0, %1, 0, implicit $exec250 251 bb.2:252 liveins: $vcc_hi253 254 S_ENDPGM 0, implicit %2, implicit $vcc_hi255 256...257 258---259 260name: shrink_scalar_imm_vgpr_v_sub_i32_e64_no_carry_out_use261tracksRegLiveness: true262 263body: |264 bb.0:265 ; GCN-LABEL: name: shrink_scalar_imm_vgpr_v_sub_i32_e64_no_carry_out_use266 ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345267 ; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF268 ; GCN-NEXT: [[V_SUB_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_SUB_CO_U32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def $vcc, implicit $exec269 ; GCN-NEXT: S_ENDPGM 0, implicit [[V_SUB_CO_U32_e32_]]270 %0:sreg_32_xm0 = S_MOV_B32 12345271 %1:vgpr_32 = IMPLICIT_DEF272 %2:vgpr_32, %3:sreg_64 = V_SUB_CO_U32_e64 %0, %1, 0, implicit $exec273 S_ENDPGM 0, implicit %2274 275...276 277---278 279name: shrink_vgpr_scalar_imm_v_sub_i32_e64_no_carry_out_use280tracksRegLiveness: true281 282body: |283 bb.0:284 ; GCN-LABEL: name: shrink_vgpr_scalar_imm_v_sub_i32_e64_no_carry_out_use285 ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF286 ; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345287 ; GCN-NEXT: [[V_SUBREV_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_SUBREV_CO_U32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def $vcc, implicit $exec288 ; GCN-NEXT: S_ENDPGM 0, implicit [[V_SUBREV_CO_U32_e32_]]289 %0:vgpr_32 = IMPLICIT_DEF290 %1:sreg_32_xm0 = S_MOV_B32 12345291 %2:vgpr_32, %3:sreg_64 = V_SUB_CO_U32_e64 %0, %1, 0, implicit $exec292 S_ENDPGM 0, implicit %2293 294...295 296---297 298name: shrink_scalar_imm_vgpr_v_subrev_i32_e64_no_carry_out_use299tracksRegLiveness: true300 301body: |302 bb.0:303 ; GCN-LABEL: name: shrink_scalar_imm_vgpr_v_subrev_i32_e64_no_carry_out_use304 ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345305 ; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF306 ; GCN-NEXT: [[V_SUBREV_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_SUBREV_CO_U32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def $vcc, implicit $exec307 ; GCN-NEXT: S_ENDPGM 0, implicit [[V_SUBREV_CO_U32_e32_]]308 %0:sreg_32_xm0 = S_MOV_B32 12345309 %1:vgpr_32 = IMPLICIT_DEF310 %2:vgpr_32, %3:sreg_64 = V_SUBREV_CO_U32_e64 %0, %1, 0, implicit $exec311 S_ENDPGM 0, implicit %2312 313...314 315---316 317name: shrink_vgpr_scalar_imm_v_subrev_i32_e64_no_carry_out_use318tracksRegLiveness: true319 320body: |321 bb.0:322 ; GCN-LABEL: name: shrink_vgpr_scalar_imm_v_subrev_i32_e64_no_carry_out_use323 ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF324 ; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345325 ; GCN-NEXT: [[V_SUB_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_SUB_CO_U32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def $vcc, implicit $exec326 ; GCN-NEXT: S_ENDPGM 0, implicit [[V_SUB_CO_U32_e32_]]327 %0:vgpr_32 = IMPLICIT_DEF328 %1:sreg_32_xm0 = S_MOV_B32 12345329 %2:vgpr_32, %3:sreg_64 = V_SUBREV_CO_U32_e64 %0, %1, 0, implicit $exec330 S_ENDPGM 0, implicit %2331 332...333 334---335 336# We know this is OK because vcc isn't live out of the block.337 338name: shrink_scalar_imm_vgpr_v_add_i32_e64_known_no_liveout339tracksRegLiveness: true340 341body: |342 ; GCN-LABEL: name: shrink_scalar_imm_vgpr_v_add_i32_e64_known_no_liveout343 ; GCN: bb.0:344 ; GCN-NEXT: successors: %bb.1(0x80000000)345 ; GCN-NEXT: {{ $}}346 ; GCN-NEXT: S_NOP 0347 ; GCN-NEXT: S_NOP 0348 ; GCN-NEXT: S_NOP 0349 ; GCN-NEXT: S_NOP 0350 ; GCN-NEXT: S_NOP 0351 ; GCN-NEXT: S_NOP 0352 ; GCN-NEXT: S_NOP 0353 ; GCN-NEXT: S_NOP 0354 ; GCN-NEXT: S_NOP 0355 ; GCN-NEXT: S_NOP 0356 ; GCN-NEXT: S_NOP 0357 ; GCN-NEXT: S_NOP 0358 ; GCN-NEXT: S_NOP 0359 ; GCN-NEXT: S_NOP 0360 ; GCN-NEXT: S_NOP 0361 ; GCN-NEXT: S_NOP 0362 ; GCN-NEXT: S_NOP 0363 ; GCN-NEXT: S_NOP 0364 ; GCN-NEXT: S_NOP 0365 ; GCN-NEXT: S_NOP 0366 ; GCN-NEXT: S_NOP 0367 ; GCN-NEXT: S_NOP 0368 ; GCN-NEXT: S_NOP 0369 ; GCN-NEXT: S_NOP 0370 ; GCN-NEXT: S_NOP 0371 ; GCN-NEXT: S_NOP 0372 ; GCN-NEXT: S_NOP 0373 ; GCN-NEXT: S_NOP 0374 ; GCN-NEXT: S_NOP 0375 ; GCN-NEXT: S_NOP 0376 ; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345377 ; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF378 ; GCN-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def $vcc, implicit $exec379 ; GCN-NEXT: S_NOP 0380 ; GCN-NEXT: S_NOP 0381 ; GCN-NEXT: {{ $}}382 ; GCN-NEXT: bb.1:383 ; GCN-NEXT: S_ENDPGM 0, implicit [[V_ADD_CO_U32_e32_]]384 bb.0:385 successors: %bb.1386 387 S_NOP 0388 S_NOP 0389 S_NOP 0390 S_NOP 0391 S_NOP 0392 S_NOP 0393 S_NOP 0394 S_NOP 0395 S_NOP 0396 S_NOP 0397 S_NOP 0398 S_NOP 0399 S_NOP 0400 S_NOP 0401 S_NOP 0402 S_NOP 0403 S_NOP 0404 S_NOP 0405 S_NOP 0406 S_NOP 0407 S_NOP 0408 S_NOP 0409 S_NOP 0410 S_NOP 0411 S_NOP 0412 S_NOP 0413 S_NOP 0414 S_NOP 0415 S_NOP 0416 S_NOP 0417 %0:sreg_32_xm0 = S_MOV_B32 12345418 %1:vgpr_32 = IMPLICIT_DEF419 %2:vgpr_32, %3:sreg_64 = V_ADD_CO_U32_e64 %0, %1, 0, implicit $exec420 S_NOP 0421 S_NOP 0422 423 bb.1:424 S_ENDPGM 0, implicit %2425 426...427 428---429 430# We know this is OK because vcc isn't live out of the block, even431# though it had a defined but unused. value432 433name: shrink_scalar_imm_vgpr_v_add_i32_e64_known_no_liveout_dead_vcc_def434tracksRegLiveness: true435 436body: |437 ; GCN-LABEL: name: shrink_scalar_imm_vgpr_v_add_i32_e64_known_no_liveout_dead_vcc_def438 ; GCN: bb.0:439 ; GCN-NEXT: successors: %bb.1(0x80000000)440 ; GCN-NEXT: {{ $}}441 ; GCN-NEXT: S_NOP 0, implicit-def $vcc442 ; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345443 ; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF444 ; GCN-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def $vcc, implicit $exec445 ; GCN-NEXT: S_NOP 0446 ; GCN-NEXT: S_NOP 0447 ; GCN-NEXT: {{ $}}448 ; GCN-NEXT: bb.1:449 ; GCN-NEXT: S_ENDPGM 0, implicit [[V_ADD_CO_U32_e32_]]450 bb.0:451 successors: %bb.1452 453 S_NOP 0, implicit-def $vcc454 %0:sreg_32_xm0 = S_MOV_B32 12345455 %1:vgpr_32 = IMPLICIT_DEF456 %2:vgpr_32, %3:sreg_64 = V_ADD_CO_U32_e64 %0, %1, 0, implicit $exec457 S_NOP 0458 S_NOP 0459 460 bb.1:461 S_ENDPGM 0, implicit %2462 463...464---465 466# This requires searching through many DBG_VALUE instructions before the insert poitn, which467# should not count against the search limit.468 469name: vcc_liveness_dbg_value_search_before470tracksRegLiveness: true471 472body: |473 bb.0:474 ; GCN-LABEL: name: vcc_liveness_dbg_value_search_before475 ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345476 ; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF477 ; GCN-NEXT: DBG_VALUE $noreg, 0478 ; GCN-NEXT: DBG_VALUE $noreg, 0479 ; GCN-NEXT: DBG_VALUE $noreg, 0480 ; GCN-NEXT: DBG_VALUE $noreg, 0481 ; GCN-NEXT: DBG_VALUE $noreg, 0482 ; GCN-NEXT: DBG_VALUE $noreg, 0483 ; GCN-NEXT: DBG_VALUE $noreg, 0484 ; GCN-NEXT: DBG_VALUE $noreg, 0485 ; GCN-NEXT: DBG_VALUE $noreg, 0486 ; GCN-NEXT: DBG_VALUE $noreg, 0487 ; GCN-NEXT: DBG_VALUE $noreg, 0488 ; GCN-NEXT: DBG_VALUE $noreg, 0489 ; GCN-NEXT: DBG_VALUE $noreg, 0490 ; GCN-NEXT: DBG_VALUE $noreg, 0491 ; GCN-NEXT: DBG_VALUE $noreg, 0492 ; GCN-NEXT: DBG_VALUE $noreg, 0493 ; GCN-NEXT: DBG_VALUE $noreg, 0494 ; GCN-NEXT: DBG_VALUE $noreg, 0495 ; GCN-NEXT: DBG_VALUE $noreg, 0496 ; GCN-NEXT: DBG_VALUE $noreg, 0497 ; GCN-NEXT: DBG_VALUE $noreg, 0498 ; GCN-NEXT: DBG_VALUE $noreg, 0499 ; GCN-NEXT: DBG_VALUE $noreg, 0500 ; GCN-NEXT: DBG_VALUE $noreg, 0501 ; GCN-NEXT: DBG_VALUE $noreg, 0502 ; GCN-NEXT: DBG_VALUE $noreg, 0503 ; GCN-NEXT: DBG_VALUE $noreg, 0504 ; GCN-NEXT: DBG_VALUE $noreg, 0505 ; GCN-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def $vcc, implicit $exec506 ; GCN-NEXT: S_ENDPGM 0, implicit [[V_ADD_CO_U32_e32_]]507 %0:sreg_32_xm0 = S_MOV_B32 12345508 %1:vgpr_32 = IMPLICIT_DEF509 DBG_VALUE $noreg, 0510 DBG_VALUE $noreg, 0511 DBG_VALUE $noreg, 0512 DBG_VALUE $noreg, 0513 DBG_VALUE $noreg, 0514 DBG_VALUE $noreg, 0515 DBG_VALUE $noreg, 0516 DBG_VALUE $noreg, 0517 DBG_VALUE $noreg, 0518 DBG_VALUE $noreg, 0519 DBG_VALUE $noreg, 0520 DBG_VALUE $noreg, 0521 DBG_VALUE $noreg, 0522 DBG_VALUE $noreg, 0523 DBG_VALUE $noreg, 0524 DBG_VALUE $noreg, 0525 DBG_VALUE $noreg, 0526 DBG_VALUE $noreg, 0527 DBG_VALUE $noreg, 0528 DBG_VALUE $noreg, 0529 DBG_VALUE $noreg, 0530 DBG_VALUE $noreg, 0531 DBG_VALUE $noreg, 0532 DBG_VALUE $noreg, 0533 DBG_VALUE $noreg, 0534 DBG_VALUE $noreg, 0535 DBG_VALUE $noreg, 0536 DBG_VALUE $noreg, 0537 %2:vgpr_32, %3:sreg_64 = V_ADD_CO_U32_e64 %0, %1, 0, implicit $exec538 S_ENDPGM 0, implicit %2539 540...541---542 543# This requires searching through many DBG_VALUE instructions after the insert point, which544# should not count against the search limit.545 546name: vcc_liveness_dbg_value_search_after547tracksRegLiveness: true548 549body: |550 bb.0:551 ; GCN-LABEL: name: vcc_liveness_dbg_value_search_after552 ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345553 ; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF554 ; GCN-NEXT: S_NOP 0555 ; GCN-NEXT: S_NOP 0556 ; GCN-NEXT: S_NOP 0557 ; GCN-NEXT: S_NOP 0558 ; GCN-NEXT: S_NOP 0559 ; GCN-NEXT: S_NOP 0560 ; GCN-NEXT: S_NOP 0561 ; GCN-NEXT: S_NOP 0562 ; GCN-NEXT: S_NOP 0563 ; GCN-NEXT: S_NOP 0564 ; GCN-NEXT: S_NOP 0565 ; GCN-NEXT: S_NOP 0566 ; GCN-NEXT: S_NOP 0567 ; GCN-NEXT: S_NOP 0568 ; GCN-NEXT: S_NOP 0569 ; GCN-NEXT: S_NOP 0570 ; GCN-NEXT: S_NOP 0571 ; GCN-NEXT: S_NOP 0572 ; GCN-NEXT: S_NOP 0573 ; GCN-NEXT: S_NOP 0574 ; GCN-NEXT: S_NOP 0575 ; GCN-NEXT: S_NOP 0576 ; GCN-NEXT: S_NOP 0577 ; GCN-NEXT: S_NOP 0578 ; GCN-NEXT: S_NOP 0579 ; GCN-NEXT: S_NOP 0580 ; GCN-NEXT: S_NOP 0581 ; GCN-NEXT: S_NOP 0582 ; GCN-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def $vcc, implicit $exec583 ; GCN-NEXT: DBG_VALUE $noreg, 0584 ; GCN-NEXT: DBG_VALUE $noreg, 0585 ; GCN-NEXT: DBG_VALUE $noreg, 0586 ; GCN-NEXT: DBG_VALUE $noreg, 0587 ; GCN-NEXT: DBG_VALUE $noreg, 0588 ; GCN-NEXT: DBG_VALUE $noreg, 0589 ; GCN-NEXT: DBG_VALUE $noreg, 0590 ; GCN-NEXT: DBG_VALUE $noreg, 0591 ; GCN-NEXT: DBG_VALUE $noreg, 0592 ; GCN-NEXT: DBG_VALUE $noreg, 0593 ; GCN-NEXT: DBG_VALUE $noreg, 0594 ; GCN-NEXT: DBG_VALUE $noreg, 0595 ; GCN-NEXT: DBG_VALUE $noreg, 0596 ; GCN-NEXT: DBG_VALUE $noreg, 0597 ; GCN-NEXT: DBG_VALUE $noreg, 0598 ; GCN-NEXT: DBG_VALUE $noreg, 0599 ; GCN-NEXT: DBG_VALUE $noreg, 0600 ; GCN-NEXT: DBG_VALUE $noreg, 0601 ; GCN-NEXT: DBG_VALUE $noreg, 0602 ; GCN-NEXT: DBG_VALUE $noreg, 0603 ; GCN-NEXT: DBG_VALUE $noreg, 0604 ; GCN-NEXT: DBG_VALUE $noreg, 0605 ; GCN-NEXT: DBG_VALUE $noreg, 0606 ; GCN-NEXT: DBG_VALUE $noreg, 0607 ; GCN-NEXT: DBG_VALUE $noreg, 0608 ; GCN-NEXT: DBG_VALUE $noreg, 0609 ; GCN-NEXT: DBG_VALUE $noreg, 0610 ; GCN-NEXT: DBG_VALUE $noreg, 0611 ; GCN-NEXT: S_ENDPGM 0, implicit [[V_ADD_CO_U32_e32_]]612 %0:sreg_32_xm0 = S_MOV_B32 12345613 %1:vgpr_32 = IMPLICIT_DEF614 S_NOP 0615 S_NOP 0616 S_NOP 0617 S_NOP 0618 S_NOP 0619 S_NOP 0620 S_NOP 0621 S_NOP 0622 S_NOP 0623 S_NOP 0624 S_NOP 0625 S_NOP 0626 S_NOP 0627 S_NOP 0628 S_NOP 0629 S_NOP 0630 S_NOP 0631 S_NOP 0632 S_NOP 0633 S_NOP 0634 S_NOP 0635 S_NOP 0636 S_NOP 0637 S_NOP 0638 S_NOP 0639 S_NOP 0640 S_NOP 0641 S_NOP 0642 %2:vgpr_32, %3:sreg_64 = V_ADD_CO_U32_e64 %0, %1, 0, implicit $exec643 DBG_VALUE $noreg, 0644 DBG_VALUE $noreg, 0645 DBG_VALUE $noreg, 0646 DBG_VALUE $noreg, 0647 DBG_VALUE $noreg, 0648 DBG_VALUE $noreg, 0649 DBG_VALUE $noreg, 0650 DBG_VALUE $noreg, 0651 DBG_VALUE $noreg, 0652 DBG_VALUE $noreg, 0653 DBG_VALUE $noreg, 0654 DBG_VALUE $noreg, 0655 DBG_VALUE $noreg, 0656 DBG_VALUE $noreg, 0657 DBG_VALUE $noreg, 0658 DBG_VALUE $noreg, 0659 DBG_VALUE $noreg, 0660 DBG_VALUE $noreg, 0661 DBG_VALUE $noreg, 0662 DBG_VALUE $noreg, 0663 DBG_VALUE $noreg, 0664 DBG_VALUE $noreg, 0665 DBG_VALUE $noreg, 0666 DBG_VALUE $noreg, 0667 DBG_VALUE $noreg, 0668 DBG_VALUE $noreg, 0669 DBG_VALUE $noreg, 0670 DBG_VALUE $noreg, 0671 $vcc = S_MOV_B64 0672 S_ENDPGM 0, implicit %2673 674...675 676---677name: shrink_add_kill_flags_src0678tracksRegLiveness: true679body: |680 bb.0:681 liveins: $vgpr0682 ; GCN-LABEL: name: shrink_add_kill_flags_src0683 ; GCN: liveins: $vgpr0684 ; GCN-NEXT: {{ $}}685 ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0686 ; GCN-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 518144, implicit $exec687 ; GCN-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 killed [[V_MOV_B32_e32_]], [[COPY]], implicit-def $vcc, implicit $exec688 ; GCN-NEXT: S_ENDPGM 0, implicit [[V_ADD_CO_U32_e32_]]689 %0:vgpr_32 = COPY $vgpr0690 %1:vgpr_32 = V_MOV_B32_e32 518144, implicit $exec691 %2:vgpr_32, %3:sreg_64_xexec = V_ADD_CO_U32_e64 killed %1, %0, 0, implicit $exec692 S_ENDPGM 0, implicit %2693...694 695---696name: shrink_add_kill_flags_src1697tracksRegLiveness: true698body: |699 bb.0:700 liveins: $vgpr0701 ; GCN-LABEL: name: shrink_add_kill_flags_src1702 ; GCN: liveins: $vgpr0703 ; GCN-NEXT: {{ $}}704 ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0705 ; GCN-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 518144, implicit $exec706 ; GCN-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[V_MOV_B32_e32_]], killed [[COPY]], implicit-def $vcc, implicit $exec707 ; GCN-NEXT: S_ENDPGM 0, implicit [[V_ADD_CO_U32_e32_]]708 %0:vgpr_32 = COPY $vgpr0709 %1:vgpr_32 = V_MOV_B32_e32 518144, implicit $exec710 %2:vgpr_32, %3:sreg_64_xexec = V_ADD_CO_U32_e64 %1, killed %0, 0, implicit $exec711 S_ENDPGM 0, implicit %2712...713 714---715name: shrink_addc_kill_flags_src2716tracksRegLiveness: true717body: |718 bb.0:719 liveins: $vgpr0, $vcc720 ; GCN-LABEL: name: shrink_addc_kill_flags_src2721 ; GCN: liveins: $vgpr0, $vcc722 ; GCN-NEXT: {{ $}}723 ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0724 ; GCN-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 518144, implicit $exec725 ; GCN-NEXT: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY $vcc726 ; GCN-NEXT: [[V_ADDC_U32_e64_:%[0-9]+]]:vgpr_32, [[V_ADDC_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADDC_U32_e64 [[V_MOV_B32_e32_]], [[COPY]], [[COPY1]], 0, implicit $exec727 ; GCN-NEXT: S_ENDPGM 0, implicit [[V_ADDC_U32_e64_]]728 %0:vgpr_32 = COPY $vgpr0729 %1:vgpr_32 = V_MOV_B32_e32 518144, implicit $exec730 %2:sreg_64_xexec = COPY $vcc731 %3:vgpr_32, %4:sreg_64_xexec = V_ADDC_U32_e64 %1, %0, %2, 0, implicit $exec732 S_ENDPGM 0, implicit %3733...734