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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=fiji -mattr=-flat-for-global < %s | FileCheck -check-prefixes=VI %s3; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx1010 -mattr=-flat-for-global < %s | FileCheck -check-prefixes=GFX10 %s4; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -mattr=-flat-for-global < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s5; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -mattr=-flat-for-global < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s6 7declare i16 @llvm.umax.i16(i16, i16)8declare i64 @llvm.umin.i64(i64, i64)9 10declare <4 x float> @llvm.ldexp.v4f32.v4i32(<4 x float>, <4 x i32>)11 12define <4 x float> @fmul_pow2_4xfloat(<4 x i32> %i) {13; VI-LABEL: fmul_pow2_4xfloat:14; VI: ; %bb.0:15; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)16; VI-NEXT: v_lshlrev_b32_e64 v0, v0, 117; VI-NEXT: v_lshlrev_b32_e64 v1, v1, 118; VI-NEXT: v_lshlrev_b32_e64 v2, v2, 119; VI-NEXT: v_lshlrev_b32_e64 v3, v3, 120; VI-NEXT: v_cvt_f32_u32_e32 v0, v021; VI-NEXT: v_cvt_f32_u32_e32 v1, v122; VI-NEXT: v_cvt_f32_u32_e32 v2, v223; VI-NEXT: v_cvt_f32_u32_e32 v3, v324; VI-NEXT: v_mul_f32_e32 v0, 0x41100000, v025; VI-NEXT: v_mul_f32_e32 v1, 0x41100000, v126; VI-NEXT: v_mul_f32_e32 v2, 0x41100000, v227; VI-NEXT: v_mul_f32_e32 v3, 0x41100000, v328; VI-NEXT: s_setpc_b64 s[30:31]29;30; GFX10-LABEL: fmul_pow2_4xfloat:31; GFX10: ; %bb.0:32; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)33; GFX10-NEXT: v_lshlrev_b32_e64 v0, v0, 134; GFX10-NEXT: v_lshlrev_b32_e64 v1, v1, 135; GFX10-NEXT: v_lshlrev_b32_e64 v2, v2, 136; GFX10-NEXT: v_lshlrev_b32_e64 v3, v3, 137; GFX10-NEXT: v_cvt_f32_u32_e32 v0, v038; GFX10-NEXT: v_cvt_f32_u32_e32 v1, v139; GFX10-NEXT: v_cvt_f32_u32_e32 v2, v240; GFX10-NEXT: v_cvt_f32_u32_e32 v3, v341; GFX10-NEXT: v_mul_f32_e32 v0, 0x41100000, v042; GFX10-NEXT: v_mul_f32_e32 v1, 0x41100000, v143; GFX10-NEXT: v_mul_f32_e32 v2, 0x41100000, v244; GFX10-NEXT: v_mul_f32_e32 v3, 0x41100000, v345; GFX10-NEXT: s_setpc_b64 s[30:31]46;47; GFX11-LABEL: fmul_pow2_4xfloat:48; GFX11: ; %bb.0:49; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)50; GFX11-NEXT: v_lshlrev_b32_e64 v0, v0, 151; GFX11-NEXT: v_lshlrev_b32_e64 v1, v1, 152; GFX11-NEXT: v_lshlrev_b32_e64 v2, v2, 153; GFX11-NEXT: v_lshlrev_b32_e64 v3, v3, 154; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)55; GFX11-NEXT: v_cvt_f32_u32_e32 v0, v056; GFX11-NEXT: v_cvt_f32_u32_e32 v1, v157; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)58; GFX11-NEXT: v_cvt_f32_u32_e32 v2, v259; GFX11-NEXT: v_cvt_f32_u32_e32 v3, v360; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)61; GFX11-NEXT: v_dual_mul_f32 v0, 0x41100000, v0 :: v_dual_mul_f32 v1, 0x41100000, v162; GFX11-NEXT: v_dual_mul_f32 v2, 0x41100000, v2 :: v_dual_mul_f32 v3, 0x41100000, v363; GFX11-NEXT: s_setpc_b64 s[30:31]64 %p2 = shl <4 x i32> <i32 1, i32 1, i32 1, i32 1>, %i65 %p2_f = uitofp <4 x i32> %p2 to <4 x float>66 %r = fmul <4 x float> <float 9.000000e+00, float 9.000000e+00, float 9.000000e+00, float 9.000000e+00>, %p2_f67 ret <4 x float> %r68}69 70define <4 x float> @fmul_pow2_ldexp_4xfloat(<4 x i32> %i) {71; VI-LABEL: fmul_pow2_ldexp_4xfloat:72; VI: ; %bb.0:73; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)74; VI-NEXT: s_mov_b32 s4, 0x4110000075; VI-NEXT: v_ldexp_f32 v0, s4, v076; VI-NEXT: v_ldexp_f32 v1, s4, v177; VI-NEXT: v_ldexp_f32 v2, s4, v278; VI-NEXT: v_ldexp_f32 v3, s4, v379; VI-NEXT: s_setpc_b64 s[30:31]80;81; GFX10-LABEL: fmul_pow2_ldexp_4xfloat:82; GFX10: ; %bb.0:83; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)84; GFX10-NEXT: v_ldexp_f32 v0, 0x41100000, v085; GFX10-NEXT: v_ldexp_f32 v1, 0x41100000, v186; GFX10-NEXT: v_ldexp_f32 v2, 0x41100000, v287; GFX10-NEXT: v_ldexp_f32 v3, 0x41100000, v388; GFX10-NEXT: s_setpc_b64 s[30:31]89;90; GFX11-LABEL: fmul_pow2_ldexp_4xfloat:91; GFX11: ; %bb.0:92; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)93; GFX11-NEXT: v_ldexp_f32 v0, 0x41100000, v094; GFX11-NEXT: v_ldexp_f32 v1, 0x41100000, v195; GFX11-NEXT: v_ldexp_f32 v2, 0x41100000, v296; GFX11-NEXT: v_ldexp_f32 v3, 0x41100000, v397; GFX11-NEXT: s_setpc_b64 s[30:31]98 %r = call <4 x float> @llvm.ldexp.v4f32.v4i32(<4 x float> <float 9.000000e+00, float 9.000000e+00, float 9.000000e+00, float 9.000000e+00>, <4 x i32> %i)99 ret <4 x float> %r100}101 102define <4 x float> @fdiv_pow2_4xfloat(<4 x i32> %i) {103; VI-LABEL: fdiv_pow2_4xfloat:104; VI: ; %bb.0:105; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)106; VI-NEXT: v_lshlrev_b32_e32 v0, 23, v0107; VI-NEXT: v_lshlrev_b32_e32 v1, 23, v1108; VI-NEXT: v_lshlrev_b32_e32 v2, 23, v2109; VI-NEXT: v_lshlrev_b32_e32 v3, 23, v3110; VI-NEXT: v_sub_u32_e32 v0, vcc, 0x41100000, v0111; VI-NEXT: v_sub_u32_e32 v1, vcc, 0x41100000, v1112; VI-NEXT: v_sub_u32_e32 v2, vcc, 0x41100000, v2113; VI-NEXT: v_sub_u32_e32 v3, vcc, 0x41100000, v3114; VI-NEXT: s_setpc_b64 s[30:31]115;116; GFX10-LABEL: fdiv_pow2_4xfloat:117; GFX10: ; %bb.0:118; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)119; GFX10-NEXT: v_lshlrev_b32_e32 v0, 23, v0120; GFX10-NEXT: v_lshlrev_b32_e32 v1, 23, v1121; GFX10-NEXT: v_lshlrev_b32_e32 v2, 23, v2122; GFX10-NEXT: v_lshlrev_b32_e32 v3, 23, v3123; GFX10-NEXT: v_sub_nc_u32_e32 v0, 0x41100000, v0124; GFX10-NEXT: v_sub_nc_u32_e32 v1, 0x41100000, v1125; GFX10-NEXT: v_sub_nc_u32_e32 v2, 0x41100000, v2126; GFX10-NEXT: v_sub_nc_u32_e32 v3, 0x41100000, v3127; GFX10-NEXT: s_setpc_b64 s[30:31]128;129; GFX11-LABEL: fdiv_pow2_4xfloat:130; GFX11: ; %bb.0:131; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)132; GFX11-NEXT: v_lshlrev_b32_e32 v0, 23, v0133; GFX11-NEXT: v_lshlrev_b32_e32 v1, 23, v1134; GFX11-NEXT: v_lshlrev_b32_e32 v2, 23, v2135; GFX11-NEXT: v_lshlrev_b32_e32 v3, 23, v3136; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)137; GFX11-NEXT: v_sub_nc_u32_e32 v0, 0x41100000, v0138; GFX11-NEXT: v_sub_nc_u32_e32 v1, 0x41100000, v1139; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)140; GFX11-NEXT: v_sub_nc_u32_e32 v2, 0x41100000, v2141; GFX11-NEXT: v_sub_nc_u32_e32 v3, 0x41100000, v3142; GFX11-NEXT: s_setpc_b64 s[30:31]143 %p2 = shl <4 x i32> <i32 1, i32 1, i32 1, i32 1>, %i144 %p2_f = uitofp <4 x i32> %p2 to <4 x float>145 %r = fdiv <4 x float> <float 9.000000e+00, float 9.000000e+00, float 9.000000e+00, float 9.000000e+00>, %p2_f146 ret <4 x float> %r147}148 149declare <8 x half> @llvm.ldexp.v8f16.v8i16(<8 x half>, <8 x i16>)150 151define <8 x half> @fmul_pow2_8xhalf(<8 x i16> %i) {152; VI-LABEL: fmul_pow2_8xhalf:153; VI: ; %bb.0:154; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)155; VI-NEXT: v_mov_b32_e32 v5, 1156; VI-NEXT: v_lshlrev_b16_e64 v4, v3, 1157; VI-NEXT: v_lshlrev_b16_sdwa v3, v3, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD158; VI-NEXT: v_lshlrev_b16_e64 v6, v2, 1159; VI-NEXT: v_lshlrev_b16_sdwa v2, v2, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD160; VI-NEXT: v_lshlrev_b16_e64 v7, v1, 1161; VI-NEXT: v_lshlrev_b16_sdwa v1, v1, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD162; VI-NEXT: v_lshlrev_b16_e64 v8, v0, 1163; VI-NEXT: v_lshlrev_b16_sdwa v0, v0, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD164; VI-NEXT: v_cvt_f16_u16_e32 v0, v0165; VI-NEXT: v_cvt_f16_u16_e32 v5, v8166; VI-NEXT: v_cvt_f16_u16_e32 v1, v1167; VI-NEXT: v_cvt_f16_u16_e32 v7, v7168; VI-NEXT: v_cvt_f16_u16_e32 v2, v2169; VI-NEXT: v_cvt_f16_u16_e32 v6, v6170; VI-NEXT: v_cvt_f16_u16_e32 v3, v3171; VI-NEXT: v_cvt_f16_u16_e32 v4, v4172; VI-NEXT: v_mov_b32_e32 v8, 0x7000173; VI-NEXT: v_mul_f16_e32 v4, 0x7000, v4174; VI-NEXT: v_mul_f16_sdwa v3, v3, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD175; VI-NEXT: v_mul_f16_e32 v6, 0x7000, v6176; VI-NEXT: v_mul_f16_sdwa v2, v2, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD177; VI-NEXT: v_mul_f16_e32 v7, 0x7000, v7178; VI-NEXT: v_mul_f16_sdwa v1, v1, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD179; VI-NEXT: v_mul_f16_e32 v5, 0x7000, v5180; VI-NEXT: v_mul_f16_sdwa v0, v0, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD181; VI-NEXT: v_or_b32_e32 v0, v5, v0182; VI-NEXT: v_or_b32_e32 v1, v7, v1183; VI-NEXT: v_or_b32_e32 v2, v6, v2184; VI-NEXT: v_or_b32_e32 v3, v4, v3185; VI-NEXT: s_setpc_b64 s[30:31]186;187; GFX10-LABEL: fmul_pow2_8xhalf:188; GFX10: ; %bb.0:189; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)190; GFX10-NEXT: v_pk_lshlrev_b16 v3, v3, 1 op_sel_hi:[1,0]191; GFX10-NEXT: v_pk_lshlrev_b16 v2, v2, 1 op_sel_hi:[1,0]192; GFX10-NEXT: v_pk_lshlrev_b16 v1, v1, 1 op_sel_hi:[1,0]193; GFX10-NEXT: v_pk_lshlrev_b16 v0, v0, 1 op_sel_hi:[1,0]194; GFX10-NEXT: v_cvt_f16_u16_e32 v4, v3195; GFX10-NEXT: v_cvt_f16_u16_e32 v5, v2196; GFX10-NEXT: v_cvt_f16_u16_e32 v6, v1197; GFX10-NEXT: v_cvt_f16_u16_e32 v7, v0198; GFX10-NEXT: v_cvt_f16_u16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1199; GFX10-NEXT: v_cvt_f16_u16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1200; GFX10-NEXT: v_cvt_f16_u16_sdwa v2, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1201; GFX10-NEXT: v_cvt_f16_u16_sdwa v3, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1202; GFX10-NEXT: v_pack_b32_f16 v0, v7, v0203; GFX10-NEXT: v_pack_b32_f16 v1, v6, v1204; GFX10-NEXT: v_pack_b32_f16 v2, v5, v2205; GFX10-NEXT: v_pack_b32_f16 v3, v4, v3206; GFX10-NEXT: v_pk_mul_f16 v0, 0x7000, v0 op_sel_hi:[0,1]207; GFX10-NEXT: v_pk_mul_f16 v1, 0x7000, v1 op_sel_hi:[0,1]208; GFX10-NEXT: v_pk_mul_f16 v2, 0x7000, v2 op_sel_hi:[0,1]209; GFX10-NEXT: v_pk_mul_f16 v3, 0x7000, v3 op_sel_hi:[0,1]210; GFX10-NEXT: s_setpc_b64 s[30:31]211;212; GFX11-TRUE16-LABEL: fmul_pow2_8xhalf:213; GFX11-TRUE16: ; %bb.0:214; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)215; GFX11-TRUE16-NEXT: v_pk_lshlrev_b16 v3, v3, 1 op_sel_hi:[1,0]216; GFX11-TRUE16-NEXT: v_pk_lshlrev_b16 v4, v2, 1 op_sel_hi:[1,0]217; GFX11-TRUE16-NEXT: v_pk_lshlrev_b16 v2, v1, 1 op_sel_hi:[1,0]218; GFX11-TRUE16-NEXT: v_pk_lshlrev_b16 v5, v0, 1 op_sel_hi:[1,0]219; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)220; GFX11-TRUE16-NEXT: v_cvt_f16_u16_e32 v0.l, v3.l221; GFX11-TRUE16-NEXT: v_cvt_f16_u16_e32 v0.h, v4.l222; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)223; GFX11-TRUE16-NEXT: v_cvt_f16_u16_e32 v1.l, v2.l224; GFX11-TRUE16-NEXT: v_cvt_f16_u16_e32 v1.h, v5.l225; GFX11-TRUE16-NEXT: v_cvt_f16_u16_e32 v2.l, v5.h226; GFX11-TRUE16-NEXT: v_cvt_f16_u16_e32 v2.h, v2.h227; GFX11-TRUE16-NEXT: v_cvt_f16_u16_e32 v3.l, v4.h228; GFX11-TRUE16-NEXT: v_cvt_f16_u16_e32 v3.h, v3.h229; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)230; GFX11-TRUE16-NEXT: v_pack_b32_f16 v4, v1.h, v2.l231; GFX11-TRUE16-NEXT: v_pack_b32_f16 v1, v1.l, v2.h232; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)233; GFX11-TRUE16-NEXT: v_pack_b32_f16 v2, v0.h, v3.l234; GFX11-TRUE16-NEXT: v_pack_b32_f16 v3, v0.l, v3.h235; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)236; GFX11-TRUE16-NEXT: v_pk_mul_f16 v0, 0x7000, v4 op_sel_hi:[0,1]237; GFX11-TRUE16-NEXT: v_pk_mul_f16 v1, 0x7000, v1 op_sel_hi:[0,1]238; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)239; GFX11-TRUE16-NEXT: v_pk_mul_f16 v2, 0x7000, v2 op_sel_hi:[0,1]240; GFX11-TRUE16-NEXT: v_pk_mul_f16 v3, 0x7000, v3 op_sel_hi:[0,1]241; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]242;243; GFX11-FAKE16-LABEL: fmul_pow2_8xhalf:244; GFX11-FAKE16: ; %bb.0:245; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)246; GFX11-FAKE16-NEXT: v_pk_lshlrev_b16 v3, v3, 1 op_sel_hi:[1,0]247; GFX11-FAKE16-NEXT: v_pk_lshlrev_b16 v2, v2, 1 op_sel_hi:[1,0]248; GFX11-FAKE16-NEXT: v_pk_lshlrev_b16 v0, v0, 1 op_sel_hi:[1,0]249; GFX11-FAKE16-NEXT: v_pk_lshlrev_b16 v1, v1, 1 op_sel_hi:[1,0]250; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)251; GFX11-FAKE16-NEXT: v_cvt_f16_u16_e32 v4, v3252; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3253; GFX11-FAKE16-NEXT: v_cvt_f16_u16_e32 v5, v2254; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0255; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v1256; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2257; GFX11-FAKE16-NEXT: v_cvt_f16_u16_e32 v1, v1258; GFX11-FAKE16-NEXT: v_cvt_f16_u16_e32 v0, v0259; GFX11-FAKE16-NEXT: v_cvt_f16_u16_e32 v6, v6260; GFX11-FAKE16-NEXT: v_cvt_f16_u16_e32 v7, v7261; GFX11-FAKE16-NEXT: v_cvt_f16_u16_e32 v2, v2262; GFX11-FAKE16-NEXT: v_cvt_f16_u16_e32 v3, v3263; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)264; GFX11-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v6265; GFX11-FAKE16-NEXT: v_pack_b32_f16 v1, v1, v7266; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)267; GFX11-FAKE16-NEXT: v_pack_b32_f16 v2, v5, v2268; GFX11-FAKE16-NEXT: v_pack_b32_f16 v3, v4, v3269; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)270; GFX11-FAKE16-NEXT: v_pk_mul_f16 v0, 0x7000, v0 op_sel_hi:[0,1]271; GFX11-FAKE16-NEXT: v_pk_mul_f16 v1, 0x7000, v1 op_sel_hi:[0,1]272; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)273; GFX11-FAKE16-NEXT: v_pk_mul_f16 v2, 0x7000, v2 op_sel_hi:[0,1]274; GFX11-FAKE16-NEXT: v_pk_mul_f16 v3, 0x7000, v3 op_sel_hi:[0,1]275; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]276 %p2 = shl <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>, %i277 %p2_f = uitofp <8 x i16> %p2 to <8 x half>278 %r = fmul <8 x half> <half 0xH7000, half 0xH7000, half 0xH7000, half 0xH7000, half 0xH7000, half 0xH7000, half 0xH7000, half 0xH7000>, %p2_f279 ret <8 x half> %r280}281 282define <8 x half> @fmul_pow2_ldexp_8xhalf(<8 x i16> %i) {283; VI-LABEL: fmul_pow2_ldexp_8xhalf:284; VI: ; %bb.0:285; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)286; VI-NEXT: v_mov_b32_e32 v5, 0x7000287; VI-NEXT: v_ldexp_f16_e32 v4, 0x7000, v3288; VI-NEXT: v_ldexp_f16_sdwa v3, v5, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1289; VI-NEXT: v_ldexp_f16_e32 v6, 0x7000, v2290; VI-NEXT: v_ldexp_f16_sdwa v2, v5, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1291; VI-NEXT: v_ldexp_f16_e32 v7, 0x7000, v1292; VI-NEXT: v_ldexp_f16_sdwa v1, v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1293; VI-NEXT: v_ldexp_f16_e32 v8, 0x7000, v0294; VI-NEXT: v_ldexp_f16_sdwa v0, v5, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1295; VI-NEXT: v_or_b32_e32 v0, v8, v0296; VI-NEXT: v_or_b32_e32 v1, v7, v1297; VI-NEXT: v_or_b32_e32 v2, v6, v2298; VI-NEXT: v_or_b32_e32 v3, v4, v3299; VI-NEXT: s_setpc_b64 s[30:31]300;301; GFX10-LABEL: fmul_pow2_ldexp_8xhalf:302; GFX10: ; %bb.0:303; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)304; GFX10-NEXT: v_mov_b32_e32 v4, 0x7000305; GFX10-NEXT: v_ldexp_f16_e32 v5, 0x7000, v3306; GFX10-NEXT: v_ldexp_f16_e32 v6, 0x7000, v2307; GFX10-NEXT: v_ldexp_f16_e32 v7, 0x7000, v1308; GFX10-NEXT: v_ldexp_f16_e32 v8, 0x7000, v0309; GFX10-NEXT: v_ldexp_f16_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1310; GFX10-NEXT: v_ldexp_f16_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1311; GFX10-NEXT: v_ldexp_f16_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1312; GFX10-NEXT: v_ldexp_f16_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1313; GFX10-NEXT: v_pack_b32_f16 v0, v8, v0314; GFX10-NEXT: v_pack_b32_f16 v1, v7, v1315; GFX10-NEXT: v_pack_b32_f16 v2, v6, v2316; GFX10-NEXT: v_pack_b32_f16 v3, v5, v3317; GFX10-NEXT: s_setpc_b64 s[30:31]318;319; GFX11-TRUE16-LABEL: fmul_pow2_ldexp_8xhalf:320; GFX11-TRUE16: ; %bb.0:321; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)322; GFX11-TRUE16-NEXT: v_ldexp_f16_e32 v3.l, 0x7000, v3.l323; GFX11-TRUE16-NEXT: v_ldexp_f16_e32 v2.l, 0x7000, v2.l324; GFX11-TRUE16-NEXT: v_ldexp_f16_e32 v1.l, 0x7000, v1.l325; GFX11-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, 0x7000, v0.l326; GFX11-TRUE16-NEXT: v_ldexp_f16_e32 v0.h, 0x7000, v0.h327; GFX11-TRUE16-NEXT: v_ldexp_f16_e32 v1.h, 0x7000, v1.h328; GFX11-TRUE16-NEXT: v_ldexp_f16_e32 v2.h, 0x7000, v2.h329; GFX11-TRUE16-NEXT: v_ldexp_f16_e32 v3.h, 0x7000, v3.h330; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)331; GFX11-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v0.h332; GFX11-TRUE16-NEXT: v_pack_b32_f16 v1, v1.l, v1.h333; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)334; GFX11-TRUE16-NEXT: v_pack_b32_f16 v2, v2.l, v2.h335; GFX11-TRUE16-NEXT: v_pack_b32_f16 v3, v3.l, v3.h336; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]337;338; GFX11-FAKE16-LABEL: fmul_pow2_ldexp_8xhalf:339; GFX11-FAKE16: ; %bb.0:340; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)341; GFX11-FAKE16-NEXT: v_ldexp_f16_e32 v4, 0x7000, v3342; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3343; GFX11-FAKE16-NEXT: v_ldexp_f16_e32 v5, 0x7000, v2344; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0345; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v1346; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2347; GFX11-FAKE16-NEXT: v_ldexp_f16_e32 v1, 0x7000, v1348; GFX11-FAKE16-NEXT: v_ldexp_f16_e32 v0, 0x7000, v0349; GFX11-FAKE16-NEXT: v_ldexp_f16_e32 v6, 0x7000, v6350; GFX11-FAKE16-NEXT: v_ldexp_f16_e32 v7, 0x7000, v7351; GFX11-FAKE16-NEXT: v_ldexp_f16_e32 v2, 0x7000, v2352; GFX11-FAKE16-NEXT: v_ldexp_f16_e32 v3, 0x7000, v3353; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)354; GFX11-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v6355; GFX11-FAKE16-NEXT: v_pack_b32_f16 v1, v1, v7356; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)357; GFX11-FAKE16-NEXT: v_pack_b32_f16 v2, v5, v2358; GFX11-FAKE16-NEXT: v_pack_b32_f16 v3, v4, v3359; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]360 %r = call <8 x half> @llvm.ldexp.v8f16.v8i16(<8 x half> <half 0xH7000, half 0xH7000, half 0xH7000, half 0xH7000, half 0xH7000, half 0xH7000, half 0xH7000, half 0xH7000>, <8 x i16> %i)361 ret <8 x half> %r362}363 364define <8 x half> @fdiv_pow2_8xhalf(<8 x i16> %i) {365; VI-LABEL: fdiv_pow2_8xhalf:366; VI: ; %bb.0:367; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)368; VI-NEXT: v_mov_b32_e32 v4, 10369; VI-NEXT: v_lshlrev_b16_sdwa v5, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1370; VI-NEXT: v_mov_b32_e32 v6, 0x7000371; VI-NEXT: v_lshlrev_b16_e32 v3, 10, v3372; VI-NEXT: v_lshlrev_b16_sdwa v7, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1373; VI-NEXT: v_lshlrev_b16_e32 v2, 10, v2374; VI-NEXT: v_lshlrev_b16_sdwa v8, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1375; VI-NEXT: v_lshlrev_b16_e32 v1, 10, v1376; VI-NEXT: v_lshlrev_b16_sdwa v4, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1377; VI-NEXT: v_lshlrev_b16_e32 v0, 10, v0378; VI-NEXT: v_sub_u16_sdwa v5, v6, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD379; VI-NEXT: v_sub_u16_sdwa v7, v6, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD380; VI-NEXT: v_sub_u16_sdwa v8, v6, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD381; VI-NEXT: v_sub_u16_sdwa v4, v6, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD382; VI-NEXT: v_sub_u16_e32 v0, 0x7000, v0383; VI-NEXT: v_sub_u16_e32 v1, 0x7000, v1384; VI-NEXT: v_sub_u16_e32 v2, 0x7000, v2385; VI-NEXT: v_sub_u16_e32 v3, 0x7000, v3386; VI-NEXT: v_or_b32_e32 v0, v0, v4387; VI-NEXT: v_or_b32_e32 v1, v1, v8388; VI-NEXT: v_or_b32_e32 v2, v2, v7389; VI-NEXT: v_or_b32_e32 v3, v3, v5390; VI-NEXT: s_setpc_b64 s[30:31]391;392; GFX10-LABEL: fdiv_pow2_8xhalf:393; GFX10: ; %bb.0:394; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)395; GFX10-NEXT: v_pk_lshlrev_b16 v0, 10, v0 op_sel_hi:[0,1]396; GFX10-NEXT: v_pk_lshlrev_b16 v1, 10, v1 op_sel_hi:[0,1]397; GFX10-NEXT: v_pk_lshlrev_b16 v2, 10, v2 op_sel_hi:[0,1]398; GFX10-NEXT: v_pk_lshlrev_b16 v3, 10, v3 op_sel_hi:[0,1]399; GFX10-NEXT: v_pk_sub_i16 v0, 0x7000, v0 op_sel_hi:[0,1]400; GFX10-NEXT: v_pk_sub_i16 v1, 0x7000, v1 op_sel_hi:[0,1]401; GFX10-NEXT: v_pk_sub_i16 v2, 0x7000, v2 op_sel_hi:[0,1]402; GFX10-NEXT: v_pk_sub_i16 v3, 0x7000, v3 op_sel_hi:[0,1]403; GFX10-NEXT: s_setpc_b64 s[30:31]404;405; GFX11-LABEL: fdiv_pow2_8xhalf:406; GFX11: ; %bb.0:407; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)408; GFX11-NEXT: v_pk_lshlrev_b16 v0, 10, v0 op_sel_hi:[0,1]409; GFX11-NEXT: v_pk_lshlrev_b16 v1, 10, v1 op_sel_hi:[0,1]410; GFX11-NEXT: v_pk_lshlrev_b16 v2, 10, v2 op_sel_hi:[0,1]411; GFX11-NEXT: v_pk_lshlrev_b16 v3, 10, v3 op_sel_hi:[0,1]412; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)413; GFX11-NEXT: v_pk_sub_i16 v0, 0x7000, v0 op_sel_hi:[0,1]414; GFX11-NEXT: v_pk_sub_i16 v1, 0x7000, v1 op_sel_hi:[0,1]415; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)416; GFX11-NEXT: v_pk_sub_i16 v2, 0x7000, v2 op_sel_hi:[0,1]417; GFX11-NEXT: v_pk_sub_i16 v3, 0x7000, v3 op_sel_hi:[0,1]418; GFX11-NEXT: s_setpc_b64 s[30:31]419 %p2 = shl <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>, %i420 %p2_f = uitofp <8 x i16> %p2 to <8 x half>421 %r = fdiv <8 x half> <half 0xH7000, half 0xH7000, half 0xH7000, half 0xH7000, half 0xH7000, half 0xH7000, half 0xH7000, half 0xH7000>, %p2_f422 ret <8 x half> %r423}424 425define double @fmul_pow_shl_cnt(i64 %cnt) nounwind {426; VI-LABEL: fmul_pow_shl_cnt:427; VI: ; %bb.0:428; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)429; VI-NEXT: v_lshlrev_b64 v[0:1], v0, 1430; VI-NEXT: s_mov_b32 s4, 0431; VI-NEXT: v_cvt_f64_u32_e32 v[1:2], v1432; VI-NEXT: v_cvt_f64_u32_e32 v[3:4], v0433; VI-NEXT: s_mov_b32 s5, 0x40220000434; VI-NEXT: v_ldexp_f64 v[1:2], v[1:2], 32435; VI-NEXT: v_add_f64 v[0:1], v[1:2], v[3:4]436; VI-NEXT: v_mul_f64 v[0:1], v[0:1], s[4:5]437; VI-NEXT: s_setpc_b64 s[30:31]438;439; GFX10-LABEL: fmul_pow_shl_cnt:440; GFX10: ; %bb.0:441; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)442; GFX10-NEXT: v_lshlrev_b64 v[0:1], v0, 1443; GFX10-NEXT: v_cvt_f64_u32_e32 v[1:2], v1444; GFX10-NEXT: v_cvt_f64_u32_e32 v[3:4], v0445; GFX10-NEXT: v_ldexp_f64 v[0:1], v[1:2], 32446; GFX10-NEXT: v_add_f64 v[0:1], v[0:1], v[3:4]447; GFX10-NEXT: v_mul_f64 v[0:1], 0x40220000, v[0:1]448; GFX10-NEXT: s_setpc_b64 s[30:31]449;450; GFX11-LABEL: fmul_pow_shl_cnt:451; GFX11: ; %bb.0:452; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)453; GFX11-NEXT: v_lshlrev_b64 v[0:1], v0, 1454; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)455; GFX11-NEXT: v_cvt_f64_u32_e32 v[1:2], v1456; GFX11-NEXT: v_cvt_f64_u32_e32 v[3:4], v0457; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)458; GFX11-NEXT: v_ldexp_f64 v[0:1], v[1:2], 32459; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], v[3:4]460; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)461; GFX11-NEXT: v_mul_f64 v[0:1], 0x40220000, v[0:1]462; GFX11-NEXT: s_setpc_b64 s[30:31]463 %shl = shl nuw i64 1, %cnt464 %conv = uitofp i64 %shl to double465 %mul = fmul double 9.000000e+00, %conv466 ret double %mul467}468 469define double @fmul_pow_shl_cnt2(i64 %cnt) nounwind {470; VI-LABEL: fmul_pow_shl_cnt2:471; VI: ; %bb.0:472; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)473; VI-NEXT: v_lshlrev_b64 v[0:1], v0, 2474; VI-NEXT: s_mov_b32 s4, 0475; VI-NEXT: v_cvt_f64_u32_e32 v[1:2], v1476; VI-NEXT: v_cvt_f64_u32_e32 v[3:4], v0477; VI-NEXT: s_mov_b32 s5, 0xc0220000478; VI-NEXT: v_ldexp_f64 v[1:2], v[1:2], 32479; VI-NEXT: v_add_f64 v[0:1], v[1:2], v[3:4]480; VI-NEXT: v_mul_f64 v[0:1], v[0:1], s[4:5]481; VI-NEXT: s_setpc_b64 s[30:31]482;483; GFX10-LABEL: fmul_pow_shl_cnt2:484; GFX10: ; %bb.0:485; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)486; GFX10-NEXT: v_lshlrev_b64 v[0:1], v0, 2487; GFX10-NEXT: v_cvt_f64_u32_e32 v[1:2], v1488; GFX10-NEXT: v_cvt_f64_u32_e32 v[3:4], v0489; GFX10-NEXT: v_ldexp_f64 v[0:1], v[1:2], 32490; GFX10-NEXT: v_add_f64 v[0:1], v[0:1], v[3:4]491; GFX10-NEXT: v_mul_f64 v[0:1], 0xc0220000, v[0:1]492; GFX10-NEXT: s_setpc_b64 s[30:31]493;494; GFX11-LABEL: fmul_pow_shl_cnt2:495; GFX11: ; %bb.0:496; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)497; GFX11-NEXT: v_lshlrev_b64 v[0:1], v0, 2498; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)499; GFX11-NEXT: v_cvt_f64_u32_e32 v[1:2], v1500; GFX11-NEXT: v_cvt_f64_u32_e32 v[3:4], v0501; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)502; GFX11-NEXT: v_ldexp_f64 v[0:1], v[1:2], 32503; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], v[3:4]504; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)505; GFX11-NEXT: v_mul_f64 v[0:1], 0xc0220000, v[0:1]506; GFX11-NEXT: s_setpc_b64 s[30:31]507 %shl = shl nuw i64 2, %cnt508 %conv = uitofp i64 %shl to double509 %mul = fmul double -9.000000e+00, %conv510 ret double %mul511}512 513define float @fmul_pow_select(i32 %cnt, i1 %c) nounwind {514; VI-LABEL: fmul_pow_select:515; VI: ; %bb.0:516; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)517; VI-NEXT: v_and_b32_e32 v1, 1, v1518; VI-NEXT: v_cmp_eq_u32_e32 vcc, 1, v1519; VI-NEXT: v_cndmask_b32_e64 v1, 2, 1, vcc520; VI-NEXT: v_lshlrev_b32_e32 v0, v0, v1521; VI-NEXT: v_cvt_f32_u32_e32 v0, v0522; VI-NEXT: v_mul_f32_e32 v0, 0x41100000, v0523; VI-NEXT: s_setpc_b64 s[30:31]524;525; GFX10-LABEL: fmul_pow_select:526; GFX10: ; %bb.0:527; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)528; GFX10-NEXT: v_and_b32_e32 v1, 1, v1529; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1530; GFX10-NEXT: v_cndmask_b32_e64 v1, 2, 1, vcc_lo531; GFX10-NEXT: v_lshlrev_b32_e32 v0, v0, v1532; GFX10-NEXT: v_cvt_f32_u32_e32 v0, v0533; GFX10-NEXT: v_mul_f32_e32 v0, 0x41100000, v0534; GFX10-NEXT: s_setpc_b64 s[30:31]535;536; GFX11-LABEL: fmul_pow_select:537; GFX11: ; %bb.0:538; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)539; GFX11-NEXT: v_and_b32_e32 v1, 1, v1540; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)541; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1542; GFX11-NEXT: v_cndmask_b32_e64 v1, 2, 1, vcc_lo543; GFX11-NEXT: v_lshlrev_b32_e32 v0, v0, v1544; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)545; GFX11-NEXT: v_cvt_f32_u32_e32 v0, v0546; GFX11-NEXT: v_mul_f32_e32 v0, 0x41100000, v0547; GFX11-NEXT: s_setpc_b64 s[30:31]548 %shl2 = shl nuw i32 2, %cnt549 %shl1 = shl nuw i32 1, %cnt550 %shl = select i1 %c, i32 %shl1, i32 %shl2551 %conv = uitofp i32 %shl to float552 %mul = fmul float 9.000000e+00, %conv553 ret float %mul554}555 556define float @fmul_fly_pow_mul_min_pow2(i64 %cnt) nounwind {557; VI-LABEL: fmul_fly_pow_mul_min_pow2:558; VI: ; %bb.0:559; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)560; VI-NEXT: v_lshlrev_b64 v[0:1], v0, 8561; VI-NEXT: s_mov_b64 s[4:5], 0x2000562; VI-NEXT: v_cmp_gt_u64_e32 vcc, s[4:5], v[0:1]563; VI-NEXT: v_mov_b32_e32 v2, 0x2000564; VI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc565; VI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc566; VI-NEXT: v_ffbh_u32_e32 v2, v1567; VI-NEXT: v_min_u32_e32 v2, 32, v2568; VI-NEXT: v_lshlrev_b64 v[0:1], v2, v[0:1]569; VI-NEXT: v_min_u32_e32 v0, 1, v0570; VI-NEXT: v_or_b32_e32 v0, v1, v0571; VI-NEXT: v_cvt_f32_u32_e32 v0, v0572; VI-NEXT: v_sub_u32_e32 v1, vcc, 32, v2573; VI-NEXT: v_ldexp_f32 v0, v0, v1574; VI-NEXT: v_mul_f32_e32 v0, 0x41100000, v0575; VI-NEXT: s_setpc_b64 s[30:31]576;577; GFX10-LABEL: fmul_fly_pow_mul_min_pow2:578; GFX10: ; %bb.0:579; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)580; GFX10-NEXT: v_lshlrev_b64 v[0:1], v0, 8581; GFX10-NEXT: v_cmp_gt_u64_e32 vcc_lo, 0x2000, v[0:1]582; GFX10-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc_lo583; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x2000, v0, vcc_lo584; GFX10-NEXT: v_ffbh_u32_e32 v2, v1585; GFX10-NEXT: v_min_u32_e32 v2, 32, v2586; GFX10-NEXT: v_lshlrev_b64 v[0:1], v2, v[0:1]587; GFX10-NEXT: v_min_u32_e32 v0, 1, v0588; GFX10-NEXT: v_or_b32_e32 v0, v1, v0589; GFX10-NEXT: v_sub_nc_u32_e32 v1, 32, v2590; GFX10-NEXT: v_cvt_f32_u32_e32 v0, v0591; GFX10-NEXT: v_ldexp_f32 v0, v0, v1592; GFX10-NEXT: v_mul_f32_e32 v0, 0x41100000, v0593; GFX10-NEXT: s_setpc_b64 s[30:31]594;595; GFX11-LABEL: fmul_fly_pow_mul_min_pow2:596; GFX11: ; %bb.0:597; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)598; GFX11-NEXT: v_lshlrev_b64 v[0:1], v0, 8599; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)600; GFX11-NEXT: v_cmp_gt_u64_e32 vcc_lo, 0x2000, v[0:1]601; GFX11-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc_lo602; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x2000, v0, vcc_lo603; GFX11-NEXT: v_clz_i32_u32_e32 v2, v1604; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)605; GFX11-NEXT: v_min_u32_e32 v2, 32, v2606; GFX11-NEXT: v_lshlrev_b64 v[0:1], v2, v[0:1]607; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)608; GFX11-NEXT: v_min_u32_e32 v0, 1, v0609; GFX11-NEXT: v_or_b32_e32 v0, v1, v0610; GFX11-NEXT: v_sub_nc_u32_e32 v1, 32, v2611; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)612; GFX11-NEXT: v_cvt_f32_u32_e32 v0, v0613; GFX11-NEXT: v_ldexp_f32 v0, v0, v1614; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)615; GFX11-NEXT: v_mul_f32_e32 v0, 0x41100000, v0616; GFX11-NEXT: s_setpc_b64 s[30:31]617 %shl8 = shl nuw i64 8, %cnt618 %shl = call i64 @llvm.umin.i64(i64 %shl8, i64 8192)619 %conv = uitofp i64 %shl to float620 %mul = fmul float 9.000000e+00, %conv621 ret float %mul622}623 624define double @fmul_pow_mul_max_pow2(i16 %cnt) nounwind {625; VI-LABEL: fmul_pow_mul_max_pow2:626; VI: ; %bb.0:627; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)628; VI-NEXT: v_lshlrev_b16_e64 v0, v0, 2629; VI-NEXT: v_cvt_f64_u32_e32 v[0:1], v0630; VI-NEXT: s_mov_b32 s4, 0631; VI-NEXT: s_mov_b32 s5, 0x40080000632; VI-NEXT: v_mul_f64 v[0:1], v[0:1], s[4:5]633; VI-NEXT: s_setpc_b64 s[30:31]634;635; GFX10-LABEL: fmul_pow_mul_max_pow2:636; GFX10: ; %bb.0:637; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)638; GFX10-NEXT: v_lshlrev_b16 v0, v0, 2639; GFX10-NEXT: v_and_b32_e32 v0, 0xffff, v0640; GFX10-NEXT: v_cvt_f64_u32_e32 v[0:1], v0641; GFX10-NEXT: v_mul_f64 v[0:1], 0x40080000, v[0:1]642; GFX10-NEXT: s_setpc_b64 s[30:31]643;644; GFX11-TRUE16-LABEL: fmul_pow_mul_max_pow2:645; GFX11-TRUE16: ; %bb.0:646; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)647; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, 0648; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, v0.l, 2649; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)650; GFX11-TRUE16-NEXT: v_cvt_f64_u32_e32 v[0:1], v0651; GFX11-TRUE16-NEXT: v_mul_f64 v[0:1], 0x40080000, v[0:1]652; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]653;654; GFX11-FAKE16-LABEL: fmul_pow_mul_max_pow2:655; GFX11-FAKE16: ; %bb.0:656; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)657; GFX11-FAKE16-NEXT: v_lshlrev_b16 v0, v0, 2658; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)659; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0660; GFX11-FAKE16-NEXT: v_cvt_f64_u32_e32 v[0:1], v0661; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)662; GFX11-FAKE16-NEXT: v_mul_f64 v[0:1], 0x40080000, v[0:1]663; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]664 %shl2 = shl nuw i16 2, %cnt665 %shl1 = shl nuw i16 1, %cnt666 %shl = call i16 @llvm.umax.i16(i16 %shl1, i16 %shl2)667 %conv = uitofp i16 %shl to double668 %mul = fmul double 3.000000e+00, %conv669 ret double %mul670}671 672define double @fmul_pow_shl_cnt_fail_maybe_non_pow2(i64 %v, i64 %cnt) nounwind {673; VI-LABEL: fmul_pow_shl_cnt_fail_maybe_non_pow2:674; VI: ; %bb.0:675; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)676; VI-NEXT: v_lshlrev_b64 v[0:1], v2, v[0:1]677; VI-NEXT: s_mov_b32 s4, 0678; VI-NEXT: v_cvt_f64_u32_e32 v[1:2], v1679; VI-NEXT: v_cvt_f64_u32_e32 v[3:4], v0680; VI-NEXT: s_mov_b32 s5, 0x40220000681; VI-NEXT: v_ldexp_f64 v[1:2], v[1:2], 32682; VI-NEXT: v_add_f64 v[0:1], v[1:2], v[3:4]683; VI-NEXT: v_mul_f64 v[0:1], v[0:1], s[4:5]684; VI-NEXT: s_setpc_b64 s[30:31]685;686; GFX10-LABEL: fmul_pow_shl_cnt_fail_maybe_non_pow2:687; GFX10: ; %bb.0:688; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)689; GFX10-NEXT: v_lshlrev_b64 v[0:1], v2, v[0:1]690; GFX10-NEXT: v_cvt_f64_u32_e32 v[1:2], v1691; GFX10-NEXT: v_cvt_f64_u32_e32 v[3:4], v0692; GFX10-NEXT: v_ldexp_f64 v[0:1], v[1:2], 32693; GFX10-NEXT: v_add_f64 v[0:1], v[0:1], v[3:4]694; GFX10-NEXT: v_mul_f64 v[0:1], 0x40220000, v[0:1]695; GFX10-NEXT: s_setpc_b64 s[30:31]696;697; GFX11-LABEL: fmul_pow_shl_cnt_fail_maybe_non_pow2:698; GFX11: ; %bb.0:699; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)700; GFX11-NEXT: v_lshlrev_b64 v[0:1], v2, v[0:1]701; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)702; GFX11-NEXT: v_cvt_f64_u32_e32 v[1:2], v1703; GFX11-NEXT: v_cvt_f64_u32_e32 v[3:4], v0704; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)705; GFX11-NEXT: v_ldexp_f64 v[0:1], v[1:2], 32706; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], v[3:4]707; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)708; GFX11-NEXT: v_mul_f64 v[0:1], 0x40220000, v[0:1]709; GFX11-NEXT: s_setpc_b64 s[30:31]710 %shl = shl nuw i64 %v, %cnt711 %conv = uitofp i64 %shl to double712 %mul = fmul double 9.000000e+00, %conv713 ret double %mul714}715 716define <2 x float> @fmul_pow_shl_cnt_vec_fail_expensive_cast(<2 x i64> %cnt) nounwind {717; VI-LABEL: fmul_pow_shl_cnt_vec_fail_expensive_cast:718; VI: ; %bb.0:719; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)720; VI-NEXT: v_lshlrev_b64 v[1:2], v2, 2721; VI-NEXT: v_ffbh_u32_e32 v3, v2722; VI-NEXT: v_min_u32_e32 v5, 32, v3723; VI-NEXT: v_lshlrev_b64 v[1:2], v5, v[1:2]724; VI-NEXT: v_lshlrev_b64 v[3:4], v0, 2725; VI-NEXT: v_min_u32_e32 v0, 1, v1726; VI-NEXT: v_or_b32_e32 v0, v2, v0727; VI-NEXT: v_cvt_f32_u32_e32 v2, v0728; VI-NEXT: v_ffbh_u32_e32 v0, v4729; VI-NEXT: v_min_u32_e32 v6, 32, v0730; VI-NEXT: v_lshlrev_b64 v[0:1], v6, v[3:4]731; VI-NEXT: v_sub_u32_e32 v3, vcc, 32, v5732; VI-NEXT: v_min_u32_e32 v0, 1, v0733; VI-NEXT: v_or_b32_e32 v0, v1, v0734; VI-NEXT: v_cvt_f32_u32_e32 v0, v0735; VI-NEXT: v_ldexp_f32 v1, v2, v3736; VI-NEXT: v_sub_u32_e32 v2, vcc, 32, v6737; VI-NEXT: v_ldexp_f32 v0, v0, v2738; VI-NEXT: v_mul_f32_e32 v0, 0x41700000, v0739; VI-NEXT: v_mul_f32_e32 v1, 0x41700000, v1740; VI-NEXT: s_setpc_b64 s[30:31]741;742; GFX10-LABEL: fmul_pow_shl_cnt_vec_fail_expensive_cast:743; GFX10: ; %bb.0:744; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)745; GFX10-NEXT: v_lshlrev_b64 v[0:1], v0, 2746; GFX10-NEXT: v_lshlrev_b64 v[2:3], v2, 2747; GFX10-NEXT: v_ffbh_u32_e32 v4, v1748; GFX10-NEXT: v_ffbh_u32_e32 v5, v3749; GFX10-NEXT: v_min_u32_e32 v4, 32, v4750; GFX10-NEXT: v_min_u32_e32 v5, 32, v5751; GFX10-NEXT: v_lshlrev_b64 v[0:1], v4, v[0:1]752; GFX10-NEXT: v_lshlrev_b64 v[2:3], v5, v[2:3]753; GFX10-NEXT: v_min_u32_e32 v0, 1, v0754; GFX10-NEXT: v_min_u32_e32 v2, 1, v2755; GFX10-NEXT: v_or_b32_e32 v0, v1, v0756; GFX10-NEXT: v_or_b32_e32 v1, v3, v2757; GFX10-NEXT: v_sub_nc_u32_e32 v2, 32, v5758; GFX10-NEXT: v_sub_nc_u32_e32 v3, 32, v4759; GFX10-NEXT: v_cvt_f32_u32_e32 v0, v0760; GFX10-NEXT: v_cvt_f32_u32_e32 v1, v1761; GFX10-NEXT: v_ldexp_f32 v0, v0, v3762; GFX10-NEXT: v_ldexp_f32 v1, v1, v2763; GFX10-NEXT: v_mul_f32_e32 v0, 0x41700000, v0764; GFX10-NEXT: v_mul_f32_e32 v1, 0x41700000, v1765; GFX10-NEXT: s_setpc_b64 s[30:31]766;767; GFX11-LABEL: fmul_pow_shl_cnt_vec_fail_expensive_cast:768; GFX11: ; %bb.0:769; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)770; GFX11-NEXT: v_lshlrev_b64 v[0:1], v0, 2771; GFX11-NEXT: v_lshlrev_b64 v[2:3], v2, 2772; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)773; GFX11-NEXT: v_clz_i32_u32_e32 v4, v1774; GFX11-NEXT: v_clz_i32_u32_e32 v5, v3775; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)776; GFX11-NEXT: v_min_u32_e32 v4, 32, v4777; GFX11-NEXT: v_min_u32_e32 v5, 32, v5778; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)779; GFX11-NEXT: v_lshlrev_b64 v[0:1], v4, v[0:1]780; GFX11-NEXT: v_lshlrev_b64 v[2:3], v5, v[2:3]781; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)782; GFX11-NEXT: v_min_u32_e32 v0, 1, v0783; GFX11-NEXT: v_min_u32_e32 v2, 1, v2784; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)785; GFX11-NEXT: v_or_b32_e32 v0, v1, v0786; GFX11-NEXT: v_or_b32_e32 v1, v3, v2787; GFX11-NEXT: v_sub_nc_u32_e32 v2, 32, v5788; GFX11-NEXT: v_sub_nc_u32_e32 v3, 32, v4789; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)790; GFX11-NEXT: v_cvt_f32_u32_e32 v0, v0791; GFX11-NEXT: v_cvt_f32_u32_e32 v1, v1792; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)793; GFX11-NEXT: v_ldexp_f32 v0, v0, v3794; GFX11-NEXT: v_ldexp_f32 v1, v1, v2795; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)796; GFX11-NEXT: v_dual_mul_f32 v0, 0x41700000, v0 :: v_dual_mul_f32 v1, 0x41700000, v1797; GFX11-NEXT: s_setpc_b64 s[30:31]798 %shl = shl nsw nuw <2 x i64> <i64 2, i64 2>, %cnt799 %conv = uitofp <2 x i64> %shl to <2 x float>800 %mul = fmul <2 x float> <float 15.000000e+00, float 15.000000e+00>, %conv801 ret <2 x float> %mul802}803 804define <2 x double> @fmul_pow_shl_cnt_vec(<2 x i64> %cnt) nounwind {805; VI-LABEL: fmul_pow_shl_cnt_vec:806; VI: ; %bb.0:807; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)808; VI-NEXT: v_lshlrev_b64 v[0:1], v0, 2809; VI-NEXT: v_lshlrev_b64 v[2:3], v2, 2810; VI-NEXT: v_cvt_f64_u32_e32 v[4:5], v1811; VI-NEXT: v_cvt_f64_u32_e32 v[6:7], v3812; VI-NEXT: v_cvt_f64_u32_e32 v[0:1], v0813; VI-NEXT: s_mov_b32 s4, 0814; VI-NEXT: v_ldexp_f64 v[3:4], v[4:5], 32815; VI-NEXT: v_ldexp_f64 v[5:6], v[6:7], 32816; VI-NEXT: v_cvt_f64_u32_e32 v[7:8], v2817; VI-NEXT: s_mov_b32 s5, 0x402e0000818; VI-NEXT: v_add_f64 v[0:1], v[3:4], v[0:1]819; VI-NEXT: v_add_f64 v[2:3], v[5:6], v[7:8]820; VI-NEXT: v_mul_f64 v[0:1], v[0:1], s[4:5]821; VI-NEXT: v_mul_f64 v[2:3], v[2:3], s[4:5]822; VI-NEXT: s_setpc_b64 s[30:31]823;824; GFX10-LABEL: fmul_pow_shl_cnt_vec:825; GFX10: ; %bb.0:826; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)827; GFX10-NEXT: v_lshlrev_b64 v[0:1], v0, 2828; GFX10-NEXT: v_lshlrev_b64 v[2:3], v2, 2829; GFX10-NEXT: v_cvt_f64_u32_e32 v[4:5], v1830; GFX10-NEXT: v_cvt_f64_u32_e32 v[6:7], v3831; GFX10-NEXT: v_cvt_f64_u32_e32 v[0:1], v0832; GFX10-NEXT: v_cvt_f64_u32_e32 v[8:9], v2833; GFX10-NEXT: v_ldexp_f64 v[3:4], v[4:5], 32834; GFX10-NEXT: v_ldexp_f64 v[5:6], v[6:7], 32835; GFX10-NEXT: v_add_f64 v[0:1], v[3:4], v[0:1]836; GFX10-NEXT: v_add_f64 v[2:3], v[5:6], v[8:9]837; GFX10-NEXT: v_mul_f64 v[0:1], 0x402e0000, v[0:1]838; GFX10-NEXT: v_mul_f64 v[2:3], 0x402e0000, v[2:3]839; GFX10-NEXT: s_setpc_b64 s[30:31]840;841; GFX11-LABEL: fmul_pow_shl_cnt_vec:842; GFX11: ; %bb.0:843; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)844; GFX11-NEXT: v_lshlrev_b64 v[0:1], v0, 2845; GFX11-NEXT: v_lshlrev_b64 v[2:3], v2, 2846; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)847; GFX11-NEXT: v_cvt_f64_u32_e32 v[4:5], v1848; GFX11-NEXT: v_cvt_f64_u32_e32 v[6:7], v3849; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)850; GFX11-NEXT: v_cvt_f64_u32_e32 v[0:1], v0851; GFX11-NEXT: v_cvt_f64_u32_e32 v[8:9], v2852; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)853; GFX11-NEXT: v_ldexp_f64 v[3:4], v[4:5], 32854; GFX11-NEXT: v_ldexp_f64 v[5:6], v[6:7], 32855; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)856; GFX11-NEXT: v_add_f64 v[0:1], v[3:4], v[0:1]857; GFX11-NEXT: v_add_f64 v[2:3], v[5:6], v[8:9]858; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)859; GFX11-NEXT: v_mul_f64 v[0:1], 0x402e0000, v[0:1]860; GFX11-NEXT: v_mul_f64 v[2:3], 0x402e0000, v[2:3]861; GFX11-NEXT: s_setpc_b64 s[30:31]862 %shl = shl nsw nuw <2 x i64> <i64 2, i64 2>, %cnt863 %conv = uitofp <2 x i64> %shl to <2 x double>864 %mul = fmul <2 x double> <double 15.000000e+00, double 15.000000e+00>, %conv865 ret <2 x double> %mul866}867 868define <4 x float> @fmul_pow_shl_cnt_vec_preserve_fma(<4 x i32> %cnt, <4 x float> %add) nounwind {869; VI-LABEL: fmul_pow_shl_cnt_vec_preserve_fma:870; VI: ; %bb.0:871; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)872; VI-NEXT: v_lshlrev_b32_e64 v3, v3, 2873; VI-NEXT: v_lshlrev_b32_e64 v2, v2, 2874; VI-NEXT: v_lshlrev_b32_e64 v1, v1, 2875; VI-NEXT: v_lshlrev_b32_e64 v0, v0, 2876; VI-NEXT: v_cvt_f32_u32_e32 v3, v3877; VI-NEXT: v_cvt_f32_u32_e32 v2, v2878; VI-NEXT: v_cvt_f32_u32_e32 v1, v1879; VI-NEXT: v_cvt_f32_u32_e32 v0, v0880; VI-NEXT: v_mul_f32_e32 v3, 0x40a00000, v3881; VI-NEXT: v_mul_f32_e32 v2, 0x40a00000, v2882; VI-NEXT: v_mul_f32_e32 v1, 0x40a00000, v1883; VI-NEXT: v_mul_f32_e32 v0, 0x40a00000, v0884; VI-NEXT: v_add_f32_e32 v0, v0, v4885; VI-NEXT: v_add_f32_e32 v1, v1, v5886; VI-NEXT: v_add_f32_e32 v2, v2, v6887; VI-NEXT: v_add_f32_e32 v3, v3, v7888; VI-NEXT: s_setpc_b64 s[30:31]889;890; GFX10-LABEL: fmul_pow_shl_cnt_vec_preserve_fma:891; GFX10: ; %bb.0:892; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)893; GFX10-NEXT: v_lshlrev_b32_e64 v0, v0, 2894; GFX10-NEXT: v_lshlrev_b32_e64 v1, v1, 2895; GFX10-NEXT: v_lshlrev_b32_e64 v2, v2, 2896; GFX10-NEXT: v_lshlrev_b32_e64 v3, v3, 2897; GFX10-NEXT: v_cvt_f32_u32_e32 v0, v0898; GFX10-NEXT: v_cvt_f32_u32_e32 v1, v1899; GFX10-NEXT: v_cvt_f32_u32_e32 v2, v2900; GFX10-NEXT: v_cvt_f32_u32_e32 v3, v3901; GFX10-NEXT: v_mul_f32_e32 v0, 0x40a00000, v0902; GFX10-NEXT: v_mul_f32_e32 v1, 0x40a00000, v1903; GFX10-NEXT: v_mul_f32_e32 v2, 0x40a00000, v2904; GFX10-NEXT: v_mul_f32_e32 v3, 0x40a00000, v3905; GFX10-NEXT: v_add_f32_e32 v0, v0, v4906; GFX10-NEXT: v_add_f32_e32 v1, v1, v5907; GFX10-NEXT: v_add_f32_e32 v2, v2, v6908; GFX10-NEXT: v_add_f32_e32 v3, v3, v7909; GFX10-NEXT: s_setpc_b64 s[30:31]910;911; GFX11-LABEL: fmul_pow_shl_cnt_vec_preserve_fma:912; GFX11: ; %bb.0:913; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)914; GFX11-NEXT: v_lshlrev_b32_e64 v0, v0, 2915; GFX11-NEXT: v_lshlrev_b32_e64 v1, v1, 2916; GFX11-NEXT: v_lshlrev_b32_e64 v2, v2, 2917; GFX11-NEXT: v_lshlrev_b32_e64 v3, v3, 2918; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)919; GFX11-NEXT: v_cvt_f32_u32_e32 v0, v0920; GFX11-NEXT: v_cvt_f32_u32_e32 v1, v1921; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)922; GFX11-NEXT: v_cvt_f32_u32_e32 v2, v2923; GFX11-NEXT: v_cvt_f32_u32_e32 v3, v3924; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)925; GFX11-NEXT: v_dual_mul_f32 v0, 0x40a00000, v0 :: v_dual_mul_f32 v1, 0x40a00000, v1926; GFX11-NEXT: v_dual_mul_f32 v2, 0x40a00000, v2 :: v_dual_mul_f32 v3, 0x40a00000, v3927; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)928; GFX11-NEXT: v_dual_add_f32 v0, v0, v4 :: v_dual_add_f32 v1, v1, v5929; GFX11-NEXT: v_dual_add_f32 v2, v2, v6 :: v_dual_add_f32 v3, v3, v7930; GFX11-NEXT: s_setpc_b64 s[30:31]931 %shl = shl nsw nuw <4 x i32> <i32 2, i32 2, i32 2, i32 2>, %cnt932 %conv = uitofp <4 x i32> %shl to <4 x float>933 %mul = fmul <4 x float> <float 5.000000e+00, float 5.000000e+00, float 5.000000e+00, float 5.000000e+00>, %conv934 %res = fadd <4 x float> %mul, %add935 ret <4 x float> %res936}937 938define <2 x double> @fmul_pow_shl_cnt_vec_non_splat_todo(<2 x i64> %cnt) nounwind {939; VI-LABEL: fmul_pow_shl_cnt_vec_non_splat_todo:940; VI: ; %bb.0:941; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)942; VI-NEXT: v_lshlrev_b64 v[0:1], v0, 2943; VI-NEXT: s_mov_b32 s4, 0944; VI-NEXT: v_cvt_f64_u32_e32 v[3:4], v1945; VI-NEXT: v_lshlrev_b64 v[1:2], v2, 2946; VI-NEXT: s_mov_b32 s5, 0x402e0000947; VI-NEXT: v_cvt_f64_u32_e32 v[5:6], v2948; VI-NEXT: v_ldexp_f64 v[2:3], v[3:4], 32949; VI-NEXT: v_ldexp_f64 v[4:5], v[5:6], 32950; VI-NEXT: v_cvt_f64_u32_e32 v[6:7], v0951; VI-NEXT: v_cvt_f64_u32_e32 v[0:1], v1952; VI-NEXT: v_add_f64 v[2:3], v[2:3], v[6:7]953; VI-NEXT: v_add_f64 v[4:5], v[4:5], v[0:1]954; VI-NEXT: v_mul_f64 v[0:1], v[2:3], s[4:5]955; VI-NEXT: s_mov_b32 s4, 0956; VI-NEXT: s_mov_b32 s5, 0x402c0000957; VI-NEXT: v_mul_f64 v[2:3], v[4:5], s[4:5]958; VI-NEXT: s_setpc_b64 s[30:31]959;960; GFX10-LABEL: fmul_pow_shl_cnt_vec_non_splat_todo:961; GFX10: ; %bb.0:962; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)963; GFX10-NEXT: v_lshlrev_b64 v[0:1], v0, 2964; GFX10-NEXT: v_lshlrev_b64 v[2:3], v2, 2965; GFX10-NEXT: v_cvt_f64_u32_e32 v[4:5], v1966; GFX10-NEXT: v_cvt_f64_u32_e32 v[6:7], v3967; GFX10-NEXT: v_cvt_f64_u32_e32 v[0:1], v0968; GFX10-NEXT: v_cvt_f64_u32_e32 v[8:9], v2969; GFX10-NEXT: v_ldexp_f64 v[3:4], v[4:5], 32970; GFX10-NEXT: v_ldexp_f64 v[5:6], v[6:7], 32971; GFX10-NEXT: v_add_f64 v[0:1], v[3:4], v[0:1]972; GFX10-NEXT: v_add_f64 v[2:3], v[5:6], v[8:9]973; GFX10-NEXT: v_mul_f64 v[0:1], 0x402e0000, v[0:1]974; GFX10-NEXT: v_mul_f64 v[2:3], 0x402c0000, v[2:3]975; GFX10-NEXT: s_setpc_b64 s[30:31]976;977; GFX11-LABEL: fmul_pow_shl_cnt_vec_non_splat_todo:978; GFX11: ; %bb.0:979; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)980; GFX11-NEXT: v_lshlrev_b64 v[0:1], v0, 2981; GFX11-NEXT: v_lshlrev_b64 v[2:3], v2, 2982; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)983; GFX11-NEXT: v_cvt_f64_u32_e32 v[4:5], v1984; GFX11-NEXT: v_cvt_f64_u32_e32 v[6:7], v3985; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)986; GFX11-NEXT: v_cvt_f64_u32_e32 v[0:1], v0987; GFX11-NEXT: v_cvt_f64_u32_e32 v[8:9], v2988; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)989; GFX11-NEXT: v_ldexp_f64 v[3:4], v[4:5], 32990; GFX11-NEXT: v_ldexp_f64 v[5:6], v[6:7], 32991; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)992; GFX11-NEXT: v_add_f64 v[0:1], v[3:4], v[0:1]993; GFX11-NEXT: v_add_f64 v[2:3], v[5:6], v[8:9]994; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)995; GFX11-NEXT: v_mul_f64 v[0:1], 0x402e0000, v[0:1]996; GFX11-NEXT: v_mul_f64 v[2:3], 0x402c0000, v[2:3]997; GFX11-NEXT: s_setpc_b64 s[30:31]998 %shl = shl nsw nuw <2 x i64> <i64 2, i64 2>, %cnt999 %conv = uitofp <2 x i64> %shl to <2 x double>1000 %mul = fmul <2 x double> <double 15.000000e+00, double 14.000000e+00>, %conv1001 ret <2 x double> %mul1002}1003 1004define <2 x double> @fmul_pow_shl_cnt_vec_non_splat2_todo(<2 x i64> %cnt) nounwind {1005; VI-LABEL: fmul_pow_shl_cnt_vec_non_splat2_todo:1006; VI: ; %bb.0:1007; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1008; VI-NEXT: v_lshlrev_b64 v[0:1], v0, 21009; VI-NEXT: v_lshlrev_b64 v[2:3], v2, 11010; VI-NEXT: v_cvt_f64_u32_e32 v[4:5], v11011; VI-NEXT: v_cvt_f64_u32_e32 v[6:7], v31012; VI-NEXT: v_cvt_f64_u32_e32 v[0:1], v01013; VI-NEXT: s_mov_b32 s4, 01014; VI-NEXT: v_ldexp_f64 v[3:4], v[4:5], 321015; VI-NEXT: v_ldexp_f64 v[5:6], v[6:7], 321016; VI-NEXT: v_cvt_f64_u32_e32 v[7:8], v21017; VI-NEXT: s_mov_b32 s5, 0x402e00001018; VI-NEXT: v_add_f64 v[0:1], v[3:4], v[0:1]1019; VI-NEXT: v_add_f64 v[2:3], v[5:6], v[7:8]1020; VI-NEXT: v_mul_f64 v[0:1], v[0:1], s[4:5]1021; VI-NEXT: v_mul_f64 v[2:3], v[2:3], s[4:5]1022; VI-NEXT: s_setpc_b64 s[30:31]1023;1024; GFX10-LABEL: fmul_pow_shl_cnt_vec_non_splat2_todo:1025; GFX10: ; %bb.0:1026; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1027; GFX10-NEXT: v_lshlrev_b64 v[0:1], v0, 21028; GFX10-NEXT: v_lshlrev_b64 v[2:3], v2, 11029; GFX10-NEXT: v_cvt_f64_u32_e32 v[4:5], v11030; GFX10-NEXT: v_cvt_f64_u32_e32 v[6:7], v31031; GFX10-NEXT: v_cvt_f64_u32_e32 v[0:1], v01032; GFX10-NEXT: v_cvt_f64_u32_e32 v[8:9], v21033; GFX10-NEXT: v_ldexp_f64 v[3:4], v[4:5], 321034; GFX10-NEXT: v_ldexp_f64 v[5:6], v[6:7], 321035; GFX10-NEXT: v_add_f64 v[0:1], v[3:4], v[0:1]1036; GFX10-NEXT: v_add_f64 v[2:3], v[5:6], v[8:9]1037; GFX10-NEXT: v_mul_f64 v[0:1], 0x402e0000, v[0:1]1038; GFX10-NEXT: v_mul_f64 v[2:3], 0x402e0000, v[2:3]1039; GFX10-NEXT: s_setpc_b64 s[30:31]1040;1041; GFX11-LABEL: fmul_pow_shl_cnt_vec_non_splat2_todo:1042; GFX11: ; %bb.0:1043; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1044; GFX11-NEXT: v_lshlrev_b64 v[0:1], v0, 21045; GFX11-NEXT: v_lshlrev_b64 v[2:3], v2, 11046; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)1047; GFX11-NEXT: v_cvt_f64_u32_e32 v[4:5], v11048; GFX11-NEXT: v_cvt_f64_u32_e32 v[6:7], v31049; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)1050; GFX11-NEXT: v_cvt_f64_u32_e32 v[0:1], v01051; GFX11-NEXT: v_cvt_f64_u32_e32 v[8:9], v21052; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)1053; GFX11-NEXT: v_ldexp_f64 v[3:4], v[4:5], 321054; GFX11-NEXT: v_ldexp_f64 v[5:6], v[6:7], 321055; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)1056; GFX11-NEXT: v_add_f64 v[0:1], v[3:4], v[0:1]1057; GFX11-NEXT: v_add_f64 v[2:3], v[5:6], v[8:9]1058; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)1059; GFX11-NEXT: v_mul_f64 v[0:1], 0x402e0000, v[0:1]1060; GFX11-NEXT: v_mul_f64 v[2:3], 0x402e0000, v[2:3]1061; GFX11-NEXT: s_setpc_b64 s[30:31]1062 %shl = shl nsw nuw <2 x i64> <i64 2, i64 1>, %cnt1063 %conv = uitofp <2 x i64> %shl to <2 x double>1064 %mul = fmul <2 x double> <double 15.000000e+00, double 15.000000e+00>, %conv1065 ret <2 x double> %mul1066}1067 1068define <2 x half> @fmul_pow_shl_cnt_vec_fail_to_large(<2 x i16> %cnt) nounwind {1069; VI-LABEL: fmul_pow_shl_cnt_vec_fail_to_large:1070; VI: ; %bb.0:1071; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1072; VI-NEXT: v_mov_b32_e32 v1, 21073; VI-NEXT: v_lshlrev_b16_sdwa v1, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1074; VI-NEXT: v_lshlrev_b16_e64 v0, v0, 21075; VI-NEXT: v_cvt_f16_u16_e32 v0, v01076; VI-NEXT: v_cvt_f16_u16_e32 v1, v11077; VI-NEXT: v_mov_b32_e32 v2, 0x4b801078; VI-NEXT: v_mul_f16_sdwa v1, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD1079; VI-NEXT: v_mul_f16_e32 v0, 0x4b80, v01080; VI-NEXT: v_or_b32_e32 v0, v0, v11081; VI-NEXT: s_setpc_b64 s[30:31]1082;1083; GFX10-LABEL: fmul_pow_shl_cnt_vec_fail_to_large:1084; GFX10: ; %bb.0:1085; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1086; GFX10-NEXT: v_pk_lshlrev_b16 v0, v0, 2 op_sel_hi:[1,0]1087; GFX10-NEXT: v_cvt_f16_u16_e32 v1, v01088; GFX10-NEXT: v_cvt_f16_u16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_11089; GFX10-NEXT: v_pack_b32_f16 v0, v1, v01090; GFX10-NEXT: v_pk_mul_f16 v0, 0x4b80, v0 op_sel_hi:[0,1]1091; GFX10-NEXT: s_setpc_b64 s[30:31]1092;1093; GFX11-TRUE16-LABEL: fmul_pow_shl_cnt_vec_fail_to_large:1094; GFX11-TRUE16: ; %bb.0:1095; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1096; GFX11-TRUE16-NEXT: v_pk_lshlrev_b16 v0, v0, 2 op_sel_hi:[1,0]1097; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)1098; GFX11-TRUE16-NEXT: v_cvt_f16_u16_e32 v0.l, v0.l1099; GFX11-TRUE16-NEXT: v_cvt_f16_u16_e32 v0.h, v0.h1100; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1101; GFX11-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v0.h1102; GFX11-TRUE16-NEXT: v_pk_mul_f16 v0, 0x4b80, v0 op_sel_hi:[0,1]1103; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]1104;1105; GFX11-FAKE16-LABEL: fmul_pow_shl_cnt_vec_fail_to_large:1106; GFX11-FAKE16: ; %bb.0:1107; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1108; GFX11-FAKE16-NEXT: v_pk_lshlrev_b16 v0, v0, 2 op_sel_hi:[1,0]1109; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)1110; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v01111; GFX11-FAKE16-NEXT: v_cvt_f16_u16_e32 v0, v01112; GFX11-FAKE16-NEXT: v_cvt_f16_u16_e32 v1, v11113; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1114; GFX11-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v11115; GFX11-FAKE16-NEXT: v_pk_mul_f16 v0, 0x4b80, v0 op_sel_hi:[0,1]1116; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]1117 %shl = shl nsw nuw <2 x i16> <i16 2, i16 2>, %cnt1118 %conv = uitofp <2 x i16> %shl to <2 x half>1119 %mul = fmul <2 x half> <half 15.000000e+00, half 15.000000e+00>, %conv1120 ret <2 x half> %mul1121}1122 1123define double @fmul_pow_shl_cnt_fail_maybe_bad_exp(i64 %cnt) nounwind {1124; VI-LABEL: fmul_pow_shl_cnt_fail_maybe_bad_exp:1125; VI: ; %bb.0:1126; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1127; VI-NEXT: v_lshlrev_b64 v[0:1], v0, 11128; VI-NEXT: s_mov_b32 s4, 0xff5f39921129; VI-NEXT: v_cvt_f64_u32_e32 v[1:2], v11130; VI-NEXT: v_cvt_f64_u32_e32 v[3:4], v01131; VI-NEXT: s_mov_b32 s5, 0x7befffff1132; VI-NEXT: v_ldexp_f64 v[1:2], v[1:2], 321133; VI-NEXT: v_add_f64 v[0:1], v[1:2], v[3:4]1134; VI-NEXT: v_mul_f64 v[0:1], v[0:1], s[4:5]1135; VI-NEXT: s_setpc_b64 s[30:31]1136;1137; GFX10-LABEL: fmul_pow_shl_cnt_fail_maybe_bad_exp:1138; GFX10: ; %bb.0:1139; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1140; GFX10-NEXT: v_lshlrev_b64 v[0:1], v0, 11141; GFX10-NEXT: s_mov_b32 s4, 0xff5f39921142; GFX10-NEXT: s_mov_b32 s5, 0x7befffff1143; GFX10-NEXT: v_cvt_f64_u32_e32 v[1:2], v11144; GFX10-NEXT: v_cvt_f64_u32_e32 v[3:4], v01145; GFX10-NEXT: v_ldexp_f64 v[0:1], v[1:2], 321146; GFX10-NEXT: v_add_f64 v[0:1], v[0:1], v[3:4]1147; GFX10-NEXT: v_mul_f64 v[0:1], v[0:1], s[4:5]1148; GFX10-NEXT: s_setpc_b64 s[30:31]1149;1150; GFX11-LABEL: fmul_pow_shl_cnt_fail_maybe_bad_exp:1151; GFX11: ; %bb.0:1152; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1153; GFX11-NEXT: v_lshlrev_b64 v[0:1], v0, 11154; GFX11-NEXT: s_mov_b32 s0, 0xff5f39921155; GFX11-NEXT: s_mov_b32 s1, 0x7befffff1156; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)1157; GFX11-NEXT: v_cvt_f64_u32_e32 v[1:2], v11158; GFX11-NEXT: v_cvt_f64_u32_e32 v[3:4], v01159; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)1160; GFX11-NEXT: v_ldexp_f64 v[0:1], v[1:2], 321161; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], v[3:4]1162; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)1163; GFX11-NEXT: v_mul_f64 v[0:1], v[0:1], s[0:1]1164; GFX11-NEXT: s_setpc_b64 s[30:31]1165 %shl = shl nuw i64 1, %cnt1166 %conv = uitofp i64 %shl to double1167 %mul = fmul double 9.745314e+288, %conv1168 ret double %mul1169}1170 1171define double @fmul_pow_shl_cnt_safe(i16 %cnt) nounwind {1172; VI-LABEL: fmul_pow_shl_cnt_safe:1173; VI: ; %bb.0:1174; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1175; VI-NEXT: v_lshlrev_b16_e64 v0, v0, 11176; VI-NEXT: v_cvt_f64_u32_e32 v[0:1], v01177; VI-NEXT: s_mov_b32 s4, 0xff5f39921178; VI-NEXT: s_mov_b32 s5, 0x7befffff1179; VI-NEXT: v_mul_f64 v[0:1], v[0:1], s[4:5]1180; VI-NEXT: s_setpc_b64 s[30:31]1181;1182; GFX10-LABEL: fmul_pow_shl_cnt_safe:1183; GFX10: ; %bb.0:1184; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1185; GFX10-NEXT: v_lshlrev_b16 v0, v0, 11186; GFX10-NEXT: s_mov_b32 s4, 0xff5f39921187; GFX10-NEXT: s_mov_b32 s5, 0x7befffff1188; GFX10-NEXT: v_and_b32_e32 v0, 0xffff, v01189; GFX10-NEXT: v_cvt_f64_u32_e32 v[0:1], v01190; GFX10-NEXT: v_mul_f64 v[0:1], v[0:1], s[4:5]1191; GFX10-NEXT: s_setpc_b64 s[30:31]1192;1193; GFX11-TRUE16-LABEL: fmul_pow_shl_cnt_safe:1194; GFX11-TRUE16: ; %bb.0:1195; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1196; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, 01197; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, v0.l, 11198; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0xff5f39921199; GFX11-TRUE16-NEXT: s_mov_b32 s1, 0x7befffff1200; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1201; GFX11-TRUE16-NEXT: v_cvt_f64_u32_e32 v[0:1], v01202; GFX11-TRUE16-NEXT: v_mul_f64 v[0:1], v[0:1], s[0:1]1203; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]1204;1205; GFX11-FAKE16-LABEL: fmul_pow_shl_cnt_safe:1206; GFX11-FAKE16: ; %bb.0:1207; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1208; GFX11-FAKE16-NEXT: v_lshlrev_b16 v0, v0, 11209; GFX11-FAKE16-NEXT: s_mov_b32 s0, 0xff5f39921210; GFX11-FAKE16-NEXT: s_mov_b32 s1, 0x7befffff1211; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1212; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v01213; GFX11-FAKE16-NEXT: v_cvt_f64_u32_e32 v[0:1], v01214; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)1215; GFX11-FAKE16-NEXT: v_mul_f64 v[0:1], v[0:1], s[0:1]1216; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]1217 %shl = shl nuw i16 1, %cnt1218 %conv = uitofp i16 %shl to double1219 %mul = fmul double 9.745314e+288, %conv1220 ret double %mul1221}1222 1223define <2 x double> @fdiv_pow_shl_cnt_vec(<2 x i64> %cnt) nounwind {1224; VI-LABEL: fdiv_pow_shl_cnt_vec:1225; VI: ; %bb.0:1226; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1227; VI-NEXT: v_lshlrev_b32_e32 v1, 20, v01228; VI-NEXT: v_mov_b32_e32 v3, 0x3ff000001229; VI-NEXT: v_sub_u32_e64 v0, vcc, 0, 01230; VI-NEXT: v_subb_u32_e32 v1, vcc, v3, v1, vcc1231; VI-NEXT: v_lshlrev_b32_e32 v4, 20, v21232; VI-NEXT: v_sub_u32_e64 v2, vcc, 0, 01233; VI-NEXT: v_subb_u32_e32 v3, vcc, v3, v4, vcc1234; VI-NEXT: s_setpc_b64 s[30:31]1235;1236; GFX10-LABEL: fdiv_pow_shl_cnt_vec:1237; GFX10: ; %bb.0:1238; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1239; GFX10-NEXT: v_lshlrev_b32_e32 v1, 20, v01240; GFX10-NEXT: v_lshlrev_b32_e32 v3, 20, v21241; GFX10-NEXT: v_sub_co_u32 v0, vcc_lo, 0, 01242; GFX10-NEXT: v_sub_co_ci_u32_e32 v1, vcc_lo, 0x3ff00000, v1, vcc_lo1243; GFX10-NEXT: v_sub_co_u32 v2, vcc_lo, 0, 01244; GFX10-NEXT: v_sub_co_ci_u32_e32 v3, vcc_lo, 0x3ff00000, v3, vcc_lo1245; GFX10-NEXT: s_setpc_b64 s[30:31]1246;1247; GFX11-LABEL: fdiv_pow_shl_cnt_vec:1248; GFX11: ; %bb.0:1249; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1250; GFX11-NEXT: v_lshlrev_b32_e32 v1, 20, v01251; GFX11-NEXT: v_lshlrev_b32_e32 v3, 20, v21252; GFX11-NEXT: v_sub_co_u32 v0, vcc_lo, 0, 01253; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)1254; GFX11-NEXT: v_sub_co_ci_u32_e64 v1, null, 0x3ff00000, v1, vcc_lo1255; GFX11-NEXT: v_sub_co_u32 v2, vcc_lo, 0, 01256; GFX11-NEXT: v_sub_co_ci_u32_e64 v3, null, 0x3ff00000, v3, vcc_lo1257; GFX11-NEXT: s_setpc_b64 s[30:31]1258 %shl = shl nuw <2 x i64> <i64 1, i64 1>, %cnt1259 %conv = uitofp <2 x i64> %shl to <2 x double>1260 %mul = fdiv <2 x double> <double 1.000000e+00, double 1.000000e+00>, %conv1261 ret <2 x double> %mul1262}1263 1264define <2 x float> @fdiv_pow_shl_cnt_vec_with_expensive_cast(<2 x i64> %cnt) nounwind {1265; VI-LABEL: fdiv_pow_shl_cnt_vec_with_expensive_cast:1266; VI: ; %bb.0:1267; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1268; VI-NEXT: v_lshlrev_b32_e32 v0, 23, v01269; VI-NEXT: v_lshlrev_b32_e32 v1, 23, v21270; VI-NEXT: v_sub_u32_e32 v0, vcc, 1.0, v01271; VI-NEXT: v_sub_u32_e32 v1, vcc, 1.0, v11272; VI-NEXT: s_setpc_b64 s[30:31]1273;1274; GFX10-LABEL: fdiv_pow_shl_cnt_vec_with_expensive_cast:1275; GFX10: ; %bb.0:1276; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1277; GFX10-NEXT: v_lshlrev_b32_e32 v0, 23, v01278; GFX10-NEXT: v_lshlrev_b32_e32 v1, 23, v21279; GFX10-NEXT: v_sub_nc_u32_e32 v0, 1.0, v01280; GFX10-NEXT: v_sub_nc_u32_e32 v1, 1.0, v11281; GFX10-NEXT: s_setpc_b64 s[30:31]1282;1283; GFX11-LABEL: fdiv_pow_shl_cnt_vec_with_expensive_cast:1284; GFX11: ; %bb.0:1285; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1286; GFX11-NEXT: v_lshlrev_b32_e32 v0, 23, v01287; GFX11-NEXT: v_lshlrev_b32_e32 v1, 23, v21288; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)1289; GFX11-NEXT: v_sub_nc_u32_e32 v0, 1.0, v01290; GFX11-NEXT: v_sub_nc_u32_e32 v1, 1.0, v11291; GFX11-NEXT: s_setpc_b64 s[30:31]1292 %shl = shl nuw <2 x i64> <i64 1, i64 1>, %cnt1293 %conv = uitofp <2 x i64> %shl to <2 x float>1294 %mul = fdiv <2 x float> <float 1.000000e+00, float 1.000000e+00>, %conv1295 ret <2 x float> %mul1296}1297 1298define float @fdiv_pow_shl_cnt_fail_maybe_z(i64 %cnt) nounwind {1299; VI-LABEL: fdiv_pow_shl_cnt_fail_maybe_z:1300; VI: ; %bb.0:1301; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1302; VI-NEXT: v_lshlrev_b64 v[0:1], v0, 81303; VI-NEXT: s_mov_b32 s6, 0xc11000001304; VI-NEXT: v_ffbh_u32_e32 v2, v11305; VI-NEXT: v_min_u32_e32 v2, 32, v21306; VI-NEXT: v_lshlrev_b64 v[0:1], v2, v[0:1]1307; VI-NEXT: v_min_u32_e32 v0, 1, v01308; VI-NEXT: v_or_b32_e32 v0, v1, v01309; VI-NEXT: v_cvt_f32_u32_e32 v0, v01310; VI-NEXT: v_sub_u32_e32 v1, vcc, 32, v21311; VI-NEXT: v_ldexp_f32 v0, v0, v11312; VI-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, s61313; VI-NEXT: v_div_scale_f32 v2, vcc, s6, v0, s61314; VI-NEXT: v_rcp_f32_e32 v3, v11315; VI-NEXT: v_fma_f32 v4, -v1, v3, 1.01316; VI-NEXT: v_fma_f32 v3, v4, v3, v31317; VI-NEXT: v_mul_f32_e32 v4, v2, v31318; VI-NEXT: v_fma_f32 v5, -v1, v4, v21319; VI-NEXT: v_fma_f32 v4, v5, v3, v41320; VI-NEXT: v_fma_f32 v1, -v1, v4, v21321; VI-NEXT: v_div_fmas_f32 v1, v1, v3, v41322; VI-NEXT: v_div_fixup_f32 v0, v1, v0, s61323; VI-NEXT: s_setpc_b64 s[30:31]1324;1325; GFX10-LABEL: fdiv_pow_shl_cnt_fail_maybe_z:1326; GFX10: ; %bb.0:1327; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1328; GFX10-NEXT: v_lshlrev_b64 v[0:1], v0, 81329; GFX10-NEXT: v_ffbh_u32_e32 v2, v11330; GFX10-NEXT: v_min_u32_e32 v2, 32, v21331; GFX10-NEXT: v_lshlrev_b64 v[0:1], v2, v[0:1]1332; GFX10-NEXT: v_min_u32_e32 v0, 1, v01333; GFX10-NEXT: v_or_b32_e32 v0, v1, v01334; GFX10-NEXT: v_sub_nc_u32_e32 v1, 32, v21335; GFX10-NEXT: v_cvt_f32_u32_e32 v0, v01336; GFX10-NEXT: v_ldexp_f32 v0, v0, v11337; GFX10-NEXT: v_div_scale_f32 v1, s4, v0, v0, 0xc11000001338; GFX10-NEXT: v_rcp_f32_e32 v2, v11339; GFX10-NEXT: v_fma_f32 v3, -v1, v2, 1.01340; GFX10-NEXT: v_fmac_f32_e32 v2, v3, v21341; GFX10-NEXT: v_div_scale_f32 v3, vcc_lo, 0xc1100000, v0, 0xc11000001342; GFX10-NEXT: v_mul_f32_e32 v4, v3, v21343; GFX10-NEXT: v_fma_f32 v5, -v1, v4, v31344; GFX10-NEXT: v_fmac_f32_e32 v4, v5, v21345; GFX10-NEXT: v_fma_f32 v1, -v1, v4, v31346; GFX10-NEXT: v_div_fmas_f32 v1, v1, v2, v41347; GFX10-NEXT: v_div_fixup_f32 v0, v1, v0, 0xc11000001348; GFX10-NEXT: s_setpc_b64 s[30:31]1349;1350; GFX11-LABEL: fdiv_pow_shl_cnt_fail_maybe_z:1351; GFX11: ; %bb.0:1352; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1353; GFX11-NEXT: v_lshlrev_b64 v[0:1], v0, 81354; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1355; GFX11-NEXT: v_clz_i32_u32_e32 v2, v11356; GFX11-NEXT: v_min_u32_e32 v2, 32, v21357; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1358; GFX11-NEXT: v_lshlrev_b64 v[0:1], v2, v[0:1]1359; GFX11-NEXT: v_min_u32_e32 v0, 1, v01360; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)1361; GFX11-NEXT: v_or_b32_e32 v0, v1, v01362; GFX11-NEXT: v_sub_nc_u32_e32 v1, 32, v21363; GFX11-NEXT: v_cvt_f32_u32_e32 v0, v01364; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1365; GFX11-NEXT: v_ldexp_f32 v0, v0, v11366; GFX11-NEXT: v_div_scale_f32 v1, null, v0, v0, 0xc11000001367; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)1368; GFX11-NEXT: v_rcp_f32_e32 v2, v11369; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)1370; GFX11-NEXT: v_fma_f32 v3, -v1, v2, 1.01371; GFX11-NEXT: v_fmac_f32_e32 v2, v3, v21372; GFX11-NEXT: v_div_scale_f32 v3, vcc_lo, 0xc1100000, v0, 0xc11000001373; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1374; GFX11-NEXT: v_mul_f32_e32 v4, v3, v21375; GFX11-NEXT: v_fma_f32 v5, -v1, v4, v31376; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1377; GFX11-NEXT: v_fmac_f32_e32 v4, v5, v21378; GFX11-NEXT: v_fma_f32 v1, -v1, v4, v31379; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1380; GFX11-NEXT: v_div_fmas_f32 v1, v1, v2, v41381; GFX11-NEXT: v_div_fixup_f32 v0, v1, v0, 0xc11000001382; GFX11-NEXT: s_setpc_b64 s[30:31]1383 %shl = shl i64 8, %cnt1384 %conv = uitofp i64 %shl to float1385 %mul = fdiv float -9.000000e+00, %conv1386 ret float %mul1387}1388 1389define float @fdiv_pow_shl_cnt_fail_neg_int(i64 %cnt) nounwind {1390; VI-LABEL: fdiv_pow_shl_cnt_fail_neg_int:1391; VI: ; %bb.0:1392; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1393; VI-NEXT: v_lshlrev_b64 v[0:1], v0, 81394; VI-NEXT: s_mov_b32 s6, 0xc11000001395; VI-NEXT: v_xor_b32_e32 v2, v0, v11396; VI-NEXT: v_ashrrev_i32_e32 v2, 31, v21397; VI-NEXT: v_ffbh_i32_e32 v3, v11398; VI-NEXT: v_add_u32_e32 v2, vcc, 32, v21399; VI-NEXT: v_add_u32_e32 v3, vcc, -1, v31400; VI-NEXT: v_min_u32_e32 v2, v3, v21401; VI-NEXT: v_lshlrev_b64 v[0:1], v2, v[0:1]1402; VI-NEXT: v_min_u32_e32 v0, 1, v01403; VI-NEXT: v_or_b32_e32 v0, v1, v01404; VI-NEXT: v_cvt_f32_i32_e32 v0, v01405; VI-NEXT: v_sub_u32_e32 v1, vcc, 32, v21406; VI-NEXT: v_ldexp_f32 v0, v0, v11407; VI-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, s61408; VI-NEXT: v_div_scale_f32 v2, vcc, s6, v0, s61409; VI-NEXT: v_rcp_f32_e32 v3, v11410; VI-NEXT: v_fma_f32 v4, -v1, v3, 1.01411; VI-NEXT: v_fma_f32 v3, v4, v3, v31412; VI-NEXT: v_mul_f32_e32 v4, v2, v31413; VI-NEXT: v_fma_f32 v5, -v1, v4, v21414; VI-NEXT: v_fma_f32 v4, v5, v3, v41415; VI-NEXT: v_fma_f32 v1, -v1, v4, v21416; VI-NEXT: v_div_fmas_f32 v1, v1, v3, v41417; VI-NEXT: v_div_fixup_f32 v0, v1, v0, s61418; VI-NEXT: s_setpc_b64 s[30:31]1419;1420; GFX10-LABEL: fdiv_pow_shl_cnt_fail_neg_int:1421; GFX10: ; %bb.0:1422; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1423; GFX10-NEXT: v_lshlrev_b64 v[0:1], v0, 81424; GFX10-NEXT: v_xor_b32_e32 v2, v0, v11425; GFX10-NEXT: v_ffbh_i32_e32 v3, v11426; GFX10-NEXT: v_ashrrev_i32_e32 v2, 31, v21427; GFX10-NEXT: v_add_nc_u32_e32 v3, -1, v31428; GFX10-NEXT: v_add_nc_u32_e32 v2, 32, v21429; GFX10-NEXT: v_min_u32_e32 v2, v3, v21430; GFX10-NEXT: v_lshlrev_b64 v[0:1], v2, v[0:1]1431; GFX10-NEXT: v_min_u32_e32 v0, 1, v01432; GFX10-NEXT: v_or_b32_e32 v0, v1, v01433; GFX10-NEXT: v_sub_nc_u32_e32 v1, 32, v21434; GFX10-NEXT: v_cvt_f32_i32_e32 v0, v01435; GFX10-NEXT: v_ldexp_f32 v0, v0, v11436; GFX10-NEXT: v_div_scale_f32 v1, s4, v0, v0, 0xc11000001437; GFX10-NEXT: v_rcp_f32_e32 v2, v11438; GFX10-NEXT: v_fma_f32 v3, -v1, v2, 1.01439; GFX10-NEXT: v_fmac_f32_e32 v2, v3, v21440; GFX10-NEXT: v_div_scale_f32 v3, vcc_lo, 0xc1100000, v0, 0xc11000001441; GFX10-NEXT: v_mul_f32_e32 v4, v3, v21442; GFX10-NEXT: v_fma_f32 v5, -v1, v4, v31443; GFX10-NEXT: v_fmac_f32_e32 v4, v5, v21444; GFX10-NEXT: v_fma_f32 v1, -v1, v4, v31445; GFX10-NEXT: v_div_fmas_f32 v1, v1, v2, v41446; GFX10-NEXT: v_div_fixup_f32 v0, v1, v0, 0xc11000001447; GFX10-NEXT: s_setpc_b64 s[30:31]1448;1449; GFX11-LABEL: fdiv_pow_shl_cnt_fail_neg_int:1450; GFX11: ; %bb.0:1451; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1452; GFX11-NEXT: v_lshlrev_b64 v[0:1], v0, 81453; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)1454; GFX11-NEXT: v_xor_b32_e32 v2, v0, v11455; GFX11-NEXT: v_cls_i32_e32 v3, v11456; GFX11-NEXT: v_ashrrev_i32_e32 v2, 31, v21457; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)1458; GFX11-NEXT: v_add_nc_u32_e32 v3, -1, v31459; GFX11-NEXT: v_add_nc_u32_e32 v2, 32, v21460; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1461; GFX11-NEXT: v_min_u32_e32 v2, v3, v21462; GFX11-NEXT: v_lshlrev_b64 v[0:1], v2, v[0:1]1463; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1464; GFX11-NEXT: v_min_u32_e32 v0, 1, v01465; GFX11-NEXT: v_or_b32_e32 v0, v1, v01466; GFX11-NEXT: v_sub_nc_u32_e32 v1, 32, v21467; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)1468; GFX11-NEXT: v_cvt_f32_i32_e32 v0, v01469; GFX11-NEXT: v_ldexp_f32 v0, v0, v11470; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1471; GFX11-NEXT: v_div_scale_f32 v1, null, v0, v0, 0xc11000001472; GFX11-NEXT: v_rcp_f32_e32 v2, v11473; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)1474; GFX11-NEXT: v_fma_f32 v3, -v1, v2, 1.01475; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)1476; GFX11-NEXT: v_fmac_f32_e32 v2, v3, v21477; GFX11-NEXT: v_div_scale_f32 v3, vcc_lo, 0xc1100000, v0, 0xc11000001478; GFX11-NEXT: v_mul_f32_e32 v4, v3, v21479; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1480; GFX11-NEXT: v_fma_f32 v5, -v1, v4, v31481; GFX11-NEXT: v_fmac_f32_e32 v4, v5, v21482; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1483; GFX11-NEXT: v_fma_f32 v1, -v1, v4, v31484; GFX11-NEXT: v_div_fmas_f32 v1, v1, v2, v41485; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)1486; GFX11-NEXT: v_div_fixup_f32 v0, v1, v0, 0xc11000001487; GFX11-NEXT: s_setpc_b64 s[30:31]1488 %shl = shl i64 8, %cnt1489 %conv = sitofp i64 %shl to float1490 %mul = fdiv float -9.000000e+00, %conv1491 ret float %mul1492}1493 1494define float @fdiv_pow_shl_cnt(i64 %cnt_in) nounwind {1495; VI-LABEL: fdiv_pow_shl_cnt:1496; VI: ; %bb.0:1497; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1498; VI-NEXT: v_and_b32_e32 v0, 31, v01499; VI-NEXT: v_lshlrev_b32_e32 v0, 23, v01500; VI-NEXT: v_sub_u32_e32 v0, vcc, 0xbd800000, v01501; VI-NEXT: s_setpc_b64 s[30:31]1502;1503; GFX10-LABEL: fdiv_pow_shl_cnt:1504; GFX10: ; %bb.0:1505; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1506; GFX10-NEXT: v_and_b32_e32 v0, 31, v01507; GFX10-NEXT: v_lshlrev_b32_e32 v0, 23, v01508; GFX10-NEXT: v_sub_nc_u32_e32 v0, 0xbd800000, v01509; GFX10-NEXT: s_setpc_b64 s[30:31]1510;1511; GFX11-LABEL: fdiv_pow_shl_cnt:1512; GFX11: ; %bb.0:1513; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1514; GFX11-NEXT: v_and_b32_e32 v0, 31, v01515; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1516; GFX11-NEXT: v_lshlrev_b32_e32 v0, 23, v01517; GFX11-NEXT: v_sub_nc_u32_e32 v0, 0xbd800000, v01518; GFX11-NEXT: s_setpc_b64 s[30:31]1519 %cnt = and i64 %cnt_in, 311520 %shl = shl i64 8, %cnt1521 %conv = sitofp i64 %shl to float1522 %mul = fdiv float -0.500000e+00, %conv1523 ret float %mul1524}1525 1526define half @fdiv_pow_shl_cnt_fail_out_of_bounds(i32 %cnt) nounwind {1527; VI-LABEL: fdiv_pow_shl_cnt_fail_out_of_bounds:1528; VI: ; %bb.0:1529; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1530; VI-NEXT: v_lshlrev_b32_e64 v0, v0, 11531; VI-NEXT: v_cvt_f32_u32_e32 v0, v01532; VI-NEXT: s_mov_b32 s4, 0x460000001533; VI-NEXT: v_cvt_f16_f32_e32 v0, v01534; VI-NEXT: v_cvt_f32_f16_e32 v1, v01535; VI-NEXT: v_rcp_f32_e32 v2, v11536; VI-NEXT: v_mul_f32_e32 v3, 0x46000000, v21537; VI-NEXT: v_mad_f32 v4, -v1, v3, s41538; VI-NEXT: v_mac_f32_e32 v3, v4, v21539; VI-NEXT: v_mad_f32 v1, -v1, v3, s41540; VI-NEXT: v_mul_f32_e32 v1, v1, v21541; VI-NEXT: v_and_b32_e32 v1, 0xff800000, v11542; VI-NEXT: v_add_f32_e32 v1, v1, v31543; VI-NEXT: v_cvt_f16_f32_e32 v1, v11544; VI-NEXT: s_movk_i32 s4, 0x70001545; VI-NEXT: v_div_fixup_f16 v0, v1, v0, s41546; VI-NEXT: s_setpc_b64 s[30:31]1547;1548; GFX10-LABEL: fdiv_pow_shl_cnt_fail_out_of_bounds:1549; GFX10: ; %bb.0:1550; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1551; GFX10-NEXT: v_lshlrev_b32_e64 v0, v0, 11552; GFX10-NEXT: v_cvt_f32_u32_e32 v0, v01553; GFX10-NEXT: v_cvt_f16_f32_e32 v0, v01554; GFX10-NEXT: v_cvt_f32_f16_e32 v1, v01555; GFX10-NEXT: v_rcp_f32_e32 v2, v11556; GFX10-NEXT: v_mul_f32_e32 v3, 0x46000000, v21557; GFX10-NEXT: v_mad_f32 v4, -v1, v3, 0x460000001558; GFX10-NEXT: v_mac_f32_e32 v3, v4, v21559; GFX10-NEXT: v_mad_f32 v1, -v1, v3, 0x460000001560; GFX10-NEXT: v_mul_f32_e32 v1, v1, v21561; GFX10-NEXT: v_and_b32_e32 v1, 0xff800000, v11562; GFX10-NEXT: v_add_f32_e32 v1, v1, v31563; GFX10-NEXT: v_cvt_f16_f32_e32 v1, v11564; GFX10-NEXT: v_div_fixup_f16 v0, v1, v0, 0x70001565; GFX10-NEXT: s_setpc_b64 s[30:31]1566;1567; GFX11-TRUE16-LABEL: fdiv_pow_shl_cnt_fail_out_of_bounds:1568; GFX11-TRUE16: ; %bb.0:1569; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1570; GFX11-TRUE16-NEXT: v_lshlrev_b32_e64 v0, v0, 11571; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0x460000001572; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1573; GFX11-TRUE16-NEXT: v_cvt_f32_u32_e32 v0, v01574; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v1.l, v01575; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1576; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v1.l1577; GFX11-TRUE16-NEXT: v_rcp_f32_e32 v0, v01578; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)1579; GFX11-TRUE16-NEXT: v_mul_f32_e32 v2, 0x46000000, v01580; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1581; GFX11-TRUE16-NEXT: v_fma_mix_f32 v3, -v1, v2, s0 op_sel_hi:[1,0,0]1582; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v2, v3, v01583; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1584; GFX11-TRUE16-NEXT: v_fma_mix_f32 v3, -v1, v2, s0 op_sel_hi:[1,0,0]1585; GFX11-TRUE16-NEXT: v_mul_f32_e32 v0, v3, v01586; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1587; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xff800000, v01588; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, v0, v21589; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1590; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v01591; GFX11-TRUE16-NEXT: v_div_fixup_f16 v0.l, v0.l, v1.l, 0x70001592; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]1593;1594; GFX11-FAKE16-LABEL: fdiv_pow_shl_cnt_fail_out_of_bounds:1595; GFX11-FAKE16: ; %bb.0:1596; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1597; GFX11-FAKE16-NEXT: v_lshlrev_b32_e64 v0, v0, 11598; GFX11-FAKE16-NEXT: s_mov_b32 s0, 0x460000001599; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1600; GFX11-FAKE16-NEXT: v_cvt_f32_u32_e32 v0, v01601; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v01602; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1603; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v1, v01604; GFX11-FAKE16-NEXT: v_rcp_f32_e32 v1, v11605; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)1606; GFX11-FAKE16-NEXT: v_mul_f32_e32 v2, 0x46000000, v11607; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1608; GFX11-FAKE16-NEXT: v_fma_mix_f32 v3, -v0, v2, s0 op_sel_hi:[1,0,0]1609; GFX11-FAKE16-NEXT: v_fmac_f32_e32 v2, v3, v11610; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1611; GFX11-FAKE16-NEXT: v_fma_mix_f32 v3, -v0, v2, s0 op_sel_hi:[1,0,0]1612; GFX11-FAKE16-NEXT: v_mul_f32_e32 v1, v3, v11613; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1614; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff800000, v11615; GFX11-FAKE16-NEXT: v_add_f32_e32 v1, v1, v21616; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1617; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v1, v11618; GFX11-FAKE16-NEXT: v_div_fixup_f16 v0, v1, v0, 0x70001619; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]1620 %shl = shl nuw i32 1, %cnt1621 %conv = uitofp i32 %shl to half1622 %mul = fdiv half 0xH7000, %conv1623 ret half %mul1624}1625 1626define half @fdiv_pow_shl_cnt_in_bounds(i16 %cnt) nounwind {1627; VI-LABEL: fdiv_pow_shl_cnt_in_bounds:1628; VI: ; %bb.0:1629; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1630; VI-NEXT: v_lshlrev_b16_e32 v0, 10, v01631; VI-NEXT: v_sub_u16_e32 v0, 0x7000, v01632; VI-NEXT: s_setpc_b64 s[30:31]1633;1634; GFX10-LABEL: fdiv_pow_shl_cnt_in_bounds:1635; GFX10: ; %bb.0:1636; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1637; GFX10-NEXT: v_lshlrev_b16 v0, 10, v01638; GFX10-NEXT: v_sub_nc_u16 v0, 0x7000, v01639; GFX10-NEXT: s_setpc_b64 s[30:31]1640;1641; GFX11-TRUE16-LABEL: fdiv_pow_shl_cnt_in_bounds:1642; GFX11-TRUE16: ; %bb.0:1643; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1644; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, 10, v0.l1645; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)1646; GFX11-TRUE16-NEXT: v_sub_nc_u16 v0.l, 0x7000, v0.l1647; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]1648;1649; GFX11-FAKE16-LABEL: fdiv_pow_shl_cnt_in_bounds:1650; GFX11-FAKE16: ; %bb.0:1651; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1652; GFX11-FAKE16-NEXT: v_lshlrev_b16 v0, 10, v01653; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)1654; GFX11-FAKE16-NEXT: v_sub_nc_u16 v0, 0x7000, v01655; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]1656 %shl = shl nuw i16 1, %cnt1657 %conv = uitofp i16 %shl to half1658 %mul = fdiv half 0xH7000, %conv1659 ret half %mul1660}1661 1662define half @fdiv_pow_shl_cnt_in_bounds2(i16 %cnt) nounwind {1663; VI-LABEL: fdiv_pow_shl_cnt_in_bounds2:1664; VI: ; %bb.0:1665; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1666; VI-NEXT: v_lshlrev_b16_e32 v0, 10, v01667; VI-NEXT: v_sub_u16_e32 v0, 0x4800, v01668; VI-NEXT: s_setpc_b64 s[30:31]1669;1670; GFX10-LABEL: fdiv_pow_shl_cnt_in_bounds2:1671; GFX10: ; %bb.0:1672; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1673; GFX10-NEXT: v_lshlrev_b16 v0, 10, v01674; GFX10-NEXT: v_sub_nc_u16 v0, 0x4800, v01675; GFX10-NEXT: s_setpc_b64 s[30:31]1676;1677; GFX11-TRUE16-LABEL: fdiv_pow_shl_cnt_in_bounds2:1678; GFX11-TRUE16: ; %bb.0:1679; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1680; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, 10, v0.l1681; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)1682; GFX11-TRUE16-NEXT: v_sub_nc_u16 v0.l, 0x4800, v0.l1683; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]1684;1685; GFX11-FAKE16-LABEL: fdiv_pow_shl_cnt_in_bounds2:1686; GFX11-FAKE16: ; %bb.0:1687; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1688; GFX11-FAKE16-NEXT: v_lshlrev_b16 v0, 10, v01689; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)1690; GFX11-FAKE16-NEXT: v_sub_nc_u16 v0, 0x4800, v01691; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]1692 %shl = shl nuw i16 1, %cnt1693 %conv = uitofp i16 %shl to half1694 %mul = fdiv half 0xH4800, %conv1695 ret half %mul1696}1697 1698define half @fdiv_pow_shl_cnt_fail_out_of_bound2(i16 %cnt) nounwind {1699; VI-LABEL: fdiv_pow_shl_cnt_fail_out_of_bound2:1700; VI: ; %bb.0:1701; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1702; VI-NEXT: v_lshlrev_b16_e64 v0, v0, 11703; VI-NEXT: v_cvt_f16_u16_e32 v0, v01704; VI-NEXT: v_cvt_f32_f16_e32 v1, v01705; VI-NEXT: v_rcp_f32_e32 v2, v11706; VI-NEXT: v_add_f32_e32 v3, v2, v21707; VI-NEXT: v_mad_f32 v4, -v1, v3, 2.01708; VI-NEXT: v_mac_f32_e32 v3, v4, v21709; VI-NEXT: v_mad_f32 v1, -v1, v3, 2.01710; VI-NEXT: v_mul_f32_e32 v1, v1, v21711; VI-NEXT: v_and_b32_e32 v1, 0xff800000, v11712; VI-NEXT: v_add_f32_e32 v1, v1, v31713; VI-NEXT: v_cvt_f16_f32_e32 v1, v11714; VI-NEXT: v_div_fixup_f16 v0, v1, v0, 2.01715; VI-NEXT: s_setpc_b64 s[30:31]1716;1717; GFX10-LABEL: fdiv_pow_shl_cnt_fail_out_of_bound2:1718; GFX10: ; %bb.0:1719; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1720; GFX10-NEXT: v_lshlrev_b16 v0, v0, 11721; GFX10-NEXT: v_cvt_f16_u16_e32 v0, v01722; GFX10-NEXT: v_cvt_f32_f16_e32 v1, v01723; GFX10-NEXT: v_rcp_f32_e32 v2, v11724; GFX10-NEXT: v_add_f32_e32 v3, v2, v21725; GFX10-NEXT: v_mad_f32 v4, -v1, v3, 2.01726; GFX10-NEXT: v_mac_f32_e32 v3, v4, v21727; GFX10-NEXT: v_mad_f32 v1, -v1, v3, 2.01728; GFX10-NEXT: v_mul_f32_e32 v1, v1, v21729; GFX10-NEXT: v_and_b32_e32 v1, 0xff800000, v11730; GFX10-NEXT: v_add_f32_e32 v1, v1, v31731; GFX10-NEXT: v_cvt_f16_f32_e32 v1, v11732; GFX10-NEXT: v_div_fixup_f16 v0, v1, v0, 2.01733; GFX10-NEXT: s_setpc_b64 s[30:31]1734;1735; GFX11-TRUE16-LABEL: fdiv_pow_shl_cnt_fail_out_of_bound2:1736; GFX11-TRUE16: ; %bb.0:1737; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1738; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, v0.l, 11739; GFX11-TRUE16-NEXT: s_mov_b32 s0, 2.01740; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1741; GFX11-TRUE16-NEXT: v_cvt_f16_u16_e32 v1.l, v0.l1742; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v1.l1743; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)1744; GFX11-TRUE16-NEXT: v_rcp_f32_e32 v0, v01745; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)1746; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, v0, v01747; GFX11-TRUE16-NEXT: v_fma_mix_f32 v3, -v1, v2, s0 op_sel_hi:[1,0,0]1748; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1749; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v2, v3, v01750; GFX11-TRUE16-NEXT: v_fma_mix_f32 v3, -v1, v2, s0 op_sel_hi:[1,0,0]1751; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1752; GFX11-TRUE16-NEXT: v_mul_f32_e32 v0, v3, v01753; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xff800000, v01754; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1755; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, v0, v21756; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v01757; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)1758; GFX11-TRUE16-NEXT: v_div_fixup_f16 v0.l, v0.l, v1.l, 2.01759; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]1760;1761; GFX11-FAKE16-LABEL: fdiv_pow_shl_cnt_fail_out_of_bound2:1762; GFX11-FAKE16: ; %bb.0:1763; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1764; GFX11-FAKE16-NEXT: v_lshlrev_b16 v0, v0, 11765; GFX11-FAKE16-NEXT: s_mov_b32 s0, 2.01766; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1767; GFX11-FAKE16-NEXT: v_cvt_f16_u16_e32 v0, v01768; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v1, v01769; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)1770; GFX11-FAKE16-NEXT: v_rcp_f32_e32 v1, v11771; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)1772; GFX11-FAKE16-NEXT: v_add_f32_e32 v2, v1, v11773; GFX11-FAKE16-NEXT: v_fma_mix_f32 v3, -v0, v2, s0 op_sel_hi:[1,0,0]1774; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1775; GFX11-FAKE16-NEXT: v_fmac_f32_e32 v2, v3, v11776; GFX11-FAKE16-NEXT: v_fma_mix_f32 v3, -v0, v2, s0 op_sel_hi:[1,0,0]1777; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1778; GFX11-FAKE16-NEXT: v_mul_f32_e32 v1, v3, v11779; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff800000, v11780; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1781; GFX11-FAKE16-NEXT: v_add_f32_e32 v1, v1, v21782; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v1, v11783; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)1784; GFX11-FAKE16-NEXT: v_div_fixup_f16 v0, v1, v0, 2.01785; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]1786 %shl = shl nuw i16 1, %cnt1787 %conv = uitofp i16 %shl to half1788 %mul = fdiv half 0xH4000, %conv1789 ret half %mul1790}1791 1792define double @fdiv_pow_shl_cnt32_to_dbl_okay(i32 %cnt) nounwind {1793; VI-LABEL: fdiv_pow_shl_cnt32_to_dbl_okay:1794; VI: ; %bb.0:1795; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1796; VI-NEXT: v_lshlrev_b32_e32 v0, 20, v01797; VI-NEXT: v_mov_b32_e32 v1, 0x36a000001798; VI-NEXT: v_sub_u32_e64 v2, vcc, 0, 01799; VI-NEXT: v_subb_u32_e32 v1, vcc, v1, v0, vcc1800; VI-NEXT: v_mov_b32_e32 v0, 01801; VI-NEXT: s_setpc_b64 s[30:31]1802;1803; GFX10-LABEL: fdiv_pow_shl_cnt32_to_dbl_okay:1804; GFX10: ; %bb.0:1805; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1806; GFX10-NEXT: v_lshlrev_b32_e32 v0, 20, v01807; GFX10-NEXT: v_sub_co_u32 v1, vcc_lo, 0, 01808; GFX10-NEXT: v_sub_co_ci_u32_e32 v1, vcc_lo, 0x36a00000, v0, vcc_lo1809; GFX10-NEXT: v_mov_b32_e32 v0, 01810; GFX10-NEXT: s_setpc_b64 s[30:31]1811;1812; GFX11-LABEL: fdiv_pow_shl_cnt32_to_dbl_okay:1813; GFX11: ; %bb.0:1814; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1815; GFX11-NEXT: v_lshlrev_b32_e32 v0, 20, v01816; GFX11-NEXT: v_sub_co_u32 v1, vcc_lo, 0, 01817; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)1818; GFX11-NEXT: v_sub_co_ci_u32_e64 v1, null, 0x36a00000, v0, vcc_lo1819; GFX11-NEXT: v_mov_b32_e32 v0, 01820; GFX11-NEXT: s_setpc_b64 s[30:31]1821 %shl = shl nuw i32 1, %cnt1822 %conv = uitofp i32 %shl to double1823 %mul = fdiv double 0x36A0000000000000, %conv1824 ret double %mul1825}1826 1827define float @fdiv_pow_shl_cnt32_out_of_bounds2(i32 %cnt) nounwind {1828; VI-LABEL: fdiv_pow_shl_cnt32_out_of_bounds2:1829; VI: ; %bb.0:1830; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1831; VI-NEXT: v_lshlrev_b32_e64 v0, v0, 11832; VI-NEXT: v_cvt_f32_u32_e32 v0, v01833; VI-NEXT: s_mov_b32 s6, 0x10fffff81834; VI-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, s61835; VI-NEXT: v_div_scale_f32 v2, vcc, s6, v0, s61836; VI-NEXT: v_rcp_f32_e32 v3, v11837; VI-NEXT: v_fma_f32 v4, -v1, v3, 1.01838; VI-NEXT: v_fma_f32 v3, v4, v3, v31839; VI-NEXT: v_mul_f32_e32 v4, v2, v31840; VI-NEXT: v_fma_f32 v5, -v1, v4, v21841; VI-NEXT: v_fma_f32 v4, v5, v3, v41842; VI-NEXT: v_fma_f32 v1, -v1, v4, v21843; VI-NEXT: v_div_fmas_f32 v1, v1, v3, v41844; VI-NEXT: v_div_fixup_f32 v0, v1, v0, s61845; VI-NEXT: s_setpc_b64 s[30:31]1846;1847; GFX10-LABEL: fdiv_pow_shl_cnt32_out_of_bounds2:1848; GFX10: ; %bb.0:1849; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1850; GFX10-NEXT: v_lshlrev_b32_e64 v0, v0, 11851; GFX10-NEXT: v_cvt_f32_u32_e32 v0, v01852; GFX10-NEXT: v_div_scale_f32 v1, s4, v0, v0, 0x10fffff81853; GFX10-NEXT: v_rcp_f32_e32 v2, v11854; GFX10-NEXT: v_fma_f32 v3, -v1, v2, 1.01855; GFX10-NEXT: v_fmac_f32_e32 v2, v3, v21856; GFX10-NEXT: v_div_scale_f32 v3, vcc_lo, 0x10fffff8, v0, 0x10fffff81857; GFX10-NEXT: v_mul_f32_e32 v4, v3, v21858; GFX10-NEXT: v_fma_f32 v5, -v1, v4, v31859; GFX10-NEXT: v_fmac_f32_e32 v4, v5, v21860; GFX10-NEXT: v_fma_f32 v1, -v1, v4, v31861; GFX10-NEXT: v_div_fmas_f32 v1, v1, v2, v41862; GFX10-NEXT: v_div_fixup_f32 v0, v1, v0, 0x10fffff81863; GFX10-NEXT: s_setpc_b64 s[30:31]1864;1865; GFX11-LABEL: fdiv_pow_shl_cnt32_out_of_bounds2:1866; GFX11: ; %bb.0:1867; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1868; GFX11-NEXT: v_lshlrev_b32_e64 v0, v0, 11869; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1870; GFX11-NEXT: v_cvt_f32_u32_e32 v0, v01871; GFX11-NEXT: v_div_scale_f32 v1, null, v0, v0, 0x10fffff81872; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)1873; GFX11-NEXT: v_rcp_f32_e32 v2, v11874; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)1875; GFX11-NEXT: v_fma_f32 v3, -v1, v2, 1.01876; GFX11-NEXT: v_fmac_f32_e32 v2, v3, v21877; GFX11-NEXT: v_div_scale_f32 v3, vcc_lo, 0x10fffff8, v0, 0x10fffff81878; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1879; GFX11-NEXT: v_mul_f32_e32 v4, v3, v21880; GFX11-NEXT: v_fma_f32 v5, -v1, v4, v31881; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1882; GFX11-NEXT: v_fmac_f32_e32 v4, v5, v21883; GFX11-NEXT: v_fma_f32 v1, -v1, v4, v31884; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1885; GFX11-NEXT: v_div_fmas_f32 v1, v1, v2, v41886; GFX11-NEXT: v_div_fixup_f32 v0, v1, v0, 0x10fffff81887; GFX11-NEXT: s_setpc_b64 s[30:31]1888 %shl = shl nuw i32 1, %cnt1889 %conv = uitofp i32 %shl to float1890 %mul = fdiv float 0x3a1fffff00000000, %conv1891 ret float %mul1892}1893 1894define float @fdiv_pow_shl_cnt32_okay(i32 %cnt) nounwind {1895; VI-LABEL: fdiv_pow_shl_cnt32_okay:1896; VI: ; %bb.0:1897; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1898; VI-NEXT: v_lshlrev_b32_e32 v0, 23, v01899; VI-NEXT: v_sub_u32_e32 v0, vcc, 0x11000000, v01900; VI-NEXT: s_setpc_b64 s[30:31]1901;1902; GFX10-LABEL: fdiv_pow_shl_cnt32_okay:1903; GFX10: ; %bb.0:1904; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1905; GFX10-NEXT: v_lshlrev_b32_e32 v0, 23, v01906; GFX10-NEXT: v_sub_nc_u32_e32 v0, 0x11000000, v01907; GFX10-NEXT: s_setpc_b64 s[30:31]1908;1909; GFX11-LABEL: fdiv_pow_shl_cnt32_okay:1910; GFX11: ; %bb.0:1911; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1912; GFX11-NEXT: v_lshlrev_b32_e32 v0, 23, v01913; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)1914; GFX11-NEXT: v_sub_nc_u32_e32 v0, 0x11000000, v01915; GFX11-NEXT: s_setpc_b64 s[30:31]1916 %shl = shl nuw i32 1, %cnt1917 %conv = uitofp i32 %shl to float1918 %mul = fdiv float 0x3a20000000000000, %conv1919 ret float %mul1920}1921