129 lines · plain
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 32# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass=si-fold-operands -o - %s | FileCheck -check-prefix=GCN %s3 4# The constant is 0xffffffff80000000. It is 64-bit negative constant, but it passes the test5# isInt<32>(). Nonetheless it is not a legal literal for a binary or unsigned operand and6# cannot be used right in the shift as HW will zero extend it.7 8---9name: imm64_shift_int32_const_0xffffffff8000000010body: |11 bb.0:12 ; GCN-LABEL: name: imm64_shift_int32_const_0xffffffff8000000013 ; GCN: [[S_MOV_B:%[0-9]+]]:sreg_64 = S_MOV_B64_IMM_PSEUDO -214748364814 ; GCN-NEXT: [[S_LSHL_B64_:%[0-9]+]]:sreg_64 = S_LSHL_B64 [[S_MOV_B]], 1, implicit-def $scc15 ; GCN-NEXT: S_ENDPGM 0, implicit [[S_LSHL_B64_]]16 %0:sreg_64 = S_MOV_B64_IMM_PSEUDO 1844674407156206796817 %1:sreg_64 = S_LSHL_B64 %0, 1, implicit-def $scc18 S_ENDPGM 0, implicit %119 20...21 22---23name: imm64_shift_int32_const_0xffffffff24body: |25 bb.0:26 ; GCN-LABEL: name: imm64_shift_int32_const_0xffffffff27 ; GCN: [[S_MOV_B:%[0-9]+]]:sreg_64 = S_MOV_B64_IMM_PSEUDO 429496729528 ; GCN-NEXT: [[S_LSHL_B64_:%[0-9]+]]:sreg_64 = S_LSHL_B64 [[S_MOV_B]], 1, implicit-def $scc29 ; GCN-NEXT: S_ENDPGM 0, implicit [[S_LSHL_B64_]]30 %0:sreg_64 = S_MOV_B64_IMM_PSEUDO 429496729531 %1:sreg_64 = S_LSHL_B64 %0, 1, implicit-def $scc32 S_ENDPGM 0, implicit %133 34...35 36---37name: imm64_shift_int32_const_0x8000000038body: |39 bb.0:40 ; GCN-LABEL: name: imm64_shift_int32_const_0x8000000041 ; GCN: [[S_MOV_B:%[0-9]+]]:sreg_64 = S_MOV_B64_IMM_PSEUDO 214748364842 ; GCN-NEXT: [[S_LSHL_B64_:%[0-9]+]]:sreg_64 = S_LSHL_B64 [[S_MOV_B]], 1, implicit-def $scc43 ; GCN-NEXT: S_ENDPGM 0, implicit [[S_LSHL_B64_]]44 %0:sreg_64 = S_MOV_B64_IMM_PSEUDO 214748364845 %1:sreg_64 = S_LSHL_B64 %0, 1, implicit-def $scc46 S_ENDPGM 0, implicit %147 48...49 50---51name: imm64_shift_int32_const_0x7fffffff52body: |53 bb.0:54 ; GCN-LABEL: name: imm64_shift_int32_const_0x7fffffff55 ; GCN: [[S_LSHL_B64_:%[0-9]+]]:sreg_64 = S_LSHL_B64 2147483647, 1, implicit-def $scc56 ; GCN-NEXT: S_ENDPGM 0, implicit [[S_LSHL_B64_]]57 %0:sreg_64 = S_MOV_B64_IMM_PSEUDO 214748364758 %1:sreg_64 = S_LSHL_B64 %0, 1, implicit-def $scc59 S_ENDPGM 0, implicit %160 61...62 63---64name: imm64_shift_int32_const_0x1ffffffff65body: |66 bb.0:67 ; GCN-LABEL: name: imm64_shift_int32_const_0x1ffffffff68 ; GCN: [[S_MOV_B:%[0-9]+]]:sreg_64 = S_MOV_B64_IMM_PSEUDO 858993459169 ; GCN-NEXT: [[S_LSHL_B64_:%[0-9]+]]:sreg_64 = S_LSHL_B64 [[S_MOV_B]], 1, implicit-def $scc70 ; GCN-NEXT: S_ENDPGM 0, implicit [[S_LSHL_B64_]]71 %0:sreg_64 = S_MOV_B64_IMM_PSEUDO 858993459172 %1:sreg_64 = S_LSHL_B64 %0, 1, implicit-def $scc73 S_ENDPGM 0, implicit %174 75...76 77---78name: imm64_shift_int32_const_0xffffffffffffffff79body: |80 bb.0:81 ; GCN-LABEL: name: imm64_shift_int32_const_0xffffffffffffffff82 ; GCN: [[S_LSHL_B64_:%[0-9]+]]:sreg_64 = S_LSHL_B64 -1, 1, implicit-def $scc83 ; GCN-NEXT: S_ENDPGM 0, implicit [[S_LSHL_B64_]]84 %0:sreg_64 = S_MOV_B64_IMM_PSEUDO -185 %1:sreg_64 = S_LSHL_B64 %0, 1, implicit-def $scc86 S_ENDPGM 0, implicit %187 88...89 90---91name: imm64_ashr_int32_const_0xffffffff92body: |93 bb.0:94 ; GCN-LABEL: name: imm64_ashr_int32_const_0xffffffff95 ; GCN: [[S_MOV_B:%[0-9]+]]:sreg_64 = S_MOV_B64_IMM_PSEUDO 429496729596 ; GCN-NEXT: [[S_ASHR_I64_:%[0-9]+]]:sreg_64 = S_ASHR_I64 [[S_MOV_B]], 1, implicit-def $scc97 ; GCN-NEXT: S_ENDPGM 0, implicit [[S_ASHR_I64_]]98 %0:sreg_64 = S_MOV_B64_IMM_PSEUDO 429496729599 %1:sreg_64 = S_ASHR_I64 %0, 1, implicit-def $scc100 S_ENDPGM 0, implicit %1101 102...103 104---105name: imm64_ashr_int32_const_0x7fffffff106body: |107 bb.0:108 ; GCN-LABEL: name: imm64_ashr_int32_const_0x7fffffff109 ; GCN: [[S_ASHR_I64_:%[0-9]+]]:sreg_64 = S_ASHR_I64 2147483647, 1, implicit-def $scc110 ; GCN-NEXT: S_ENDPGM 0, implicit [[S_ASHR_I64_]]111 %0:sreg_64 = S_MOV_B64_IMM_PSEUDO 2147483647112 %1:sreg_64 = S_ASHR_I64 %0, 1, implicit-def $scc113 S_ENDPGM 0, implicit %1114 115...116 117---118name: imm64_ashr_int32_const_0xffffffffffffffff119body: |120 bb.0:121 ; GCN-LABEL: name: imm64_ashr_int32_const_0xffffffffffffffff122 ; GCN: [[S_ASHR_I64_:%[0-9]+]]:sreg_64 = S_ASHR_I64 -1, 1, implicit-def $scc123 ; GCN-NEXT: S_ENDPGM 0, implicit [[S_ASHR_I64_]]124 %0:sreg_64 = S_MOV_B64_IMM_PSEUDO -1125 %1:sreg_64 = S_ASHR_I64 %0, 1, implicit-def $scc126 S_ENDPGM 0, implicit %1127 128...129