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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: llc -mtriple=amdgcn < %s | FileCheck -enable-var-scope -check-prefixes=SI %s3; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -enable-var-scope -check-prefixes=VI %s4; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX11,GFX11-TRUE16 %s5; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX11,GFX11-FAKE16 %s6 7declare float @llvm.fabs.f32(float) #18declare double @llvm.fabs.f64(double) #19 10define amdgpu_kernel void @test_isinf_pattern(ptr addrspace(1) nocapture %out, float %x) #0 {11; SI-LABEL: test_isinf_pattern:12; SI: ; %bb.0:13; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x914; SI-NEXT: s_load_dword s4, s[4:5], 0xb15; SI-NEXT: s_mov_b32 s3, 0xf00016; SI-NEXT: s_mov_b32 s2, -117; SI-NEXT: v_mov_b32_e32 v0, 0x20418; SI-NEXT: s_waitcnt lgkmcnt(0)19; SI-NEXT: v_cmp_class_f32_e32 vcc, s4, v020; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc21; SI-NEXT: buffer_store_dword v0, off, s[0:3], 022; SI-NEXT: s_endpgm23;24; VI-LABEL: test_isinf_pattern:25; VI: ; %bb.0:26; VI-NEXT: s_load_dword s2, s[4:5], 0x2c27; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2428; VI-NEXT: v_mov_b32_e32 v0, 0x20429; VI-NEXT: s_waitcnt lgkmcnt(0)30; VI-NEXT: v_cmp_class_f32_e32 vcc, s2, v031; VI-NEXT: v_mov_b32_e32 v0, s032; VI-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc33; VI-NEXT: v_mov_b32_e32 v1, s134; VI-NEXT: flat_store_dword v[0:1], v235; VI-NEXT: s_endpgm36;37; GFX11-LABEL: test_isinf_pattern:38; GFX11: ; %bb.0:39; GFX11-NEXT: s_clause 0x140; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c41; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x2442; GFX11-NEXT: v_mov_b32_e32 v0, 043; GFX11-NEXT: s_waitcnt lgkmcnt(0)44; GFX11-NEXT: v_cmp_class_f32_e64 s2, s2, 0x20445; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)46; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 1, s247; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]48; GFX11-NEXT: s_endpgm49 %fabs = tail call float @llvm.fabs.f32(float %x) #150 %cmp = fcmp oeq float %fabs, 0x7FF000000000000051 %ext = zext i1 %cmp to i3252 store i32 %ext, ptr addrspace(1) %out, align 453 ret void54}55 56define amdgpu_kernel void @test_not_isinf_pattern_0(ptr addrspace(1) nocapture %out, float %x) #0 {57; SI-LABEL: test_not_isinf_pattern_0:58; SI: ; %bb.0:59; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x960; SI-NEXT: s_load_dword s4, s[4:5], 0xb61; SI-NEXT: s_mov_b32 s3, 0xf00062; SI-NEXT: s_mov_b32 s2, -163; SI-NEXT: v_mov_b32_e32 v0, 0x7f80000064; SI-NEXT: s_waitcnt lgkmcnt(0)65; SI-NEXT: v_cmp_nlg_f32_e64 s[4:5], |s4|, v066; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]67; SI-NEXT: buffer_store_dword v0, off, s[0:3], 068; SI-NEXT: s_endpgm69;70; VI-LABEL: test_not_isinf_pattern_0:71; VI: ; %bb.0:72; VI-NEXT: s_load_dword s2, s[4:5], 0x2c73; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2474; VI-NEXT: v_mov_b32_e32 v0, 0x7f80000075; VI-NEXT: s_waitcnt lgkmcnt(0)76; VI-NEXT: v_cmp_nlg_f32_e64 s[2:3], |s2|, v077; VI-NEXT: v_mov_b32_e32 v0, s078; VI-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[2:3]79; VI-NEXT: v_mov_b32_e32 v1, s180; VI-NEXT: flat_store_dword v[0:1], v281; VI-NEXT: s_endpgm82;83; GFX11-LABEL: test_not_isinf_pattern_0:84; GFX11: ; %bb.0:85; GFX11-NEXT: s_clause 0x186; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c87; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x2488; GFX11-NEXT: v_mov_b32_e32 v0, 089; GFX11-NEXT: s_waitcnt lgkmcnt(0)90; GFX11-NEXT: v_cmp_nlg_f32_e64 s2, 0x7f800000, |s2|91; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)92; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 1, s293; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]94; GFX11-NEXT: s_endpgm95 %fabs = tail call float @llvm.fabs.f32(float %x) #196 %cmp = fcmp ueq float %fabs, 0x7FF000000000000097 %ext = zext i1 %cmp to i3298 store i32 %ext, ptr addrspace(1) %out, align 499 ret void100}101 102define amdgpu_kernel void @test_not_isinf_pattern_1(ptr addrspace(1) nocapture %out, float %x) #0 {103; SI-LABEL: test_not_isinf_pattern_1:104; SI: ; %bb.0:105; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9106; SI-NEXT: s_mov_b32 s3, 0xf000107; SI-NEXT: s_mov_b32 s2, -1108; SI-NEXT: v_mov_b32_e32 v0, 0109; SI-NEXT: s_waitcnt lgkmcnt(0)110; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0111; SI-NEXT: s_endpgm112;113; VI-LABEL: test_not_isinf_pattern_1:114; VI: ; %bb.0:115; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24116; VI-NEXT: v_mov_b32_e32 v2, 0117; VI-NEXT: s_waitcnt lgkmcnt(0)118; VI-NEXT: v_mov_b32_e32 v0, s0119; VI-NEXT: v_mov_b32_e32 v1, s1120; VI-NEXT: flat_store_dword v[0:1], v2121; VI-NEXT: s_endpgm122;123; GFX11-LABEL: test_not_isinf_pattern_1:124; GFX11: ; %bb.0:125; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24126; GFX11-NEXT: v_mov_b32_e32 v0, 0127; GFX11-NEXT: s_waitcnt lgkmcnt(0)128; GFX11-NEXT: global_store_b32 v0, v0, s[0:1]129; GFX11-NEXT: s_endpgm130 %fabs = tail call float @llvm.fabs.f32(float %x) #1131 %cmp = fcmp oeq float %fabs, 0xFFF0000000000000132 %ext = zext i1 %cmp to i32133 store i32 %ext, ptr addrspace(1) %out, align 4134 ret void135}136 137define amdgpu_kernel void @test_isfinite_pattern_0(ptr addrspace(1) nocapture %out, float %x) #0 {138; SI-LABEL: test_isfinite_pattern_0:139; SI: ; %bb.0:140; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9141; SI-NEXT: s_load_dword s4, s[4:5], 0xb142; SI-NEXT: s_mov_b32 s3, 0xf000143; SI-NEXT: s_mov_b32 s2, -1144; SI-NEXT: v_mov_b32_e32 v0, 0x1f8145; SI-NEXT: s_waitcnt lgkmcnt(0)146; SI-NEXT: v_cmp_class_f32_e32 vcc, s4, v0147; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc148; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0149; SI-NEXT: s_endpgm150;151; VI-LABEL: test_isfinite_pattern_0:152; VI: ; %bb.0:153; VI-NEXT: s_load_dword s2, s[4:5], 0x2c154; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24155; VI-NEXT: v_mov_b32_e32 v0, 0x1f8156; VI-NEXT: s_waitcnt lgkmcnt(0)157; VI-NEXT: v_cmp_class_f32_e32 vcc, s2, v0158; VI-NEXT: v_mov_b32_e32 v0, s0159; VI-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc160; VI-NEXT: v_mov_b32_e32 v1, s1161; VI-NEXT: flat_store_dword v[0:1], v2162; VI-NEXT: s_endpgm163;164; GFX11-LABEL: test_isfinite_pattern_0:165; GFX11: ; %bb.0:166; GFX11-NEXT: s_clause 0x1167; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c168; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24169; GFX11-NEXT: v_mov_b32_e32 v0, 0170; GFX11-NEXT: s_waitcnt lgkmcnt(0)171; GFX11-NEXT: v_cmp_class_f32_e64 s2, s2, 0x1f8172; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)173; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 1, s2174; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]175; GFX11-NEXT: s_endpgm176 %ord = fcmp ord float %x, 0.000000e+00177 %x.fabs = tail call float @llvm.fabs.f32(float %x) #1178 %ninf = fcmp une float %x.fabs, 0x7FF0000000000000179 %and = and i1 %ord, %ninf180 %ext = zext i1 %and to i32181 store i32 %ext, ptr addrspace(1) %out, align 4182 ret void183}184 185define amdgpu_kernel void @test_isfinite_pattern_1(ptr addrspace(1) nocapture %out, float %x) #0 {186; SI-LABEL: test_isfinite_pattern_1:187; SI: ; %bb.0:188; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9189; SI-NEXT: s_load_dword s4, s[4:5], 0xb190; SI-NEXT: s_mov_b32 s3, 0xf000191; SI-NEXT: s_mov_b32 s2, -1192; SI-NEXT: v_mov_b32_e32 v0, 0x1f8193; SI-NEXT: s_waitcnt lgkmcnt(0)194; SI-NEXT: v_cmp_class_f32_e32 vcc, s4, v0195; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc196; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0197; SI-NEXT: s_endpgm198;199; VI-LABEL: test_isfinite_pattern_1:200; VI: ; %bb.0:201; VI-NEXT: s_load_dword s2, s[4:5], 0x2c202; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24203; VI-NEXT: v_mov_b32_e32 v0, 0x1f8204; VI-NEXT: s_waitcnt lgkmcnt(0)205; VI-NEXT: v_cmp_class_f32_e32 vcc, s2, v0206; VI-NEXT: v_mov_b32_e32 v0, s0207; VI-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc208; VI-NEXT: v_mov_b32_e32 v1, s1209; VI-NEXT: flat_store_dword v[0:1], v2210; VI-NEXT: s_endpgm211;212; GFX11-LABEL: test_isfinite_pattern_1:213; GFX11: ; %bb.0:214; GFX11-NEXT: s_clause 0x1215; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c216; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24217; GFX11-NEXT: v_mov_b32_e32 v0, 0218; GFX11-NEXT: s_waitcnt lgkmcnt(0)219; GFX11-NEXT: v_cmp_class_f32_e64 s2, s2, 0x1f8220; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)221; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 1, s2222; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]223; GFX11-NEXT: s_endpgm224 %x.fabs = tail call float @llvm.fabs.f32(float %x) #3225 %cmpinf = fcmp one float %x.fabs, 0x7FF0000000000000226 %ext = zext i1 %cmpinf to i32227 store i32 %ext, ptr addrspace(1) %out, align 4228 ret void229}230 231; Use negative infinity232define amdgpu_kernel void @test_isfinite_not_pattern_0(ptr addrspace(1) nocapture %out, float %x) #0 {233; SI-LABEL: test_isfinite_not_pattern_0:234; SI: ; %bb.0:235; SI-NEXT: s_load_dword s6, s[4:5], 0xb236; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9237; SI-NEXT: s_mov_b32 s3, 0xf000238; SI-NEXT: s_mov_b32 s2, -1239; SI-NEXT: s_waitcnt lgkmcnt(0)240; SI-NEXT: v_cmp_o_f32_e64 s[4:5], s6, s6241; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]242; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0243; SI-NEXT: s_endpgm244;245; VI-LABEL: test_isfinite_not_pattern_0:246; VI: ; %bb.0:247; VI-NEXT: s_load_dword s2, s[4:5], 0x2c248; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24249; VI-NEXT: s_waitcnt lgkmcnt(0)250; VI-NEXT: v_cmp_o_f32_e64 s[2:3], s2, s2251; VI-NEXT: v_mov_b32_e32 v0, s0252; VI-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[2:3]253; VI-NEXT: v_mov_b32_e32 v1, s1254; VI-NEXT: flat_store_dword v[0:1], v2255; VI-NEXT: s_endpgm256;257; GFX11-LABEL: test_isfinite_not_pattern_0:258; GFX11: ; %bb.0:259; GFX11-NEXT: s_clause 0x1260; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c261; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24262; GFX11-NEXT: v_mov_b32_e32 v0, 0263; GFX11-NEXT: s_waitcnt lgkmcnt(0)264; GFX11-NEXT: v_cmp_o_f32_e64 s2, s2, s2265; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)266; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 1, s2267; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]268; GFX11-NEXT: s_endpgm269 %ord = fcmp ord float %x, 0.000000e+00270 %x.fabs = tail call float @llvm.fabs.f32(float %x) #1271 %ninf = fcmp une float %x.fabs, 0xFFF0000000000000272 %and = and i1 %ord, %ninf273 %ext = zext i1 %and to i32274 store i32 %ext, ptr addrspace(1) %out, align 4275 ret void276}277 278; No fabs279define amdgpu_kernel void @test_isfinite_not_pattern_1(ptr addrspace(1) nocapture %out, float %x) #0 {280; SI-LABEL: test_isfinite_not_pattern_1:281; SI: ; %bb.0:282; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9283; SI-NEXT: s_load_dword s6, s[4:5], 0xb284; SI-NEXT: s_mov_b32 s3, 0xf000285; SI-NEXT: s_mov_b32 s2, -1286; SI-NEXT: v_mov_b32_e32 v0, 0x7f800000287; SI-NEXT: s_waitcnt lgkmcnt(0)288; SI-NEXT: v_cmp_o_f32_e64 s[4:5], s6, s6289; SI-NEXT: v_cmp_neq_f32_e32 vcc, s6, v0290; SI-NEXT: s_and_b64 s[4:5], s[4:5], vcc291; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]292; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0293; SI-NEXT: s_endpgm294;295; VI-LABEL: test_isfinite_not_pattern_1:296; VI: ; %bb.0:297; VI-NEXT: s_load_dword s6, s[4:5], 0x2c298; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24299; VI-NEXT: v_mov_b32_e32 v0, 0x7f800000300; VI-NEXT: s_waitcnt lgkmcnt(0)301; VI-NEXT: v_cmp_o_f32_e64 s[2:3], s6, s6302; VI-NEXT: v_cmp_neq_f32_e32 vcc, s6, v0303; VI-NEXT: s_and_b64 s[2:3], s[2:3], vcc304; VI-NEXT: v_mov_b32_e32 v0, s0305; VI-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[2:3]306; VI-NEXT: v_mov_b32_e32 v1, s1307; VI-NEXT: flat_store_dword v[0:1], v2308; VI-NEXT: s_endpgm309;310; GFX11-LABEL: test_isfinite_not_pattern_1:311; GFX11: ; %bb.0:312; GFX11-NEXT: s_clause 0x1313; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c314; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24315; GFX11-NEXT: v_mov_b32_e32 v0, 0316; GFX11-NEXT: s_waitcnt lgkmcnt(0)317; GFX11-NEXT: v_cmp_o_f32_e64 s3, s2, s2318; GFX11-NEXT: v_cmp_neq_f32_e64 s2, 0x7f800000, s2319; GFX11-NEXT: s_and_b32 s2, s3, s2320; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)321; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 1, s2322; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]323; GFX11-NEXT: s_endpgm324 %ord = fcmp ord float %x, 0.000000e+00325 %ninf = fcmp une float %x, 0x7FF0000000000000326 %and = and i1 %ord, %ninf327 %ext = zext i1 %and to i32328 store i32 %ext, ptr addrspace(1) %out, align 4329 ret void330}331 332; fabs of different value333define amdgpu_kernel void @test_isfinite_not_pattern_2(ptr addrspace(1) nocapture %out, float %x, float %y) #0 {334; SI-LABEL: test_isfinite_not_pattern_2:335; SI: ; %bb.0:336; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9337; SI-NEXT: s_mov_b32 s7, 0xf000338; SI-NEXT: s_mov_b32 s6, -1339; SI-NEXT: v_mov_b32_e32 v0, 0x7f800000340; SI-NEXT: s_waitcnt lgkmcnt(0)341; SI-NEXT: s_mov_b32 s4, s0342; SI-NEXT: s_mov_b32 s5, s1343; SI-NEXT: v_cmp_o_f32_e64 s[0:1], s2, s2344; SI-NEXT: v_cmp_neq_f32_e64 s[2:3], |s3|, v0345; SI-NEXT: s_and_b64 s[0:1], s[0:1], s[2:3]346; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]347; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0348; SI-NEXT: s_endpgm349;350; VI-LABEL: test_isfinite_not_pattern_2:351; VI: ; %bb.0:352; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24353; VI-NEXT: v_mov_b32_e32 v0, 0x7f800000354; VI-NEXT: s_waitcnt lgkmcnt(0)355; VI-NEXT: v_cmp_o_f32_e64 s[4:5], s2, s2356; VI-NEXT: v_cmp_neq_f32_e64 s[2:3], |s3|, v0357; VI-NEXT: s_and_b64 s[2:3], s[4:5], s[2:3]358; VI-NEXT: v_mov_b32_e32 v0, s0359; VI-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[2:3]360; VI-NEXT: v_mov_b32_e32 v1, s1361; VI-NEXT: flat_store_dword v[0:1], v2362; VI-NEXT: s_endpgm363;364; GFX11-LABEL: test_isfinite_not_pattern_2:365; GFX11: ; %bb.0:366; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24367; GFX11-NEXT: v_mov_b32_e32 v0, 0368; GFX11-NEXT: s_waitcnt lgkmcnt(0)369; GFX11-NEXT: v_cmp_o_f32_e64 s2, s2, s2370; GFX11-NEXT: v_cmp_neq_f32_e64 s3, 0x7f800000, |s3|371; GFX11-NEXT: s_and_b32 s2, s2, s3372; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)373; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 1, s2374; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]375; GFX11-NEXT: s_endpgm376 %ord = fcmp ord float %x, 0.000000e+00377 %x.fabs = tail call float @llvm.fabs.f32(float %y) #1378 %ninf = fcmp une float %x.fabs, 0x7FF0000000000000379 %and = and i1 %ord, %ninf380 %ext = zext i1 %and to i32381 store i32 %ext, ptr addrspace(1) %out, align 4382 ret void383}384 385; Wrong ordered compare type386define amdgpu_kernel void @test_isfinite_not_pattern_3(ptr addrspace(1) nocapture %out, float %x) #0 {387; SI-LABEL: test_isfinite_not_pattern_3:388; SI: ; %bb.0:389; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9390; SI-NEXT: s_load_dword s6, s[4:5], 0xb391; SI-NEXT: s_mov_b32 s3, 0xf000392; SI-NEXT: s_mov_b32 s2, -1393; SI-NEXT: v_mov_b32_e32 v0, 0x7f800000394; SI-NEXT: s_waitcnt lgkmcnt(0)395; SI-NEXT: v_cmp_u_f32_e64 s[4:5], s6, s6396; SI-NEXT: v_cmp_neq_f32_e64 s[6:7], |s6|, v0397; SI-NEXT: s_and_b64 s[4:5], s[4:5], s[6:7]398; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]399; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0400; SI-NEXT: s_endpgm401;402; VI-LABEL: test_isfinite_not_pattern_3:403; VI: ; %bb.0:404; VI-NEXT: s_load_dword s6, s[4:5], 0x2c405; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24406; VI-NEXT: v_mov_b32_e32 v0, 0x7f800000407; VI-NEXT: s_waitcnt lgkmcnt(0)408; VI-NEXT: v_cmp_u_f32_e64 s[2:3], s6, s6409; VI-NEXT: v_cmp_neq_f32_e64 s[4:5], |s6|, v0410; VI-NEXT: s_and_b64 s[2:3], s[2:3], s[4:5]411; VI-NEXT: v_mov_b32_e32 v0, s0412; VI-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[2:3]413; VI-NEXT: v_mov_b32_e32 v1, s1414; VI-NEXT: flat_store_dword v[0:1], v2415; VI-NEXT: s_endpgm416;417; GFX11-LABEL: test_isfinite_not_pattern_3:418; GFX11: ; %bb.0:419; GFX11-NEXT: s_clause 0x1420; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c421; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24422; GFX11-NEXT: v_mov_b32_e32 v0, 0423; GFX11-NEXT: s_waitcnt lgkmcnt(0)424; GFX11-NEXT: v_cmp_u_f32_e64 s3, s2, s2425; GFX11-NEXT: v_cmp_neq_f32_e64 s2, 0x7f800000, |s2|426; GFX11-NEXT: s_and_b32 s2, s3, s2427; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)428; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 1, s2429; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]430; GFX11-NEXT: s_endpgm431 %ord = fcmp uno float %x, 0.000000e+00432 %x.fabs = tail call float @llvm.fabs.f32(float %x) #1433 %ninf = fcmp une float %x.fabs, 0x7FF0000000000000434 %and = and i1 %ord, %ninf435 %ext = zext i1 %and to i32436 store i32 %ext, ptr addrspace(1) %out, align 4437 ret void438}439 440define amdgpu_kernel void @test_isfinite_pattern_4(ptr addrspace(1) nocapture %out, float %x) #0 {441; SI-LABEL: test_isfinite_pattern_4:442; SI: ; %bb.0:443; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9444; SI-NEXT: s_load_dword s4, s[4:5], 0xb445; SI-NEXT: s_mov_b32 s3, 0xf000446; SI-NEXT: s_mov_b32 s2, -1447; SI-NEXT: v_mov_b32_e32 v0, 0x1f8448; SI-NEXT: s_waitcnt lgkmcnt(0)449; SI-NEXT: v_cmp_class_f32_e32 vcc, s4, v0450; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc451; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0452; SI-NEXT: s_endpgm453;454; VI-LABEL: test_isfinite_pattern_4:455; VI: ; %bb.0:456; VI-NEXT: s_load_dword s2, s[4:5], 0x2c457; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24458; VI-NEXT: v_mov_b32_e32 v0, 0x1f8459; VI-NEXT: s_waitcnt lgkmcnt(0)460; VI-NEXT: v_cmp_class_f32_e32 vcc, s2, v0461; VI-NEXT: v_mov_b32_e32 v0, s0462; VI-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc463; VI-NEXT: v_mov_b32_e32 v1, s1464; VI-NEXT: flat_store_dword v[0:1], v2465; VI-NEXT: s_endpgm466;467; GFX11-LABEL: test_isfinite_pattern_4:468; GFX11: ; %bb.0:469; GFX11-NEXT: s_clause 0x1470; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c471; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24472; GFX11-NEXT: v_mov_b32_e32 v0, 0473; GFX11-NEXT: s_waitcnt lgkmcnt(0)474; GFX11-NEXT: v_cmp_class_f32_e64 s2, s2, 0x1f8475; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)476; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 1, s2477; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]478; GFX11-NEXT: s_endpgm479 %ord = fcmp ord float %x, 0.000000e+00480 %x.fabs = tail call float @llvm.fabs.f32(float %x) #1481 %ninf = fcmp one float %x.fabs, 0x7FF0000000000000482 %and = and i1 %ord, %ninf483 %ext = zext i1 %and to i32484 store i32 %ext, ptr addrspace(1) %out, align 4485 ret void486}487 488define amdgpu_kernel void @test_isfinite_pattern_4_commute_and(ptr addrspace(1) nocapture %out, float %x) #0 {489; SI-LABEL: test_isfinite_pattern_4_commute_and:490; SI: ; %bb.0:491; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9492; SI-NEXT: s_load_dword s4, s[4:5], 0xb493; SI-NEXT: s_mov_b32 s3, 0xf000494; SI-NEXT: s_mov_b32 s2, -1495; SI-NEXT: v_mov_b32_e32 v0, 0x1f8496; SI-NEXT: s_waitcnt lgkmcnt(0)497; SI-NEXT: v_cmp_class_f32_e32 vcc, s4, v0498; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc499; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0500; SI-NEXT: s_endpgm501;502; VI-LABEL: test_isfinite_pattern_4_commute_and:503; VI: ; %bb.0:504; VI-NEXT: s_load_dword s2, s[4:5], 0x2c505; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24506; VI-NEXT: v_mov_b32_e32 v0, 0x1f8507; VI-NEXT: s_waitcnt lgkmcnt(0)508; VI-NEXT: v_cmp_class_f32_e32 vcc, s2, v0509; VI-NEXT: v_mov_b32_e32 v0, s0510; VI-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc511; VI-NEXT: v_mov_b32_e32 v1, s1512; VI-NEXT: flat_store_dword v[0:1], v2513; VI-NEXT: s_endpgm514;515; GFX11-LABEL: test_isfinite_pattern_4_commute_and:516; GFX11: ; %bb.0:517; GFX11-NEXT: s_clause 0x1518; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c519; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24520; GFX11-NEXT: v_mov_b32_e32 v0, 0521; GFX11-NEXT: s_waitcnt lgkmcnt(0)522; GFX11-NEXT: v_cmp_class_f32_e64 s2, s2, 0x1f8523; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)524; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 1, s2525; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]526; GFX11-NEXT: s_endpgm527 %ord = fcmp ord float %x, 0.000000e+00528 %x.fabs = tail call float @llvm.fabs.f32(float %x) #1529 %ninf = fcmp one float %x.fabs, 0x7FF0000000000000530 %and = and i1 %ninf, %ord531 %ext = zext i1 %and to i32532 store i32 %ext, ptr addrspace(1) %out, align 4533 ret void534}535 536define amdgpu_kernel void @test_not_isfinite_pattern_4_wrong_ord_test(ptr addrspace(1) nocapture %out, float %x, [8 x i32], float %y) #0 {537; SI-LABEL: test_not_isfinite_pattern_4_wrong_ord_test:538; SI: ; %bb.0:539; SI-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x9540; SI-NEXT: s_load_dword s0, s[4:5], 0x14541; SI-NEXT: s_load_dword s1, s[4:5], 0xb542; SI-NEXT: s_mov_b32 s11, 0xf000543; SI-NEXT: s_mov_b32 s10, -1544; SI-NEXT: v_mov_b32_e32 v0, 0x1f8545; SI-NEXT: s_waitcnt lgkmcnt(0)546; SI-NEXT: v_mov_b32_e32 v1, s0547; SI-NEXT: v_cmp_o_f32_e32 vcc, s1, v1548; SI-NEXT: v_cmp_class_f32_e64 s[0:1], s1, v0549; SI-NEXT: s_and_b64 s[0:1], vcc, s[0:1]550; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]551; SI-NEXT: buffer_store_dword v0, off, s[8:11], 0552; SI-NEXT: s_endpgm553;554; VI-LABEL: test_not_isfinite_pattern_4_wrong_ord_test:555; VI: ; %bb.0:556; VI-NEXT: s_load_dword s0, s[4:5], 0x50557; VI-NEXT: s_load_dword s1, s[4:5], 0x2c558; VI-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24559; VI-NEXT: v_mov_b32_e32 v0, 0x1f8560; VI-NEXT: s_waitcnt lgkmcnt(0)561; VI-NEXT: v_mov_b32_e32 v1, s0562; VI-NEXT: v_cmp_class_f32_e32 vcc, s1, v0563; VI-NEXT: v_cmp_o_f32_e64 s[0:1], s1, v1564; VI-NEXT: s_and_b64 s[0:1], s[0:1], vcc565; VI-NEXT: v_mov_b32_e32 v0, s2566; VI-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]567; VI-NEXT: v_mov_b32_e32 v1, s3568; VI-NEXT: flat_store_dword v[0:1], v2569; VI-NEXT: s_endpgm570;571; GFX11-LABEL: test_not_isfinite_pattern_4_wrong_ord_test:572; GFX11: ; %bb.0:573; GFX11-NEXT: s_clause 0x2574; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c575; GFX11-NEXT: s_load_b32 s3, s[4:5], 0x50576; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24577; GFX11-NEXT: v_mov_b32_e32 v0, 0578; GFX11-NEXT: s_waitcnt lgkmcnt(0)579; GFX11-NEXT: v_cmp_o_f32_e64 s3, s2, s3580; GFX11-NEXT: v_cmp_class_f32_e64 s2, s2, 0x1f8581; GFX11-NEXT: s_and_b32 s2, s3, s2582; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)583; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 1, s2584; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]585; GFX11-NEXT: s_endpgm586 %ord = fcmp ord float %x, %y587 %x.fabs = tail call float @llvm.fabs.f32(float %x) #1588 %ninf = fcmp one float %x.fabs, 0x7FF0000000000000589 %and = and i1 %ord, %ninf590 %ext = zext i1 %and to i32591 store i32 %ext, ptr addrspace(1) %out, align 4592 ret void593}594 595define amdgpu_kernel void @test_isinf_pattern_f16(ptr addrspace(1) nocapture %out, half %x) #0 {596; SI-LABEL: test_isinf_pattern_f16:597; SI: ; %bb.0:598; SI-NEXT: s_load_dword s6, s[4:5], 0xb599; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9600; SI-NEXT: s_mov_b32 s3, 0xf000601; SI-NEXT: s_mov_b32 s2, -1602; SI-NEXT: s_waitcnt lgkmcnt(0)603; SI-NEXT: s_and_b32 s4, s6, 0x7fff604; SI-NEXT: s_cmpk_eq_i32 s4, 0x7c00605; SI-NEXT: s_cselect_b64 s[4:5], -1, 0606; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]607; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0608; SI-NEXT: s_endpgm609;610; VI-LABEL: test_isinf_pattern_f16:611; VI: ; %bb.0:612; VI-NEXT: s_load_dword s2, s[4:5], 0x2c613; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24614; VI-NEXT: v_mov_b32_e32 v0, 0x204615; VI-NEXT: s_waitcnt lgkmcnt(0)616; VI-NEXT: v_cmp_class_f16_e32 vcc, s2, v0617; VI-NEXT: v_mov_b32_e32 v0, s0618; VI-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc619; VI-NEXT: v_mov_b32_e32 v1, s1620; VI-NEXT: flat_store_dword v[0:1], v2621; VI-NEXT: s_endpgm622;623; GFX11-LABEL: test_isinf_pattern_f16:624; GFX11: ; %bb.0:625; GFX11-NEXT: s_clause 0x1626; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c627; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24628; GFX11-NEXT: v_mov_b32_e32 v0, 0629; GFX11-NEXT: s_waitcnt lgkmcnt(0)630; GFX11-NEXT: v_cmp_class_f16_e64 s2, s2, 0x204631; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)632; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 1, s2633; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]634; GFX11-NEXT: s_endpgm635 %fabs = tail call half @llvm.fabs.f16(half %x) #1636 %cmp = fcmp oeq half %fabs, 0xH7C00637 %ext = zext i1 %cmp to i32638 store i32 %ext, ptr addrspace(1) %out, align 4639 ret void640}641 642define amdgpu_kernel void @test_isfinite_pattern_0_f16(ptr addrspace(1) nocapture %out, half %x) #0 {643; SI-LABEL: test_isfinite_pattern_0_f16:644; SI: ; %bb.0:645; SI-NEXT: s_load_dword s6, s[4:5], 0xb646; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9647; SI-NEXT: s_mov_b32 s3, 0xf000648; SI-NEXT: s_mov_b32 s2, -1649; SI-NEXT: s_waitcnt lgkmcnt(0)650; SI-NEXT: v_cvt_f32_f16_e32 v0, s6651; SI-NEXT: s_and_b32 s4, s6, 0x7fff652; SI-NEXT: v_cmp_o_f32_e32 vcc, v0, v0653; SI-NEXT: s_cmpk_lg_i32 s4, 0x7c00654; SI-NEXT: s_cselect_b64 s[4:5], -1, 0655; SI-NEXT: s_and_b64 s[4:5], vcc, s[4:5]656; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]657; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0658; SI-NEXT: s_endpgm659;660; VI-LABEL: test_isfinite_pattern_0_f16:661; VI: ; %bb.0:662; VI-NEXT: s_load_dword s2, s[4:5], 0x2c663; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24664; VI-NEXT: v_mov_b32_e32 v0, 0x1f8665; VI-NEXT: s_waitcnt lgkmcnt(0)666; VI-NEXT: v_cmp_class_f16_e32 vcc, s2, v0667; VI-NEXT: v_mov_b32_e32 v0, s0668; VI-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc669; VI-NEXT: v_mov_b32_e32 v1, s1670; VI-NEXT: flat_store_dword v[0:1], v2671; VI-NEXT: s_endpgm672;673; GFX11-LABEL: test_isfinite_pattern_0_f16:674; GFX11: ; %bb.0:675; GFX11-NEXT: s_clause 0x1676; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c677; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24678; GFX11-NEXT: v_mov_b32_e32 v0, 0679; GFX11-NEXT: s_waitcnt lgkmcnt(0)680; GFX11-NEXT: v_cmp_class_f16_e64 s2, s2, 0x1f8681; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)682; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 1, s2683; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]684; GFX11-NEXT: s_endpgm685 %ord = fcmp ord half %x, 0.0686 %x.fabs = tail call half @llvm.fabs.f16(half %x) #1687 %ninf = fcmp une half %x.fabs, 0xH7C00688 %and = and i1 %ord, %ninf689 %ext = zext i1 %and to i32690 store i32 %ext, ptr addrspace(1) %out, align 4691 ret void692}693 694define amdgpu_kernel void @test_isfinite_pattern_4_f16(ptr addrspace(1) nocapture %out, half %x) #0 {695; SI-LABEL: test_isfinite_pattern_4_f16:696; SI: ; %bb.0:697; SI-NEXT: s_load_dword s6, s[4:5], 0xb698; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9699; SI-NEXT: s_mov_b32 s3, 0xf000700; SI-NEXT: s_mov_b32 s2, -1701; SI-NEXT: s_waitcnt lgkmcnt(0)702; SI-NEXT: s_and_b32 s4, s6, 0x7fff703; SI-NEXT: s_cmpk_lt_i32 s4, 0x7c00704; SI-NEXT: s_cselect_b64 s[4:5], -1, 0705; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]706; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0707; SI-NEXT: s_endpgm708;709; VI-LABEL: test_isfinite_pattern_4_f16:710; VI: ; %bb.0:711; VI-NEXT: s_load_dword s2, s[4:5], 0x2c712; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24713; VI-NEXT: v_mov_b32_e32 v0, 0x1f8714; VI-NEXT: s_waitcnt lgkmcnt(0)715; VI-NEXT: v_cmp_class_f16_e32 vcc, s2, v0716; VI-NEXT: v_mov_b32_e32 v0, s0717; VI-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc718; VI-NEXT: v_mov_b32_e32 v1, s1719; VI-NEXT: flat_store_dword v[0:1], v2720; VI-NEXT: s_endpgm721;722; GFX11-LABEL: test_isfinite_pattern_4_f16:723; GFX11: ; %bb.0:724; GFX11-NEXT: s_clause 0x1725; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c726; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24727; GFX11-NEXT: v_mov_b32_e32 v0, 0728; GFX11-NEXT: s_waitcnt lgkmcnt(0)729; GFX11-NEXT: v_cmp_class_f16_e64 s2, s2, 0x1f8730; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)731; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 1, s2732; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]733; GFX11-NEXT: s_endpgm734 %ord = fcmp ord half %x, 0.0735 %x.fabs = tail call half @llvm.fabs.f16(half %x) #1736 %ninf = fcmp one half %x.fabs, 0xH7C00737 %and = and i1 %ord, %ninf738 %ext = zext i1 %and to i32739 store i32 %ext, ptr addrspace(1) %out, align 4740 ret void741}742 743declare half @llvm.fabs.f16(half) #1744 745attributes #0 = { nounwind }746attributes #1 = { nounwind readnone }747;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:748; GFX11-FAKE16: {{.*}}749; GFX11-TRUE16: {{.*}}750