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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn < %s | FileCheck %s --check-prefixes=SI3; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck %s --check-prefixes=VI4; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck %s -check-prefixes=GFX11,GFX11-SDAG5; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck %s -check-prefixes=GFX11,GFX11-GISEL6; RUN: llc -mtriple=r600 -mcpu=redwood < %s | FileCheck %s --check-prefixes=EG7 8declare float @llvm.fabs.f32(float) #19 10define amdgpu_kernel void @fp_to_sint_i32(ptr addrspace(1) %out, float %in) {11; SI-LABEL: fp_to_sint_i32:12; SI: ; %bb.0:13; SI-NEXT: s_load_dword s6, s[4:5], 0xb14; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x915; SI-NEXT: s_mov_b32 s3, 0xf00016; SI-NEXT: s_mov_b32 s2, -117; SI-NEXT: s_waitcnt lgkmcnt(0)18; SI-NEXT: v_cvt_i32_f32_e32 v0, s619; SI-NEXT: buffer_store_dword v0, off, s[0:3], 020; SI-NEXT: s_endpgm21;22; VI-LABEL: fp_to_sint_i32:23; VI: ; %bb.0:24; VI-NEXT: s_load_dword s2, s[4:5], 0x2c25; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2426; VI-NEXT: s_mov_b32 s3, 0xf00027; VI-NEXT: s_waitcnt lgkmcnt(0)28; VI-NEXT: v_cvt_i32_f32_e32 v0, s229; VI-NEXT: s_mov_b32 s2, -130; VI-NEXT: buffer_store_dword v0, off, s[0:3], 031; VI-NEXT: s_endpgm32;33; GFX11-SDAG-LABEL: fp_to_sint_i32:34; GFX11-SDAG: ; %bb.0:35; GFX11-SDAG-NEXT: s_clause 0x136; GFX11-SDAG-NEXT: s_load_b32 s2, s[4:5], 0x2c37; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x2438; GFX11-SDAG-NEXT: v_mov_b32_e32 v0, 039; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)40; GFX11-SDAG-NEXT: v_cvt_i32_f32_e32 v1, s241; GFX11-SDAG-NEXT: global_store_b32 v0, v1, s[0:1]42; GFX11-SDAG-NEXT: s_endpgm43;44; GFX11-GISEL-LABEL: fp_to_sint_i32:45; GFX11-GISEL: ; %bb.0:46; GFX11-GISEL-NEXT: s_clause 0x147; GFX11-GISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c48; GFX11-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x2449; GFX11-GISEL-NEXT: v_mov_b32_e32 v1, 050; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)51; GFX11-GISEL-NEXT: v_cvt_i32_f32_e32 v0, s252; GFX11-GISEL-NEXT: global_store_b32 v1, v0, s[0:1]53; GFX11-GISEL-NEXT: s_endpgm54;55; EG-LABEL: fp_to_sint_i32:56; EG: ; %bb.0:57; EG-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[]58; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 159; EG-NEXT: CF_END60; EG-NEXT: PAD61; EG-NEXT: ALU clause starting at 4:62; EG-NEXT: TRUNC * T0.W, KC0[2].Z,63; EG-NEXT: FLT_TO_INT T0.X, PV.W,64; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,65; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)66 %conv = fptosi float %in to i3267 store i32 %conv, ptr addrspace(1) %out68 ret void69}70 71define amdgpu_kernel void @fp_to_sint_i32_fabs(ptr addrspace(1) %out, float %in) {72; SI-LABEL: fp_to_sint_i32_fabs:73; SI: ; %bb.0:74; SI-NEXT: s_load_dword s6, s[4:5], 0xb75; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x976; SI-NEXT: s_mov_b32 s3, 0xf00077; SI-NEXT: s_mov_b32 s2, -178; SI-NEXT: s_waitcnt lgkmcnt(0)79; SI-NEXT: v_cvt_i32_f32_e64 v0, |s6|80; SI-NEXT: buffer_store_dword v0, off, s[0:3], 081; SI-NEXT: s_endpgm82;83; VI-LABEL: fp_to_sint_i32_fabs:84; VI: ; %bb.0:85; VI-NEXT: s_load_dword s2, s[4:5], 0x2c86; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2487; VI-NEXT: s_mov_b32 s3, 0xf00088; VI-NEXT: s_waitcnt lgkmcnt(0)89; VI-NEXT: v_cvt_i32_f32_e64 v0, |s2|90; VI-NEXT: s_mov_b32 s2, -191; VI-NEXT: buffer_store_dword v0, off, s[0:3], 092; VI-NEXT: s_endpgm93;94; GFX11-SDAG-LABEL: fp_to_sint_i32_fabs:95; GFX11-SDAG: ; %bb.0:96; GFX11-SDAG-NEXT: s_clause 0x197; GFX11-SDAG-NEXT: s_load_b32 s2, s[4:5], 0x2c98; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x2499; GFX11-SDAG-NEXT: v_mov_b32_e32 v0, 0100; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)101; GFX11-SDAG-NEXT: v_cvt_i32_f32_e64 v1, |s2|102; GFX11-SDAG-NEXT: global_store_b32 v0, v1, s[0:1]103; GFX11-SDAG-NEXT: s_endpgm104;105; GFX11-GISEL-LABEL: fp_to_sint_i32_fabs:106; GFX11-GISEL: ; %bb.0:107; GFX11-GISEL-NEXT: s_clause 0x1108; GFX11-GISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c109; GFX11-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24110; GFX11-GISEL-NEXT: v_mov_b32_e32 v1, 0111; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)112; GFX11-GISEL-NEXT: v_cvt_i32_f32_e64 v0, |s2|113; GFX11-GISEL-NEXT: global_store_b32 v1, v0, s[0:1]114; GFX11-GISEL-NEXT: s_endpgm115;116; EG-LABEL: fp_to_sint_i32_fabs:117; EG: ; %bb.0:118; EG-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[]119; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1120; EG-NEXT: CF_END121; EG-NEXT: PAD122; EG-NEXT: ALU clause starting at 4:123; EG-NEXT: TRUNC * T0.W, |KC0[2].Z|,124; EG-NEXT: FLT_TO_INT T0.X, PV.W,125; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,126; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)127 %in.fabs = call float @llvm.fabs.f32(float %in)128 %conv = fptosi float %in.fabs to i32129 store i32 %conv, ptr addrspace(1) %out130 ret void131}132 133define amdgpu_kernel void @fp_to_sint_v2i32(ptr addrspace(1) %out, <2 x float> %in) {134; SI-LABEL: fp_to_sint_v2i32:135; SI: ; %bb.0:136; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9137; SI-NEXT: s_waitcnt lgkmcnt(0)138; SI-NEXT: s_mov_b64 s[4:5], s[2:3]139; SI-NEXT: s_mov_b32 s3, 0xf000140; SI-NEXT: s_mov_b32 s2, -1141; SI-NEXT: v_cvt_i32_f32_e32 v1, s5142; SI-NEXT: v_cvt_i32_f32_e32 v0, s4143; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0144; SI-NEXT: s_endpgm145;146; VI-LABEL: fp_to_sint_v2i32:147; VI: ; %bb.0:148; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24149; VI-NEXT: s_waitcnt lgkmcnt(0)150; VI-NEXT: v_cvt_i32_f32_e32 v1, s3151; VI-NEXT: v_cvt_i32_f32_e32 v0, s2152; VI-NEXT: s_mov_b32 s3, 0xf000153; VI-NEXT: s_mov_b32 s2, -1154; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0155; VI-NEXT: s_endpgm156;157; GFX11-SDAG-LABEL: fp_to_sint_v2i32:158; GFX11-SDAG: ; %bb.0:159; GFX11-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x24160; GFX11-SDAG-NEXT: v_mov_b32_e32 v2, 0161; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)162; GFX11-SDAG-NEXT: v_cvt_i32_f32_e32 v1, s3163; GFX11-SDAG-NEXT: v_cvt_i32_f32_e32 v0, s2164; GFX11-SDAG-NEXT: global_store_b64 v2, v[0:1], s[0:1]165; GFX11-SDAG-NEXT: s_endpgm166;167; GFX11-GISEL-LABEL: fp_to_sint_v2i32:168; GFX11-GISEL: ; %bb.0:169; GFX11-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24170; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, 0171; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)172; GFX11-GISEL-NEXT: v_cvt_i32_f32_e32 v0, s2173; GFX11-GISEL-NEXT: v_cvt_i32_f32_e32 v1, s3174; GFX11-GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1]175; GFX11-GISEL-NEXT: s_endpgm176;177; EG-LABEL: fp_to_sint_v2i32:178; EG: ; %bb.0:179; EG-NEXT: ALU 5, @4, KC0[CB0:0-32], KC1[]180; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1181; EG-NEXT: CF_END182; EG-NEXT: PAD183; EG-NEXT: ALU clause starting at 4:184; EG-NEXT: TRUNC * T0.W, KC0[3].X,185; EG-NEXT: FLT_TO_INT T0.Y, PV.W,186; EG-NEXT: TRUNC * T0.W, KC0[2].W,187; EG-NEXT: FLT_TO_INT T0.X, PV.W,188; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,189; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)190 %result = fptosi <2 x float> %in to <2 x i32>191 store <2 x i32> %result, ptr addrspace(1) %out192 ret void193}194 195define amdgpu_kernel void @fp_to_sint_v4i32(ptr addrspace(1) %out, ptr addrspace(1) %in) {196; SI-LABEL: fp_to_sint_v4i32:197; SI: ; %bb.0:198; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9199; SI-NEXT: s_waitcnt lgkmcnt(0)200; SI-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0201; SI-NEXT: s_mov_b32 s3, 0xf000202; SI-NEXT: s_mov_b32 s2, -1203; SI-NEXT: s_waitcnt lgkmcnt(0)204; SI-NEXT: v_cvt_i32_f32_e32 v3, s7205; SI-NEXT: v_cvt_i32_f32_e32 v2, s6206; SI-NEXT: v_cvt_i32_f32_e32 v1, s5207; SI-NEXT: v_cvt_i32_f32_e32 v0, s4208; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0209; SI-NEXT: s_endpgm210;211; VI-LABEL: fp_to_sint_v4i32:212; VI: ; %bb.0:213; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24214; VI-NEXT: s_waitcnt lgkmcnt(0)215; VI-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0216; VI-NEXT: s_mov_b32 s3, 0xf000217; VI-NEXT: s_mov_b32 s2, -1218; VI-NEXT: s_waitcnt lgkmcnt(0)219; VI-NEXT: v_cvt_i32_f32_e32 v3, s7220; VI-NEXT: v_cvt_i32_f32_e32 v2, s6221; VI-NEXT: v_cvt_i32_f32_e32 v1, s5222; VI-NEXT: v_cvt_i32_f32_e32 v0, s4223; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0224; VI-NEXT: s_endpgm225;226; GFX11-SDAG-LABEL: fp_to_sint_v4i32:227; GFX11-SDAG: ; %bb.0:228; GFX11-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x24229; GFX11-SDAG-NEXT: v_mov_b32_e32 v4, 0230; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)231; GFX11-SDAG-NEXT: s_load_b128 s[4:7], s[2:3], 0x0232; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)233; GFX11-SDAG-NEXT: v_cvt_i32_f32_e32 v3, s7234; GFX11-SDAG-NEXT: v_cvt_i32_f32_e32 v2, s6235; GFX11-SDAG-NEXT: v_cvt_i32_f32_e32 v1, s5236; GFX11-SDAG-NEXT: v_cvt_i32_f32_e32 v0, s4237; GFX11-SDAG-NEXT: global_store_b128 v4, v[0:3], s[0:1]238; GFX11-SDAG-NEXT: s_endpgm239;240; GFX11-GISEL-LABEL: fp_to_sint_v4i32:241; GFX11-GISEL: ; %bb.0:242; GFX11-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24243; GFX11-GISEL-NEXT: v_mov_b32_e32 v4, 0244; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)245; GFX11-GISEL-NEXT: s_load_b128 s[4:7], s[2:3], 0x0246; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)247; GFX11-GISEL-NEXT: v_cvt_i32_f32_e32 v0, s4248; GFX11-GISEL-NEXT: v_cvt_i32_f32_e32 v1, s5249; GFX11-GISEL-NEXT: v_cvt_i32_f32_e32 v2, s6250; GFX11-GISEL-NEXT: v_cvt_i32_f32_e32 v3, s7251; GFX11-GISEL-NEXT: global_store_b128 v4, v[0:3], s[0:1]252; GFX11-GISEL-NEXT: s_endpgm253;254; EG-LABEL: fp_to_sint_v4i32:255; EG: ; %bb.0:256; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]257; EG-NEXT: TEX 0 @6258; EG-NEXT: ALU 9, @9, KC0[CB0:0-32], KC1[]259; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1260; EG-NEXT: CF_END261; EG-NEXT: PAD262; EG-NEXT: Fetch clause starting at 6:263; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 0, #1264; EG-NEXT: ALU clause starting at 8:265; EG-NEXT: MOV * T0.X, KC0[2].Z,266; EG-NEXT: ALU clause starting at 9:267; EG-NEXT: TRUNC T0.W, T0.W,268; EG-NEXT: TRUNC * T1.W, T0.Z,269; EG-NEXT: FLT_TO_INT * T0.W, PV.W,270; EG-NEXT: FLT_TO_INT T0.Z, T1.W,271; EG-NEXT: TRUNC * T1.W, T0.Y,272; EG-NEXT: FLT_TO_INT T0.Y, PV.W,273; EG-NEXT: TRUNC * T1.W, T0.X,274; EG-NEXT: FLT_TO_INT T0.X, PV.W,275; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,276; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)277 %value = load <4 x float>, ptr addrspace(1) %in278 %result = fptosi <4 x float> %value to <4 x i32>279 store <4 x i32> %result, ptr addrspace(1) %out280 ret void281}282 283; Check that the compiler doesn't crash with a "cannot select" error284define amdgpu_kernel void @fp_to_sint_i64 (ptr addrspace(1) %out, float %in) {285; SI-LABEL: fp_to_sint_i64:286; SI: ; %bb.0: ; %entry287; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9288; SI-NEXT: s_load_dword s4, s[4:5], 0xb289; SI-NEXT: s_mov_b32 s3, 0xf000290; SI-NEXT: s_mov_b32 s2, -1291; SI-NEXT: s_mov_b32 s5, 0x2f800000292; SI-NEXT: s_mov_b32 s6, 0xcf800000293; SI-NEXT: s_waitcnt lgkmcnt(0)294; SI-NEXT: v_trunc_f32_e32 v0, s4295; SI-NEXT: v_mul_f32_e64 v1, |v0|, s5296; SI-NEXT: v_ashrrev_i32_e32 v2, 31, v0297; SI-NEXT: v_floor_f32_e32 v1, v1298; SI-NEXT: v_cvt_u32_f32_e32 v3, v1299; SI-NEXT: v_fma_f32 v0, v1, s6, |v0|300; SI-NEXT: v_cvt_u32_f32_e32 v0, v0301; SI-NEXT: v_xor_b32_e32 v1, v3, v2302; SI-NEXT: v_xor_b32_e32 v0, v0, v2303; SI-NEXT: v_sub_i32_e32 v0, vcc, v0, v2304; SI-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc305; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0306; SI-NEXT: s_endpgm307;308; VI-LABEL: fp_to_sint_i64:309; VI: ; %bb.0: ; %entry310; VI-NEXT: s_load_dword s2, s[4:5], 0x2c311; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24312; VI-NEXT: s_mov_b32 s4, 0x2f800000313; VI-NEXT: s_mov_b32 s5, 0xcf800000314; VI-NEXT: s_mov_b32 s3, 0xf000315; VI-NEXT: s_waitcnt lgkmcnt(0)316; VI-NEXT: v_trunc_f32_e32 v0, s2317; VI-NEXT: v_mul_f32_e64 v1, |v0|, s4318; VI-NEXT: v_floor_f32_e32 v1, v1319; VI-NEXT: v_fma_f32 v2, v1, s5, |v0|320; VI-NEXT: v_cvt_u32_f32_e32 v2, v2321; VI-NEXT: v_cvt_u32_f32_e32 v1, v1322; VI-NEXT: v_ashrrev_i32_e32 v3, 31, v0323; VI-NEXT: s_mov_b32 s2, -1324; VI-NEXT: v_xor_b32_e32 v0, v2, v3325; VI-NEXT: v_xor_b32_e32 v1, v1, v3326; VI-NEXT: v_sub_u32_e32 v0, vcc, v0, v3327; VI-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc328; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0329; VI-NEXT: s_endpgm330;331; GFX11-SDAG-LABEL: fp_to_sint_i64:332; GFX11-SDAG: ; %bb.0: ; %entry333; GFX11-SDAG-NEXT: s_load_b32 s0, s[4:5], 0x2c334; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)335; GFX11-SDAG-NEXT: v_trunc_f32_e32 v0, s0336; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24337; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)338; GFX11-SDAG-NEXT: v_mul_f32_e64 v1, 0x2f800000, |v0|339; GFX11-SDAG-NEXT: v_ashrrev_i32_e32 v3, 31, v0340; GFX11-SDAG-NEXT: v_floor_f32_e32 v1, v1341; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)342; GFX11-SDAG-NEXT: v_fma_f32 v2, 0xcf800000, v1, |v0|343; GFX11-SDAG-NEXT: v_cvt_u32_f32_e32 v1, v1344; GFX11-SDAG-NEXT: v_cvt_u32_f32_e32 v0, v2345; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)346; GFX11-SDAG-NEXT: v_xor_b32_e32 v1, v1, v3347; GFX11-SDAG-NEXT: v_mov_b32_e32 v2, 0348; GFX11-SDAG-NEXT: v_xor_b32_e32 v0, v0, v3349; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)350; GFX11-SDAG-NEXT: v_sub_co_u32 v0, vcc_lo, v0, v3351; GFX11-SDAG-NEXT: v_sub_co_ci_u32_e64 v1, null, v1, v3, vcc_lo352; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)353; GFX11-SDAG-NEXT: global_store_b64 v2, v[0:1], s[0:1]354; GFX11-SDAG-NEXT: s_endpgm355;356; GFX11-GISEL-LABEL: fp_to_sint_i64:357; GFX11-GISEL: ; %bb.0: ; %entry358; GFX11-GISEL-NEXT: s_clause 0x1359; GFX11-GISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c360; GFX11-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24361; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, 0362; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)363; GFX11-GISEL-NEXT: v_trunc_f32_e32 v0, s2364; GFX11-GISEL-NEXT: s_ashr_i32 s2, s2, 31365; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)366; GFX11-GISEL-NEXT: v_mul_f32_e64 v1, 0x2f800000, |v0|367; GFX11-GISEL-NEXT: v_floor_f32_e32 v1, v1368; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)369; GFX11-GISEL-NEXT: v_fma_f32 v0, 0xcf800000, v1, |v0|370; GFX11-GISEL-NEXT: v_cvt_u32_f32_e32 v1, v1371; GFX11-GISEL-NEXT: v_cvt_u32_f32_e32 v0, v0372; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)373; GFX11-GISEL-NEXT: v_xor_b32_e32 v1, s2, v1374; GFX11-GISEL-NEXT: v_xor_b32_e32 v0, s2, v0375; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)376; GFX11-GISEL-NEXT: v_sub_co_u32 v0, vcc_lo, v0, s2377; GFX11-GISEL-NEXT: v_subrev_co_ci_u32_e64 v1, null, s2, v1, vcc_lo378; GFX11-GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1]379; GFX11-GISEL-NEXT: s_endpgm380;381; EG-LABEL: fp_to_sint_i64:382; EG: ; %bb.0: ; %entry383; EG-NEXT: ALU 40, @4, KC0[CB0:0-32], KC1[]384; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1385; EG-NEXT: CF_END386; EG-NEXT: PAD387; EG-NEXT: ALU clause starting at 4:388; EG-NEXT: MOV * T0.W, literal.x,389; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)390; EG-NEXT: BFE_UINT T0.W, KC0[2].Z, literal.x, PV.W,391; EG-NEXT: AND_INT * T1.W, KC0[2].Z, literal.y,392; EG-NEXT: 23(3.222986e-44), 8388607(1.175494e-38)393; EG-NEXT: OR_INT T1.W, PS, literal.x,394; EG-NEXT: ADD_INT * T2.W, PV.W, literal.y,395; EG-NEXT: 8388608(1.175494e-38), -150(nan)396; EG-NEXT: ADD_INT T0.X, T0.W, literal.x,397; EG-NEXT: AND_INT T0.Y, PS, literal.y,398; EG-NEXT: SUB_INT T0.Z, literal.z, T0.W,399; EG-NEXT: NOT_INT T0.W, PS,400; EG-NEXT: LSHR * T3.W, PV.W, 1,401; EG-NEXT: -127(nan), 31(4.344025e-44)402; EG-NEXT: 150(2.101948e-43), 0(0.000000e+00)403; EG-NEXT: BIT_ALIGN_INT T1.X, 0.0, PS, PV.W,404; EG-NEXT: AND_INT T1.Y, PV.Z, literal.x,405; EG-NEXT: BIT_ALIGN_INT T0.Z, 0.0, T1.W, PV.Z,406; EG-NEXT: LSHL T0.W, T1.W, PV.Y,407; EG-NEXT: AND_INT * T1.W, T2.W, literal.x,408; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)409; EG-NEXT: CNDE_INT T0.Y, PS, PV.W, 0.0,410; EG-NEXT: CNDE_INT T0.Z, PV.Y, PV.Z, 0.0,411; EG-NEXT: CNDE_INT T0.W, PS, PV.X, PV.W,412; EG-NEXT: SETGT_INT * T1.W, T0.X, literal.x,413; EG-NEXT: 23(3.222986e-44), 0(0.000000e+00)414; EG-NEXT: CNDE_INT T1.Z, PS, 0.0, PV.W,415; EG-NEXT: CNDE_INT T0.W, PS, PV.Z, PV.Y,416; EG-NEXT: ASHR * T1.W, KC0[2].Z, literal.x,417; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)418; EG-NEXT: XOR_INT T0.W, PV.W, PS,419; EG-NEXT: XOR_INT * T2.W, PV.Z, PS,420; EG-NEXT: SUB_INT T2.W, PS, T1.W,421; EG-NEXT: SUBB_UINT * T3.W, PV.W, T1.W,422; EG-NEXT: SUB_INT T2.W, PV.W, PS,423; EG-NEXT: SETGT_INT * T3.W, 0.0, T0.X,424; EG-NEXT: CNDE_INT T0.Y, PS, PV.W, 0.0,425; EG-NEXT: SUB_INT * T0.W, T0.W, T1.W,426; EG-NEXT: CNDE_INT T0.X, T3.W, PV.W, 0.0,427; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,428; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)429entry:430 %0 = fptosi float %in to i64431 store i64 %0, ptr addrspace(1) %out432 ret void433}434 435define amdgpu_kernel void @fp_to_sint_v2i64(ptr addrspace(1) %out, <2 x float> %x) {436; SI-LABEL: fp_to_sint_v2i64:437; SI: ; %bb.0:438; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9439; SI-NEXT: s_mov_b32 s6, 0x2f800000440; SI-NEXT: s_mov_b32 s7, 0xcf800000441; SI-NEXT: s_waitcnt lgkmcnt(0)442; SI-NEXT: s_mov_b64 s[4:5], s[2:3]443; SI-NEXT: s_mov_b32 s3, 0xf000444; SI-NEXT: s_mov_b32 s2, -1445; SI-NEXT: v_trunc_f32_e32 v0, s5446; SI-NEXT: v_trunc_f32_e32 v1, s4447; SI-NEXT: v_mul_f32_e64 v2, |v0|, s6448; SI-NEXT: v_ashrrev_i32_e32 v3, 31, v0449; SI-NEXT: v_mul_f32_e64 v4, |v1|, s6450; SI-NEXT: v_ashrrev_i32_e32 v5, 31, v1451; SI-NEXT: v_floor_f32_e32 v2, v2452; SI-NEXT: v_floor_f32_e32 v4, v4453; SI-NEXT: v_cvt_u32_f32_e32 v6, v2454; SI-NEXT: v_fma_f32 v0, v2, s7, |v0|455; SI-NEXT: v_cvt_u32_f32_e32 v2, v4456; SI-NEXT: v_fma_f32 v1, v4, s7, |v1|457; SI-NEXT: v_cvt_u32_f32_e32 v0, v0458; SI-NEXT: v_xor_b32_e32 v4, v6, v3459; SI-NEXT: v_cvt_u32_f32_e32 v1, v1460; SI-NEXT: v_xor_b32_e32 v6, v2, v5461; SI-NEXT: v_xor_b32_e32 v0, v0, v3462; SI-NEXT: v_xor_b32_e32 v1, v1, v5463; SI-NEXT: v_sub_i32_e32 v2, vcc, v0, v3464; SI-NEXT: v_subb_u32_e32 v3, vcc, v4, v3, vcc465; SI-NEXT: v_sub_i32_e32 v0, vcc, v1, v5466; SI-NEXT: v_subb_u32_e32 v1, vcc, v6, v5, vcc467; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0468; SI-NEXT: s_endpgm469;470; VI-LABEL: fp_to_sint_v2i64:471; VI: ; %bb.0:472; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24473; VI-NEXT: s_mov_b32 s6, 0x2f800000474; VI-NEXT: s_mov_b32 s7, 0xcf800000475; VI-NEXT: s_waitcnt lgkmcnt(0)476; VI-NEXT: s_mov_b64 s[4:5], s[2:3]477; VI-NEXT: v_trunc_f32_e32 v0, s5478; VI-NEXT: v_mul_f32_e64 v1, |v0|, s6479; VI-NEXT: v_floor_f32_e32 v1, v1480; VI-NEXT: v_cvt_u32_f32_e32 v2, v1481; VI-NEXT: v_fma_f32 v1, v1, s7, |v0|482; VI-NEXT: v_ashrrev_i32_e32 v0, 31, v0483; VI-NEXT: v_trunc_f32_e32 v4, s4484; VI-NEXT: v_xor_b32_e32 v3, v2, v0485; VI-NEXT: v_mul_f32_e64 v2, |v4|, s6486; VI-NEXT: v_cvt_u32_f32_e32 v1, v1487; VI-NEXT: v_floor_f32_e32 v2, v2488; VI-NEXT: v_cvt_u32_f32_e32 v5, v2489; VI-NEXT: v_fma_f32 v2, v2, s7, |v4|490; VI-NEXT: v_cvt_u32_f32_e32 v6, v2491; VI-NEXT: v_xor_b32_e32 v1, v1, v0492; VI-NEXT: v_sub_u32_e32 v2, vcc, v1, v0493; VI-NEXT: v_ashrrev_i32_e32 v1, 31, v4494; VI-NEXT: v_subb_u32_e32 v3, vcc, v3, v0, vcc495; VI-NEXT: v_xor_b32_e32 v0, v6, v1496; VI-NEXT: v_xor_b32_e32 v4, v5, v1497; VI-NEXT: v_sub_u32_e32 v0, vcc, v0, v1498; VI-NEXT: s_mov_b32 s3, 0xf000499; VI-NEXT: s_mov_b32 s2, -1500; VI-NEXT: v_subb_u32_e32 v1, vcc, v4, v1, vcc501; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0502; VI-NEXT: s_endpgm503;504; GFX11-SDAG-LABEL: fp_to_sint_v2i64:505; GFX11-SDAG: ; %bb.0:506; GFX11-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x24507; GFX11-SDAG-NEXT: v_mov_b32_e32 v6, 0508; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)509; GFX11-SDAG-NEXT: v_trunc_f32_e32 v0, s3510; GFX11-SDAG-NEXT: v_trunc_f32_e32 v1, s2511; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)512; GFX11-SDAG-NEXT: v_mul_f32_e64 v2, 0x2f800000, |v0|513; GFX11-SDAG-NEXT: v_mul_f32_e64 v3, 0x2f800000, |v1|514; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)515; GFX11-SDAG-NEXT: v_floor_f32_e32 v2, v2516; GFX11-SDAG-NEXT: v_floor_f32_e32 v3, v3517; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)518; GFX11-SDAG-NEXT: v_fma_f32 v4, 0xcf800000, v2, |v0|519; GFX11-SDAG-NEXT: v_fma_f32 v5, 0xcf800000, v3, |v1|520; GFX11-SDAG-NEXT: v_ashrrev_i32_e32 v0, 31, v0521; GFX11-SDAG-NEXT: v_ashrrev_i32_e32 v1, 31, v1522; GFX11-SDAG-NEXT: v_cvt_u32_f32_e32 v2, v2523; GFX11-SDAG-NEXT: v_cvt_u32_f32_e32 v4, v4524; GFX11-SDAG-NEXT: v_cvt_u32_f32_e32 v5, v5525; GFX11-SDAG-NEXT: v_cvt_u32_f32_e32 v3, v3526; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)527; GFX11-SDAG-NEXT: v_xor_b32_e32 v7, v2, v0528; GFX11-SDAG-NEXT: v_xor_b32_e32 v4, v4, v0529; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)530; GFX11-SDAG-NEXT: v_xor_b32_e32 v5, v5, v1531; GFX11-SDAG-NEXT: v_xor_b32_e32 v8, v3, v1532; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)533; GFX11-SDAG-NEXT: v_sub_co_u32 v2, vcc_lo, v4, v0534; GFX11-SDAG-NEXT: v_sub_co_ci_u32_e64 v3, null, v7, v0, vcc_lo535; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)536; GFX11-SDAG-NEXT: v_sub_co_u32 v0, vcc_lo, v5, v1537; GFX11-SDAG-NEXT: v_sub_co_ci_u32_e64 v1, null, v8, v1, vcc_lo538; GFX11-SDAG-NEXT: global_store_b128 v6, v[0:3], s[0:1]539; GFX11-SDAG-NEXT: s_endpgm540;541; GFX11-GISEL-LABEL: fp_to_sint_v2i64:542; GFX11-GISEL: ; %bb.0:543; GFX11-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24544; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)545; GFX11-GISEL-NEXT: v_trunc_f32_e32 v0, s2546; GFX11-GISEL-NEXT: v_trunc_f32_e32 v1, s3547; GFX11-GISEL-NEXT: s_ashr_i32 s2, s2, 31548; GFX11-GISEL-NEXT: s_ashr_i32 s3, s3, 31549; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)550; GFX11-GISEL-NEXT: v_mul_f32_e64 v2, 0x2f800000, |v0|551; GFX11-GISEL-NEXT: v_mul_f32_e64 v3, 0x2f800000, |v1|552; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)553; GFX11-GISEL-NEXT: v_floor_f32_e32 v2, v2554; GFX11-GISEL-NEXT: v_floor_f32_e32 v3, v3555; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)556; GFX11-GISEL-NEXT: v_fma_f32 v0, 0xcf800000, v2, |v0|557; GFX11-GISEL-NEXT: v_fma_f32 v1, 0xcf800000, v3, |v1|558; GFX11-GISEL-NEXT: v_cvt_u32_f32_e32 v2, v2559; GFX11-GISEL-NEXT: v_cvt_u32_f32_e32 v3, v3560; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)561; GFX11-GISEL-NEXT: v_cvt_u32_f32_e32 v0, v0562; GFX11-GISEL-NEXT: v_cvt_u32_f32_e32 v1, v1563; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)564; GFX11-GISEL-NEXT: v_xor_b32_e32 v2, s2, v2565; GFX11-GISEL-NEXT: v_xor_b32_e32 v3, s3, v3566; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)567; GFX11-GISEL-NEXT: v_xor_b32_e32 v0, s2, v0568; GFX11-GISEL-NEXT: v_xor_b32_e32 v4, s3, v1569; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)570; GFX11-GISEL-NEXT: v_sub_co_u32 v0, vcc_lo, v0, s2571; GFX11-GISEL-NEXT: v_subrev_co_ci_u32_e64 v1, null, s2, v2, vcc_lo572; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)573; GFX11-GISEL-NEXT: v_sub_co_u32 v2, vcc_lo, v4, s3574; GFX11-GISEL-NEXT: v_subrev_co_ci_u32_e64 v3, null, s3, v3, vcc_lo575; GFX11-GISEL-NEXT: v_mov_b32_e32 v4, 0576; GFX11-GISEL-NEXT: global_store_b128 v4, v[0:3], s[0:1]577; GFX11-GISEL-NEXT: s_endpgm578;579; EG-LABEL: fp_to_sint_v2i64:580; EG: ; %bb.0:581; EG-NEXT: ALU 74, @4, KC0[CB0:0-32], KC1[]582; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XYZW, T0.X, 1583; EG-NEXT: CF_END584; EG-NEXT: PAD585; EG-NEXT: ALU clause starting at 4:586; EG-NEXT: MOV * T0.W, literal.x,587; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)588; EG-NEXT: BFE_UINT T0.Z, KC0[3].X, literal.x, PV.W,589; EG-NEXT: BFE_UINT T0.W, KC0[2].W, literal.x, PV.W,590; EG-NEXT: AND_INT * T1.Z, KC0[2].W, literal.y,591; EG-NEXT: 23(3.222986e-44), 8388607(1.175494e-38)592; EG-NEXT: ADD_INT T1.W, PV.W, literal.x,593; EG-NEXT: ADD_INT * T2.W, PV.Z, literal.x,594; EG-NEXT: -150(nan), 0(0.000000e+00)595; EG-NEXT: AND_INT T0.X, PS, literal.x,596; EG-NEXT: AND_INT T0.Y, PV.W, literal.x,597; EG-NEXT: OR_INT T1.Z, T1.Z, literal.y,598; EG-NEXT: SUB_INT T3.W, literal.z, T0.W,599; EG-NEXT: AND_INT * T4.W, KC0[3].X, literal.w,600; EG-NEXT: 31(4.344025e-44), 8388608(1.175494e-38)601; EG-NEXT: 150(2.101948e-43), 8388607(1.175494e-38)602; EG-NEXT: OR_INT T1.X, PS, literal.x,603; EG-NEXT: AND_INT T1.Y, PV.W, literal.y,604; EG-NEXT: BIT_ALIGN_INT T2.Z, 0.0, PV.Z, PV.W,605; EG-NEXT: LSHL T3.W, PV.Z, PV.Y,606; EG-NEXT: AND_INT * T4.W, T1.W, literal.y,607; EG-NEXT: 8388608(1.175494e-38), 32(4.484155e-44)608; EG-NEXT: CNDE_INT T0.Y, PS, PV.W, 0.0,609; EG-NEXT: CNDE_INT T2.Z, PV.Y, PV.Z, 0.0,610; EG-NEXT: LSHL T5.W, PV.X, T0.X,611; EG-NEXT: AND_INT * T6.W, T2.W, literal.x,612; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)613; EG-NEXT: CNDE_INT T0.X, PS, PV.W, 0.0,614; EG-NEXT: NOT_INT T1.Y, T1.W,615; EG-NEXT: SUB_INT T3.Z, literal.x, T0.Z,616; EG-NEXT: NOT_INT T1.W, T2.W, BS:VEC_120/SCL_212617; EG-NEXT: LSHR * T2.W, T1.X, 1,618; EG-NEXT: 150(2.101948e-43), 0(0.000000e+00)619; EG-NEXT: LSHR T2.X, T1.Z, 1,620; EG-NEXT: ADD_INT T2.Y, T0.Z, literal.x, BS:VEC_120/SCL_212621; EG-NEXT: BIT_ALIGN_INT T0.Z, 0.0, PS, PV.W,622; EG-NEXT: BIT_ALIGN_INT T1.W, 0.0, T1.X, PV.Z,623; EG-NEXT: AND_INT * T2.W, PV.Z, literal.y,624; EG-NEXT: -127(nan), 32(4.484155e-44)625; EG-NEXT: CNDE_INT T1.X, PS, PV.W, 0.0,626; EG-NEXT: CNDE_INT T3.Y, T6.W, PV.Z, T5.W, BS:VEC_021/SCL_122627; EG-NEXT: SETGT_INT T0.Z, PV.Y, literal.x,628; EG-NEXT: BIT_ALIGN_INT T1.W, 0.0, PV.X, T1.Y,629; EG-NEXT: ADD_INT * T0.W, T0.W, literal.y,630; EG-NEXT: 23(3.222986e-44), -127(nan)631; EG-NEXT: CNDE_INT T2.X, T4.W, PV.W, T3.W,632; EG-NEXT: SETGT_INT T1.Y, PS, literal.x,633; EG-NEXT: CNDE_INT T1.Z, PV.Z, 0.0, PV.Y,634; EG-NEXT: CNDE_INT T1.W, PV.Z, PV.X, T0.X,635; EG-NEXT: ASHR * T2.W, KC0[3].X, literal.y,636; EG-NEXT: 23(3.222986e-44), 31(4.344025e-44)637; EG-NEXT: XOR_INT T0.X, PV.W, PS,638; EG-NEXT: XOR_INT T3.Y, PV.Z, PS,639; EG-NEXT: CNDE_INT T0.Z, PV.Y, 0.0, PV.X,640; EG-NEXT: CNDE_INT T1.W, PV.Y, T2.Z, T0.Y,641; EG-NEXT: ASHR * T3.W, KC0[2].W, literal.x,642; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)643; EG-NEXT: XOR_INT T0.Y, PV.W, PS,644; EG-NEXT: XOR_INT T0.Z, PV.Z, PS,645; EG-NEXT: SUB_INT T1.W, PV.Y, T2.W,646; EG-NEXT: SUBB_UINT * T4.W, PV.X, T2.W,647; EG-NEXT: SUB_INT T1.Y, PV.W, PS,648; EG-NEXT: SETGT_INT T1.Z, 0.0, T2.Y,649; EG-NEXT: SUB_INT T1.W, PV.Z, T3.W,650; EG-NEXT: SUBB_UINT * T4.W, PV.Y, T3.W,651; EG-NEXT: SUB_INT T0.Z, PV.W, PS,652; EG-NEXT: SETGT_INT T0.W, 0.0, T0.W,653; EG-NEXT: CNDE_INT * T1.W, PV.Z, PV.Y, 0.0,654; EG-NEXT: CNDE_INT T1.Y, PV.W, PV.Z, 0.0,655; EG-NEXT: SUB_INT * T2.W, T0.X, T2.W,656; EG-NEXT: CNDE_INT T1.Z, T1.Z, PV.W, 0.0,657; EG-NEXT: SUB_INT * T2.W, T0.Y, T3.W,658; EG-NEXT: CNDE_INT T1.X, T0.W, PV.W, 0.0,659; EG-NEXT: LSHR * T0.X, KC0[2].Y, literal.x,660; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)661 %conv = fptosi <2 x float> %x to <2 x i64>662 store <2 x i64> %conv, ptr addrspace(1) %out663 ret void664}665 666define amdgpu_kernel void @fp_to_sint_v4i64(ptr addrspace(1) %out, <4 x float> %x) {667; SI-LABEL: fp_to_sint_v4i64:668; SI: ; %bb.0:669; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9670; SI-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0xd671; SI-NEXT: s_mov_b32 s3, 0xf000672; SI-NEXT: s_mov_b32 s2, -1673; SI-NEXT: s_mov_b32 s8, 0x2f800000674; SI-NEXT: s_mov_b32 s9, 0xcf800000675; SI-NEXT: s_waitcnt lgkmcnt(0)676; SI-NEXT: v_trunc_f32_e32 v0, s5677; SI-NEXT: v_trunc_f32_e32 v1, s4678; SI-NEXT: v_trunc_f32_e32 v2, s7679; SI-NEXT: v_trunc_f32_e32 v3, s6680; SI-NEXT: v_mul_f32_e64 v4, |v0|, s8681; SI-NEXT: v_ashrrev_i32_e32 v5, 31, v0682; SI-NEXT: v_mul_f32_e64 v6, |v1|, s8683; SI-NEXT: v_ashrrev_i32_e32 v7, 31, v1684; SI-NEXT: v_mul_f32_e64 v8, |v2|, s8685; SI-NEXT: v_ashrrev_i32_e32 v9, 31, v2686; SI-NEXT: v_mul_f32_e64 v10, |v3|, s8687; SI-NEXT: v_ashrrev_i32_e32 v11, 31, v3688; SI-NEXT: v_floor_f32_e32 v4, v4689; SI-NEXT: v_floor_f32_e32 v6, v6690; SI-NEXT: v_floor_f32_e32 v8, v8691; SI-NEXT: v_floor_f32_e32 v10, v10692; SI-NEXT: v_cvt_u32_f32_e32 v12, v4693; SI-NEXT: v_fma_f32 v0, v4, s9, |v0|694; SI-NEXT: v_cvt_u32_f32_e32 v4, v6695; SI-NEXT: v_fma_f32 v1, v6, s9, |v1|696; SI-NEXT: v_cvt_u32_f32_e32 v6, v8697; SI-NEXT: v_fma_f32 v2, v8, s9, |v2|698; SI-NEXT: v_cvt_u32_f32_e32 v8, v10699; SI-NEXT: v_fma_f32 v3, v10, s9, |v3|700; SI-NEXT: v_cvt_u32_f32_e32 v0, v0701; SI-NEXT: v_xor_b32_e32 v10, v12, v5702; SI-NEXT: v_cvt_u32_f32_e32 v1, v1703; SI-NEXT: v_xor_b32_e32 v4, v4, v7704; SI-NEXT: v_cvt_u32_f32_e32 v2, v2705; SI-NEXT: v_xor_b32_e32 v12, v6, v9706; SI-NEXT: v_cvt_u32_f32_e32 v3, v3707; SI-NEXT: v_xor_b32_e32 v8, v8, v11708; SI-NEXT: v_xor_b32_e32 v0, v0, v5709; SI-NEXT: v_xor_b32_e32 v1, v1, v7710; SI-NEXT: v_xor_b32_e32 v6, v2, v9711; SI-NEXT: v_xor_b32_e32 v13, v3, v11712; SI-NEXT: v_sub_i32_e32 v2, vcc, v0, v5713; SI-NEXT: v_subb_u32_e32 v3, vcc, v10, v5, vcc714; SI-NEXT: v_sub_i32_e32 v0, vcc, v1, v7715; SI-NEXT: v_subb_u32_e32 v1, vcc, v4, v7, vcc716; SI-NEXT: v_sub_i32_e32 v6, vcc, v6, v9717; SI-NEXT: v_subb_u32_e32 v7, vcc, v12, v9, vcc718; SI-NEXT: v_sub_i32_e32 v4, vcc, v13, v11719; SI-NEXT: v_subb_u32_e32 v5, vcc, v8, v11, vcc720; SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16721; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0722; SI-NEXT: s_endpgm723;724; VI-LABEL: fp_to_sint_v4i64:725; VI: ; %bb.0:726; VI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x34727; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24728; VI-NEXT: s_mov_b32 s4, 0x2f800000729; VI-NEXT: s_mov_b32 s5, 0xcf800000730; VI-NEXT: s_mov_b32 s3, 0xf000731; VI-NEXT: s_waitcnt lgkmcnt(0)732; VI-NEXT: v_trunc_f32_e32 v0, s9733; VI-NEXT: v_mul_f32_e64 v1, |v0|, s4734; VI-NEXT: v_floor_f32_e32 v1, v1735; VI-NEXT: v_fma_f32 v2, v1, s5, |v0|736; VI-NEXT: v_cvt_u32_f32_e32 v2, v2737; VI-NEXT: v_trunc_f32_e32 v4, s8738; VI-NEXT: v_cvt_u32_f32_e32 v1, v1739; VI-NEXT: v_mul_f32_e64 v3, |v4|, s4740; VI-NEXT: v_floor_f32_e32 v3, v3741; VI-NEXT: v_ashrrev_i32_e32 v0, 31, v0742; VI-NEXT: v_cvt_u32_f32_e32 v5, v3743; VI-NEXT: v_fma_f32 v3, v3, s5, |v4|744; VI-NEXT: v_xor_b32_e32 v2, v2, v0745; VI-NEXT: v_cvt_u32_f32_e32 v6, v3746; VI-NEXT: v_xor_b32_e32 v1, v1, v0747; VI-NEXT: v_sub_u32_e32 v2, vcc, v2, v0748; VI-NEXT: v_subb_u32_e32 v3, vcc, v1, v0, vcc749; VI-NEXT: v_ashrrev_i32_e32 v1, 31, v4750; VI-NEXT: v_xor_b32_e32 v4, v5, v1751; VI-NEXT: v_trunc_f32_e32 v5, s11752; VI-NEXT: v_xor_b32_e32 v0, v6, v1753; VI-NEXT: v_mul_f32_e64 v6, |v5|, s4754; VI-NEXT: v_floor_f32_e32 v6, v6755; VI-NEXT: v_cvt_u32_f32_e32 v7, v6756; VI-NEXT: v_fma_f32 v6, v6, s5, |v5|757; VI-NEXT: v_cvt_u32_f32_e32 v6, v6758; VI-NEXT: v_sub_u32_e32 v0, vcc, v0, v1759; VI-NEXT: v_subb_u32_e32 v1, vcc, v4, v1, vcc760; VI-NEXT: v_ashrrev_i32_e32 v4, 31, v5761; VI-NEXT: v_trunc_f32_e32 v8, s10762; VI-NEXT: v_xor_b32_e32 v5, v6, v4763; VI-NEXT: v_mul_f32_e64 v6, |v8|, s4764; VI-NEXT: v_floor_f32_e32 v6, v6765; VI-NEXT: v_cvt_u32_f32_e32 v9, v6766; VI-NEXT: v_fma_f32 v6, v6, s5, |v8|767; VI-NEXT: v_cvt_u32_f32_e32 v10, v6768; VI-NEXT: v_xor_b32_e32 v7, v7, v4769; VI-NEXT: v_sub_u32_e32 v6, vcc, v5, v4770; VI-NEXT: v_ashrrev_i32_e32 v5, 31, v8771; VI-NEXT: v_subb_u32_e32 v7, vcc, v7, v4, vcc772; VI-NEXT: v_xor_b32_e32 v4, v10, v5773; VI-NEXT: v_xor_b32_e32 v8, v9, v5774; VI-NEXT: v_sub_u32_e32 v4, vcc, v4, v5775; VI-NEXT: s_mov_b32 s2, -1776; VI-NEXT: v_subb_u32_e32 v5, vcc, v8, v5, vcc777; VI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16778; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0779; VI-NEXT: s_endpgm780;781; GFX11-SDAG-LABEL: fp_to_sint_v4i64:782; GFX11-SDAG: ; %bb.0:783; GFX11-SDAG-NEXT: s_clause 0x1784; GFX11-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x34785; GFX11-SDAG-NEXT: s_load_b64 s[4:5], s[4:5], 0x24786; GFX11-SDAG-NEXT: v_mov_b32_e32 v8, 0787; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)788; GFX11-SDAG-NEXT: v_trunc_f32_e32 v0, s1789; GFX11-SDAG-NEXT: v_trunc_f32_e32 v2, s3790; GFX11-SDAG-NEXT: v_trunc_f32_e32 v3, s2791; GFX11-SDAG-NEXT: v_trunc_f32_e32 v1, s0792; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)793; GFX11-SDAG-NEXT: v_mul_f32_e64 v4, 0x2f800000, |v0|794; GFX11-SDAG-NEXT: v_mul_f32_e64 v7, 0x2f800000, |v2|795; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)796; GFX11-SDAG-NEXT: v_mul_f32_e64 v11, 0x2f800000, |v3|797; GFX11-SDAG-NEXT: v_mul_f32_e64 v6, 0x2f800000, |v1|798; GFX11-SDAG-NEXT: v_ashrrev_i32_e32 v5, 31, v0799; GFX11-SDAG-NEXT: v_floor_f32_e32 v4, v4800; GFX11-SDAG-NEXT: v_floor_f32_e32 v7, v7801; GFX11-SDAG-NEXT: v_floor_f32_e32 v11, v11802; GFX11-SDAG-NEXT: v_floor_f32_e32 v6, v6803; GFX11-SDAG-NEXT: v_ashrrev_i32_e32 v10, 31, v2804; GFX11-SDAG-NEXT: v_fma_f32 v0, 0xcf800000, v4, |v0|805; GFX11-SDAG-NEXT: v_fma_f32 v2, 0xcf800000, v7, |v2|806; GFX11-SDAG-NEXT: v_ashrrev_i32_e32 v12, 31, v3807; GFX11-SDAG-NEXT: v_fma_f32 v3, 0xcf800000, v11, |v3|808; GFX11-SDAG-NEXT: v_ashrrev_i32_e32 v9, 31, v1809; GFX11-SDAG-NEXT: v_cvt_u32_f32_e32 v0, v0810; GFX11-SDAG-NEXT: v_fma_f32 v1, 0xcf800000, v6, |v1|811; GFX11-SDAG-NEXT: v_cvt_u32_f32_e32 v13, v4812; GFX11-SDAG-NEXT: v_cvt_u32_f32_e32 v4, v6813; GFX11-SDAG-NEXT: v_cvt_u32_f32_e32 v6, v7814; GFX11-SDAG-NEXT: v_cvt_u32_f32_e32 v2, v2815; GFX11-SDAG-NEXT: v_cvt_u32_f32_e32 v3, v3816; GFX11-SDAG-NEXT: v_xor_b32_e32 v0, v0, v5817; GFX11-SDAG-NEXT: v_cvt_u32_f32_e32 v7, v11818; GFX11-SDAG-NEXT: v_cvt_u32_f32_e32 v1, v1819; GFX11-SDAG-NEXT: v_xor_b32_e32 v11, v13, v5820; GFX11-SDAG-NEXT: v_xor_b32_e32 v13, v4, v9821; GFX11-SDAG-NEXT: v_xor_b32_e32 v4, v6, v10822; GFX11-SDAG-NEXT: v_xor_b32_e32 v6, v2, v10823; GFX11-SDAG-NEXT: v_xor_b32_e32 v15, v3, v12824; GFX11-SDAG-NEXT: v_sub_co_u32 v2, vcc_lo, v0, v5825; GFX11-SDAG-NEXT: v_xor_b32_e32 v14, v7, v12826; GFX11-SDAG-NEXT: v_xor_b32_e32 v1, v1, v9827; GFX11-SDAG-NEXT: v_sub_co_ci_u32_e64 v3, null, v11, v5, vcc_lo828; GFX11-SDAG-NEXT: v_sub_co_u32 v6, vcc_lo, v6, v10829; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)830; GFX11-SDAG-NEXT: v_sub_co_ci_u32_e64 v7, null, v4, v10, vcc_lo831; GFX11-SDAG-NEXT: v_sub_co_u32 v4, vcc_lo, v15, v12832; GFX11-SDAG-NEXT: v_sub_co_ci_u32_e64 v5, null, v14, v12, vcc_lo833; GFX11-SDAG-NEXT: v_sub_co_u32 v0, vcc_lo, v1, v9834; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)835; GFX11-SDAG-NEXT: v_sub_co_ci_u32_e64 v1, null, v13, v9, vcc_lo836; GFX11-SDAG-NEXT: s_clause 0x1837; GFX11-SDAG-NEXT: global_store_b128 v8, v[4:7], s[4:5] offset:16838; GFX11-SDAG-NEXT: global_store_b128 v8, v[0:3], s[4:5]839; GFX11-SDAG-NEXT: s_endpgm840;841; GFX11-GISEL-LABEL: fp_to_sint_v4i64:842; GFX11-GISEL: ; %bb.0:843; GFX11-GISEL-NEXT: s_clause 0x1844; GFX11-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x34845; GFX11-GISEL-NEXT: s_load_b64 s[4:5], s[4:5], 0x24846; GFX11-GISEL-NEXT: v_mov_b32_e32 v8, 0847; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)848; GFX11-GISEL-NEXT: v_trunc_f32_e32 v0, s0849; GFX11-GISEL-NEXT: v_trunc_f32_e32 v1, s1850; GFX11-GISEL-NEXT: v_trunc_f32_e32 v2, s2851; GFX11-GISEL-NEXT: v_trunc_f32_e32 v3, s3852; GFX11-GISEL-NEXT: s_ashr_i32 s0, s0, 31853; GFX11-GISEL-NEXT: v_mul_f32_e64 v4, 0x2f800000, |v0|854; GFX11-GISEL-NEXT: v_mul_f32_e64 v5, 0x2f800000, |v1|855; GFX11-GISEL-NEXT: v_mul_f32_e64 v6, 0x2f800000, |v2|856; GFX11-GISEL-NEXT: v_mul_f32_e64 v7, 0x2f800000, |v3|857; GFX11-GISEL-NEXT: s_ashr_i32 s1, s1, 31858; GFX11-GISEL-NEXT: v_floor_f32_e32 v4, v4859; GFX11-GISEL-NEXT: v_floor_f32_e32 v5, v5860; GFX11-GISEL-NEXT: v_floor_f32_e32 v6, v6861; GFX11-GISEL-NEXT: v_floor_f32_e32 v7, v7862; GFX11-GISEL-NEXT: s_ashr_i32 s2, s2, 31863; GFX11-GISEL-NEXT: v_fma_f32 v0, 0xcf800000, v4, |v0|864; GFX11-GISEL-NEXT: v_fma_f32 v1, 0xcf800000, v5, |v1|865; GFX11-GISEL-NEXT: v_fma_f32 v2, 0xcf800000, v6, |v2|866; GFX11-GISEL-NEXT: v_fma_f32 v3, 0xcf800000, v7, |v3|867; GFX11-GISEL-NEXT: v_cvt_u32_f32_e32 v4, v4868; GFX11-GISEL-NEXT: v_cvt_u32_f32_e32 v0, v0869; GFX11-GISEL-NEXT: v_cvt_u32_f32_e32 v1, v1870; GFX11-GISEL-NEXT: v_cvt_u32_f32_e32 v5, v5871; GFX11-GISEL-NEXT: v_cvt_u32_f32_e32 v2, v2872; GFX11-GISEL-NEXT: v_cvt_u32_f32_e32 v6, v6873; GFX11-GISEL-NEXT: v_xor_b32_e32 v0, s0, v0874; GFX11-GISEL-NEXT: v_cvt_u32_f32_e32 v3, v3875; GFX11-GISEL-NEXT: v_xor_b32_e32 v4, s0, v4876; GFX11-GISEL-NEXT: v_xor_b32_e32 v9, s1, v1877; GFX11-GISEL-NEXT: v_cvt_u32_f32_e32 v7, v7878; GFX11-GISEL-NEXT: s_ashr_i32 s3, s3, 31879; GFX11-GISEL-NEXT: v_xor_b32_e32 v5, s1, v5880; GFX11-GISEL-NEXT: v_xor_b32_e32 v10, s2, v2881; GFX11-GISEL-NEXT: v_sub_co_u32 v0, vcc_lo, v0, s0882; GFX11-GISEL-NEXT: v_xor_b32_e32 v6, s2, v6883; GFX11-GISEL-NEXT: v_xor_b32_e32 v11, s3, v3884; GFX11-GISEL-NEXT: v_subrev_co_ci_u32_e64 v1, null, s0, v4, vcc_lo885; GFX11-GISEL-NEXT: v_sub_co_u32 v2, vcc_lo, v9, s1886; GFX11-GISEL-NEXT: v_xor_b32_e32 v7, s3, v7887; GFX11-GISEL-NEXT: v_subrev_co_ci_u32_e64 v3, null, s1, v5, vcc_lo888; GFX11-GISEL-NEXT: v_sub_co_u32 v4, vcc_lo, v10, s2889; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)890; GFX11-GISEL-NEXT: v_subrev_co_ci_u32_e64 v5, null, s2, v6, vcc_lo891; GFX11-GISEL-NEXT: v_sub_co_u32 v6, vcc_lo, v11, s3892; GFX11-GISEL-NEXT: v_subrev_co_ci_u32_e64 v7, null, s3, v7, vcc_lo893; GFX11-GISEL-NEXT: s_clause 0x1894; GFX11-GISEL-NEXT: global_store_b128 v8, v[0:3], s[4:5]895; GFX11-GISEL-NEXT: global_store_b128 v8, v[4:7], s[4:5] offset:16896; GFX11-GISEL-NEXT: s_endpgm897;898; EG-LABEL: fp_to_sint_v4i64:899; EG: ; %bb.0:900; EG-NEXT: ALU 99, @6, KC0[CB0:0-32], KC1[]901; EG-NEXT: ALU 54, @106, KC0[CB0:0-32], KC1[]902; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XYZW, T2.X, 0903; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T6.XYZW, T0.X, 1904; EG-NEXT: CF_END905; EG-NEXT: PAD906; EG-NEXT: ALU clause starting at 6:907; EG-NEXT: MOV * T0.W, literal.x,908; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)909; EG-NEXT: BFE_UINT T1.W, KC0[3].Z, literal.x, PV.W,910; EG-NEXT: AND_INT * T2.W, KC0[3].Z, literal.y,911; EG-NEXT: 23(3.222986e-44), 8388607(1.175494e-38)912; EG-NEXT: OR_INT T2.W, PS, literal.x,913; EG-NEXT: ADD_INT * T3.W, PV.W, literal.y,914; EG-NEXT: 8388608(1.175494e-38), -150(nan)915; EG-NEXT: ADD_INT T0.X, T1.W, literal.x,916; EG-NEXT: BFE_UINT T0.Y, KC0[4].X, literal.y, T0.W,917; EG-NEXT: AND_INT T0.Z, PS, literal.z,918; EG-NEXT: NOT_INT T4.W, PS,919; EG-NEXT: LSHR * T5.W, PV.W, 1,920; EG-NEXT: -127(nan), 23(3.222986e-44)921; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)922; EG-NEXT: BIT_ALIGN_INT T1.X, 0.0, PS, PV.W,923; EG-NEXT: AND_INT T1.Y, T3.W, literal.x,924; EG-NEXT: LSHL T0.Z, T2.W, PV.Z, BS:VEC_120/SCL_212925; EG-NEXT: AND_INT T3.W, KC0[4].X, literal.y,926; EG-NEXT: ADD_INT * T4.W, PV.Y, literal.z,927; EG-NEXT: 32(4.484155e-44), 8388607(1.175494e-38)928; EG-NEXT: -150(nan), 0(0.000000e+00)929; EG-NEXT: AND_INT T2.Y, PS, literal.x,930; EG-NEXT: OR_INT T1.Z, PV.W, literal.y,931; EG-NEXT: CNDE_INT T3.W, PV.Y, PV.X, PV.Z,932; EG-NEXT: SETGT_INT * T5.W, T0.X, literal.z,933; EG-NEXT: 31(4.344025e-44), 8388608(1.175494e-38)934; EG-NEXT: 23(3.222986e-44), 0(0.000000e+00)935; EG-NEXT: CNDE_INT T3.Y, PS, 0.0, PV.W,936; EG-NEXT: SUB_INT T2.Z, literal.x, T1.W,937; EG-NEXT: LSHL T1.W, PV.Z, PV.Y,938; EG-NEXT: AND_INT * T3.W, T4.W, literal.y,939; EG-NEXT: 150(2.101948e-43), 32(4.484155e-44)940; EG-NEXT: CNDE_INT T1.X, PS, PV.W, 0.0,941; EG-NEXT: AND_INT T2.Y, PV.Z, literal.x,942; EG-NEXT: SUB_INT T3.Z, literal.y, T0.Y,943; EG-NEXT: NOT_INT T4.W, T4.W,944; EG-NEXT: LSHR * T6.W, T1.Z, 1,945; EG-NEXT: 32(4.484155e-44), 150(2.101948e-43)946; EG-NEXT: BIT_ALIGN_INT T2.X, 0.0, T2.W, T2.Z,947; EG-NEXT: ADD_INT T0.Y, T0.Y, literal.x,948; EG-NEXT: BIT_ALIGN_INT T2.Z, 0.0, PS, PV.W,949; EG-NEXT: BIT_ALIGN_INT T2.W, 0.0, T1.Z, PV.Z,950; EG-NEXT: AND_INT * T4.W, PV.Z, literal.y,951; EG-NEXT: -127(nan), 32(4.484155e-44)952; EG-NEXT: CNDE_INT T3.X, PS, PV.W, 0.0,953; EG-NEXT: CNDE_INT T4.Y, T3.W, PV.Z, T1.W,954; EG-NEXT: SETGT_INT T1.Z, PV.Y, literal.x,955; EG-NEXT: CNDE_INT T1.W, T1.Y, T0.Z, 0.0,956; EG-NEXT: CNDE_INT * T2.W, T2.Y, PV.X, 0.0,957; EG-NEXT: 23(3.222986e-44), 0(0.000000e+00)958; EG-NEXT: CNDE_INT T2.X, T5.W, PS, PV.W,959; EG-NEXT: ASHR T1.Y, KC0[3].Z, literal.x,960; EG-NEXT: CNDE_INT T0.Z, PV.Z, 0.0, PV.Y,961; EG-NEXT: CNDE_INT T1.W, PV.Z, PV.X, T1.X,962; EG-NEXT: ASHR * T2.W, KC0[4].X, literal.x,963; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)964; EG-NEXT: XOR_INT T2.Y, PV.W, PS,965; EG-NEXT: XOR_INT T0.Z, PV.Z, PS,966; EG-NEXT: XOR_INT T1.W, PV.X, PV.Y,967; EG-NEXT: XOR_INT * T3.W, T3.Y, PV.Y,968; EG-NEXT: SUB_INT T3.Y, PS, T1.Y,969; EG-NEXT: SUBB_UINT T1.Z, PV.W, T1.Y,970; EG-NEXT: SUB_INT T3.W, PV.Z, T2.W,971; EG-NEXT: SUBB_UINT * T4.W, PV.Y, T2.W,972; EG-NEXT: SUB_INT T4.Y, PV.W, PS,973; EG-NEXT: SUB_INT T0.Z, PV.Y, PV.Z,974; EG-NEXT: BFE_UINT T3.W, KC0[3].Y, literal.x, T0.W,975; EG-NEXT: AND_INT * T4.W, KC0[3].Y, literal.y,976; EG-NEXT: 23(3.222986e-44), 8388607(1.175494e-38)977; EG-NEXT: SETGT_INT T0.X, 0.0, T0.X,978; EG-NEXT: ADD_INT T3.Y, PV.W, literal.x,979; EG-NEXT: OR_INT T1.Z, PS, literal.y,980; EG-NEXT: BFE_UINT T0.W, KC0[3].W, literal.z, T0.W,981; EG-NEXT: ADD_INT * T4.W, PV.W, literal.w,982; EG-NEXT: -127(nan), 8388608(1.175494e-38)983; EG-NEXT: 23(3.222986e-44), -150(nan)984; EG-NEXT: AND_INT T1.X, KC0[3].W, literal.x,985; EG-NEXT: ADD_INT T5.Y, PV.W, literal.y,986; EG-NEXT: SUB_INT T2.Z, literal.z, T3.W,987; EG-NEXT: NOT_INT T3.W, PS,988; EG-NEXT: LSHR * T5.W, PV.Z, 1,989; EG-NEXT: 8388607(1.175494e-38), -150(nan)990; EG-NEXT: 150(2.101948e-43), 0(0.000000e+00)991; EG-NEXT: BIT_ALIGN_INT T2.X, 0.0, PS, PV.W,992; EG-NEXT: AND_INT T6.Y, PV.Z, literal.x,993; EG-NEXT: AND_INT T3.Z, PV.Y, literal.y,994; EG-NEXT: OR_INT T3.W, PV.X, literal.z,995; EG-NEXT: AND_INT * T5.W, T4.W, literal.y,996; EG-NEXT: 32(4.484155e-44), 31(4.344025e-44)997; EG-NEXT: 8388608(1.175494e-38), 0(0.000000e+00)998; EG-NEXT: BIT_ALIGN_INT T1.X, 0.0, T1.Z, T2.Z,999; EG-NEXT: LSHL T7.Y, T1.Z, PS,1000; EG-NEXT: AND_INT T1.Z, T4.W, literal.x,1001; EG-NEXT: LSHL T4.W, PV.W, PV.Z,1002; EG-NEXT: AND_INT * T5.W, T5.Y, literal.x,1003; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)1004; EG-NEXT: CNDE_INT T3.X, PS, PV.W, 0.0,1005; EG-NEXT: CNDE_INT T8.Y, PV.Z, PV.Y, 0.0,1006; EG-NEXT: CNDE_INT * T2.Z, T6.Y, PV.X, 0.0,1007; EG-NEXT: ALU clause starting at 106:1008; EG-NEXT: CNDE_INT T6.W, T1.Z, T2.X, T7.Y, BS:VEC_021/SCL_1221009; EG-NEXT: SETGT_INT * T7.W, T3.Y, literal.x,1010; EG-NEXT: 23(3.222986e-44), 0(0.000000e+00)1011; EG-NEXT: CNDE_INT T1.X, PS, 0.0, PV.W,1012; EG-NEXT: CNDE_INT T6.Y, PS, T2.Z, T8.Y,1013; EG-NEXT: SUB_INT T1.Z, literal.x, T0.W,1014; EG-NEXT: NOT_INT T6.W, T5.Y,1015; EG-NEXT: LSHR * T7.W, T3.W, 1,1016; EG-NEXT: 150(2.101948e-43), 0(0.000000e+00)1017; EG-NEXT: ASHR T2.X, KC0[3].Y, literal.x,1018; EG-NEXT: ADD_INT T5.Y, T0.W, literal.y,1019; EG-NEXT: BIT_ALIGN_INT T2.Z, 0.0, PS, PV.W,1020; EG-NEXT: BIT_ALIGN_INT T0.W, 0.0, T3.W, PV.Z,1021; EG-NEXT: AND_INT * T3.W, PV.Z, literal.z,1022; EG-NEXT: 31(4.344025e-44), -127(nan)1023; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)1024; EG-NEXT: CNDE_INT T4.X, PS, PV.W, 0.0,1025; EG-NEXT: CNDE_INT T7.Y, T5.W, PV.Z, T4.W,1026; EG-NEXT: SETGT_INT T1.Z, PV.Y, literal.x,1027; EG-NEXT: XOR_INT T0.W, T6.Y, PV.X,1028; EG-NEXT: XOR_INT * T3.W, T1.X, PV.X,1029; EG-NEXT: 23(3.222986e-44), 0(0.000000e+00)1030; EG-NEXT: SUB_INT T1.X, PS, T2.X,1031; EG-NEXT: SUBB_UINT T6.Y, PV.W, T2.X,1032; EG-NEXT: CNDE_INT T2.Z, PV.Z, 0.0, PV.Y,1033; EG-NEXT: CNDE_INT T3.W, PV.Z, PV.X, T3.X,1034; EG-NEXT: ASHR * T4.W, KC0[3].W, literal.x,1035; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)1036; EG-NEXT: XOR_INT T3.X, PV.W, PS,1037; EG-NEXT: XOR_INT T7.Y, PV.Z, PS,1038; EG-NEXT: SUB_INT T1.Z, PV.X, PV.Y,1039; EG-NEXT: SETGT_INT T3.W, 0.0, T3.Y,1040; EG-NEXT: CNDE_INT * T6.W, T0.X, T0.Z, 0.0,1041; EG-NEXT: SETGT_INT T1.X, 0.0, T0.Y,1042; EG-NEXT: CNDE_INT T6.Y, PV.W, PV.Z, 0.0,1043; EG-NEXT: SUB_INT T0.Z, T1.W, T1.Y, BS:VEC_021/SCL_1221044; EG-NEXT: SUB_INT T1.W, PV.Y, T4.W,1045; EG-NEXT: SUBB_UINT * T5.W, PV.X, T4.W,1046; EG-NEXT: SUB_INT T4.X, PV.W, PS,1047; EG-NEXT: SETGT_INT T0.Y, 0.0, T5.Y, BS:VEC_021/SCL_1221048; EG-NEXT: CNDE_INT T6.Z, T0.X, PV.Z, 0.0,1049; EG-NEXT: SUB_INT T0.W, T0.W, T2.X,1050; EG-NEXT: CNDE_INT * T1.W, PV.X, T4.Y, 0.0,1051; EG-NEXT: CNDE_INT T6.X, T3.W, PV.W, 0.0,1052; EG-NEXT: CNDE_INT T1.Y, PV.Y, PV.X, 0.0,1053; EG-NEXT: SUB_INT T0.W, T2.Y, T2.W,1054; EG-NEXT: LSHR * T0.X, KC0[2].Y, literal.x,1055; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1056; EG-NEXT: CNDE_INT T1.Z, T1.X, PV.W, 0.0,1057; EG-NEXT: SUB_INT * T0.W, T3.X, T4.W, BS:VEC_120/SCL_2121058; EG-NEXT: CNDE_INT T1.X, T0.Y, PV.W, 0.0,1059; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x,1060; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)1061; EG-NEXT: LSHR * T2.X, PV.W, literal.x,1062; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1063 %conv = fptosi <4 x float> %x to <4 x i64>1064 store <4 x i64> %conv, ptr addrspace(1) %out1065 ret void1066}1067 1068define amdgpu_kernel void @fp_to_uint_f32_to_i1(ptr addrspace(1) %out, float %in) #0 {1069; SI-LABEL: fp_to_uint_f32_to_i1:1070; SI: ; %bb.0:1071; SI-NEXT: s_load_dword s6, s[4:5], 0xb1072; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x91073; SI-NEXT: s_mov_b32 s3, 0xf0001074; SI-NEXT: s_mov_b32 s2, -11075; SI-NEXT: s_waitcnt lgkmcnt(0)1076; SI-NEXT: v_cmp_eq_f32_e64 s[4:5], -1.0, s61077; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]1078; SI-NEXT: buffer_store_byte v0, off, s[0:3], 01079; SI-NEXT: s_endpgm1080;1081; VI-LABEL: fp_to_uint_f32_to_i1:1082; VI: ; %bb.0:1083; VI-NEXT: s_load_dword s6, s[4:5], 0x2c1084; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x241085; VI-NEXT: s_mov_b32 s3, 0xf0001086; VI-NEXT: s_mov_b32 s2, -11087; VI-NEXT: s_waitcnt lgkmcnt(0)1088; VI-NEXT: v_cmp_eq_f32_e64 s[4:5], -1.0, s61089; VI-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]1090; VI-NEXT: buffer_store_byte v0, off, s[0:3], 01091; VI-NEXT: s_endpgm1092;1093; GFX11-SDAG-LABEL: fp_to_uint_f32_to_i1:1094; GFX11-SDAG: ; %bb.0:1095; GFX11-SDAG-NEXT: s_clause 0x11096; GFX11-SDAG-NEXT: s_load_b32 s2, s[4:5], 0x2c1097; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x241098; GFX11-SDAG-NEXT: v_mov_b32_e32 v0, 01099; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)1100; GFX11-SDAG-NEXT: v_cmp_eq_f32_e64 s2, -1.0, s21101; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)1102; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 1, s21103; GFX11-SDAG-NEXT: global_store_b8 v0, v1, s[0:1]1104; GFX11-SDAG-NEXT: s_endpgm1105;1106; GFX11-GISEL-LABEL: fp_to_uint_f32_to_i1:1107; GFX11-GISEL: ; %bb.0:1108; GFX11-GISEL-NEXT: s_clause 0x11109; GFX11-GISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c1110; GFX11-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x241111; GFX11-GISEL-NEXT: v_mov_b32_e32 v1, 01112; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)1113; GFX11-GISEL-NEXT: v_cvt_i32_f32_e32 v0, s21114; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)1115; GFX11-GISEL-NEXT: v_and_b32_e32 v0, 1, v01116; GFX11-GISEL-NEXT: global_store_b8 v1, v0, s[0:1]1117; GFX11-GISEL-NEXT: s_endpgm1118;1119; EG-LABEL: fp_to_uint_f32_to_i1:1120; EG: ; %bb.0:1121; EG-NEXT: ALU 12, @4, KC0[CB0:0-32], KC1[]1122; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X1123; EG-NEXT: CF_END1124; EG-NEXT: PAD1125; EG-NEXT: ALU clause starting at 4:1126; EG-NEXT: AND_INT T0.W, KC0[2].Y, literal.x,1127; EG-NEXT: SETE_DX10 * T1.W, KC0[2].Z, literal.y,1128; EG-NEXT: 3(4.203895e-45), -1082130432(-1.000000e+00)1129; EG-NEXT: AND_INT T1.W, PS, 1,1130; EG-NEXT: LSHL * T0.W, PV.W, literal.x,1131; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)1132; EG-NEXT: LSHL T0.X, PV.W, PS,1133; EG-NEXT: LSHL * T0.W, literal.x, PS,1134; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00)1135; EG-NEXT: MOV T0.Y, 0.0,1136; EG-NEXT: MOV * T0.Z, 0.0,1137; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,1138; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1139 %conv = fptosi float %in to i11140 store i1 %conv, ptr addrspace(1) %out1141 ret void1142}1143 1144define amdgpu_kernel void @fp_to_uint_fabs_f32_to_i1(ptr addrspace(1) %out, float %in) #0 {1145; SI-LABEL: fp_to_uint_fabs_f32_to_i1:1146; SI: ; %bb.0:1147; SI-NEXT: s_load_dword s6, s[4:5], 0xb1148; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x91149; SI-NEXT: s_mov_b32 s3, 0xf0001150; SI-NEXT: s_mov_b32 s2, -11151; SI-NEXT: s_waitcnt lgkmcnt(0)1152; SI-NEXT: v_cmp_eq_f32_e64 s[4:5], -1.0, |s6|1153; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]1154; SI-NEXT: buffer_store_byte v0, off, s[0:3], 01155; SI-NEXT: s_endpgm1156;1157; VI-LABEL: fp_to_uint_fabs_f32_to_i1:1158; VI: ; %bb.0:1159; VI-NEXT: s_load_dword s6, s[4:5], 0x2c1160; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x241161; VI-NEXT: s_mov_b32 s3, 0xf0001162; VI-NEXT: s_mov_b32 s2, -11163; VI-NEXT: s_waitcnt lgkmcnt(0)1164; VI-NEXT: v_cmp_eq_f32_e64 s[4:5], -1.0, |s6|1165; VI-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]1166; VI-NEXT: buffer_store_byte v0, off, s[0:3], 01167; VI-NEXT: s_endpgm1168;1169; GFX11-SDAG-LABEL: fp_to_uint_fabs_f32_to_i1:1170; GFX11-SDAG: ; %bb.0:1171; GFX11-SDAG-NEXT: s_clause 0x11172; GFX11-SDAG-NEXT: s_load_b32 s2, s[4:5], 0x2c1173; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x241174; GFX11-SDAG-NEXT: v_mov_b32_e32 v0, 01175; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)1176; GFX11-SDAG-NEXT: v_cmp_eq_f32_e64 s2, -1.0, |s2|1177; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)1178; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 1, s21179; GFX11-SDAG-NEXT: global_store_b8 v0, v1, s[0:1]1180; GFX11-SDAG-NEXT: s_endpgm1181;1182; GFX11-GISEL-LABEL: fp_to_uint_fabs_f32_to_i1:1183; GFX11-GISEL: ; %bb.0:1184; GFX11-GISEL-NEXT: s_clause 0x11185; GFX11-GISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c1186; GFX11-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x241187; GFX11-GISEL-NEXT: v_mov_b32_e32 v1, 01188; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)1189; GFX11-GISEL-NEXT: v_cvt_i32_f32_e64 v0, |s2|1190; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)1191; GFX11-GISEL-NEXT: v_and_b32_e32 v0, 1, v01192; GFX11-GISEL-NEXT: global_store_b8 v1, v0, s[0:1]1193; GFX11-GISEL-NEXT: s_endpgm1194;1195; EG-LABEL: fp_to_uint_fabs_f32_to_i1:1196; EG: ; %bb.0:1197; EG-NEXT: ALU 12, @4, KC0[CB0:0-32], KC1[]1198; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X1199; EG-NEXT: CF_END1200; EG-NEXT: PAD1201; EG-NEXT: ALU clause starting at 4:1202; EG-NEXT: AND_INT T0.W, KC0[2].Y, literal.x,1203; EG-NEXT: SETE_DX10 * T1.W, |KC0[2].Z|, literal.y,1204; EG-NEXT: 3(4.203895e-45), -1082130432(-1.000000e+00)1205; EG-NEXT: AND_INT T1.W, PS, 1,1206; EG-NEXT: LSHL * T0.W, PV.W, literal.x,1207; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)1208; EG-NEXT: LSHL T0.X, PV.W, PS,1209; EG-NEXT: LSHL * T0.W, literal.x, PS,1210; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00)1211; EG-NEXT: MOV T0.Y, 0.0,1212; EG-NEXT: MOV * T0.Z, 0.0,1213; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,1214; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1215 %in.fabs = call float @llvm.fabs.f32(float %in)1216 %conv = fptosi float %in.fabs to i11217 store i1 %conv, ptr addrspace(1) %out1218 ret void1219}1220 1221define amdgpu_kernel void @fp_to_sint_f32_i16(ptr addrspace(1) %out, float %in) #0 {1222; SI-LABEL: fp_to_sint_f32_i16:1223; SI: ; %bb.0:1224; SI-NEXT: s_load_dword s6, s[4:5], 0xb1225; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x91226; SI-NEXT: s_mov_b32 s3, 0xf0001227; SI-NEXT: s_mov_b32 s2, -11228; SI-NEXT: s_waitcnt lgkmcnt(0)1229; SI-NEXT: v_cvt_i32_f32_e32 v0, s61230; SI-NEXT: buffer_store_short v0, off, s[0:3], 01231; SI-NEXT: s_endpgm1232;1233; VI-LABEL: fp_to_sint_f32_i16:1234; VI: ; %bb.0:1235; VI-NEXT: s_load_dword s2, s[4:5], 0x2c1236; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x241237; VI-NEXT: s_mov_b32 s3, 0xf0001238; VI-NEXT: s_waitcnt lgkmcnt(0)1239; VI-NEXT: v_cvt_i32_f32_e32 v0, s21240; VI-NEXT: s_mov_b32 s2, -11241; VI-NEXT: buffer_store_short v0, off, s[0:3], 01242; VI-NEXT: s_endpgm1243;1244; GFX11-SDAG-LABEL: fp_to_sint_f32_i16:1245; GFX11-SDAG: ; %bb.0:1246; GFX11-SDAG-NEXT: s_clause 0x11247; GFX11-SDAG-NEXT: s_load_b32 s2, s[4:5], 0x2c1248; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x241249; GFX11-SDAG-NEXT: v_mov_b32_e32 v0, 01250; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)1251; GFX11-SDAG-NEXT: v_cvt_i32_f32_e32 v1, s21252; GFX11-SDAG-NEXT: global_store_b16 v0, v1, s[0:1]1253; GFX11-SDAG-NEXT: s_endpgm1254;1255; GFX11-GISEL-LABEL: fp_to_sint_f32_i16:1256; GFX11-GISEL: ; %bb.0:1257; GFX11-GISEL-NEXT: s_clause 0x11258; GFX11-GISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c1259; GFX11-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x241260; GFX11-GISEL-NEXT: v_mov_b32_e32 v1, 01261; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)1262; GFX11-GISEL-NEXT: v_cvt_i32_f32_e32 v0, s21263; GFX11-GISEL-NEXT: global_store_b16 v1, v0, s[0:1]1264; GFX11-GISEL-NEXT: s_endpgm1265;1266; EG-LABEL: fp_to_sint_f32_i16:1267; EG: ; %bb.0:1268; EG-NEXT: ALU 13, @4, KC0[CB0:0-32], KC1[]1269; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X1270; EG-NEXT: CF_END1271; EG-NEXT: PAD1272; EG-NEXT: ALU clause starting at 4:1273; EG-NEXT: TRUNC T0.W, KC0[2].Z,1274; EG-NEXT: AND_INT * T1.W, KC0[2].Y, literal.x,1275; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)1276; EG-NEXT: FLT_TO_INT * T0.W, PV.W,1277; EG-NEXT: AND_INT T0.W, PV.W, literal.x,1278; EG-NEXT: LSHL * T1.W, T1.W, literal.y,1279; EG-NEXT: 65535(9.183409e-41), 3(4.203895e-45)1280; EG-NEXT: LSHL T0.X, PV.W, PS,1281; EG-NEXT: LSHL * T0.W, literal.x, PS,1282; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)1283; EG-NEXT: MOV T0.Y, 0.0,1284; EG-NEXT: MOV * T0.Z, 0.0,1285; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,1286; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1287 %sint = fptosi float %in to i161288 store i16 %sint, ptr addrspace(1) %out1289 ret void1290}1291 1292define amdgpu_kernel void @fp_to_sint_v2f32_to_v2i16(ptr addrspace(1) %out, <2 x float> %in) {1293; SI-LABEL: fp_to_sint_v2f32_to_v2i16:1294; SI: ; %bb.0:1295; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91296; SI-NEXT: s_waitcnt lgkmcnt(0)1297; SI-NEXT: s_mov_b64 s[4:5], s[2:3]1298; SI-NEXT: s_mov_b32 s3, 0xf0001299; SI-NEXT: s_mov_b32 s2, -11300; SI-NEXT: v_cvt_i32_f32_e32 v0, s51301; SI-NEXT: v_cvt_i32_f32_e32 v1, s41302; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v01303; SI-NEXT: v_and_b32_e32 v1, 0xffff, v11304; SI-NEXT: v_or_b32_e32 v0, v1, v01305; SI-NEXT: buffer_store_dword v0, off, s[0:3], 01306; SI-NEXT: s_endpgm1307;1308; VI-LABEL: fp_to_sint_v2f32_to_v2i16:1309; VI: ; %bb.0:1310; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241311; VI-NEXT: s_waitcnt lgkmcnt(0)1312; VI-NEXT: v_mov_b32_e32 v0, s31313; VI-NEXT: v_cvt_i32_f32_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD1314; VI-NEXT: v_cvt_i32_f32_e32 v1, s21315; VI-NEXT: s_mov_b32 s3, 0xf0001316; VI-NEXT: s_mov_b32 s2, -11317; VI-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD1318; VI-NEXT: buffer_store_dword v0, off, s[0:3], 01319; VI-NEXT: s_endpgm1320;1321; GFX11-SDAG-LABEL: fp_to_sint_v2f32_to_v2i16:1322; GFX11-SDAG: ; %bb.0:1323; GFX11-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x241324; GFX11-SDAG-NEXT: v_mov_b32_e32 v1, 01325; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)1326; GFX11-SDAG-NEXT: v_cvt_i32_f32_e32 v0, s31327; GFX11-SDAG-NEXT: v_cvt_i32_f32_e32 v2, s21328; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2)1329; GFX11-SDAG-NEXT: v_mov_b16_e32 v2.h, v0.l1330; GFX11-SDAG-NEXT: global_store_b32 v1, v2, s[0:1]1331; GFX11-SDAG-NEXT: s_endpgm1332;1333; GFX11-GISEL-LABEL: fp_to_sint_v2f32_to_v2i16:1334; GFX11-GISEL: ; %bb.0:1335; GFX11-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x241336; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)1337; GFX11-GISEL-NEXT: v_cvt_i32_f32_e32 v0, s31338; GFX11-GISEL-NEXT: v_cvt_i32_f32_e32 v1, s21339; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)1340; GFX11-GISEL-NEXT: v_mov_b16_e32 v1.h, v0.l1341; GFX11-GISEL-NEXT: v_mov_b32_e32 v0, 01342; GFX11-GISEL-NEXT: global_store_b32 v0, v1, s[0:1]1343; GFX11-GISEL-NEXT: s_endpgm1344;1345; EG-LABEL: fp_to_sint_v2f32_to_v2i16:1346; EG: ; %bb.0:1347; EG-NEXT: ALU 9, @4, KC0[CB0:0-32], KC1[]1348; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T4.X, T5.X, 11349; EG-NEXT: CF_END1350; EG-NEXT: PAD1351; EG-NEXT: ALU clause starting at 4:1352; EG-NEXT: TRUNC T0.W, KC0[2].W,1353; EG-NEXT: TRUNC * T1.W, KC0[3].X,1354; EG-NEXT: FLT_TO_INT T1.W, PS,1355; EG-NEXT: FLT_TO_INT * T0.W, PV.W,1356; EG-NEXT: AND_INT T0.W, PS, literal.x,1357; EG-NEXT: LSHL * T1.W, PV.W, literal.y,1358; EG-NEXT: 65535(9.183409e-41), 16(2.242078e-44)1359; EG-NEXT: OR_INT T4.X, PV.W, PS,1360; EG-NEXT: LSHR * T5.X, KC0[2].Y, literal.x,1361; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1362 %sint = fptosi <2 x float> %in to <2 x i16>1363 store <2 x i16> %sint, ptr addrspace(1) %out1364 ret void1365}1366 1367define amdgpu_kernel void @fp_to_sint_f32_to_v2i16(ptr addrspace(1) %out, float %in0, float %in1) {1368; SI-LABEL: fp_to_sint_f32_to_v2i16:1369; SI: ; %bb.0:1370; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91371; SI-NEXT: s_waitcnt lgkmcnt(0)1372; SI-NEXT: s_mov_b64 s[4:5], s[2:3]1373; SI-NEXT: s_mov_b32 s3, 0xf0001374; SI-NEXT: s_mov_b32 s2, -11375; SI-NEXT: v_cvt_i32_f32_e32 v0, s41376; SI-NEXT: v_cvt_i32_f32_e32 v1, s51377; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v11378; SI-NEXT: v_and_b32_e32 v0, 0xffff, v01379; SI-NEXT: v_or_b32_e32 v0, v0, v11380; SI-NEXT: buffer_store_dword v0, off, s[0:3], 01381; SI-NEXT: s_endpgm1382;1383; VI-LABEL: fp_to_sint_f32_to_v2i16:1384; VI: ; %bb.0:1385; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241386; VI-NEXT: s_waitcnt lgkmcnt(0)1387; VI-NEXT: v_mov_b32_e32 v1, s31388; VI-NEXT: v_cvt_i32_f32_e32 v0, s21389; VI-NEXT: v_cvt_i32_f32_sdwa v1, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD1390; VI-NEXT: s_mov_b32 s3, 0xf0001391; VI-NEXT: s_mov_b32 s2, -11392; VI-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD1393; VI-NEXT: buffer_store_dword v0, off, s[0:3], 01394; VI-NEXT: s_endpgm1395;1396; GFX11-SDAG-LABEL: fp_to_sint_f32_to_v2i16:1397; GFX11-SDAG: ; %bb.0:1398; GFX11-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x241399; GFX11-SDAG-NEXT: v_mov_b32_e32 v1, 01400; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)1401; GFX11-SDAG-NEXT: v_cvt_i32_f32_e32 v0, s31402; GFX11-SDAG-NEXT: v_cvt_i32_f32_e32 v2, s21403; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2)1404; GFX11-SDAG-NEXT: v_mov_b16_e32 v2.h, v0.l1405; GFX11-SDAG-NEXT: global_store_b32 v1, v2, s[0:1]1406; GFX11-SDAG-NEXT: s_endpgm1407;1408; GFX11-GISEL-LABEL: fp_to_sint_f32_to_v2i16:1409; GFX11-GISEL: ; %bb.0:1410; GFX11-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x241411; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)1412; GFX11-GISEL-NEXT: v_cvt_i32_f32_e32 v0, s31413; GFX11-GISEL-NEXT: v_cvt_i32_f32_e32 v1, s21414; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)1415; GFX11-GISEL-NEXT: v_mov_b16_e32 v1.h, v0.l1416; GFX11-GISEL-NEXT: v_mov_b32_e32 v0, 01417; GFX11-GISEL-NEXT: global_store_b32 v0, v1, s[0:1]1418; GFX11-GISEL-NEXT: s_endpgm1419;1420; EG-LABEL: fp_to_sint_f32_to_v2i16:1421; EG: ; %bb.0:1422; EG-NEXT: ALU 9, @4, KC0[CB0:0-32], KC1[]1423; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T4.X, T5.X, 11424; EG-NEXT: CF_END1425; EG-NEXT: PAD1426; EG-NEXT: ALU clause starting at 4:1427; EG-NEXT: TRUNC T0.W, KC0[2].W,1428; EG-NEXT: TRUNC * T1.W, KC0[2].Z,1429; EG-NEXT: FLT_TO_INT T1.W, PS,1430; EG-NEXT: FLT_TO_INT * T0.W, PV.W,1431; EG-NEXT: LSHL T0.W, PS, literal.x,1432; EG-NEXT: AND_INT * T1.W, PV.W, literal.y,1433; EG-NEXT: 16(2.242078e-44), 65535(9.183409e-41)1434; EG-NEXT: OR_INT T4.X, PV.W, PS,1435; EG-NEXT: LSHR * T5.X, KC0[2].Y, literal.x,1436; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1437 %sint0 = fptosi float %in0 to i161438 %sint1 = fptosi float %in1 to i161439 %res0 = insertelement <2 x i16> poison, i16 %sint0, i32 01440 %res1 = insertelement <2 x i16> %res0, i16 %sint1, i32 11441 store <2 x i16> %res1, ptr addrspace(1) %out1442 ret void1443}1444 1445attributes #0 = { nounwind }1446attributes #1 = { nounwind readnone }1447;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:1448; GFX11: {{.*}}1449