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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn < %s | FileCheck %s -check-prefixes=SI3; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck %s -check-prefixes=VI4; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck %s -check-prefixes=GFX11,GFX11-SDAG5; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck %s -check-prefixes=GFX11,GFX11-GISEL6; RUN: llc -mtriple=r600 -mcpu=redwood < %s | FileCheck %s -check-prefixes=EG7 8declare float @llvm.fabs.f32(float) #19 10define amdgpu_kernel void @fp_to_uint_f32_to_i32 (ptr addrspace(1) %out, float %in) {11; SI-LABEL: fp_to_uint_f32_to_i32:12; SI: ; %bb.0:13; SI-NEXT: s_load_dword s6, s[4:5], 0xb14; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x915; SI-NEXT: s_mov_b32 s3, 0xf00016; SI-NEXT: s_mov_b32 s2, -117; SI-NEXT: s_waitcnt lgkmcnt(0)18; SI-NEXT: v_cvt_u32_f32_e32 v0, s619; SI-NEXT: buffer_store_dword v0, off, s[0:3], 020; SI-NEXT: s_endpgm21;22; VI-LABEL: fp_to_uint_f32_to_i32:23; VI: ; %bb.0:24; VI-NEXT: s_load_dword s2, s[4:5], 0x2c25; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2426; VI-NEXT: s_mov_b32 s3, 0xf00027; VI-NEXT: s_waitcnt lgkmcnt(0)28; VI-NEXT: v_cvt_u32_f32_e32 v0, s229; VI-NEXT: s_mov_b32 s2, -130; VI-NEXT: buffer_store_dword v0, off, s[0:3], 031; VI-NEXT: s_endpgm32;33; GFX11-SDAG-LABEL: fp_to_uint_f32_to_i32:34; GFX11-SDAG: ; %bb.0:35; GFX11-SDAG-NEXT: s_clause 0x136; GFX11-SDAG-NEXT: s_load_b32 s2, s[4:5], 0x2c37; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x2438; GFX11-SDAG-NEXT: v_mov_b32_e32 v0, 039; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)40; GFX11-SDAG-NEXT: v_cvt_u32_f32_e32 v1, s241; GFX11-SDAG-NEXT: global_store_b32 v0, v1, s[0:1]42; GFX11-SDAG-NEXT: s_endpgm43;44; GFX11-GISEL-LABEL: fp_to_uint_f32_to_i32:45; GFX11-GISEL: ; %bb.0:46; GFX11-GISEL-NEXT: s_clause 0x147; GFX11-GISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c48; GFX11-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x2449; GFX11-GISEL-NEXT: v_mov_b32_e32 v1, 050; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)51; GFX11-GISEL-NEXT: v_cvt_u32_f32_e32 v0, s252; GFX11-GISEL-NEXT: global_store_b32 v1, v0, s[0:1]53; GFX11-GISEL-NEXT: s_endpgm54;55; EG-LABEL: fp_to_uint_f32_to_i32:56; EG: ; %bb.0:57; EG-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[]58; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 159; EG-NEXT: CF_END60; EG-NEXT: PAD61; EG-NEXT: ALU clause starting at 4:62; EG-NEXT: TRUNC * T0.W, KC0[2].Z,63; EG-NEXT: LSHR T0.X, KC0[2].Y, literal.x,64; EG-NEXT: FLT_TO_UINT * T1.X, PV.W,65; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)66 %conv = fptoui float %in to i3267 store i32 %conv, ptr addrspace(1) %out68 ret void69}70 71define amdgpu_kernel void @fp_to_uint_v2f32_to_v2i32(ptr addrspace(1) %out, <2 x float> %in) {72; SI-LABEL: fp_to_uint_v2f32_to_v2i32:73; SI: ; %bb.0:74; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x975; SI-NEXT: s_waitcnt lgkmcnt(0)76; SI-NEXT: s_mov_b64 s[4:5], s[2:3]77; SI-NEXT: s_mov_b32 s3, 0xf00078; SI-NEXT: s_mov_b32 s2, -179; SI-NEXT: v_cvt_u32_f32_e32 v1, s580; SI-NEXT: v_cvt_u32_f32_e32 v0, s481; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 082; SI-NEXT: s_endpgm83;84; VI-LABEL: fp_to_uint_v2f32_to_v2i32:85; VI: ; %bb.0:86; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2487; VI-NEXT: s_waitcnt lgkmcnt(0)88; VI-NEXT: v_cvt_u32_f32_e32 v1, s389; VI-NEXT: v_cvt_u32_f32_e32 v0, s290; VI-NEXT: s_mov_b32 s3, 0xf00091; VI-NEXT: s_mov_b32 s2, -192; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 093; VI-NEXT: s_endpgm94;95; GFX11-SDAG-LABEL: fp_to_uint_v2f32_to_v2i32:96; GFX11-SDAG: ; %bb.0:97; GFX11-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x2498; GFX11-SDAG-NEXT: v_mov_b32_e32 v2, 099; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)100; GFX11-SDAG-NEXT: v_cvt_u32_f32_e32 v1, s3101; GFX11-SDAG-NEXT: v_cvt_u32_f32_e32 v0, s2102; GFX11-SDAG-NEXT: global_store_b64 v2, v[0:1], s[0:1]103; GFX11-SDAG-NEXT: s_endpgm104;105; GFX11-GISEL-LABEL: fp_to_uint_v2f32_to_v2i32:106; GFX11-GISEL: ; %bb.0:107; GFX11-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24108; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, 0109; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)110; GFX11-GISEL-NEXT: v_cvt_u32_f32_e32 v0, s2111; GFX11-GISEL-NEXT: v_cvt_u32_f32_e32 v1, s3112; GFX11-GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1]113; GFX11-GISEL-NEXT: s_endpgm114;115; EG-LABEL: fp_to_uint_v2f32_to_v2i32:116; EG: ; %bb.0:117; EG-NEXT: ALU 5, @4, KC0[CB0:0-32], KC1[]118; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1119; EG-NEXT: CF_END120; EG-NEXT: PAD121; EG-NEXT: ALU clause starting at 4:122; EG-NEXT: TRUNC T0.W, KC0[3].X,123; EG-NEXT: TRUNC * T1.W, KC0[2].W,124; EG-NEXT: FLT_TO_UINT * T0.Y, PV.W,125; EG-NEXT: LSHR T1.X, KC0[2].Y, literal.x,126; EG-NEXT: FLT_TO_UINT * T0.X, T1.W,127; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)128 %result = fptoui <2 x float> %in to <2 x i32>129 store <2 x i32> %result, ptr addrspace(1) %out130 ret void131}132 133define amdgpu_kernel void @fp_to_uint_v4f32_to_v4i32(ptr addrspace(1) %out, ptr addrspace(1) %in) {134; SI-LABEL: fp_to_uint_v4f32_to_v4i32:135; SI: ; %bb.0:136; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9137; SI-NEXT: s_waitcnt lgkmcnt(0)138; SI-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0139; SI-NEXT: s_mov_b32 s3, 0xf000140; SI-NEXT: s_mov_b32 s2, -1141; SI-NEXT: s_waitcnt lgkmcnt(0)142; SI-NEXT: v_cvt_u32_f32_e32 v3, s7143; SI-NEXT: v_cvt_u32_f32_e32 v2, s6144; SI-NEXT: v_cvt_u32_f32_e32 v1, s5145; SI-NEXT: v_cvt_u32_f32_e32 v0, s4146; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0147; SI-NEXT: s_endpgm148;149; VI-LABEL: fp_to_uint_v4f32_to_v4i32:150; VI: ; %bb.0:151; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24152; VI-NEXT: s_waitcnt lgkmcnt(0)153; VI-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0154; VI-NEXT: s_mov_b32 s3, 0xf000155; VI-NEXT: s_mov_b32 s2, -1156; VI-NEXT: s_waitcnt lgkmcnt(0)157; VI-NEXT: v_cvt_u32_f32_e32 v3, s7158; VI-NEXT: v_cvt_u32_f32_e32 v2, s6159; VI-NEXT: v_cvt_u32_f32_e32 v1, s5160; VI-NEXT: v_cvt_u32_f32_e32 v0, s4161; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0162; VI-NEXT: s_endpgm163;164; GFX11-SDAG-LABEL: fp_to_uint_v4f32_to_v4i32:165; GFX11-SDAG: ; %bb.0:166; GFX11-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x24167; GFX11-SDAG-NEXT: v_mov_b32_e32 v4, 0168; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)169; GFX11-SDAG-NEXT: s_load_b128 s[4:7], s[2:3], 0x0170; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)171; GFX11-SDAG-NEXT: v_cvt_u32_f32_e32 v3, s7172; GFX11-SDAG-NEXT: v_cvt_u32_f32_e32 v2, s6173; GFX11-SDAG-NEXT: v_cvt_u32_f32_e32 v1, s5174; GFX11-SDAG-NEXT: v_cvt_u32_f32_e32 v0, s4175; GFX11-SDAG-NEXT: global_store_b128 v4, v[0:3], s[0:1]176; GFX11-SDAG-NEXT: s_endpgm177;178; GFX11-GISEL-LABEL: fp_to_uint_v4f32_to_v4i32:179; GFX11-GISEL: ; %bb.0:180; GFX11-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24181; GFX11-GISEL-NEXT: v_mov_b32_e32 v4, 0182; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)183; GFX11-GISEL-NEXT: s_load_b128 s[4:7], s[2:3], 0x0184; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)185; GFX11-GISEL-NEXT: v_cvt_u32_f32_e32 v0, s4186; GFX11-GISEL-NEXT: v_cvt_u32_f32_e32 v1, s5187; GFX11-GISEL-NEXT: v_cvt_u32_f32_e32 v2, s6188; GFX11-GISEL-NEXT: v_cvt_u32_f32_e32 v3, s7189; GFX11-GISEL-NEXT: global_store_b128 v4, v[0:3], s[0:1]190; GFX11-GISEL-NEXT: s_endpgm191;192; EG-LABEL: fp_to_uint_v4f32_to_v4i32:193; EG: ; %bb.0:194; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]195; EG-NEXT: TEX 0 @6196; EG-NEXT: ALU 9, @9, KC0[CB0:0-32], KC1[]197; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1198; EG-NEXT: CF_END199; EG-NEXT: PAD200; EG-NEXT: Fetch clause starting at 6:201; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 0, #1202; EG-NEXT: ALU clause starting at 8:203; EG-NEXT: MOV * T0.X, KC0[2].Z,204; EG-NEXT: ALU clause starting at 9:205; EG-NEXT: TRUNC T0.W, T0.W,206; EG-NEXT: TRUNC * T1.W, T0.Z,207; EG-NEXT: FLT_TO_UINT * T0.W, PV.W,208; EG-NEXT: TRUNC T2.W, T0.Y,209; EG-NEXT: FLT_TO_UINT * T0.Z, T1.W,210; EG-NEXT: TRUNC T1.W, T0.X,211; EG-NEXT: FLT_TO_UINT * T0.Y, PV.W,212; EG-NEXT: LSHR T1.X, KC0[2].Y, literal.x,213; EG-NEXT: FLT_TO_UINT * T0.X, PV.W,214; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)215 %value = load <4 x float>, ptr addrspace(1) %in216 %result = fptoui <4 x float> %value to <4 x i32>217 store <4 x i32> %result, ptr addrspace(1) %out218 ret void219}220 221define amdgpu_kernel void @fp_to_uint_f32_to_i64(ptr addrspace(1) %out, float %x) {222; SI-LABEL: fp_to_uint_f32_to_i64:223; SI: ; %bb.0:224; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9225; SI-NEXT: s_load_dword s4, s[4:5], 0xb226; SI-NEXT: s_mov_b32 s3, 0xf000227; SI-NEXT: s_mov_b32 s2, -1228; SI-NEXT: s_mov_b32 s5, 0xcf800000229; SI-NEXT: s_waitcnt lgkmcnt(0)230; SI-NEXT: v_trunc_f32_e32 v0, s4231; SI-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0232; SI-NEXT: v_floor_f32_e32 v2, v1233; SI-NEXT: v_cvt_u32_f32_e32 v1, v2234; SI-NEXT: v_fma_f32 v0, v2, s5, v0235; SI-NEXT: v_cvt_u32_f32_e32 v0, v0236; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0237; SI-NEXT: s_endpgm238;239; VI-LABEL: fp_to_uint_f32_to_i64:240; VI: ; %bb.0:241; VI-NEXT: s_load_dword s2, s[4:5], 0x2c242; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24243; VI-NEXT: s_mov_b32 s3, 0xcf800000244; VI-NEXT: s_waitcnt lgkmcnt(0)245; VI-NEXT: v_trunc_f32_e32 v0, s2246; VI-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0247; VI-NEXT: v_floor_f32_e32 v2, v1248; VI-NEXT: v_fma_f32 v0, v2, s3, v0249; VI-NEXT: v_cvt_u32_f32_e32 v1, v2250; VI-NEXT: v_cvt_u32_f32_e32 v0, v0251; VI-NEXT: s_mov_b32 s3, 0xf000252; VI-NEXT: s_mov_b32 s2, -1253; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0254; VI-NEXT: s_endpgm255;256; GFX11-SDAG-LABEL: fp_to_uint_f32_to_i64:257; GFX11-SDAG: ; %bb.0:258; GFX11-SDAG-NEXT: s_load_b32 s0, s[4:5], 0x2c259; GFX11-SDAG-NEXT: v_mov_b32_e32 v2, 0260; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)261; GFX11-SDAG-NEXT: v_trunc_f32_e32 v0, s0262; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24263; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)264; GFX11-SDAG-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0265; GFX11-SDAG-NEXT: v_floor_f32_e32 v1, v1266; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)267; GFX11-SDAG-NEXT: v_fmamk_f32 v0, v1, 0xcf800000, v0268; GFX11-SDAG-NEXT: v_cvt_u32_f32_e32 v1, v1269; GFX11-SDAG-NEXT: v_cvt_u32_f32_e32 v0, v0270; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)271; GFX11-SDAG-NEXT: global_store_b64 v2, v[0:1], s[0:1]272; GFX11-SDAG-NEXT: s_endpgm273;274; GFX11-GISEL-LABEL: fp_to_uint_f32_to_i64:275; GFX11-GISEL: ; %bb.0:276; GFX11-GISEL-NEXT: s_load_b32 s0, s[4:5], 0x2c277; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, 0278; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)279; GFX11-GISEL-NEXT: v_trunc_f32_e32 v0, s0280; GFX11-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24281; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)282; GFX11-GISEL-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0283; GFX11-GISEL-NEXT: v_floor_f32_e32 v1, v1284; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)285; GFX11-GISEL-NEXT: v_fmac_f32_e32 v0, 0xcf800000, v1286; GFX11-GISEL-NEXT: v_cvt_u32_f32_e32 v1, v1287; GFX11-GISEL-NEXT: v_cvt_u32_f32_e32 v0, v0288; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)289; GFX11-GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1]290; GFX11-GISEL-NEXT: s_endpgm291;292; EG-LABEL: fp_to_uint_f32_to_i64:293; EG: ; %bb.0:294; EG-NEXT: ALU 40, @4, KC0[CB0:0-32], KC1[]295; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1296; EG-NEXT: CF_END297; EG-NEXT: PAD298; EG-NEXT: ALU clause starting at 4:299; EG-NEXT: MOV * T0.W, literal.x,300; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)301; EG-NEXT: BFE_UINT T0.W, KC0[2].Z, literal.x, PV.W,302; EG-NEXT: AND_INT * T1.W, KC0[2].Z, literal.y,303; EG-NEXT: 23(3.222986e-44), 8388607(1.175494e-38)304; EG-NEXT: OR_INT T1.W, PS, literal.x,305; EG-NEXT: ADD_INT * T2.W, PV.W, literal.y,306; EG-NEXT: 8388608(1.175494e-38), -150(nan)307; EG-NEXT: ADD_INT T0.X, T0.W, literal.x,308; EG-NEXT: AND_INT T0.Y, PS, literal.y,309; EG-NEXT: SUB_INT T0.Z, literal.z, T0.W,310; EG-NEXT: NOT_INT T0.W, PS,311; EG-NEXT: LSHR * T3.W, PV.W, 1,312; EG-NEXT: -127(nan), 31(4.344025e-44)313; EG-NEXT: 150(2.101948e-43), 0(0.000000e+00)314; EG-NEXT: BIT_ALIGN_INT T1.X, 0.0, PS, PV.W,315; EG-NEXT: AND_INT T1.Y, PV.Z, literal.x,316; EG-NEXT: BIT_ALIGN_INT T0.Z, 0.0, T1.W, PV.Z,317; EG-NEXT: LSHL T0.W, T1.W, PV.Y,318; EG-NEXT: AND_INT * T1.W, T2.W, literal.x,319; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)320; EG-NEXT: CNDE_INT T0.Y, PS, PV.W, 0.0,321; EG-NEXT: CNDE_INT T0.Z, PV.Y, PV.Z, 0.0,322; EG-NEXT: CNDE_INT T0.W, PS, PV.X, PV.W,323; EG-NEXT: SETGT_INT * T1.W, T0.X, literal.x,324; EG-NEXT: 23(3.222986e-44), 0(0.000000e+00)325; EG-NEXT: CNDE_INT T1.Z, PS, 0.0, PV.W,326; EG-NEXT: CNDE_INT T0.W, PS, PV.Z, PV.Y,327; EG-NEXT: ASHR * T1.W, KC0[2].Z, literal.x,328; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)329; EG-NEXT: XOR_INT T0.W, PV.W, PS,330; EG-NEXT: XOR_INT * T2.W, PV.Z, PS,331; EG-NEXT: SUB_INT T2.W, PS, T1.W,332; EG-NEXT: SUBB_UINT * T3.W, PV.W, T1.W,333; EG-NEXT: SUB_INT T2.W, PV.W, PS,334; EG-NEXT: SETGT_INT * T3.W, 0.0, T0.X,335; EG-NEXT: CNDE_INT T0.Y, PS, PV.W, 0.0,336; EG-NEXT: SUB_INT * T0.W, T0.W, T1.W,337; EG-NEXT: CNDE_INT T0.X, T3.W, PV.W, 0.0,338; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,339; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)340 %conv = fptoui float %x to i64341 store i64 %conv, ptr addrspace(1) %out342 ret void343}344 345define amdgpu_kernel void @fp_to_uint_v2f32_to_v2i64(ptr addrspace(1) %out, <2 x float> %x) {346; SI-LABEL: fp_to_uint_v2f32_to_v2i64:347; SI: ; %bb.0:348; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9349; SI-NEXT: s_mov_b32 s6, 0xcf800000350; SI-NEXT: s_waitcnt lgkmcnt(0)351; SI-NEXT: s_mov_b64 s[4:5], s[2:3]352; SI-NEXT: s_mov_b32 s3, 0xf000353; SI-NEXT: s_mov_b32 s2, -1354; SI-NEXT: v_trunc_f32_e32 v0, s5355; SI-NEXT: v_trunc_f32_e32 v2, s4356; SI-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0357; SI-NEXT: v_mul_f32_e32 v3, 0x2f800000, v2358; SI-NEXT: v_floor_f32_e32 v4, v1359; SI-NEXT: v_floor_f32_e32 v5, v3360; SI-NEXT: v_cvt_u32_f32_e32 v3, v4361; SI-NEXT: v_cvt_u32_f32_e32 v1, v5362; SI-NEXT: v_fma_f32 v0, v4, s6, v0363; SI-NEXT: v_fma_f32 v4, v5, s6, v2364; SI-NEXT: v_cvt_u32_f32_e32 v2, v0365; SI-NEXT: v_cvt_u32_f32_e32 v0, v4366; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0367; SI-NEXT: s_endpgm368;369; VI-LABEL: fp_to_uint_v2f32_to_v2i64:370; VI: ; %bb.0:371; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24372; VI-NEXT: s_waitcnt lgkmcnt(0)373; VI-NEXT: v_trunc_f32_e32 v0, s3374; VI-NEXT: v_trunc_f32_e32 v4, s2375; VI-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0376; VI-NEXT: v_mul_f32_e32 v2, 0x2f800000, v4377; VI-NEXT: v_floor_f32_e32 v5, v1378; VI-NEXT: s_mov_b32 s2, 0xcf800000379; VI-NEXT: v_floor_f32_e32 v6, v2380; VI-NEXT: v_fma_f32 v0, v5, s2, v0381; VI-NEXT: v_cvt_u32_f32_e32 v2, v0382; VI-NEXT: v_fma_f32 v0, v6, s2, v4383; VI-NEXT: v_cvt_u32_f32_e32 v3, v5384; VI-NEXT: v_cvt_u32_f32_e32 v1, v6385; VI-NEXT: v_cvt_u32_f32_e32 v0, v0386; VI-NEXT: s_mov_b32 s3, 0xf000387; VI-NEXT: s_mov_b32 s2, -1388; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0389; VI-NEXT: s_endpgm390;391; GFX11-SDAG-LABEL: fp_to_uint_v2f32_to_v2i64:392; GFX11-SDAG: ; %bb.0:393; GFX11-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x24394; GFX11-SDAG-NEXT: v_mov_b32_e32 v5, 0395; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)396; GFX11-SDAG-NEXT: v_trunc_f32_e32 v0, s3397; GFX11-SDAG-NEXT: v_trunc_f32_e32 v4, s2398; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)399; GFX11-SDAG-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0400; GFX11-SDAG-NEXT: v_mul_f32_e32 v2, 0x2f800000, v4401; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)402; GFX11-SDAG-NEXT: v_floor_f32_e32 v1, v1403; GFX11-SDAG-NEXT: v_floor_f32_e32 v2, v2404; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)405; GFX11-SDAG-NEXT: v_fmac_f32_e32 v0, 0xcf800000, v1406; GFX11-SDAG-NEXT: v_fmac_f32_e32 v4, 0xcf800000, v2407; GFX11-SDAG-NEXT: v_cvt_u32_f32_e32 v3, v1408; GFX11-SDAG-NEXT: v_cvt_u32_f32_e32 v1, v2409; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)410; GFX11-SDAG-NEXT: v_cvt_u32_f32_e32 v2, v0411; GFX11-SDAG-NEXT: v_cvt_u32_f32_e32 v0, v4412; GFX11-SDAG-NEXT: global_store_b128 v5, v[0:3], s[0:1]413; GFX11-SDAG-NEXT: s_endpgm414;415; GFX11-GISEL-LABEL: fp_to_uint_v2f32_to_v2i64:416; GFX11-GISEL: ; %bb.0:417; GFX11-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24418; GFX11-GISEL-NEXT: v_mov_b32_e32 v4, 0419; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)420; GFX11-GISEL-NEXT: v_trunc_f32_e32 v0, s2421; GFX11-GISEL-NEXT: v_trunc_f32_e32 v2, s3422; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)423; GFX11-GISEL-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0424; GFX11-GISEL-NEXT: v_mul_f32_e32 v3, 0x2f800000, v2425; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)426; GFX11-GISEL-NEXT: v_floor_f32_e32 v1, v1427; GFX11-GISEL-NEXT: v_floor_f32_e32 v3, v3428; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)429; GFX11-GISEL-NEXT: v_fmac_f32_e32 v0, 0xcf800000, v1430; GFX11-GISEL-NEXT: v_fmac_f32_e32 v2, 0xcf800000, v3431; GFX11-GISEL-NEXT: v_cvt_u32_f32_e32 v1, v1432; GFX11-GISEL-NEXT: v_cvt_u32_f32_e32 v3, v3433; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)434; GFX11-GISEL-NEXT: v_cvt_u32_f32_e32 v0, v0435; GFX11-GISEL-NEXT: v_cvt_u32_f32_e32 v2, v2436; GFX11-GISEL-NEXT: global_store_b128 v4, v[0:3], s[0:1]437; GFX11-GISEL-NEXT: s_endpgm438;439; EG-LABEL: fp_to_uint_v2f32_to_v2i64:440; EG: ; %bb.0:441; EG-NEXT: ALU 74, @4, KC0[CB0:0-32], KC1[]442; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XYZW, T0.X, 1443; EG-NEXT: CF_END444; EG-NEXT: PAD445; EG-NEXT: ALU clause starting at 4:446; EG-NEXT: MOV * T0.W, literal.x,447; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)448; EG-NEXT: BFE_UINT T0.Z, KC0[3].X, literal.x, PV.W,449; EG-NEXT: BFE_UINT T0.W, KC0[2].W, literal.x, PV.W,450; EG-NEXT: AND_INT * T1.Z, KC0[2].W, literal.y,451; EG-NEXT: 23(3.222986e-44), 8388607(1.175494e-38)452; EG-NEXT: ADD_INT T1.W, PV.W, literal.x,453; EG-NEXT: ADD_INT * T2.W, PV.Z, literal.x,454; EG-NEXT: -150(nan), 0(0.000000e+00)455; EG-NEXT: AND_INT T0.X, PS, literal.x,456; EG-NEXT: AND_INT T0.Y, PV.W, literal.x,457; EG-NEXT: OR_INT T1.Z, T1.Z, literal.y,458; EG-NEXT: SUB_INT T3.W, literal.z, T0.W,459; EG-NEXT: AND_INT * T4.W, KC0[3].X, literal.w,460; EG-NEXT: 31(4.344025e-44), 8388608(1.175494e-38)461; EG-NEXT: 150(2.101948e-43), 8388607(1.175494e-38)462; EG-NEXT: OR_INT T1.X, PS, literal.x,463; EG-NEXT: AND_INT T1.Y, PV.W, literal.y,464; EG-NEXT: BIT_ALIGN_INT T2.Z, 0.0, PV.Z, PV.W,465; EG-NEXT: LSHL T3.W, PV.Z, PV.Y,466; EG-NEXT: AND_INT * T4.W, T1.W, literal.y,467; EG-NEXT: 8388608(1.175494e-38), 32(4.484155e-44)468; EG-NEXT: CNDE_INT T0.Y, PS, PV.W, 0.0,469; EG-NEXT: CNDE_INT T2.Z, PV.Y, PV.Z, 0.0,470; EG-NEXT: LSHL T5.W, PV.X, T0.X,471; EG-NEXT: AND_INT * T6.W, T2.W, literal.x,472; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)473; EG-NEXT: CNDE_INT T0.X, PS, PV.W, 0.0,474; EG-NEXT: NOT_INT T1.Y, T1.W,475; EG-NEXT: SUB_INT T3.Z, literal.x, T0.Z,476; EG-NEXT: NOT_INT T1.W, T2.W, BS:VEC_120/SCL_212477; EG-NEXT: LSHR * T2.W, T1.X, 1,478; EG-NEXT: 150(2.101948e-43), 0(0.000000e+00)479; EG-NEXT: LSHR T2.X, T1.Z, 1,480; EG-NEXT: ADD_INT T2.Y, T0.Z, literal.x, BS:VEC_120/SCL_212481; EG-NEXT: BIT_ALIGN_INT T0.Z, 0.0, PS, PV.W,482; EG-NEXT: BIT_ALIGN_INT T1.W, 0.0, T1.X, PV.Z,483; EG-NEXT: AND_INT * T2.W, PV.Z, literal.y,484; EG-NEXT: -127(nan), 32(4.484155e-44)485; EG-NEXT: CNDE_INT T1.X, PS, PV.W, 0.0,486; EG-NEXT: CNDE_INT T3.Y, T6.W, PV.Z, T5.W, BS:VEC_021/SCL_122487; EG-NEXT: SETGT_INT T0.Z, PV.Y, literal.x,488; EG-NEXT: BIT_ALIGN_INT T1.W, 0.0, PV.X, T1.Y,489; EG-NEXT: ADD_INT * T0.W, T0.W, literal.y,490; EG-NEXT: 23(3.222986e-44), -127(nan)491; EG-NEXT: CNDE_INT T2.X, T4.W, PV.W, T3.W,492; EG-NEXT: SETGT_INT T1.Y, PS, literal.x,493; EG-NEXT: CNDE_INT T1.Z, PV.Z, 0.0, PV.Y,494; EG-NEXT: CNDE_INT T1.W, PV.Z, PV.X, T0.X,495; EG-NEXT: ASHR * T2.W, KC0[3].X, literal.y,496; EG-NEXT: 23(3.222986e-44), 31(4.344025e-44)497; EG-NEXT: XOR_INT T0.X, PV.W, PS,498; EG-NEXT: XOR_INT T3.Y, PV.Z, PS,499; EG-NEXT: CNDE_INT T0.Z, PV.Y, 0.0, PV.X,500; EG-NEXT: CNDE_INT T1.W, PV.Y, T2.Z, T0.Y,501; EG-NEXT: ASHR * T3.W, KC0[2].W, literal.x,502; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)503; EG-NEXT: XOR_INT T0.Y, PV.W, PS,504; EG-NEXT: XOR_INT T0.Z, PV.Z, PS,505; EG-NEXT: SUB_INT T1.W, PV.Y, T2.W,506; EG-NEXT: SUBB_UINT * T4.W, PV.X, T2.W,507; EG-NEXT: SUB_INT T1.Y, PV.W, PS,508; EG-NEXT: SETGT_INT T1.Z, 0.0, T2.Y,509; EG-NEXT: SUB_INT T1.W, PV.Z, T3.W,510; EG-NEXT: SUBB_UINT * T4.W, PV.Y, T3.W,511; EG-NEXT: SUB_INT T0.Z, PV.W, PS,512; EG-NEXT: SETGT_INT T0.W, 0.0, T0.W,513; EG-NEXT: CNDE_INT * T1.W, PV.Z, PV.Y, 0.0,514; EG-NEXT: CNDE_INT T1.Y, PV.W, PV.Z, 0.0,515; EG-NEXT: SUB_INT * T2.W, T0.X, T2.W,516; EG-NEXT: CNDE_INT T1.Z, T1.Z, PV.W, 0.0,517; EG-NEXT: SUB_INT * T2.W, T0.Y, T3.W,518; EG-NEXT: CNDE_INT T1.X, T0.W, PV.W, 0.0,519; EG-NEXT: LSHR * T0.X, KC0[2].Y, literal.x,520; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)521 %conv = fptoui <2 x float> %x to <2 x i64>522 store <2 x i64> %conv, ptr addrspace(1) %out523 ret void524}525 526define amdgpu_kernel void @fp_to_uint_v4f32_to_v4i64(ptr addrspace(1) %out, <4 x float> %x) {527; SI-LABEL: fp_to_uint_v4f32_to_v4i64:528; SI: ; %bb.0:529; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9530; SI-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0xd531; SI-NEXT: s_mov_b32 s3, 0xf000532; SI-NEXT: s_mov_b32 s2, -1533; SI-NEXT: s_mov_b32 s8, 0xcf800000534; SI-NEXT: s_waitcnt lgkmcnt(0)535; SI-NEXT: v_trunc_f32_e32 v0, s5536; SI-NEXT: v_trunc_f32_e32 v2, s4537; SI-NEXT: v_trunc_f32_e32 v4, s7538; SI-NEXT: v_trunc_f32_e32 v6, s6539; SI-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0540; SI-NEXT: v_mul_f32_e32 v3, 0x2f800000, v2541; SI-NEXT: v_mul_f32_e32 v5, 0x2f800000, v4542; SI-NEXT: v_mul_f32_e32 v7, 0x2f800000, v6543; SI-NEXT: v_floor_f32_e32 v8, v1544; SI-NEXT: v_floor_f32_e32 v9, v3545; SI-NEXT: v_floor_f32_e32 v10, v5546; SI-NEXT: v_floor_f32_e32 v11, v7547; SI-NEXT: v_cvt_u32_f32_e32 v3, v8548; SI-NEXT: v_cvt_u32_f32_e32 v1, v9549; SI-NEXT: v_fma_f32 v0, v8, s8, v0550; SI-NEXT: v_fma_f32 v8, v9, s8, v2551; SI-NEXT: v_cvt_u32_f32_e32 v7, v10552; SI-NEXT: v_cvt_u32_f32_e32 v5, v11553; SI-NEXT: v_fma_f32 v4, v10, s8, v4554; SI-NEXT: v_fma_f32 v9, v11, s8, v6555; SI-NEXT: v_cvt_u32_f32_e32 v2, v0556; SI-NEXT: v_cvt_u32_f32_e32 v0, v8557; SI-NEXT: v_cvt_u32_f32_e32 v6, v4558; SI-NEXT: v_cvt_u32_f32_e32 v4, v9559; SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16560; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0561; SI-NEXT: s_endpgm562;563; VI-LABEL: fp_to_uint_v4f32_to_v4i64:564; VI: ; %bb.0:565; VI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x34566; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24567; VI-NEXT: s_mov_b32 s2, 0xcf800000568; VI-NEXT: s_mov_b32 s3, 0xf000569; VI-NEXT: s_waitcnt lgkmcnt(0)570; VI-NEXT: v_trunc_f32_e32 v0, s9571; VI-NEXT: v_trunc_f32_e32 v4, s8572; VI-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0573; VI-NEXT: v_mul_f32_e32 v2, 0x2f800000, v4574; VI-NEXT: v_floor_f32_e32 v5, v1575; VI-NEXT: v_floor_f32_e32 v6, v2576; VI-NEXT: v_fma_f32 v0, v5, s2, v0577; VI-NEXT: v_cvt_u32_f32_e32 v2, v0578; VI-NEXT: v_fma_f32 v0, v6, s2, v4579; VI-NEXT: v_trunc_f32_e32 v4, s11580; VI-NEXT: v_cvt_u32_f32_e32 v3, v5581; VI-NEXT: v_mul_f32_e32 v5, 0x2f800000, v4582; VI-NEXT: v_trunc_f32_e32 v8, s10583; VI-NEXT: v_cvt_u32_f32_e32 v1, v6584; VI-NEXT: v_floor_f32_e32 v6, v5585; VI-NEXT: v_mul_f32_e32 v5, 0x2f800000, v8586; VI-NEXT: v_floor_f32_e32 v9, v5587; VI-NEXT: v_fma_f32 v4, v6, s2, v4588; VI-NEXT: v_cvt_u32_f32_e32 v7, v6589; VI-NEXT: v_cvt_u32_f32_e32 v6, v4590; VI-NEXT: v_fma_f32 v4, v9, s2, v8591; VI-NEXT: v_cvt_u32_f32_e32 v5, v9592; VI-NEXT: v_cvt_u32_f32_e32 v4, v4593; VI-NEXT: v_cvt_u32_f32_e32 v0, v0594; VI-NEXT: s_mov_b32 s2, -1595; VI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16596; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0597; VI-NEXT: s_endpgm598;599; GFX11-SDAG-LABEL: fp_to_uint_v4f32_to_v4i64:600; GFX11-SDAG: ; %bb.0:601; GFX11-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x34602; GFX11-SDAG-NEXT: v_mov_b32_e32 v10, 0603; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)604; GFX11-SDAG-NEXT: v_trunc_f32_e32 v0, s1605; GFX11-SDAG-NEXT: v_trunc_f32_e32 v8, s0606; GFX11-SDAG-NEXT: v_trunc_f32_e32 v4, s3607; GFX11-SDAG-NEXT: v_trunc_f32_e32 v9, s2608; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24609; GFX11-SDAG-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0610; GFX11-SDAG-NEXT: v_mul_f32_e32 v2, 0x2f800000, v8611; GFX11-SDAG-NEXT: v_mul_f32_e32 v3, 0x2f800000, v4612; GFX11-SDAG-NEXT: v_mul_f32_e32 v5, 0x2f800000, v9613; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)614; GFX11-SDAG-NEXT: v_floor_f32_e32 v6, v1615; GFX11-SDAG-NEXT: v_floor_f32_e32 v2, v2616; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)617; GFX11-SDAG-NEXT: v_floor_f32_e32 v7, v3618; GFX11-SDAG-NEXT: v_floor_f32_e32 v5, v5619; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)620; GFX11-SDAG-NEXT: v_fmac_f32_e32 v0, 0xcf800000, v6621; GFX11-SDAG-NEXT: v_fmac_f32_e32 v8, 0xcf800000, v2622; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)623; GFX11-SDAG-NEXT: v_dual_fmac_f32 v4, 0xcf800000, v7 :: v_dual_fmac_f32 v9, 0xcf800000, v5624; GFX11-SDAG-NEXT: v_cvt_u32_f32_e32 v3, v6625; GFX11-SDAG-NEXT: v_cvt_u32_f32_e32 v7, v7626; GFX11-SDAG-NEXT: v_cvt_u32_f32_e32 v5, v5627; GFX11-SDAG-NEXT: v_cvt_u32_f32_e32 v6, v4628; GFX11-SDAG-NEXT: v_cvt_u32_f32_e32 v4, v9629; GFX11-SDAG-NEXT: v_cvt_u32_f32_e32 v1, v2630; GFX11-SDAG-NEXT: v_cvt_u32_f32_e32 v2, v0631; GFX11-SDAG-NEXT: v_cvt_u32_f32_e32 v0, v8632; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)633; GFX11-SDAG-NEXT: s_clause 0x1634; GFX11-SDAG-NEXT: global_store_b128 v10, v[4:7], s[0:1] offset:16635; GFX11-SDAG-NEXT: global_store_b128 v10, v[0:3], s[0:1]636; GFX11-SDAG-NEXT: s_endpgm637;638; GFX11-GISEL-LABEL: fp_to_uint_v4f32_to_v4i64:639; GFX11-GISEL: ; %bb.0:640; GFX11-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x34641; GFX11-GISEL-NEXT: v_mov_b32_e32 v8, 0642; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)643; GFX11-GISEL-NEXT: v_trunc_f32_e32 v0, s0644; GFX11-GISEL-NEXT: v_trunc_f32_e32 v2, s1645; GFX11-GISEL-NEXT: v_trunc_f32_e32 v4, s2646; GFX11-GISEL-NEXT: v_trunc_f32_e32 v6, s3647; GFX11-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24648; GFX11-GISEL-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0649; GFX11-GISEL-NEXT: v_mul_f32_e32 v3, 0x2f800000, v2650; GFX11-GISEL-NEXT: v_mul_f32_e32 v5, 0x2f800000, v4651; GFX11-GISEL-NEXT: v_mul_f32_e32 v7, 0x2f800000, v6652; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)653; GFX11-GISEL-NEXT: v_floor_f32_e32 v1, v1654; GFX11-GISEL-NEXT: v_floor_f32_e32 v3, v3655; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)656; GFX11-GISEL-NEXT: v_floor_f32_e32 v5, v5657; GFX11-GISEL-NEXT: v_floor_f32_e32 v7, v7658; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)659; GFX11-GISEL-NEXT: v_fmac_f32_e32 v0, 0xcf800000, v1660; GFX11-GISEL-NEXT: v_fmac_f32_e32 v2, 0xcf800000, v3661; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)662; GFX11-GISEL-NEXT: v_fmac_f32_e32 v4, 0xcf800000, v5663; GFX11-GISEL-NEXT: v_fmac_f32_e32 v6, 0xcf800000, v7664; GFX11-GISEL-NEXT: v_cvt_u32_f32_e32 v1, v1665; GFX11-GISEL-NEXT: v_cvt_u32_f32_e32 v3, v3666; GFX11-GISEL-NEXT: v_cvt_u32_f32_e32 v0, v0667; GFX11-GISEL-NEXT: v_cvt_u32_f32_e32 v2, v2668; GFX11-GISEL-NEXT: v_cvt_u32_f32_e32 v5, v5669; GFX11-GISEL-NEXT: v_cvt_u32_f32_e32 v7, v7670; GFX11-GISEL-NEXT: v_cvt_u32_f32_e32 v4, v4671; GFX11-GISEL-NEXT: v_cvt_u32_f32_e32 v6, v6672; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)673; GFX11-GISEL-NEXT: s_clause 0x1674; GFX11-GISEL-NEXT: global_store_b128 v8, v[0:3], s[0:1]675; GFX11-GISEL-NEXT: global_store_b128 v8, v[4:7], s[0:1] offset:16676; GFX11-GISEL-NEXT: s_endpgm677;678; EG-LABEL: fp_to_uint_v4f32_to_v4i64:679; EG: ; %bb.0:680; EG-NEXT: ALU 99, @6, KC0[CB0:0-32], KC1[]681; EG-NEXT: ALU 54, @106, KC0[CB0:0-32], KC1[]682; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XYZW, T2.X, 0683; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T6.XYZW, T0.X, 1684; EG-NEXT: CF_END685; EG-NEXT: PAD686; EG-NEXT: ALU clause starting at 6:687; EG-NEXT: MOV * T0.W, literal.x,688; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)689; EG-NEXT: BFE_UINT T1.W, KC0[3].Z, literal.x, PV.W,690; EG-NEXT: AND_INT * T2.W, KC0[3].Z, literal.y,691; EG-NEXT: 23(3.222986e-44), 8388607(1.175494e-38)692; EG-NEXT: OR_INT T2.W, PS, literal.x,693; EG-NEXT: ADD_INT * T3.W, PV.W, literal.y,694; EG-NEXT: 8388608(1.175494e-38), -150(nan)695; EG-NEXT: ADD_INT T0.X, T1.W, literal.x,696; EG-NEXT: BFE_UINT T0.Y, KC0[4].X, literal.y, T0.W,697; EG-NEXT: AND_INT T0.Z, PS, literal.z,698; EG-NEXT: NOT_INT T4.W, PS,699; EG-NEXT: LSHR * T5.W, PV.W, 1,700; EG-NEXT: -127(nan), 23(3.222986e-44)701; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)702; EG-NEXT: BIT_ALIGN_INT T1.X, 0.0, PS, PV.W,703; EG-NEXT: AND_INT T1.Y, T3.W, literal.x,704; EG-NEXT: LSHL T0.Z, T2.W, PV.Z, BS:VEC_120/SCL_212705; EG-NEXT: AND_INT T3.W, KC0[4].X, literal.y,706; EG-NEXT: ADD_INT * T4.W, PV.Y, literal.z,707; EG-NEXT: 32(4.484155e-44), 8388607(1.175494e-38)708; EG-NEXT: -150(nan), 0(0.000000e+00)709; EG-NEXT: AND_INT T2.Y, PS, literal.x,710; EG-NEXT: OR_INT T1.Z, PV.W, literal.y,711; EG-NEXT: CNDE_INT T3.W, PV.Y, PV.X, PV.Z,712; EG-NEXT: SETGT_INT * T5.W, T0.X, literal.z,713; EG-NEXT: 31(4.344025e-44), 8388608(1.175494e-38)714; EG-NEXT: 23(3.222986e-44), 0(0.000000e+00)715; EG-NEXT: CNDE_INT T3.Y, PS, 0.0, PV.W,716; EG-NEXT: SUB_INT T2.Z, literal.x, T1.W,717; EG-NEXT: LSHL T1.W, PV.Z, PV.Y,718; EG-NEXT: AND_INT * T3.W, T4.W, literal.y,719; EG-NEXT: 150(2.101948e-43), 32(4.484155e-44)720; EG-NEXT: CNDE_INT T1.X, PS, PV.W, 0.0,721; EG-NEXT: AND_INT T2.Y, PV.Z, literal.x,722; EG-NEXT: SUB_INT T3.Z, literal.y, T0.Y,723; EG-NEXT: NOT_INT T4.W, T4.W,724; EG-NEXT: LSHR * T6.W, T1.Z, 1,725; EG-NEXT: 32(4.484155e-44), 150(2.101948e-43)726; EG-NEXT: BIT_ALIGN_INT T2.X, 0.0, T2.W, T2.Z,727; EG-NEXT: ADD_INT T0.Y, T0.Y, literal.x,728; EG-NEXT: BIT_ALIGN_INT T2.Z, 0.0, PS, PV.W,729; EG-NEXT: BIT_ALIGN_INT T2.W, 0.0, T1.Z, PV.Z,730; EG-NEXT: AND_INT * T4.W, PV.Z, literal.y,731; EG-NEXT: -127(nan), 32(4.484155e-44)732; EG-NEXT: CNDE_INT T3.X, PS, PV.W, 0.0,733; EG-NEXT: CNDE_INT T4.Y, T3.W, PV.Z, T1.W,734; EG-NEXT: SETGT_INT T1.Z, PV.Y, literal.x,735; EG-NEXT: CNDE_INT T1.W, T1.Y, T0.Z, 0.0,736; EG-NEXT: CNDE_INT * T2.W, T2.Y, PV.X, 0.0,737; EG-NEXT: 23(3.222986e-44), 0(0.000000e+00)738; EG-NEXT: CNDE_INT T2.X, T5.W, PS, PV.W,739; EG-NEXT: ASHR T1.Y, KC0[3].Z, literal.x,740; EG-NEXT: CNDE_INT T0.Z, PV.Z, 0.0, PV.Y,741; EG-NEXT: CNDE_INT T1.W, PV.Z, PV.X, T1.X,742; EG-NEXT: ASHR * T2.W, KC0[4].X, literal.x,743; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)744; EG-NEXT: XOR_INT T2.Y, PV.W, PS,745; EG-NEXT: XOR_INT T0.Z, PV.Z, PS,746; EG-NEXT: XOR_INT T1.W, PV.X, PV.Y,747; EG-NEXT: XOR_INT * T3.W, T3.Y, PV.Y,748; EG-NEXT: SUB_INT T3.Y, PS, T1.Y,749; EG-NEXT: SUBB_UINT T1.Z, PV.W, T1.Y,750; EG-NEXT: SUB_INT T3.W, PV.Z, T2.W,751; EG-NEXT: SUBB_UINT * T4.W, PV.Y, T2.W,752; EG-NEXT: SUB_INT T4.Y, PV.W, PS,753; EG-NEXT: SUB_INT T0.Z, PV.Y, PV.Z,754; EG-NEXT: BFE_UINT T3.W, KC0[3].Y, literal.x, T0.W,755; EG-NEXT: AND_INT * T4.W, KC0[3].Y, literal.y,756; EG-NEXT: 23(3.222986e-44), 8388607(1.175494e-38)757; EG-NEXT: SETGT_INT T0.X, 0.0, T0.X,758; EG-NEXT: ADD_INT T3.Y, PV.W, literal.x,759; EG-NEXT: OR_INT T1.Z, PS, literal.y,760; EG-NEXT: BFE_UINT T0.W, KC0[3].W, literal.z, T0.W,761; EG-NEXT: ADD_INT * T4.W, PV.W, literal.w,762; EG-NEXT: -127(nan), 8388608(1.175494e-38)763; EG-NEXT: 23(3.222986e-44), -150(nan)764; EG-NEXT: AND_INT T1.X, KC0[3].W, literal.x,765; EG-NEXT: ADD_INT T5.Y, PV.W, literal.y,766; EG-NEXT: SUB_INT T2.Z, literal.z, T3.W,767; EG-NEXT: NOT_INT T3.W, PS,768; EG-NEXT: LSHR * T5.W, PV.Z, 1,769; EG-NEXT: 8388607(1.175494e-38), -150(nan)770; EG-NEXT: 150(2.101948e-43), 0(0.000000e+00)771; EG-NEXT: BIT_ALIGN_INT T2.X, 0.0, PS, PV.W,772; EG-NEXT: AND_INT T6.Y, PV.Z, literal.x,773; EG-NEXT: AND_INT T3.Z, PV.Y, literal.y,774; EG-NEXT: OR_INT T3.W, PV.X, literal.z,775; EG-NEXT: AND_INT * T5.W, T4.W, literal.y,776; EG-NEXT: 32(4.484155e-44), 31(4.344025e-44)777; EG-NEXT: 8388608(1.175494e-38), 0(0.000000e+00)778; EG-NEXT: BIT_ALIGN_INT T1.X, 0.0, T1.Z, T2.Z,779; EG-NEXT: LSHL T7.Y, T1.Z, PS,780; EG-NEXT: AND_INT T1.Z, T4.W, literal.x,781; EG-NEXT: LSHL T4.W, PV.W, PV.Z,782; EG-NEXT: AND_INT * T5.W, T5.Y, literal.x,783; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)784; EG-NEXT: CNDE_INT T3.X, PS, PV.W, 0.0,785; EG-NEXT: CNDE_INT T8.Y, PV.Z, PV.Y, 0.0,786; EG-NEXT: CNDE_INT * T2.Z, T6.Y, PV.X, 0.0,787; EG-NEXT: ALU clause starting at 106:788; EG-NEXT: CNDE_INT T6.W, T1.Z, T2.X, T7.Y, BS:VEC_021/SCL_122789; EG-NEXT: SETGT_INT * T7.W, T3.Y, literal.x,790; EG-NEXT: 23(3.222986e-44), 0(0.000000e+00)791; EG-NEXT: CNDE_INT T1.X, PS, 0.0, PV.W,792; EG-NEXT: CNDE_INT T6.Y, PS, T2.Z, T8.Y,793; EG-NEXT: SUB_INT T1.Z, literal.x, T0.W,794; EG-NEXT: NOT_INT T6.W, T5.Y,795; EG-NEXT: LSHR * T7.W, T3.W, 1,796; EG-NEXT: 150(2.101948e-43), 0(0.000000e+00)797; EG-NEXT: ASHR T2.X, KC0[3].Y, literal.x,798; EG-NEXT: ADD_INT T5.Y, T0.W, literal.y,799; EG-NEXT: BIT_ALIGN_INT T2.Z, 0.0, PS, PV.W,800; EG-NEXT: BIT_ALIGN_INT T0.W, 0.0, T3.W, PV.Z,801; EG-NEXT: AND_INT * T3.W, PV.Z, literal.z,802; EG-NEXT: 31(4.344025e-44), -127(nan)803; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)804; EG-NEXT: CNDE_INT T4.X, PS, PV.W, 0.0,805; EG-NEXT: CNDE_INT T7.Y, T5.W, PV.Z, T4.W,806; EG-NEXT: SETGT_INT T1.Z, PV.Y, literal.x,807; EG-NEXT: XOR_INT T0.W, T6.Y, PV.X,808; EG-NEXT: XOR_INT * T3.W, T1.X, PV.X,809; EG-NEXT: 23(3.222986e-44), 0(0.000000e+00)810; EG-NEXT: SUB_INT T1.X, PS, T2.X,811; EG-NEXT: SUBB_UINT T6.Y, PV.W, T2.X,812; EG-NEXT: CNDE_INT T2.Z, PV.Z, 0.0, PV.Y,813; EG-NEXT: CNDE_INT T3.W, PV.Z, PV.X, T3.X,814; EG-NEXT: ASHR * T4.W, KC0[3].W, literal.x,815; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)816; EG-NEXT: XOR_INT T3.X, PV.W, PS,817; EG-NEXT: XOR_INT T7.Y, PV.Z, PS,818; EG-NEXT: SUB_INT T1.Z, PV.X, PV.Y,819; EG-NEXT: SETGT_INT T3.W, 0.0, T3.Y,820; EG-NEXT: CNDE_INT * T6.W, T0.X, T0.Z, 0.0,821; EG-NEXT: SETGT_INT T1.X, 0.0, T0.Y,822; EG-NEXT: CNDE_INT T6.Y, PV.W, PV.Z, 0.0,823; EG-NEXT: SUB_INT T0.Z, T1.W, T1.Y, BS:VEC_021/SCL_122824; EG-NEXT: SUB_INT T1.W, PV.Y, T4.W,825; EG-NEXT: SUBB_UINT * T5.W, PV.X, T4.W,826; EG-NEXT: SUB_INT T4.X, PV.W, PS,827; EG-NEXT: SETGT_INT T0.Y, 0.0, T5.Y, BS:VEC_021/SCL_122828; EG-NEXT: CNDE_INT T6.Z, T0.X, PV.Z, 0.0,829; EG-NEXT: SUB_INT T0.W, T0.W, T2.X,830; EG-NEXT: CNDE_INT * T1.W, PV.X, T4.Y, 0.0,831; EG-NEXT: CNDE_INT T6.X, T3.W, PV.W, 0.0,832; EG-NEXT: CNDE_INT T1.Y, PV.Y, PV.X, 0.0,833; EG-NEXT: SUB_INT T0.W, T2.Y, T2.W,834; EG-NEXT: LSHR * T0.X, KC0[2].Y, literal.x,835; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)836; EG-NEXT: CNDE_INT T1.Z, T1.X, PV.W, 0.0,837; EG-NEXT: SUB_INT * T0.W, T3.X, T4.W, BS:VEC_120/SCL_212838; EG-NEXT: CNDE_INT T1.X, T0.Y, PV.W, 0.0,839; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x,840; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)841; EG-NEXT: LSHR * T2.X, PV.W, literal.x,842; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)843 %conv = fptoui <4 x float> %x to <4 x i64>844 store <4 x i64> %conv, ptr addrspace(1) %out845 ret void846}847 848define amdgpu_kernel void @fp_to_uint_f32_to_i1(ptr addrspace(1) %out, float %in) #0 {849; SI-LABEL: fp_to_uint_f32_to_i1:850; SI: ; %bb.0:851; SI-NEXT: s_load_dword s6, s[4:5], 0xb852; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9853; SI-NEXT: s_mov_b32 s3, 0xf000854; SI-NEXT: s_mov_b32 s2, -1855; SI-NEXT: s_waitcnt lgkmcnt(0)856; SI-NEXT: v_cmp_eq_f32_e64 s[4:5], 1.0, s6857; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]858; SI-NEXT: buffer_store_byte v0, off, s[0:3], 0859; SI-NEXT: s_endpgm860;861; VI-LABEL: fp_to_uint_f32_to_i1:862; VI: ; %bb.0:863; VI-NEXT: s_load_dword s6, s[4:5], 0x2c864; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24865; VI-NEXT: s_mov_b32 s3, 0xf000866; VI-NEXT: s_mov_b32 s2, -1867; VI-NEXT: s_waitcnt lgkmcnt(0)868; VI-NEXT: v_cmp_eq_f32_e64 s[4:5], 1.0, s6869; VI-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]870; VI-NEXT: buffer_store_byte v0, off, s[0:3], 0871; VI-NEXT: s_endpgm872;873; GFX11-SDAG-LABEL: fp_to_uint_f32_to_i1:874; GFX11-SDAG: ; %bb.0:875; GFX11-SDAG-NEXT: s_clause 0x1876; GFX11-SDAG-NEXT: s_load_b32 s2, s[4:5], 0x2c877; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24878; GFX11-SDAG-NEXT: v_mov_b32_e32 v0, 0879; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)880; GFX11-SDAG-NEXT: v_cmp_eq_f32_e64 s2, 1.0, s2881; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)882; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 1, s2883; GFX11-SDAG-NEXT: global_store_b8 v0, v1, s[0:1]884; GFX11-SDAG-NEXT: s_endpgm885;886; GFX11-GISEL-LABEL: fp_to_uint_f32_to_i1:887; GFX11-GISEL: ; %bb.0:888; GFX11-GISEL-NEXT: s_clause 0x1889; GFX11-GISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c890; GFX11-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24891; GFX11-GISEL-NEXT: v_mov_b32_e32 v1, 0892; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)893; GFX11-GISEL-NEXT: v_cvt_u32_f32_e32 v0, s2894; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)895; GFX11-GISEL-NEXT: v_and_b32_e32 v0, 1, v0896; GFX11-GISEL-NEXT: global_store_b8 v1, v0, s[0:1]897; GFX11-GISEL-NEXT: s_endpgm898;899; EG-LABEL: fp_to_uint_f32_to_i1:900; EG: ; %bb.0:901; EG-NEXT: ALU 12, @4, KC0[CB0:0-32], KC1[]902; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X903; EG-NEXT: CF_END904; EG-NEXT: PAD905; EG-NEXT: ALU clause starting at 4:906; EG-NEXT: AND_INT T0.W, KC0[2].Y, literal.x,907; EG-NEXT: SETE_DX10 * T1.W, KC0[2].Z, 1.0,908; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)909; EG-NEXT: AND_INT T1.W, PS, 1,910; EG-NEXT: LSHL * T0.W, PV.W, literal.x,911; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)912; EG-NEXT: LSHL T0.X, PV.W, PS,913; EG-NEXT: LSHL * T0.W, literal.x, PS,914; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00)915; EG-NEXT: MOV T0.Y, 0.0,916; EG-NEXT: MOV * T0.Z, 0.0,917; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,918; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)919 %conv = fptoui float %in to i1920 store i1 %conv, ptr addrspace(1) %out921 ret void922}923 924define amdgpu_kernel void @fp_to_uint_fabs_f32_to_i1(ptr addrspace(1) %out, float %in) #0 {925; SI-LABEL: fp_to_uint_fabs_f32_to_i1:926; SI: ; %bb.0:927; SI-NEXT: s_load_dword s6, s[4:5], 0xb928; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9929; SI-NEXT: s_mov_b32 s3, 0xf000930; SI-NEXT: s_mov_b32 s2, -1931; SI-NEXT: s_waitcnt lgkmcnt(0)932; SI-NEXT: v_cmp_eq_f32_e64 s[4:5], 1.0, |s6|933; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]934; SI-NEXT: buffer_store_byte v0, off, s[0:3], 0935; SI-NEXT: s_endpgm936;937; VI-LABEL: fp_to_uint_fabs_f32_to_i1:938; VI: ; %bb.0:939; VI-NEXT: s_load_dword s6, s[4:5], 0x2c940; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24941; VI-NEXT: s_mov_b32 s3, 0xf000942; VI-NEXT: s_mov_b32 s2, -1943; VI-NEXT: s_waitcnt lgkmcnt(0)944; VI-NEXT: v_cmp_eq_f32_e64 s[4:5], 1.0, |s6|945; VI-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]946; VI-NEXT: buffer_store_byte v0, off, s[0:3], 0947; VI-NEXT: s_endpgm948;949; GFX11-SDAG-LABEL: fp_to_uint_fabs_f32_to_i1:950; GFX11-SDAG: ; %bb.0:951; GFX11-SDAG-NEXT: s_clause 0x1952; GFX11-SDAG-NEXT: s_load_b32 s2, s[4:5], 0x2c953; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24954; GFX11-SDAG-NEXT: v_mov_b32_e32 v0, 0955; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)956; GFX11-SDAG-NEXT: v_cmp_eq_f32_e64 s2, 1.0, |s2|957; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)958; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 1, s2959; GFX11-SDAG-NEXT: global_store_b8 v0, v1, s[0:1]960; GFX11-SDAG-NEXT: s_endpgm961;962; GFX11-GISEL-LABEL: fp_to_uint_fabs_f32_to_i1:963; GFX11-GISEL: ; %bb.0:964; GFX11-GISEL-NEXT: s_clause 0x1965; GFX11-GISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c966; GFX11-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24967; GFX11-GISEL-NEXT: v_mov_b32_e32 v1, 0968; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)969; GFX11-GISEL-NEXT: v_cvt_u32_f32_e64 v0, |s2|970; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)971; GFX11-GISEL-NEXT: v_and_b32_e32 v0, 1, v0972; GFX11-GISEL-NEXT: global_store_b8 v1, v0, s[0:1]973; GFX11-GISEL-NEXT: s_endpgm974;975; EG-LABEL: fp_to_uint_fabs_f32_to_i1:976; EG: ; %bb.0:977; EG-NEXT: ALU 12, @4, KC0[CB0:0-32], KC1[]978; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X979; EG-NEXT: CF_END980; EG-NEXT: PAD981; EG-NEXT: ALU clause starting at 4:982; EG-NEXT: AND_INT T0.W, KC0[2].Y, literal.x,983; EG-NEXT: SETE_DX10 * T1.W, |KC0[2].Z|, 1.0,984; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)985; EG-NEXT: AND_INT T1.W, PS, 1,986; EG-NEXT: LSHL * T0.W, PV.W, literal.x,987; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)988; EG-NEXT: LSHL T0.X, PV.W, PS,989; EG-NEXT: LSHL * T0.W, literal.x, PS,990; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00)991; EG-NEXT: MOV T0.Y, 0.0,992; EG-NEXT: MOV * T0.Z, 0.0,993; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,994; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)995 %in.fabs = call float @llvm.fabs.f32(float %in)996 %conv = fptoui float %in.fabs to i1997 store i1 %conv, ptr addrspace(1) %out998 ret void999}1000 1001define amdgpu_kernel void @fp_to_uint_f32_to_i16(ptr addrspace(1) %out, float %in) #0 {1002; SI-LABEL: fp_to_uint_f32_to_i16:1003; SI: ; %bb.0:1004; SI-NEXT: s_load_dword s6, s[4:5], 0xb1005; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x91006; SI-NEXT: s_mov_b32 s3, 0xf0001007; SI-NEXT: s_mov_b32 s2, -11008; SI-NEXT: s_waitcnt lgkmcnt(0)1009; SI-NEXT: v_cvt_u32_f32_e32 v0, s61010; SI-NEXT: buffer_store_short v0, off, s[0:3], 01011; SI-NEXT: s_endpgm1012;1013; VI-LABEL: fp_to_uint_f32_to_i16:1014; VI: ; %bb.0:1015; VI-NEXT: s_load_dword s2, s[4:5], 0x2c1016; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x241017; VI-NEXT: s_mov_b32 s3, 0xf0001018; VI-NEXT: s_waitcnt lgkmcnt(0)1019; VI-NEXT: v_cvt_u32_f32_e32 v0, s21020; VI-NEXT: s_mov_b32 s2, -11021; VI-NEXT: buffer_store_short v0, off, s[0:3], 01022; VI-NEXT: s_endpgm1023;1024; GFX11-SDAG-LABEL: fp_to_uint_f32_to_i16:1025; GFX11-SDAG: ; %bb.0:1026; GFX11-SDAG-NEXT: s_clause 0x11027; GFX11-SDAG-NEXT: s_load_b32 s2, s[4:5], 0x2c1028; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x241029; GFX11-SDAG-NEXT: v_mov_b32_e32 v0, 01030; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)1031; GFX11-SDAG-NEXT: v_cvt_u32_f32_e32 v1, s21032; GFX11-SDAG-NEXT: global_store_b16 v0, v1, s[0:1]1033; GFX11-SDAG-NEXT: s_endpgm1034;1035; GFX11-GISEL-LABEL: fp_to_uint_f32_to_i16:1036; GFX11-GISEL: ; %bb.0:1037; GFX11-GISEL-NEXT: s_clause 0x11038; GFX11-GISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c1039; GFX11-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x241040; GFX11-GISEL-NEXT: v_mov_b32_e32 v1, 01041; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)1042; GFX11-GISEL-NEXT: v_cvt_u32_f32_e32 v0, s21043; GFX11-GISEL-NEXT: global_store_b16 v1, v0, s[0:1]1044; GFX11-GISEL-NEXT: s_endpgm1045;1046; EG-LABEL: fp_to_uint_f32_to_i16:1047; EG: ; %bb.0:1048; EG-NEXT: ALU 12, @4, KC0[CB0:0-32], KC1[]1049; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X1050; EG-NEXT: CF_END1051; EG-NEXT: PAD1052; EG-NEXT: ALU clause starting at 4:1053; EG-NEXT: TRUNC T0.W, KC0[2].Z,1054; EG-NEXT: AND_INT * T1.W, KC0[2].Y, literal.x,1055; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)1056; EG-NEXT: LSHL T1.W, PS, literal.x,1057; EG-NEXT: FLT_TO_UINT * T0.X, PV.W,1058; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)1059; EG-NEXT: LSHL T0.X, PS, PV.W,1060; EG-NEXT: LSHL * T0.W, literal.x, PV.W,1061; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)1062; EG-NEXT: MOV T0.Y, 0.0,1063; EG-NEXT: MOV * T0.Z, 0.0,1064; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,1065; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1066 %uint = fptoui float %in to i161067 store i16 %uint, ptr addrspace(1) %out1068 ret void1069}1070 1071define amdgpu_kernel void @fp_to_uint_v2f32_to_v2i16(ptr addrspace(1) %out, <2 x float> %in) {1072; SI-LABEL: fp_to_uint_v2f32_to_v2i16:1073; SI: ; %bb.0:1074; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91075; SI-NEXT: s_waitcnt lgkmcnt(0)1076; SI-NEXT: s_mov_b64 s[4:5], s[2:3]1077; SI-NEXT: s_mov_b32 s3, 0xf0001078; SI-NEXT: s_mov_b32 s2, -11079; SI-NEXT: v_cvt_u32_f32_e32 v0, s51080; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v01081; SI-NEXT: v_cvt_u32_f32_e32 v1, s41082; SI-NEXT: v_or_b32_e32 v0, v1, v01083; SI-NEXT: buffer_store_dword v0, off, s[0:3], 01084; SI-NEXT: s_endpgm1085;1086; VI-LABEL: fp_to_uint_v2f32_to_v2i16:1087; VI: ; %bb.0:1088; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241089; VI-NEXT: s_waitcnt lgkmcnt(0)1090; VI-NEXT: v_mov_b32_e32 v0, s31091; VI-NEXT: v_cvt_u32_f32_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD1092; VI-NEXT: v_cvt_u32_f32_e32 v1, s21093; VI-NEXT: s_mov_b32 s3, 0xf0001094; VI-NEXT: s_mov_b32 s2, -11095; VI-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD1096; VI-NEXT: buffer_store_dword v0, off, s[0:3], 01097; VI-NEXT: s_endpgm1098;1099; GFX11-SDAG-LABEL: fp_to_uint_v2f32_to_v2i16:1100; GFX11-SDAG: ; %bb.0:1101; GFX11-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x241102; GFX11-SDAG-NEXT: v_mov_b32_e32 v1, 01103; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)1104; GFX11-SDAG-NEXT: v_cvt_u32_f32_e32 v0, s31105; GFX11-SDAG-NEXT: v_cvt_u32_f32_e32 v2, s21106; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2)1107; GFX11-SDAG-NEXT: v_mov_b16_e32 v2.h, v0.l1108; GFX11-SDAG-NEXT: global_store_b32 v1, v2, s[0:1]1109; GFX11-SDAG-NEXT: s_endpgm1110;1111; GFX11-GISEL-LABEL: fp_to_uint_v2f32_to_v2i16:1112; GFX11-GISEL: ; %bb.0:1113; GFX11-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x241114; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)1115; GFX11-GISEL-NEXT: v_cvt_u32_f32_e32 v0, s31116; GFX11-GISEL-NEXT: v_cvt_u32_f32_e32 v1, s21117; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)1118; GFX11-GISEL-NEXT: v_mov_b16_e32 v1.h, v0.l1119; GFX11-GISEL-NEXT: v_mov_b32_e32 v0, 01120; GFX11-GISEL-NEXT: global_store_b32 v0, v1, s[0:1]1121; GFX11-GISEL-NEXT: s_endpgm1122;1123; EG-LABEL: fp_to_uint_v2f32_to_v2i16:1124; EG: ; %bb.0:1125; EG-NEXT: ALU 8, @4, KC0[CB0:0-32], KC1[]1126; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T4.X, T5.X, 11127; EG-NEXT: CF_END1128; EG-NEXT: PAD1129; EG-NEXT: ALU clause starting at 4:1130; EG-NEXT: TRUNC T0.W, KC0[3].X,1131; EG-NEXT: TRUNC * T1.W, KC0[2].W,1132; EG-NEXT: FLT_TO_UINT * T0.Y, PV.W,1133; EG-NEXT: LSHL T0.W, PS, literal.x,1134; EG-NEXT: FLT_TO_UINT * T0.Y, T1.W,1135; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)1136; EG-NEXT: OR_INT T4.X, PS, PV.W,1137; EG-NEXT: LSHR * T5.X, KC0[2].Y, literal.x,1138; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1139 %uint = fptoui <2 x float> %in to <2 x i16>1140 store <2 x i16> %uint, ptr addrspace(1) %out1141 ret void1142}1143 1144define amdgpu_kernel void @fp_to_uint_f32_to_v2i16(ptr addrspace(1) %out, float %in0, float %in1) {1145; SI-LABEL: fp_to_uint_f32_to_v2i16:1146; SI: ; %bb.0:1147; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91148; SI-NEXT: s_waitcnt lgkmcnt(0)1149; SI-NEXT: s_mov_b64 s[4:5], s[2:3]1150; SI-NEXT: s_mov_b32 s3, 0xf0001151; SI-NEXT: s_mov_b32 s2, -11152; SI-NEXT: v_cvt_u32_f32_e32 v0, s41153; SI-NEXT: v_cvt_u32_f32_e32 v1, s51154; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v11155; SI-NEXT: v_or_b32_e32 v0, v0, v11156; SI-NEXT: buffer_store_dword v0, off, s[0:3], 01157; SI-NEXT: s_endpgm1158;1159; VI-LABEL: fp_to_uint_f32_to_v2i16:1160; VI: ; %bb.0:1161; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241162; VI-NEXT: s_waitcnt lgkmcnt(0)1163; VI-NEXT: v_mov_b32_e32 v1, s31164; VI-NEXT: v_cvt_u32_f32_e32 v0, s21165; VI-NEXT: v_cvt_u32_f32_sdwa v1, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD1166; VI-NEXT: s_mov_b32 s3, 0xf0001167; VI-NEXT: s_mov_b32 s2, -11168; VI-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD1169; VI-NEXT: buffer_store_dword v0, off, s[0:3], 01170; VI-NEXT: s_endpgm1171;1172; GFX11-SDAG-LABEL: fp_to_uint_f32_to_v2i16:1173; GFX11-SDAG: ; %bb.0:1174; GFX11-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x241175; GFX11-SDAG-NEXT: v_mov_b32_e32 v1, 01176; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)1177; GFX11-SDAG-NEXT: v_cvt_u32_f32_e32 v0, s31178; GFX11-SDAG-NEXT: v_cvt_u32_f32_e32 v2, s21179; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2)1180; GFX11-SDAG-NEXT: v_mov_b16_e32 v2.h, v0.l1181; GFX11-SDAG-NEXT: global_store_b32 v1, v2, s[0:1]1182; GFX11-SDAG-NEXT: s_endpgm1183;1184; GFX11-GISEL-LABEL: fp_to_uint_f32_to_v2i16:1185; GFX11-GISEL: ; %bb.0:1186; GFX11-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x241187; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)1188; GFX11-GISEL-NEXT: v_cvt_u32_f32_e32 v0, s31189; GFX11-GISEL-NEXT: v_cvt_u32_f32_e32 v1, s21190; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)1191; GFX11-GISEL-NEXT: v_mov_b16_e32 v1.h, v0.l1192; GFX11-GISEL-NEXT: v_mov_b32_e32 v0, 01193; GFX11-GISEL-NEXT: global_store_b32 v0, v1, s[0:1]1194; GFX11-GISEL-NEXT: s_endpgm1195;1196; EG-LABEL: fp_to_uint_f32_to_v2i16:1197; EG: ; %bb.0:1198; EG-NEXT: ALU 8, @4, KC0[CB0:0-32], KC1[]1199; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T4.X, T5.X, 11200; EG-NEXT: CF_END1201; EG-NEXT: PAD1202; EG-NEXT: ALU clause starting at 4:1203; EG-NEXT: TRUNC T0.W, KC0[2].W,1204; EG-NEXT: TRUNC * T1.W, KC0[2].Z,1205; EG-NEXT: FLT_TO_UINT * T0.Y, PV.W,1206; EG-NEXT: LSHL T0.W, PS, literal.x,1207; EG-NEXT: FLT_TO_UINT * T0.Y, T1.W,1208; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)1209; EG-NEXT: OR_INT T4.X, PV.W, PS,1210; EG-NEXT: LSHR * T5.X, KC0[2].Y, literal.x,1211; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1212 %uint0 = fptoui float %in0 to i161213 %uint1 = fptoui float %in1 to i161214 %res0 = insertelement <2 x i16> poison, i16 %uint0, i32 01215 %res1 = insertelement <2 x i16> %res0, i16 %uint1, i32 11216 store <2 x i16> %res1, ptr addrspace(1) %out1217 ret void1218}1219 1220attributes #0 = { nounwind }1221attributes #1 = { nounwind readnone }1222;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:1223; GFX11: {{.*}}1224