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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=amdgcn -mcpu=gfx950 -global-isel=0 < %s | FileCheck -check-prefixes=GFX950,GFX950-SDAG %s3; RUN: llc -mtriple=amdgcn -mcpu=gfx950 -global-isel=1 < %s | FileCheck -check-prefixes=GFX950,GFX950-GISEL %s4 5define <2 x half> @v_test_cvt_v2f32_v2f16(<2 x float> %src) {6; GFX950-LABEL: v_test_cvt_v2f32_v2f16:7; GFX950: ; %bb.0:8; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)9; GFX950-NEXT: v_cvt_pk_f16_f32 v0, v0, v110; GFX950-NEXT: s_setpc_b64 s[30:31]11 %res = fptrunc <2 x float> %src to <2 x half>12 ret <2 x half> %res13}14 15define <3 x half> @v_test_cvt_v3f32_v3f16(<3 x float> %src) {16; GFX950-LABEL: v_test_cvt_v3f32_v3f16:17; GFX950: ; %bb.0:18; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)19; GFX950-NEXT: v_cvt_f16_f32_e32 v2, v220; GFX950-NEXT: v_cvt_pk_f16_f32 v0, v0, v121; GFX950-NEXT: v_mov_b32_e32 v1, v222; GFX950-NEXT: s_setpc_b64 s[30:31]23 %res = fptrunc <3 x float> %src to <3 x half>24 ret <3 x half> %res25}26 27define <4 x half> @v_test_cvt_v4f32_v4f16(<4 x float> %src) {28; GFX950-LABEL: v_test_cvt_v4f32_v4f16:29; GFX950: ; %bb.0:30; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)31; GFX950-NEXT: v_cvt_pk_f16_f32 v0, v0, v132; GFX950-NEXT: v_cvt_pk_f16_f32 v1, v2, v333; GFX950-NEXT: s_setpc_b64 s[30:31]34 %res = fptrunc <4 x float> %src to <4 x half>35 ret <4 x half> %res36}37 38define <8 x half> @v_test_cvt_v8f32_v2f16(<8 x float> %src) {39; GFX950-LABEL: v_test_cvt_v8f32_v2f16:40; GFX950: ; %bb.0:41; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)42; GFX950-NEXT: v_cvt_pk_f16_f32 v0, v0, v143; GFX950-NEXT: v_cvt_pk_f16_f32 v1, v2, v344; GFX950-NEXT: v_cvt_pk_f16_f32 v2, v4, v545; GFX950-NEXT: v_cvt_pk_f16_f32 v3, v6, v746; GFX950-NEXT: s_setpc_b64 s[30:31]47 %res = fptrunc <8 x float> %src to <8 x half>48 ret <8 x half> %res49}50 51define <16 x half> @v_test_cvt_v16f32_v16f16(<16 x float> %src) {52; GFX950-LABEL: v_test_cvt_v16f32_v16f16:53; GFX950: ; %bb.0:54; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)55; GFX950-NEXT: v_cvt_pk_f16_f32 v0, v0, v156; GFX950-NEXT: v_cvt_pk_f16_f32 v1, v2, v357; GFX950-NEXT: v_cvt_pk_f16_f32 v2, v4, v558; GFX950-NEXT: v_cvt_pk_f16_f32 v3, v6, v759; GFX950-NEXT: v_cvt_pk_f16_f32 v4, v8, v960; GFX950-NEXT: v_cvt_pk_f16_f32 v5, v10, v1161; GFX950-NEXT: v_cvt_pk_f16_f32 v6, v12, v1362; GFX950-NEXT: v_cvt_pk_f16_f32 v7, v14, v1563; GFX950-NEXT: s_setpc_b64 s[30:31]64 %res = fptrunc <16 x float> %src to <16 x half>65 ret <16 x half> %res66}67 68define half @fptrunc_v2f32_v2f16_extract_uses(<2 x float> %src) {69; GFX950-LABEL: fptrunc_v2f32_v2f16_extract_uses:70; GFX950: ; %bb.0:71; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)72; GFX950-NEXT: v_cvt_pk_f16_f32 v0, v0, v173; GFX950-NEXT: v_add_f16_sdwa v0, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_174; GFX950-NEXT: s_setpc_b64 s[30:31]75 %vec_half = fptrunc <2 x float> %src to <2 x half>76 %f0 = extractelement <2 x half> %vec_half, i64 077 %f1 = extractelement <2 x half> %vec_half, i64 178 %rslt = fadd half %f0, %f179 ret half %rslt80}81 82define half @fptrunc_v3f32_v3f16_extract_uses(<3 x float> %vec_float) {83; GFX950-SDAG-LABEL: fptrunc_v3f32_v3f16_extract_uses:84; GFX950-SDAG: ; %bb.0:85; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)86; GFX950-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v187; GFX950-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v088; GFX950-SDAG-NEXT: v_cvt_f16_f32_e32 v2, v289; GFX950-SDAG-NEXT: v_add_f16_e32 v0, v0, v190; GFX950-SDAG-NEXT: v_add_f16_e32 v0, v2, v091; GFX950-SDAG-NEXT: s_setpc_b64 s[30:31]92;93; GFX950-GISEL-LABEL: fptrunc_v3f32_v3f16_extract_uses:94; GFX950-GISEL: ; %bb.0:95; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)96; GFX950-GISEL-NEXT: v_cvt_f16_f32_e32 v2, v297; GFX950-GISEL-NEXT: v_cvt_pk_f16_f32 v0, v0, v198; GFX950-GISEL-NEXT: v_add_f16_sdwa v0, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_199; GFX950-GISEL-NEXT: v_add_f16_e32 v0, v2, v0100; GFX950-GISEL-NEXT: s_setpc_b64 s[30:31]101 %vec_half = fptrunc <3 x float> %vec_float to <3 x half>102 %f0 = extractelement <3 x half> %vec_half, i64 0103 %f1 = extractelement <3 x half> %vec_half, i64 1104 %f2 = extractelement <3 x half> %vec_half, i64 2105 %sum0 = fadd half %f0, %f1106 %rslt = fadd half %f2, %sum0107 ret half %rslt108}109 110define half @fptrunc_v4f32_v4f16_extract_uses(<4 x float> %vec_float) {111; GFX950-SDAG-LABEL: fptrunc_v4f32_v4f16_extract_uses:112; GFX950-SDAG: ; %bb.0:113; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)114; GFX950-SDAG-NEXT: v_cvt_pk_f16_f32 v2, v2, v3115; GFX950-SDAG-NEXT: v_cvt_pk_f16_f32 v0, v0, v1116; GFX950-SDAG-NEXT: v_add_f16_sdwa v0, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1117; GFX950-SDAG-NEXT: v_add_f16_sdwa v1, v2, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1118; GFX950-SDAG-NEXT: v_add_f16_e32 v0, v0, v1119; GFX950-SDAG-NEXT: s_setpc_b64 s[30:31]120;121; GFX950-GISEL-LABEL: fptrunc_v4f32_v4f16_extract_uses:122; GFX950-GISEL: ; %bb.0:123; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)124; GFX950-GISEL-NEXT: v_cvt_pk_f16_f32 v0, v0, v1125; GFX950-GISEL-NEXT: v_cvt_pk_f16_f32 v1, v2, v3126; GFX950-GISEL-NEXT: v_add_f16_sdwa v0, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1127; GFX950-GISEL-NEXT: v_add_f16_sdwa v1, v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1128; GFX950-GISEL-NEXT: v_add_f16_e32 v0, v0, v1129; GFX950-GISEL-NEXT: s_setpc_b64 s[30:31]130 %vec_half = fptrunc <4 x float> %vec_float to <4 x half>131 %f0 = extractelement <4 x half> %vec_half, i64 0132 %f1 = extractelement <4 x half> %vec_half, i64 1133 %f2 = extractelement <4 x half> %vec_half, i64 2134 %f3 = extractelement <4 x half> %vec_half, i64 3135 %sum0 = fadd half %f0, %f1136 %sum1 = fadd half %f2, %f3137 %rslt = fadd half %sum0, %sum1138 ret half %rslt139}140 141define half @fptrunc_v8f32_v8f16_extract_uses(<8 x float> %vec_float) {142; GFX950-SDAG-LABEL: fptrunc_v8f32_v8f16_extract_uses:143; GFX950-SDAG: ; %bb.0:144; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)145; GFX950-SDAG-NEXT: v_cvt_pk_f16_f32 v6, v6, v7146; GFX950-SDAG-NEXT: v_cvt_pk_f16_f32 v4, v4, v5147; GFX950-SDAG-NEXT: v_cvt_pk_f16_f32 v2, v2, v3148; GFX950-SDAG-NEXT: v_cvt_pk_f16_f32 v0, v0, v1149; GFX950-SDAG-NEXT: v_add_f16_sdwa v0, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1150; GFX950-SDAG-NEXT: v_add_f16_sdwa v1, v2, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1151; GFX950-SDAG-NEXT: v_add_f16_sdwa v2, v4, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1152; GFX950-SDAG-NEXT: v_add_f16_sdwa v3, v6, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1153; GFX950-SDAG-NEXT: v_add_f16_e32 v0, v0, v1154; GFX950-SDAG-NEXT: v_add_f16_e32 v1, v2, v3155; GFX950-SDAG-NEXT: v_add_f16_e32 v0, v0, v1156; GFX950-SDAG-NEXT: s_setpc_b64 s[30:31]157;158; GFX950-GISEL-LABEL: fptrunc_v8f32_v8f16_extract_uses:159; GFX950-GISEL: ; %bb.0:160; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)161; GFX950-GISEL-NEXT: v_cvt_pk_f16_f32 v0, v0, v1162; GFX950-GISEL-NEXT: v_cvt_pk_f16_f32 v1, v2, v3163; GFX950-GISEL-NEXT: v_cvt_pk_f16_f32 v2, v4, v5164; GFX950-GISEL-NEXT: v_cvt_pk_f16_f32 v3, v6, v7165; GFX950-GISEL-NEXT: v_add_f16_sdwa v0, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1166; GFX950-GISEL-NEXT: v_add_f16_sdwa v1, v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1167; GFX950-GISEL-NEXT: v_add_f16_sdwa v2, v2, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1168; GFX950-GISEL-NEXT: v_add_f16_sdwa v3, v3, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1169; GFX950-GISEL-NEXT: v_add_f16_e32 v0, v0, v1170; GFX950-GISEL-NEXT: v_add_f16_e32 v1, v2, v3171; GFX950-GISEL-NEXT: v_add_f16_e32 v0, v0, v1172; GFX950-GISEL-NEXT: s_setpc_b64 s[30:31]173 %vec_half = fptrunc <8 x float> %vec_float to <8 x half>174 %f0 = extractelement <8 x half> %vec_half, i64 0175 %f1 = extractelement <8 x half> %vec_half, i64 1176 %f2 = extractelement <8 x half> %vec_half, i64 2177 %f3 = extractelement <8 x half> %vec_half, i64 3178 %f4 = extractelement <8 x half> %vec_half, i64 4179 %f5 = extractelement <8 x half> %vec_half, i64 5180 %f6 = extractelement <8 x half> %vec_half, i64 6181 %f7 = extractelement <8 x half> %vec_half, i64 7182 %sum0 = fadd half %f0, %f1183 %sum1 = fadd half %f2, %f3184 %sum2 = fadd half %f4, %f5185 %sum3 = fadd half %f6, %f7186 %sum4 = fadd half %sum0, %sum1187 %sum5 = fadd half %sum2, %sum3188 %rslt = fadd half %sum4, %sum5189 ret half %rslt190}191 192define half @fptrunc_v16f32_v16f16_extract_uses(<16 x float> %vec_float) {193; GFX950-SDAG-LABEL: fptrunc_v16f32_v16f16_extract_uses:194; GFX950-SDAG: ; %bb.0:195; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)196; GFX950-SDAG-NEXT: v_cvt_pk_f16_f32 v14, v14, v15197; GFX950-SDAG-NEXT: v_cvt_pk_f16_f32 v12, v12, v13198; GFX950-SDAG-NEXT: v_cvt_pk_f16_f32 v10, v10, v11199; GFX950-SDAG-NEXT: v_cvt_pk_f16_f32 v8, v8, v9200; GFX950-SDAG-NEXT: v_cvt_pk_f16_f32 v6, v6, v7201; GFX950-SDAG-NEXT: v_cvt_pk_f16_f32 v4, v4, v5202; GFX950-SDAG-NEXT: v_cvt_pk_f16_f32 v2, v2, v3203; GFX950-SDAG-NEXT: v_cvt_pk_f16_f32 v0, v0, v1204; GFX950-SDAG-NEXT: v_add_f16_sdwa v0, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1205; GFX950-SDAG-NEXT: v_add_f16_sdwa v1, v2, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1206; GFX950-SDAG-NEXT: v_add_f16_sdwa v2, v4, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1207; GFX950-SDAG-NEXT: v_add_f16_sdwa v3, v6, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1208; GFX950-SDAG-NEXT: v_add_f16_sdwa v4, v8, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1209; GFX950-SDAG-NEXT: v_add_f16_sdwa v5, v10, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1210; GFX950-SDAG-NEXT: v_add_f16_sdwa v6, v12, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1211; GFX950-SDAG-NEXT: v_add_f16_sdwa v7, v14, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1212; GFX950-SDAG-NEXT: v_add_f16_e32 v0, v0, v1213; GFX950-SDAG-NEXT: v_add_f16_e32 v1, v2, v3214; GFX950-SDAG-NEXT: v_add_f16_e32 v2, v4, v5215; GFX950-SDAG-NEXT: v_add_f16_e32 v3, v6, v7216; GFX950-SDAG-NEXT: v_add_f16_e32 v0, v0, v1217; GFX950-SDAG-NEXT: v_add_f16_e32 v1, v2, v3218; GFX950-SDAG-NEXT: v_add_f16_e32 v0, v0, v1219; GFX950-SDAG-NEXT: s_setpc_b64 s[30:31]220;221; GFX950-GISEL-LABEL: fptrunc_v16f32_v16f16_extract_uses:222; GFX950-GISEL: ; %bb.0:223; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)224; GFX950-GISEL-NEXT: v_cvt_pk_f16_f32 v0, v0, v1225; GFX950-GISEL-NEXT: v_cvt_pk_f16_f32 v1, v2, v3226; GFX950-GISEL-NEXT: v_cvt_pk_f16_f32 v2, v4, v5227; GFX950-GISEL-NEXT: v_cvt_pk_f16_f32 v3, v6, v7228; GFX950-GISEL-NEXT: v_cvt_pk_f16_f32 v4, v8, v9229; GFX950-GISEL-NEXT: v_cvt_pk_f16_f32 v5, v10, v11230; GFX950-GISEL-NEXT: v_cvt_pk_f16_f32 v6, v12, v13231; GFX950-GISEL-NEXT: v_cvt_pk_f16_f32 v7, v14, v15232; GFX950-GISEL-NEXT: v_add_f16_sdwa v0, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1233; GFX950-GISEL-NEXT: v_add_f16_sdwa v1, v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1234; GFX950-GISEL-NEXT: v_add_f16_sdwa v2, v2, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1235; GFX950-GISEL-NEXT: v_add_f16_sdwa v3, v3, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1236; GFX950-GISEL-NEXT: v_add_f16_sdwa v4, v4, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1237; GFX950-GISEL-NEXT: v_add_f16_sdwa v5, v5, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1238; GFX950-GISEL-NEXT: v_add_f16_sdwa v6, v6, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1239; GFX950-GISEL-NEXT: v_add_f16_sdwa v7, v7, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1240; GFX950-GISEL-NEXT: v_add_f16_e32 v0, v0, v1241; GFX950-GISEL-NEXT: v_add_f16_e32 v1, v2, v3242; GFX950-GISEL-NEXT: v_add_f16_e32 v2, v4, v5243; GFX950-GISEL-NEXT: v_add_f16_e32 v3, v6, v7244; GFX950-GISEL-NEXT: v_add_f16_e32 v0, v0, v1245; GFX950-GISEL-NEXT: v_add_f16_e32 v1, v2, v3246; GFX950-GISEL-NEXT: v_add_f16_e32 v0, v0, v1247; GFX950-GISEL-NEXT: s_setpc_b64 s[30:31]248 %vec_half = fptrunc <16 x float> %vec_float to <16 x half>249 %f0 = extractelement <16 x half> %vec_half, i64 0250 %f1 = extractelement <16 x half> %vec_half, i64 1251 %f2 = extractelement <16 x half> %vec_half, i64 2252 %f3 = extractelement <16 x half> %vec_half, i64 3253 %f4 = extractelement <16 x half> %vec_half, i64 4254 %f5 = extractelement <16 x half> %vec_half, i64 5255 %f6 = extractelement <16 x half> %vec_half, i64 6256 %f7 = extractelement <16 x half> %vec_half, i64 7257 %f8 = extractelement <16 x half> %vec_half, i64 8258 %f9 = extractelement <16 x half> %vec_half, i64 9259 %f10 = extractelement <16 x half> %vec_half, i64 10260 %f11 = extractelement <16 x half> %vec_half, i64 11261 %f12 = extractelement <16 x half> %vec_half, i64 12262 %f13 = extractelement <16 x half> %vec_half, i64 13263 %f14 = extractelement <16 x half> %vec_half, i64 14264 %f15 = extractelement <16 x half> %vec_half, i64 15265 %sum0 = fadd half %f0, %f1266 %sum1 = fadd half %f2, %f3267 %sum2 = fadd half %f4, %f5268 %sum3 = fadd half %f6, %f7269 %sum4 = fadd half %f8, %f9270 %sum5 = fadd half %f10, %f11271 %sum6 = fadd half %f12, %f13272 %sum7 = fadd half %f14, %f15273 %sum8 = fadd half %sum0, %sum1274 %sum9 = fadd half %sum2, %sum3275 %sum10 = fadd half %sum4, %sum5276 %sum11 = fadd half %sum6, %sum7277 %sum12 = fadd half %sum8, %sum9278 %sum13 = fadd half %sum10, %sum11279 %rslt = fadd half %sum12, %sum13280 ret half %rslt281}282 283define <2 x half> @v_test_cvt_v2f64_v2f16(<2 x double> %src) {284; GFX950-SDAG-LABEL: v_test_cvt_v2f64_v2f16:285; GFX950-SDAG: ; %bb.0:286; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)287; GFX950-SDAG-NEXT: s_movk_i32 s0, 0x1ff288; GFX950-SDAG-NEXT: v_and_or_b32 v0, v1, s0, v0289; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0290; GFX950-SDAG-NEXT: v_lshrrev_b32_e32 v4, 8, v1291; GFX950-SDAG-NEXT: s_movk_i32 s1, 0xffe292; GFX950-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc293; GFX950-SDAG-NEXT: v_bfe_u32 v5, v1, 20, 11294; GFX950-SDAG-NEXT: v_and_or_b32 v0, v4, s1, v0295; GFX950-SDAG-NEXT: v_sub_u32_e32 v6, 0x3f1, v5296; GFX950-SDAG-NEXT: v_or_b32_e32 v4, 0x1000, v0297; GFX950-SDAG-NEXT: v_med3_i32 v6, v6, 0, 13298; GFX950-SDAG-NEXT: v_lshrrev_b32_e32 v7, v6, v4299; GFX950-SDAG-NEXT: v_lshlrev_b32_e32 v6, v6, v7300; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, v6, v4301; GFX950-SDAG-NEXT: v_add_u32_e32 v5, 0xfffffc10, v5302; GFX950-SDAG-NEXT: v_lshl_or_b32 v6, v5, 12, v0303; GFX950-SDAG-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc304; GFX950-SDAG-NEXT: v_or_b32_e32 v4, v7, v4305; GFX950-SDAG-NEXT: v_cmp_gt_i32_e32 vcc, 1, v5306; GFX950-SDAG-NEXT: s_movk_i32 s2, 0x40f307; GFX950-SDAG-NEXT: v_lshrrev_b32_e32 v1, 16, v1308; GFX950-SDAG-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc309; GFX950-SDAG-NEXT: v_and_b32_e32 v6, 7, v4310; GFX950-SDAG-NEXT: v_cmp_lt_i32_e32 vcc, 5, v6311; GFX950-SDAG-NEXT: v_lshrrev_b32_e32 v4, 2, v4312; GFX950-SDAG-NEXT: s_mov_b32 s3, 0x8000313; GFX950-SDAG-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc314; GFX950-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 3, v6315; GFX950-SDAG-NEXT: s_nop 1316; GFX950-SDAG-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc317; GFX950-SDAG-NEXT: v_or_b32_e32 v6, v6, v7318; GFX950-SDAG-NEXT: v_add_u32_e32 v4, v4, v6319; GFX950-SDAG-NEXT: v_mov_b32_e32 v6, 0x7c00320; GFX950-SDAG-NEXT: v_cmp_gt_i32_e32 vcc, 31, v5321; GFX950-SDAG-NEXT: v_mov_b32_e32 v7, 0x7e00322; GFX950-SDAG-NEXT: s_nop 0323; GFX950-SDAG-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc324; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0325; GFX950-SDAG-NEXT: s_nop 1326; GFX950-SDAG-NEXT: v_cndmask_b32_e32 v0, v6, v7, vcc327; GFX950-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, s2, v5328; GFX950-SDAG-NEXT: s_nop 1329; GFX950-SDAG-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc330; GFX950-SDAG-NEXT: v_and_or_b32 v0, v1, s3, v0331; GFX950-SDAG-NEXT: v_and_or_b32 v1, v3, s0, v2332; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1333; GFX950-SDAG-NEXT: v_lshrrev_b32_e32 v2, 8, v3334; GFX950-SDAG-NEXT: v_bfe_u32 v4, v3, 20, 11335; GFX950-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc336; GFX950-SDAG-NEXT: v_and_or_b32 v1, v2, s1, v1337; GFX950-SDAG-NEXT: v_sub_u32_e32 v5, 0x3f1, v4338; GFX950-SDAG-NEXT: v_or_b32_e32 v2, 0x1000, v1339; GFX950-SDAG-NEXT: v_med3_i32 v5, v5, 0, 13340; GFX950-SDAG-NEXT: v_lshrrev_b32_e32 v8, v5, v2341; GFX950-SDAG-NEXT: v_lshlrev_b32_e32 v5, v5, v8342; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, v5, v2343; GFX950-SDAG-NEXT: v_add_u32_e32 v4, 0xfffffc10, v4344; GFX950-SDAG-NEXT: v_lshl_or_b32 v5, v4, 12, v1345; GFX950-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc346; GFX950-SDAG-NEXT: v_or_b32_e32 v2, v8, v2347; GFX950-SDAG-NEXT: v_cmp_gt_i32_e32 vcc, 1, v4348; GFX950-SDAG-NEXT: s_mov_b32 s0, 0x5040100349; GFX950-SDAG-NEXT: s_nop 0350; GFX950-SDAG-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc351; GFX950-SDAG-NEXT: v_and_b32_e32 v5, 7, v2352; GFX950-SDAG-NEXT: v_cmp_lt_i32_e32 vcc, 5, v5353; GFX950-SDAG-NEXT: v_lshrrev_b32_e32 v2, 2, v2354; GFX950-SDAG-NEXT: s_nop 0355; GFX950-SDAG-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc356; GFX950-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 3, v5357; GFX950-SDAG-NEXT: s_nop 1358; GFX950-SDAG-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc359; GFX950-SDAG-NEXT: v_or_b32_e32 v5, v5, v8360; GFX950-SDAG-NEXT: v_add_u32_e32 v2, v2, v5361; GFX950-SDAG-NEXT: v_cmp_gt_i32_e32 vcc, 31, v4362; GFX950-SDAG-NEXT: s_nop 1363; GFX950-SDAG-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc364; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1365; GFX950-SDAG-NEXT: s_nop 1366; GFX950-SDAG-NEXT: v_cndmask_b32_e32 v1, v6, v7, vcc367; GFX950-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, s2, v4368; GFX950-SDAG-NEXT: s_nop 1369; GFX950-SDAG-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc370; GFX950-SDAG-NEXT: v_lshrrev_b32_e32 v2, 16, v3371; GFX950-SDAG-NEXT: v_and_or_b32 v1, v2, s3, v1372; GFX950-SDAG-NEXT: v_perm_b32 v0, v1, v0, s0373; GFX950-SDAG-NEXT: s_setpc_b64 s[30:31]374;375; GFX950-GISEL-LABEL: v_test_cvt_v2f64_v2f16:376; GFX950-GISEL: ; %bb.0:377; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)378; GFX950-GISEL-NEXT: v_mov_b32_e32 v7, 0x1ff379; GFX950-GISEL-NEXT: v_and_or_b32 v0, v1, v7, v0380; GFX950-GISEL-NEXT: v_bfe_u32 v4, v1, 20, 11381; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0382; GFX950-GISEL-NEXT: v_add_u32_e32 v4, 0xfffffc10, v4383; GFX950-GISEL-NEXT: v_lshrrev_b32_e32 v5, 8, v1384; GFX950-GISEL-NEXT: v_mov_b32_e32 v6, 0xffe385; GFX950-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc386; GFX950-GISEL-NEXT: v_and_or_b32 v0, v5, v6, v0387; GFX950-GISEL-NEXT: v_sub_u32_e32 v10, 1, v4388; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0389; GFX950-GISEL-NEXT: v_lshl_or_b32 v9, v4, 12, v0390; GFX950-GISEL-NEXT: v_med3_i32 v10, v10, 0, 13391; GFX950-GISEL-NEXT: v_or_b32_e32 v0, 0x1000, v0392; GFX950-GISEL-NEXT: v_lshrrev_b32_e32 v11, v10, v0393; GFX950-GISEL-NEXT: v_lshlrev_b32_e32 v10, v10, v11394; GFX950-GISEL-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc395; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, v10, v0396; GFX950-GISEL-NEXT: v_mov_b32_e32 v8, 0x7c00397; GFX950-GISEL-NEXT: v_lshl_or_b32 v5, v5, 9, v8398; GFX950-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc399; GFX950-GISEL-NEXT: v_or_b32_e32 v0, v11, v0400; GFX950-GISEL-NEXT: v_cmp_gt_i32_e32 vcc, 1, v4401; GFX950-GISEL-NEXT: v_lshrrev_b32_e32 v1, 16, v1402; GFX950-GISEL-NEXT: v_and_or_b32 v2, v3, v7, v2403; GFX950-GISEL-NEXT: v_cndmask_b32_e32 v0, v9, v0, vcc404; GFX950-GISEL-NEXT: v_and_b32_e32 v9, 7, v0405; GFX950-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 3, v9406; GFX950-GISEL-NEXT: v_cmp_lt_i32_e64 s[0:1], 5, v9407; GFX950-GISEL-NEXT: s_or_b64 s[0:1], vcc, s[0:1]408; GFX950-GISEL-NEXT: v_lshrrev_b32_e32 v0, 2, v0409; GFX950-GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, s[0:1]410; GFX950-GISEL-NEXT: v_add_u32_e32 v0, v0, v9411; GFX950-GISEL-NEXT: v_cmp_lt_i32_e32 vcc, 30, v4412; GFX950-GISEL-NEXT: v_mov_b32_e32 v9, 0x40f413; GFX950-GISEL-NEXT: s_nop 0414; GFX950-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc415; GFX950-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v4, v9416; GFX950-GISEL-NEXT: v_mov_b32_e32 v4, 0x8000417; GFX950-GISEL-NEXT: s_nop 0418; GFX950-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc419; GFX950-GISEL-NEXT: v_and_or_b32 v0, v1, v4, v0420; GFX950-GISEL-NEXT: v_bfe_u32 v1, v3, 20, 11421; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2422; GFX950-GISEL-NEXT: v_add_u32_e32 v1, 0xfffffc10, v1423; GFX950-GISEL-NEXT: v_lshrrev_b32_e32 v5, 8, v3424; GFX950-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc425; GFX950-GISEL-NEXT: v_and_or_b32 v2, v5, v6, v2426; GFX950-GISEL-NEXT: v_sub_u32_e32 v7, 1, v1427; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2428; GFX950-GISEL-NEXT: v_lshl_or_b32 v6, v1, 12, v2429; GFX950-GISEL-NEXT: v_med3_i32 v7, v7, 0, 13430; GFX950-GISEL-NEXT: v_or_b32_e32 v2, 0x1000, v2431; GFX950-GISEL-NEXT: v_lshrrev_b32_e32 v10, v7, v2432; GFX950-GISEL-NEXT: v_lshlrev_b32_e32 v7, v7, v10433; GFX950-GISEL-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc434; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, v7, v2435; GFX950-GISEL-NEXT: v_lshl_or_b32 v5, v5, 9, v8436; GFX950-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0437; GFX950-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc438; GFX950-GISEL-NEXT: v_or_b32_e32 v2, v10, v2439; GFX950-GISEL-NEXT: v_cmp_gt_i32_e32 vcc, 1, v1440; GFX950-GISEL-NEXT: s_nop 1441; GFX950-GISEL-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc442; GFX950-GISEL-NEXT: v_and_b32_e32 v6, 7, v2443; GFX950-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 3, v6444; GFX950-GISEL-NEXT: v_cmp_lt_i32_e64 s[0:1], 5, v6445; GFX950-GISEL-NEXT: s_or_b64 s[0:1], vcc, s[0:1]446; GFX950-GISEL-NEXT: v_lshrrev_b32_e32 v2, 2, v2447; GFX950-GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 1, s[0:1]448; GFX950-GISEL-NEXT: v_add_u32_e32 v2, v2, v6449; GFX950-GISEL-NEXT: v_cmp_lt_i32_e32 vcc, 30, v1450; GFX950-GISEL-NEXT: s_nop 1451; GFX950-GISEL-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc452; GFX950-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v1, v9453; GFX950-GISEL-NEXT: s_nop 1454; GFX950-GISEL-NEXT: v_cndmask_b32_e32 v1, v2, v5, vcc455; GFX950-GISEL-NEXT: v_lshrrev_b32_e32 v2, 16, v3456; GFX950-GISEL-NEXT: v_and_or_b32 v1, v2, v4, v1457; GFX950-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0458; GFX950-GISEL-NEXT: s_setpc_b64 s[30:31]459 %res = fptrunc <2 x double> %src to <2 x half>460 ret <2 x half> %res461}462