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1; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn < %s | FileCheck --check-prefixes=GCN,SI,FUNC %s2; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=bonaire < %s | FileCheck --check-prefixes=GCN,CI,FUNC %s3; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck --check-prefixes=GCN,CI,FUNC %s4 5; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn < %s | FileCheck --check-prefixes=GCN,SI,FUNC %s6; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck --check-prefixes=GCN,CI,FUNC %s7 8declare double @llvm.fabs.f64(double) #09declare double @llvm.floor.f64(double) #010 11; FUNC-LABEL: {{^}}fract_f64:12; SI-DAG: v_fract_f64_e32 [[FRC:v\[[0-9]+:[0-9]+\]]], v[[[LO:[0-9]+]]:[[HI:[0-9]+]]]13; SI-DAG: v_mov_b32_e32 v[[UPLO:[0-9]+]], -114; SI-DAG: v_mov_b32_e32 v[[UPHI:[0-9]+]], 0x3fefffff15; SI-DAG: v_min_f64 v[[[MINLO:[0-9]+]]:[[MINHI:[0-9]+]]], [[FRC]], v[[[UPLO]]:[[UPHI]]]16; SI-DAG: v_cmp_class_f64_e64 vcc, v[[[LO]]:[[HI]]], 317; SI: v_cndmask_b32_e32 v[[RESLO:[0-9]+]], v[[MINLO]], v[[LO]], vcc18; SI: v_cndmask_b32_e32 v[[RESHI:[0-9]+]], v[[MINHI]], v[[HI]], vcc19; SI: v_add_f64 [[SUB0:v\[[0-9]+:[0-9]+\]]], v[[[LO]]:[[HI]]], -v[[[RESLO]]:[[RESHI]]]20; SI: v_add_f64 [[FRACT:v\[[0-9]+:[0-9]+\]]], v[[[LO]]:[[HI]]], -[[SUB0]]21 22; CI: buffer_load_dwordx2 [[X:v\[[0-9]+:[0-9]+\]]]23; CI: v_floor_f64_e32 [[FLOORX:v\[[0-9]+:[0-9]+\]]], [[X]]24; CI: v_add_f64 [[FRACT:v\[[0-9]+:[0-9]+\]]], [[X]], -[[FLOORX]]25 26; GCN: buffer_store_dwordx2 [[FRACT]]27define amdgpu_kernel void @fract_f64(ptr addrspace(1) %out, ptr addrspace(1) %src) #1 {28 %x = load double, ptr addrspace(1) %src29 %floor.x = call double @llvm.floor.f64(double %x)30 %fract = fsub double %x, %floor.x31 store double %fract, ptr addrspace(1) %out32 ret void33}34 35; FUNC-LABEL: {{^}}fract_f64_neg:36; SI-DAG: v_fract_f64_e64 [[FRC:v\[[0-9]+:[0-9]+\]]], -v[[[LO:[0-9]+]]:[[HI:[0-9]+]]]37; SI-DAG: v_mov_b32_e32 v[[UPLO:[0-9]+]], -138; SI-DAG: v_mov_b32_e32 v[[UPHI:[0-9]+]], 0x3fefffff39; SI-DAG: v_min_f64 v[[[MINLO:[0-9]+]]:[[MINHI:[0-9]+]]], [[FRC]], v[[[UPLO]]:[[UPHI]]]40; SI-DAG: v_cmp_class_f64_e64 vcc, v[[[LO]]:[[HI]]], 341; SI: v_cndmask_b32_e32 v[[RESLO:[0-9]+]], v[[MINLO]], v[[LO]], vcc42; SI: v_cndmask_b32_e32 v[[RESHI:[0-9]+]], v[[MINHI]], v[[HI]], vcc43; SI: v_add_f64 [[SUB0:v\[[0-9]+:[0-9]+\]]], -v[[[LO]]:[[HI]]], -v[[[RESLO]]:[[RESHI]]]44; SI: v_add_f64 [[FRACT:v\[[0-9]+:[0-9]+\]]], -v[[[LO]]:[[HI]]], -[[SUB0]]45 46; CI: buffer_load_dwordx2 [[X:v\[[0-9]+:[0-9]+\]]]47; CI: v_floor_f64_e64 [[FLOORX:v\[[0-9]+:[0-9]+\]]], -[[X]]48; CI: v_add_f64 [[FRACT:v\[[0-9]+:[0-9]+\]]], -[[X]], -[[FLOORX]]49 50; GCN: buffer_store_dwordx2 [[FRACT]]51define amdgpu_kernel void @fract_f64_neg(ptr addrspace(1) %out, ptr addrspace(1) %src) #1 {52 %x = load double, ptr addrspace(1) %src53 %neg.x = fneg double %x54 %floor.neg.x = call double @llvm.floor.f64(double %neg.x)55 %fract = fsub double %neg.x, %floor.neg.x56 store double %fract, ptr addrspace(1) %out57 ret void58}59 60; FUNC-LABEL: {{^}}fract_f64_neg_abs:61; SI-DAG: v_fract_f64_e64 [[FRC:v\[[0-9]+:[0-9]+\]]], -|v[[[LO:[0-9]+]]:[[HI:[0-9]+]]]|62; SI-DAG: v_mov_b32_e32 v[[UPLO:[0-9]+]], -163; SI-DAG: v_mov_b32_e32 v[[UPHI:[0-9]+]], 0x3fefffff64; SI-DAG: v_min_f64 v[[[MINLO:[0-9]+]]:[[MINHI:[0-9]+]]], [[FRC]], v[[[UPLO]]:[[UPHI]]]65; SI-DAG: v_cmp_class_f64_e64 vcc, v[[[LO]]:[[HI]]], 366; SI: v_cndmask_b32_e32 v[[RESLO:[0-9]+]], v[[MINLO]], v[[LO]], vcc67; SI: v_cndmask_b32_e32 v[[RESHI:[0-9]+]], v[[MINHI]], v[[HI]], vcc68; SI: v_add_f64 [[SUB0:v\[[0-9]+:[0-9]+\]]], -|v[[[LO]]:[[HI]]]|, -v[[[RESLO]]:[[RESHI]]]69; SI: v_add_f64 [[FRACT:v\[[0-9]+:[0-9]+\]]], -|v[[[LO]]:[[HI]]]|, -[[SUB0]]70 71; CI: buffer_load_dwordx2 [[X:v\[[0-9]+:[0-9]+\]]]72; CI: v_floor_f64_e64 [[FLOORX:v\[[0-9]+:[0-9]+\]]], -|[[X]]|73; CI: v_add_f64 [[FRACT:v\[[0-9]+:[0-9]+\]]], -|[[X]]|, -[[FLOORX]]74 75; GCN: buffer_store_dwordx2 [[FRACT]]76define amdgpu_kernel void @fract_f64_neg_abs(ptr addrspace(1) %out, ptr addrspace(1) %src) #1 {77 %x = load double, ptr addrspace(1) %src78 %abs.x = call double @llvm.fabs.f64(double %x)79 %neg.abs.x = fneg double %abs.x80 %floor.neg.abs.x = call double @llvm.floor.f64(double %neg.abs.x)81 %fract = fsub double %neg.abs.x, %floor.neg.abs.x82 store double %fract, ptr addrspace(1) %out83 ret void84}85 86; FUNC-LABEL: {{^}}multi_use_floor_fract_f64:87define amdgpu_kernel void @multi_use_floor_fract_f64(ptr addrspace(1) %out, ptr addrspace(1) %src) #1 {88 %x = load double, ptr addrspace(1) %src89 %floor.x = call double @llvm.floor.f64(double %x)90 %fract = fsub double %x, %floor.x91 store volatile double %floor.x, ptr addrspace(1) %out92 store volatile double %fract, ptr addrspace(1) %out93 ret void94}95 96attributes #0 = { nounwind readnone }97attributes #1 = { nounwind }98