253 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 < %s | FileCheck %s3 4define float @freeze_fneg(float %input) nounwind {5; CHECK-LABEL: freeze_fneg:6; CHECK: ; %bb.0:7; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8; CHECK-NEXT: s_setpc_b64 s[30:31]9 %x = fneg reassoc nsz arcp contract afn float %input10 %y = freeze float %x11 %z = fneg reassoc nsz arcp contract afn float %y12 ret float %z13}14 15define float @freeze_fadd(float %input) nounwind {16; CHECK-LABEL: freeze_fadd:17; CHECK: ; %bb.0:18; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)19; CHECK-NEXT: v_add_f32_e32 v0, 2.0, v020; CHECK-NEXT: s_setpc_b64 s[30:31]21 %x = fadd reassoc nsz arcp contract afn float %input, 1.000000e+0022 %y = freeze float %x23 %z = fadd reassoc nsz arcp contract afn float %y, 1.000000e+0024 ret float %z25}26 27define <4 x float> @freeze_fadd_vec(<4 x float> %input) nounwind {28; CHECK-LABEL: freeze_fadd_vec:29; CHECK: ; %bb.0:30; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)31; CHECK-NEXT: v_dual_add_f32 v0, 0x40a00000, v0 :: v_dual_add_f32 v1, 0x40a00000, v132; CHECK-NEXT: v_dual_add_f32 v2, 0x40a00000, v2 :: v_dual_add_f32 v3, 0x40a00000, v333; CHECK-NEXT: s_setpc_b64 s[30:31]34 %x = fadd reassoc nsz arcp contract afn <4 x float> %input, <float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00>35 %y = freeze <4 x float> %x36 %z = fadd reassoc nsz arcp contract afn <4 x float> %y, <float 4.000000e+00, float 3.000000e+00, float 2.000000e+00, float 1.000000e+00>37 ret <4 x float> %z38}39 40define float @freeze_fsub(float %input) nounwind {41; CHECK-LABEL: freeze_fsub:42; CHECK: ; %bb.0:43; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)44; CHECK-NEXT: v_subrev_f32_e32 v0, 1.0, v045; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1)46; CHECK-NEXT: v_subrev_f32_e32 v0, 1.0, v047; CHECK-NEXT: s_setpc_b64 s[30:31]48 %x = fsub reassoc nsz arcp contract afn float %input, 1.000000e+0049 %y = freeze float %x50 %z = fsub reassoc nsz arcp contract afn float %y, 1.000000e+0051 ret float %z52}53 54define <4 x float> @freeze_fsub_vec(<4 x float> %input) nounwind {55; CHECK-LABEL: freeze_fsub_vec:56; CHECK: ; %bb.0:57; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)58; CHECK-NEXT: v_dual_add_f32 v0, 0xc0a00000, v0 :: v_dual_add_f32 v1, 0xc0a00000, v159; CHECK-NEXT: v_dual_add_f32 v2, 0xc0a00000, v2 :: v_dual_add_f32 v3, 0xc0a00000, v360; CHECK-NEXT: s_setpc_b64 s[30:31]61 %x = fsub reassoc nsz arcp contract afn <4 x float> %input, <float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00>62 %y = freeze <4 x float> %x63 %z = fsub reassoc nsz arcp contract afn <4 x float> %y, <float 4.000000e+00, float 3.000000e+00, float 2.000000e+00, float 1.000000e+00>64 ret <4 x float> %z65}66 67define float @freeze_fmul(float %input) nounwind {68; CHECK-LABEL: freeze_fmul:69; CHECK: ; %bb.0:70; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)71; CHECK-NEXT: v_mul_f32_e32 v0, 4.0, v072; CHECK-NEXT: s_setpc_b64 s[30:31]73 %x = fmul reassoc nsz arcp contract afn float %input, 2.000000e+0074 %y = freeze float %x75 %z = fmul reassoc nsz arcp contract afn float %y, 2.000000e+0076 ret float %z77}78 79define <8 x float> @freeze_fmul_vec(<8 x float> %input) nounwind {80; CHECK-LABEL: freeze_fmul_vec:81; CHECK: ; %bb.0:82; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)83; CHECK-NEXT: v_dual_mul_f32 v0, 4.0, v0 :: v_dual_mul_f32 v1, 0x40c00000, v184; CHECK-NEXT: v_dual_mul_f32 v2, 0x40c00000, v2 :: v_dual_mul_f32 v3, 4.0, v385; CHECK-NEXT: v_dual_mul_f32 v4, 4.0, v4 :: v_dual_mul_f32 v5, 0x40c00000, v586; CHECK-NEXT: v_dual_mul_f32 v6, 0x40c00000, v6 :: v_dual_mul_f32 v7, 4.0, v787; CHECK-NEXT: s_setpc_b64 s[30:31]88 %x = fmul reassoc nsz arcp contract afn <8 x float> %input, <float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00, float 4.000000e+00, float 3.000000e+00, float 2.000000e+00, float 1.000000e+00>89 %y = freeze <8 x float> %x90 %z = fmul reassoc nsz arcp contract afn <8 x float> %y, <float 4.000000e+00, float 3.000000e+00, float 2.000000e+00, float 1.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00>91 ret <8 x float> %z92}93 94define float @freeze_fdiv(float %input) nounwind {95; CHECK-LABEL: freeze_fdiv:96; CHECK: ; %bb.0:97; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)98; CHECK-NEXT: v_mul_f32_e32 v0, 0x3e800000, v099; CHECK-NEXT: s_setpc_b64 s[30:31]100 %x = fdiv reassoc nsz arcp contract afn float %input, 2.000000e+00101 %y = freeze float %x102 %z = fdiv reassoc nsz arcp contract afn float %y, 2.000000e+00103 ret float %z104}105 106define <8 x float> @freeze_fdiv_vec(<8 x float> %input) nounwind {107; CHECK-LABEL: freeze_fdiv_vec:108; CHECK: ; %bb.0:109; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)110; CHECK-NEXT: v_dual_mul_f32 v3, 0x3e800000, v3 :: v_dual_mul_f32 v4, 0x3e800000, v4111; CHECK-NEXT: v_dual_mul_f32 v0, 0x3e800000, v0 :: v_dual_mul_f32 v7, 0x3e800000, v7112; CHECK-NEXT: v_dual_mul_f32 v1, 0x3e2aaaab, v1 :: v_dual_mul_f32 v2, 0x3e2aaaab, v2113; CHECK-NEXT: v_dual_mul_f32 v5, 0x3e2aaaab, v5 :: v_dual_mul_f32 v6, 0x3e2aaaab, v6114; CHECK-NEXT: s_setpc_b64 s[30:31]115 %x = fdiv reassoc nsz arcp contract afn <8 x float> %input, <float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00, float 4.000000e+00, float 3.000000e+00, float 2.000000e+00, float 1.000000e+00>116 %y = freeze <8 x float> %x117 %z = fdiv reassoc nsz arcp contract afn <8 x float> %y, <float 4.000000e+00, float 3.000000e+00, float 2.000000e+00, float 1.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00>118 ret <8 x float> %z119}120 121define float @freeze_frem(float %input) nounwind {122; CHECK-LABEL: freeze_frem:123; CHECK: ; %bb.0:124; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)125; CHECK-NEXT: v_mul_f32_e32 v1, 0.5, v0126; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)127; CHECK-NEXT: v_trunc_f32_e32 v1, v1128; CHECK-NEXT: v_fmac_f32_e32 v0, -2.0, v1129; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)130; CHECK-NEXT: v_mul_f32_e32 v1, 0.5, v0131; CHECK-NEXT: v_trunc_f32_e32 v1, v1132; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1)133; CHECK-NEXT: v_fmac_f32_e32 v0, -2.0, v1134; CHECK-NEXT: s_setpc_b64 s[30:31]135 %x = frem reassoc nsz arcp contract afn float %input, 2.000000e+00136 %y = freeze float %x137 %z = frem reassoc nsz arcp contract afn float %y, 2.000000e+00138 ret float %z139}140 141define <8 x float> @freeze_frem_vec(<8 x float> %input) nounwind {142; CHECK-LABEL: freeze_frem_vec:143; CHECK: ; %bb.0:144; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)145; CHECK-NEXT: v_div_scale_f32 v11, null, 0x40400000, 0x40400000, v5146; CHECK-NEXT: v_div_scale_f32 v8, null, 0x40400000, 0x40400000, v2147; CHECK-NEXT: v_div_scale_f32 v20, s0, v5, 0x40400000, v5148; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)149; CHECK-NEXT: v_rcp_f32_e32 v13, v11150; CHECK-NEXT: v_rcp_f32_e32 v10, v8151; CHECK-NEXT: v_div_scale_f32 v14, vcc_lo, v2, 0x40400000, v2152; CHECK-NEXT: v_trunc_f32_e32 v12, v0153; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)154; CHECK-NEXT: v_sub_f32_e32 v0, v0, v12155; CHECK-NEXT: s_waitcnt_depctr depctr_va_vdst(0)156; CHECK-NEXT: v_fma_f32 v17, -v11, v13, 1.0157; CHECK-NEXT: v_fmac_f32_e32 v13, v17, v13158; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)159; CHECK-NEXT: v_dual_mul_f32 v15, 0.5, v6 :: v_dual_mul_f32 v22, v20, v13160; CHECK-NEXT: v_trunc_f32_e32 v15, v15161; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)162; CHECK-NEXT: v_dual_mul_f32 v9, 0.5, v1 :: v_dual_fmac_f32 v6, -2.0, v15163; CHECK-NEXT: v_trunc_f32_e32 v9, v9164; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)165; CHECK-NEXT: v_div_scale_f32 v21, null, 0x40400000, 0x40400000, v6166; CHECK-NEXT: v_fmac_f32_e32 v1, -2.0, v9167; CHECK-NEXT: v_fma_f32 v9, -v8, v10, 1.0168; CHECK-NEXT: v_div_scale_f32 v12, s2, v6, 0x40400000, v6169; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)170; CHECK-NEXT: v_rcp_f32_e32 v24, v21171; CHECK-NEXT: v_fmac_f32_e32 v10, v9, v10172; CHECK-NEXT: v_div_scale_f32 v16, null, 0x40400000, 0x40400000, v1173; CHECK-NEXT: v_div_scale_f32 v23, s1, v1, 0x40400000, v1174; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)175; CHECK-NEXT: v_mul_f32_e32 v19, v14, v10176; CHECK-NEXT: v_rcp_f32_e32 v18, v16177; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)178; CHECK-NEXT: v_fma_f32 v15, -v8, v19, v14179; CHECK-NEXT: v_fmac_f32_e32 v19, v15, v10180; CHECK-NEXT: s_waitcnt_depctr depctr_va_vdst(0)181; CHECK-NEXT: v_fma_f32 v15, -v16, v18, 1.0182; CHECK-NEXT: v_mul_f32_e32 v9, 0x3e800000, v3183; CHECK-NEXT: v_fma_f32 v8, -v8, v19, v14184; CHECK-NEXT: v_fma_f32 v14, -v11, v22, v20185; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)186; CHECK-NEXT: v_fmac_f32_e32 v18, v15, v18187; CHECK-NEXT: v_trunc_f32_e32 v9, v9188; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)189; CHECK-NEXT: v_div_fmas_f32 v8, v8, v10, v19190; CHECK-NEXT: s_mov_b32 vcc_lo, s0191; CHECK-NEXT: v_dual_mul_f32 v10, v23, v18 :: v_dual_mul_f32 v17, 0x3e800000, v4192; CHECK-NEXT: v_fmac_f32_e32 v22, v14, v13193; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)194; CHECK-NEXT: v_div_fixup_f32 v8, v8, 0x40400000, v2195; CHECK-NEXT: v_fma_f32 v14, -v21, v24, 1.0196; CHECK-NEXT: v_fma_f32 v15, -v16, v10, v23197; CHECK-NEXT: v_fmac_f32_e32 v3, -4.0, v9198; CHECK-NEXT: v_fma_f32 v11, -v11, v22, v20199; CHECK-NEXT: v_trunc_f32_e32 v8, v8200; CHECK-NEXT: v_fmac_f32_e32 v24, v14, v24201; CHECK-NEXT: v_fmac_f32_e32 v10, v15, v18202; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)203; CHECK-NEXT: v_div_fmas_f32 v11, v11, v13, v22204; CHECK-NEXT: v_fmac_f32_e32 v2, 0xc0400000, v8205; CHECK-NEXT: v_trunc_f32_e32 v13, v17206; CHECK-NEXT: s_mov_b32 vcc_lo, s1207; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)208; CHECK-NEXT: v_div_fixup_f32 v8, v11, 0x40400000, v5209; CHECK-NEXT: v_mul_f32_e32 v11, v12, v24210; CHECK-NEXT: v_fma_f32 v9, -v16, v10, v23211; CHECK-NEXT: v_trunc_f32_e32 v8, v8212; CHECK-NEXT: v_fmac_f32_e32 v4, -4.0, v13213; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)214; CHECK-NEXT: v_fma_f32 v13, -v21, v11, v12215; CHECK-NEXT: v_div_fmas_f32 v9, v9, v18, v10216; CHECK-NEXT: v_mul_f32_e32 v10, 0x3e800000, v0217; CHECK-NEXT: v_fmac_f32_e32 v5, 0xc0400000, v8218; CHECK-NEXT: v_trunc_f32_e32 v8, v7219; CHECK-NEXT: v_fmac_f32_e32 v11, v13, v24220; CHECK-NEXT: v_div_fixup_f32 v9, v9, 0x40400000, v1221; CHECK-NEXT: v_mul_f32_e32 v13, 0.5, v2222; CHECK-NEXT: s_mov_b32 vcc_lo, s2223; CHECK-NEXT: v_sub_f32_e32 v7, v7, v8224; CHECK-NEXT: v_trunc_f32_e32 v8, v10225; CHECK-NEXT: v_trunc_f32_e32 v9, v9226; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)227; CHECK-NEXT: v_dual_fmac_f32 v0, -4.0, v8 :: v_dual_fmac_f32 v1, 0xc0400000, v9228; CHECK-NEXT: v_mul_f32_e32 v8, 0.5, v5229; CHECK-NEXT: v_fma_f32 v10, -v21, v11, v12230; CHECK-NEXT: v_trunc_f32_e32 v12, v13231; CHECK-NEXT: v_trunc_f32_e32 v8, v8232; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)233; CHECK-NEXT: v_div_fmas_f32 v10, v10, v24, v11234; CHECK-NEXT: v_trunc_f32_e32 v11, v3235; CHECK-NEXT: v_fmac_f32_e32 v2, -2.0, v12236; CHECK-NEXT: v_trunc_f32_e32 v12, v4237; CHECK-NEXT: v_fmac_f32_e32 v5, -2.0, v8238; CHECK-NEXT: v_div_fixup_f32 v9, v10, 0x40400000, v6239; CHECK-NEXT: v_sub_f32_e32 v3, v3, v11240; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)241; CHECK-NEXT: v_trunc_f32_e32 v9, v9242; CHECK-NEXT: v_fmac_f32_e32 v6, 0xc0400000, v9243; CHECK-NEXT: v_mul_f32_e32 v10, 0x3e800000, v7244; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)245; CHECK-NEXT: v_trunc_f32_e32 v10, v10246; CHECK-NEXT: v_dual_sub_f32 v4, v4, v12 :: v_dual_fmac_f32 v7, -4.0, v10247; CHECK-NEXT: s_setpc_b64 s[30:31]248 %x = frem reassoc nsz arcp contract afn <8 x float> %input, <float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00, float 4.000000e+00, float 3.000000e+00, float 2.000000e+00, float 1.000000e+00>249 %y = freeze <8 x float> %x250 %z = frem reassoc nsz arcp contract afn <8 x float> %y, <float 4.000000e+00, float 3.000000e+00, float 2.000000e+00, float 1.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00>251 ret <8 x float> %z252}253