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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck %s3 4declare { float, i32 } @llvm.frexp.f32.i32(float)5declare { <2 x float>, <2 x i32> } @llvm.frexp.v2f32.v2i32(<2 x float>)6declare { <4 x float>, <4 x i32> } @llvm.frexp.v4f32.v4i32(<4 x float>)7 8 9define { float, i32 } @frexp_frexp(float %x) {10; CHECK-LABEL: frexp_frexp:11; CHECK: ; %bb.0:12; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)13; CHECK-NEXT: v_frexp_mant_f32_e32 v1, v014; CHECK-NEXT: v_frexp_mant_f32_e32 v0, v115; CHECK-NEXT: v_frexp_exp_i32_f32_e32 v1, v116; CHECK-NEXT: s_setpc_b64 s[30:31]17 %frexp0 = call { float, i32 } @llvm.frexp.f32.i32(float %x)18 %frexp0.0 = extractvalue { float, i32 } %frexp0, 019 %frexp1 = call { float, i32 } @llvm.frexp.f32.i32(float %frexp0.0)20 ret { float, i32 } %frexp121}22 23define { <2 x float>, <2 x i32> } @frexp_frexp_vector(<2 x float> %x) {24; CHECK-LABEL: frexp_frexp_vector:25; CHECK: ; %bb.0:26; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)27; CHECK-NEXT: v_frexp_mant_f32_e32 v3, v128; CHECK-NEXT: v_frexp_mant_f32_e32 v2, v029; CHECK-NEXT: v_frexp_mant_f32_e32 v0, v230; CHECK-NEXT: v_frexp_mant_f32_e32 v1, v331; CHECK-NEXT: v_frexp_exp_i32_f32_e32 v2, v232; CHECK-NEXT: v_frexp_exp_i32_f32_e32 v3, v333; CHECK-NEXT: s_setpc_b64 s[30:31]34 %frexp0 = call { <2 x float>, <2 x i32> } @llvm.frexp.v2f32.v2i32(<2 x float> %x)35 %frexp0.0 = extractvalue { <2 x float>, <2 x i32> } %frexp0, 036 %frexp1 = call { <2 x float>, <2 x i32> } @llvm.frexp.v2f32.v2i32(<2 x float> %frexp0.0)37 ret { <2 x float>, <2 x i32> } %frexp138}39 40define { float, i32 } @frexp_frexp_const(float %x) {41; CHECK-LABEL: frexp_frexp_const:42; CHECK: ; %bb.0:43; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)44; CHECK-NEXT: v_mov_b32_e32 v0, 0x3f28000045; CHECK-NEXT: v_mov_b32_e32 v1, 046; CHECK-NEXT: s_setpc_b64 s[30:31]47 %frexp0 = call { float, i32 } @llvm.frexp.f32.i32(float 42.0)48 %frexp0.0 = extractvalue { float, i32 } %frexp0, 049 %frexp1 = call { float, i32 } @llvm.frexp.f32.i32(float %frexp0.0)50 ret { float, i32 } %frexp151}52 53define { float, i32 } @frexp_poison() {54; CHECK-LABEL: frexp_poison:55; CHECK: ; %bb.0:56; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)57; CHECK-NEXT: s_setpc_b64 s[30:31]58 %ret = call { float, i32 } @llvm.frexp.f32.i32(float poison)59 ret { float, i32 } %ret60}61 62define { <2 x float>, <2 x i32> } @frexp_poison_vector() {63; CHECK-LABEL: frexp_poison_vector:64; CHECK: ; %bb.0:65; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)66; CHECK-NEXT: s_setpc_b64 s[30:31]67 %ret = call { <2 x float>, <2 x i32> } @llvm.frexp.v2f32.v2i32(<2 x float> poison)68 ret { <2 x float>, <2 x i32> } %ret69}70 71define { float, i32 } @frexp_undef() {72; CHECK-LABEL: frexp_undef:73; CHECK: ; %bb.0:74; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)75; CHECK-NEXT: v_frexp_mant_f32_e32 v0, s476; CHECK-NEXT: v_frexp_exp_i32_f32_e32 v1, s477; CHECK-NEXT: s_setpc_b64 s[30:31]78 %ret = call { float, i32 } @llvm.frexp.f32.i32(float undef)79 ret { float, i32 } %ret80}81define { <2 x float>, <2 x i32> } @frexp_undef_vector() {82; CHECK-LABEL: frexp_undef_vector:83; CHECK: ; %bb.0:84; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)85; CHECK-NEXT: v_frexp_mant_f32_e32 v0, s486; CHECK-NEXT: v_frexp_exp_i32_f32_e32 v2, s487; CHECK-NEXT: v_mov_b32_e32 v1, v088; CHECK-NEXT: v_mov_b32_e32 v3, v289; CHECK-NEXT: s_setpc_b64 s[30:31]90 %ret = call { <2 x float>, <2 x i32> } @llvm.frexp.v2f32.v2i32(<2 x float> undef)91 ret { <2 x float>, <2 x i32> } %ret92}93 94define { <2 x float>, <2 x i32> } @frexp_zero_vector() {95; CHECK-LABEL: frexp_zero_vector:96; CHECK: ; %bb.0:97; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)98; CHECK-NEXT: v_mov_b32_e32 v0, 099; CHECK-NEXT: v_mov_b32_e32 v1, 0100; CHECK-NEXT: v_mov_b32_e32 v2, 0101; CHECK-NEXT: v_mov_b32_e32 v3, 0102; CHECK-NEXT: s_setpc_b64 s[30:31]103 %ret = call { <2 x float>, <2 x i32> } @llvm.frexp.v2f32.v2i32(<2 x float> zeroinitializer)104 ret { <2 x float>, <2 x i32> } %ret105}106 107define { <2 x float>, <2 x i32> } @frexp_zero_negzero_vector() {108; CHECK-LABEL: frexp_zero_negzero_vector:109; CHECK: ; %bb.0:110; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)111; CHECK-NEXT: v_mov_b32_e32 v0, 0112; CHECK-NEXT: v_bfrev_b32_e32 v1, 1113; CHECK-NEXT: v_mov_b32_e32 v2, 0114; CHECK-NEXT: v_mov_b32_e32 v3, 0115; CHECK-NEXT: s_setpc_b64 s[30:31]116 %ret = call { <2 x float>, <2 x i32> } @llvm.frexp.v2f32.v2i32(<2 x float> <float 0.0, float -0.0>)117 ret { <2 x float>, <2 x i32> } %ret118}119 120define { <4 x float>, <4 x i32> } @frexp_nonsplat_vector() {121; CHECK-LABEL: frexp_nonsplat_vector:122; CHECK: ; %bb.0:123; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)124; CHECK-NEXT: v_frexp_mant_f32_e32 v2, s4125; CHECK-NEXT: v_frexp_exp_i32_f32_e32 v6, s4126; CHECK-NEXT: v_mov_b32_e32 v0, 0.5127; CHECK-NEXT: v_mov_b32_e32 v1, -0.5128; CHECK-NEXT: v_mov_b32_e32 v3, 0x3f1c3c00129; CHECK-NEXT: v_mov_b32_e32 v4, 5130; CHECK-NEXT: v_mov_b32_e32 v5, 6131; CHECK-NEXT: v_mov_b32_e32 v7, 14132; CHECK-NEXT: s_setpc_b64 s[30:31]133 %ret = call { <4 x float>, <4 x i32> } @llvm.frexp.v4f32.v4i32(<4 x float> <float 16.0, float -32.0, float undef, float 9999.0>)134 ret { <4 x float>, <4 x i32> } %ret135}136 137define { float, i32 } @frexp_zero() {138; CHECK-LABEL: frexp_zero:139; CHECK: ; %bb.0:140; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)141; CHECK-NEXT: v_mov_b32_e32 v0, 0142; CHECK-NEXT: v_mov_b32_e32 v1, 0143; CHECK-NEXT: s_setpc_b64 s[30:31]144 %ret = call { float, i32 } @llvm.frexp.f32.i32(float 0.0)145 ret { float, i32 } %ret146}147 148define { float, i32 } @frexp_negzero() {149; CHECK-LABEL: frexp_negzero:150; CHECK: ; %bb.0:151; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)152; CHECK-NEXT: v_bfrev_b32_e32 v0, 1153; CHECK-NEXT: v_mov_b32_e32 v1, 0154; CHECK-NEXT: s_setpc_b64 s[30:31]155 %ret = call { float, i32 } @llvm.frexp.f32.i32(float -0.0)156 ret { float, i32 } %ret157}158 159define { float, i32 } @frexp_one() {160; CHECK-LABEL: frexp_one:161; CHECK: ; %bb.0:162; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)163; CHECK-NEXT: v_mov_b32_e32 v0, 0.5164; CHECK-NEXT: v_mov_b32_e32 v1, 1165; CHECK-NEXT: s_setpc_b64 s[30:31]166 %ret = call { float, i32 } @llvm.frexp.f32.i32(float 1.0)167 ret { float, i32 } %ret168}169 170define { float, i32 } @frexp_negone() {171; CHECK-LABEL: frexp_negone:172; CHECK: ; %bb.0:173; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)174; CHECK-NEXT: v_mov_b32_e32 v0, -0.5175; CHECK-NEXT: v_mov_b32_e32 v1, 1176; CHECK-NEXT: s_setpc_b64 s[30:31]177 %ret = call { float, i32 } @llvm.frexp.f32.i32(float -1.0)178 ret { float, i32 } %ret179}180 181define { float, i32 } @frexp_two() {182; CHECK-LABEL: frexp_two:183; CHECK: ; %bb.0:184; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)185; CHECK-NEXT: v_mov_b32_e32 v0, 0.5186; CHECK-NEXT: v_mov_b32_e32 v1, 2187; CHECK-NEXT: s_setpc_b64 s[30:31]188 %ret = call { float, i32 } @llvm.frexp.f32.i32(float 2.0)189 ret { float, i32 } %ret190}191 192define { float, i32 } @frexp_negtwo() {193; CHECK-LABEL: frexp_negtwo:194; CHECK: ; %bb.0:195; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)196; CHECK-NEXT: v_mov_b32_e32 v0, -0.5197; CHECK-NEXT: v_mov_b32_e32 v1, 2198; CHECK-NEXT: s_setpc_b64 s[30:31]199 %ret = call { float, i32 } @llvm.frexp.f32.i32(float -2.0)200 ret { float, i32 } %ret201}202 203define { float, i32 } @frexp_inf() {204; CHECK-LABEL: frexp_inf:205; CHECK: ; %bb.0:206; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)207; CHECK-NEXT: v_mov_b32_e32 v0, 0x7f800000208; CHECK-NEXT: v_mov_b32_e32 v1, 0209; CHECK-NEXT: s_setpc_b64 s[30:31]210 %ret = call { float, i32 } @llvm.frexp.f32.i32(float 0x7FF0000000000000)211 ret { float, i32 } %ret212}213 214define { float, i32 } @frexp_neginf() {215; CHECK-LABEL: frexp_neginf:216; CHECK: ; %bb.0:217; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)218; CHECK-NEXT: v_mov_b32_e32 v0, 0xff800000219; CHECK-NEXT: v_mov_b32_e32 v1, 0220; CHECK-NEXT: s_setpc_b64 s[30:31]221 %ret = call { float, i32 } @llvm.frexp.f32.i32(float 0xFFF0000000000000)222 ret { float, i32 } %ret223}224 225define { float, i32 } @frexp_qnan() {226; CHECK-LABEL: frexp_qnan:227; CHECK: ; %bb.0:228; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)229; CHECK-NEXT: v_mov_b32_e32 v0, 0x7fc00000230; CHECK-NEXT: v_mov_b32_e32 v1, 0231; CHECK-NEXT: s_setpc_b64 s[30:31]232 %ret = call { float, i32 } @llvm.frexp.f32.i32(float 0x7FF8000000000000)233 ret { float, i32 } %ret234}235 236define { float, i32 } @frexp_snan() {237; CHECK-LABEL: frexp_snan:238; CHECK: ; %bb.0:239; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)240; CHECK-NEXT: v_mov_b32_e32 v0, 0x7fc00001241; CHECK-NEXT: v_mov_b32_e32 v1, 0242; CHECK-NEXT: s_setpc_b64 s[30:31]243 %ret = call { float, i32 } @llvm.frexp.f32.i32(float bitcast (i32 2139095041 to float))244 ret { float, i32 } %ret245}246 247define { float, i32 } @frexp_pos_denorm() {248; CHECK-LABEL: frexp_pos_denorm:249; CHECK: ; %bb.0:250; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)251; CHECK-NEXT: v_mov_b32_e32 v0, 0x3f7ffffe252; CHECK-NEXT: v_mov_b32_e32 v1, 0xffffff82253; CHECK-NEXT: s_setpc_b64 s[30:31]254 %ret = call { float, i32 } @llvm.frexp.f32.i32(float bitcast (i32 8388607 to float))255 ret { float, i32 } %ret256}257 258define { float, i32 } @frexp_neg_denorm() {259; CHECK-LABEL: frexp_neg_denorm:260; CHECK: ; %bb.0:261; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)262; CHECK-NEXT: v_mov_b32_e32 v0, 0xbf7ffffe263; CHECK-NEXT: v_mov_b32_e32 v1, 0xffffff82264; CHECK-NEXT: s_setpc_b64 s[30:31]265 %ret = call { float, i32 } @llvm.frexp.f32.i32(float bitcast (i32 -2139095041 to float))266 ret { float, i32 } %ret267}268 269define { <2 x float>, <2 x i32> } @frexp_splat_4() {270; CHECK-LABEL: frexp_splat_4:271; CHECK: ; %bb.0:272; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)273; CHECK-NEXT: v_mov_b32_e32 v0, 0.5274; CHECK-NEXT: v_mov_b32_e32 v1, 0.5275; CHECK-NEXT: v_mov_b32_e32 v2, 3276; CHECK-NEXT: v_mov_b32_e32 v3, 3277; CHECK-NEXT: s_setpc_b64 s[30:31]278 %ret = call { <2 x float>, <2 x i32> } @llvm.frexp.v2f32.v2i32(<2 x float> <float 4.0, float 4.0>)279 ret { <2 x float>, <2 x i32> } %ret280}281 282define { <2 x float>, <2 x i32> } @frexp_splat_qnan() {283; CHECK-LABEL: frexp_splat_qnan:284; CHECK: ; %bb.0:285; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)286; CHECK-NEXT: v_mov_b32_e32 v0, 0x7fc00000287; CHECK-NEXT: v_mov_b32_e32 v1, 0x7fc00000288; CHECK-NEXT: v_mov_b32_e32 v2, 0289; CHECK-NEXT: v_mov_b32_e32 v3, 0290; CHECK-NEXT: s_setpc_b64 s[30:31]291 %ret = call { <2 x float>, <2 x i32> } @llvm.frexp.v2f32.v2i32(<2 x float> <float 0x7FF8000000000000, float 0x7FF8000000000000>)292 ret { <2 x float>, <2 x i32> } %ret293}294 295define { <2 x float>, <2 x i32> } @frexp_splat_inf() {296; CHECK-LABEL: frexp_splat_inf:297; CHECK: ; %bb.0:298; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)299; CHECK-NEXT: v_mov_b32_e32 v0, 0x7f800000300; CHECK-NEXT: v_mov_b32_e32 v1, 0x7f800000301; CHECK-NEXT: v_mov_b32_e32 v2, 0302; CHECK-NEXT: v_mov_b32_e32 v3, 0303; CHECK-NEXT: s_setpc_b64 s[30:31]304 %ret = call { <2 x float>, <2 x i32> } @llvm.frexp.v2f32.v2i32(<2 x float> <float 0x7FF0000000000000, float 0x7FF0000000000000>)305 ret { <2 x float>, <2 x i32> } %ret306}307 308define { <2 x float>, <2 x i32> } @frexp_splat_neginf() {309; CHECK-LABEL: frexp_splat_neginf:310; CHECK: ; %bb.0:311; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)312; CHECK-NEXT: v_mov_b32_e32 v0, 0xff800000313; CHECK-NEXT: v_mov_b32_e32 v1, 0xff800000314; CHECK-NEXT: v_mov_b32_e32 v2, 0315; CHECK-NEXT: v_mov_b32_e32 v3, 0316; CHECK-NEXT: s_setpc_b64 s[30:31]317 %ret = call { <2 x float>, <2 x i32> } @llvm.frexp.v2f32.v2i32(<2 x float> <float 0xFFF0000000000000, float 0xFFF0000000000000>)318 ret { <2 x float>, <2 x i32> } %ret319}320 321define { <2 x float>, <2 x i32> } @frexp_splat_undef_inf() {322; CHECK-LABEL: frexp_splat_undef_inf:323; CHECK: ; %bb.0:324; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)325; CHECK-NEXT: v_frexp_mant_f32_e32 v0, s4326; CHECK-NEXT: v_frexp_exp_i32_f32_e32 v2, s4327; CHECK-NEXT: v_mov_b32_e32 v1, 0x7f800000328; CHECK-NEXT: v_mov_b32_e32 v3, 0329; CHECK-NEXT: s_setpc_b64 s[30:31]330 %ret = call { <2 x float>, <2 x i32> } @llvm.frexp.v2f32.v2i32(<2 x float> <float undef, float 0x7FF0000000000000>)331 ret { <2 x float>, <2 x i32> } %ret332}333