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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=amdgcn -mcpu=tahiti | FileCheck %s --check-prefix=SI3; RUN: llc < %s -mtriple=amdgcn -mcpu=tonga | FileCheck %s --check-prefix=VI4; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx900 | FileCheck %s --check-prefix=GFX95; RUN: llc < %s -mtriple=r600 -mcpu=redwood | FileCheck %s --check-prefix=R6006; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1010 | FileCheck %s --check-prefix=GFX107; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 | FileCheck %s --check-prefix=GFX118 9declare i32 @llvm.fshl.i32(i32, i32, i32) nounwind readnone10declare <2 x i32> @llvm.fshl.v2i32(<2 x i32>, <2 x i32>, <2 x i32>) nounwind readnone11declare <4 x i32> @llvm.fshl.v4i32(<4 x i32>, <4 x i32>, <4 x i32>) nounwind readnone12 13define amdgpu_kernel void @fshl_i32(ptr addrspace(1) %in, i32 %x, i32 %y, i32 %z) {14; SI-LABEL: fshl_i32:15; SI: ; %bb.0: ; %entry16; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xb17; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x918; SI-NEXT: s_mov_b32 s7, 0xf00019; SI-NEXT: s_mov_b32 s6, -120; SI-NEXT: s_waitcnt lgkmcnt(0)21; SI-NEXT: s_mov_b32 s8, s122; SI-NEXT: s_mov_b32 s9, s023; SI-NEXT: s_lshr_b32 s3, s0, 124; SI-NEXT: s_lshr_b64 s[0:1], s[8:9], 125; SI-NEXT: s_not_b32 s2, s226; SI-NEXT: s_mov_b32 s1, s327; SI-NEXT: s_and_b32 s2, s2, 3128; SI-NEXT: s_lshr_b64 s[0:1], s[0:1], s229; SI-NEXT: v_mov_b32_e32 v0, s030; SI-NEXT: buffer_store_dword v0, off, s[4:7], 031; SI-NEXT: s_endpgm32;33; VI-LABEL: fshl_i32:34; VI: ; %bb.0: ; %entry35; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c36; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x2437; VI-NEXT: s_waitcnt lgkmcnt(0)38; VI-NEXT: s_mov_b32 s6, s139; VI-NEXT: s_mov_b32 s7, s040; VI-NEXT: s_lshr_b32 s3, s0, 141; VI-NEXT: s_not_b32 s2, s242; VI-NEXT: s_lshr_b64 s[0:1], s[6:7], 143; VI-NEXT: s_mov_b32 s1, s344; VI-NEXT: s_and_b32 s2, s2, 3145; VI-NEXT: s_lshr_b64 s[0:1], s[0:1], s246; VI-NEXT: v_mov_b32_e32 v0, s447; VI-NEXT: v_mov_b32_e32 v1, s548; VI-NEXT: v_mov_b32_e32 v2, s049; VI-NEXT: flat_store_dword v[0:1], v250; VI-NEXT: s_endpgm51;52; GFX9-LABEL: fshl_i32:53; GFX9: ; %bb.0: ; %entry54; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c55; GFX9-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x2456; GFX9-NEXT: v_mov_b32_e32 v0, 057; GFX9-NEXT: s_waitcnt lgkmcnt(0)58; GFX9-NEXT: s_mov_b32 s4, s159; GFX9-NEXT: s_mov_b32 s5, s060; GFX9-NEXT: s_lshr_b32 s3, s0, 161; GFX9-NEXT: s_lshr_b64 s[0:1], s[4:5], 162; GFX9-NEXT: s_not_b32 s2, s263; GFX9-NEXT: s_mov_b32 s1, s364; GFX9-NEXT: s_and_b32 s2, s2, 3165; GFX9-NEXT: s_lshr_b64 s[0:1], s[0:1], s266; GFX9-NEXT: v_mov_b32_e32 v1, s067; GFX9-NEXT: global_store_dword v0, v1, s[6:7]68; GFX9-NEXT: s_endpgm69;70; R600-LABEL: fshl_i32:71; R600: ; %bb.0: ; %entry72; R600-NEXT: ALU 5, @4, KC0[CB0:0-32], KC1[]73; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 174; R600-NEXT: CF_END75; R600-NEXT: PAD76; R600-NEXT: ALU clause starting at 4:77; R600-NEXT: LSHR T0.Z, KC0[2].Z, 1,78; R600-NEXT: BIT_ALIGN_INT T0.W, KC0[2].Z, KC0[2].W, 1,79; R600-NEXT: NOT_INT * T1.W, KC0[3].X,80; R600-NEXT: BIT_ALIGN_INT T0.X, PV.Z, PV.W, PS,81; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,82; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)83;84; GFX10-LABEL: fshl_i32:85; GFX10: ; %bb.0: ; %entry86; GFX10-NEXT: s_clause 0x187; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c88; GFX10-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x2489; GFX10-NEXT: v_mov_b32_e32 v0, 090; GFX10-NEXT: s_waitcnt lgkmcnt(0)91; GFX10-NEXT: s_mov_b32 s4, s192; GFX10-NEXT: s_mov_b32 s5, s093; GFX10-NEXT: s_lshr_b32 s3, s0, 194; GFX10-NEXT: s_not_b32 s2, s295; GFX10-NEXT: s_lshr_b64 s[0:1], s[4:5], 196; GFX10-NEXT: s_mov_b32 s1, s397; GFX10-NEXT: s_and_b32 s2, s2, 3198; GFX10-NEXT: s_lshr_b64 s[0:1], s[0:1], s299; GFX10-NEXT: v_mov_b32_e32 v1, s0100; GFX10-NEXT: global_store_dword v0, v1, s[6:7]101; GFX10-NEXT: s_endpgm102;103; GFX11-LABEL: fshl_i32:104; GFX11: ; %bb.0: ; %entry105; GFX11-NEXT: s_clause 0x1106; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x2c107; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x24108; GFX11-NEXT: s_waitcnt lgkmcnt(0)109; GFX11-NEXT: s_mov_b32 s6, s1110; GFX11-NEXT: s_mov_b32 s7, s0111; GFX11-NEXT: s_lshr_b32 s3, s0, 1112; GFX11-NEXT: s_not_b32 s2, s2113; GFX11-NEXT: s_lshr_b64 s[0:1], s[6:7], 1114; GFX11-NEXT: s_mov_b32 s1, s3115; GFX11-NEXT: s_and_b32 s2, s2, 31116; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)117; GFX11-NEXT: s_lshr_b64 s[0:1], s[0:1], s2118; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0119; GFX11-NEXT: global_store_b32 v0, v1, s[4:5]120; GFX11-NEXT: s_endpgm121entry:122 %0 = call i32 @llvm.fshl.i32(i32 %x, i32 %y, i32 %z)123 store i32 %0, ptr addrspace(1) %in124 ret void125}126 127define amdgpu_kernel void @fshl_i32_imm(ptr addrspace(1) %in, i32 %x, i32 %y) {128; SI-LABEL: fshl_i32_imm:129; SI: ; %bb.0: ; %entry130; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9131; SI-NEXT: s_mov_b32 s7, 0xf000132; SI-NEXT: s_mov_b32 s6, -1133; SI-NEXT: s_waitcnt lgkmcnt(0)134; SI-NEXT: s_mov_b32 s4, s0135; SI-NEXT: s_mov_b32 s5, s1136; SI-NEXT: s_mov_b32 s0, s3137; SI-NEXT: s_mov_b32 s1, s2138; SI-NEXT: s_lshr_b64 s[0:1], s[0:1], 25139; SI-NEXT: v_mov_b32_e32 v0, s0140; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0141; SI-NEXT: s_endpgm142;143; VI-LABEL: fshl_i32_imm:144; VI: ; %bb.0: ; %entry145; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24146; VI-NEXT: s_waitcnt lgkmcnt(0)147; VI-NEXT: s_mov_b32 s4, s3148; VI-NEXT: s_mov_b32 s5, s2149; VI-NEXT: s_lshr_b64 s[2:3], s[4:5], 25150; VI-NEXT: v_mov_b32_e32 v0, s0151; VI-NEXT: v_mov_b32_e32 v1, s1152; VI-NEXT: v_mov_b32_e32 v2, s2153; VI-NEXT: flat_store_dword v[0:1], v2154; VI-NEXT: s_endpgm155;156; GFX9-LABEL: fshl_i32_imm:157; GFX9: ; %bb.0: ; %entry158; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24159; GFX9-NEXT: v_mov_b32_e32 v0, 0160; GFX9-NEXT: s_waitcnt lgkmcnt(0)161; GFX9-NEXT: s_mov_b32 s4, s3162; GFX9-NEXT: s_mov_b32 s5, s2163; GFX9-NEXT: s_lshr_b64 s[2:3], s[4:5], 25164; GFX9-NEXT: v_mov_b32_e32 v1, s2165; GFX9-NEXT: global_store_dword v0, v1, s[0:1]166; GFX9-NEXT: s_endpgm167;168; R600-LABEL: fshl_i32_imm:169; R600: ; %bb.0: ; %entry170; R600-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[]171; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1172; R600-NEXT: CF_END173; R600-NEXT: PAD174; R600-NEXT: ALU clause starting at 4:175; R600-NEXT: LSHR * T0.X, KC0[2].Y, literal.x,176; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)177; R600-NEXT: BIT_ALIGN_INT * T1.X, KC0[2].Z, KC0[2].W, literal.x,178; R600-NEXT: 25(3.503246e-44), 0(0.000000e+00)179;180; GFX10-LABEL: fshl_i32_imm:181; GFX10: ; %bb.0: ; %entry182; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24183; GFX10-NEXT: v_mov_b32_e32 v0, 0184; GFX10-NEXT: s_waitcnt lgkmcnt(0)185; GFX10-NEXT: s_mov_b32 s4, s3186; GFX10-NEXT: s_mov_b32 s5, s2187; GFX10-NEXT: s_lshr_b64 s[2:3], s[4:5], 25188; GFX10-NEXT: v_mov_b32_e32 v1, s2189; GFX10-NEXT: global_store_dword v0, v1, s[0:1]190; GFX10-NEXT: s_endpgm191;192; GFX11-LABEL: fshl_i32_imm:193; GFX11: ; %bb.0: ; %entry194; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24195; GFX11-NEXT: s_waitcnt lgkmcnt(0)196; GFX11-NEXT: s_mov_b32 s4, s3197; GFX11-NEXT: s_mov_b32 s5, s2198; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)199; GFX11-NEXT: s_lshr_b64 s[2:3], s[4:5], 25200; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2201; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]202; GFX11-NEXT: s_endpgm203entry:204 %0 = call i32 @llvm.fshl.i32(i32 %x, i32 %y, i32 7)205 store i32 %0, ptr addrspace(1) %in206 ret void207}208 209define amdgpu_kernel void @fshl_v2i32(ptr addrspace(1) %in, <2 x i32> %x, <2 x i32> %y, <2 x i32> %z) {210; SI-LABEL: fshl_v2i32:211; SI: ; %bb.0: ; %entry212; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xb213; SI-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x9214; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xf215; SI-NEXT: s_mov_b32 s11, 0xf000216; SI-NEXT: s_mov_b32 s10, -1217; SI-NEXT: s_waitcnt lgkmcnt(0)218; SI-NEXT: s_mov_b32 s6, s3219; SI-NEXT: s_mov_b32 s7, s1220; SI-NEXT: s_lshr_b32 s12, s1, 1221; SI-NEXT: s_lshr_b64 s[6:7], s[6:7], 1222; SI-NEXT: s_not_b32 s1, s5223; SI-NEXT: s_mov_b32 s7, s12224; SI-NEXT: s_and_b32 s1, s1, 31225; SI-NEXT: s_mov_b32 s3, s0226; SI-NEXT: s_lshr_b64 s[6:7], s[6:7], s1227; SI-NEXT: s_lshr_b32 s5, s0, 1228; SI-NEXT: s_lshr_b64 s[0:1], s[2:3], 1229; SI-NEXT: s_not_b32 s2, s4230; SI-NEXT: s_mov_b32 s1, s5231; SI-NEXT: s_and_b32 s2, s2, 31232; SI-NEXT: s_lshr_b64 s[0:1], s[0:1], s2233; SI-NEXT: v_mov_b32_e32 v0, s0234; SI-NEXT: v_mov_b32_e32 v1, s6235; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0236; SI-NEXT: s_endpgm237;238; VI-LABEL: fshl_v2i32:239; VI: ; %bb.0: ; %entry240; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c241; VI-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24242; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x3c243; VI-NEXT: s_waitcnt lgkmcnt(0)244; VI-NEXT: s_mov_b32 s8, s3245; VI-NEXT: s_mov_b32 s9, s1246; VI-NEXT: s_lshr_b32 s10, s1, 1247; VI-NEXT: s_lshr_b64 s[8:9], s[8:9], 1248; VI-NEXT: s_not_b32 s1, s5249; VI-NEXT: s_mov_b32 s9, s10250; VI-NEXT: s_and_b32 s1, s1, 31251; VI-NEXT: s_mov_b32 s3, s0252; VI-NEXT: s_lshr_b64 s[8:9], s[8:9], s1253; VI-NEXT: s_lshr_b32 s5, s0, 1254; VI-NEXT: s_lshr_b64 s[0:1], s[2:3], 1255; VI-NEXT: s_not_b32 s2, s4256; VI-NEXT: s_mov_b32 s1, s5257; VI-NEXT: s_and_b32 s2, s2, 31258; VI-NEXT: s_lshr_b64 s[0:1], s[0:1], s2259; VI-NEXT: v_mov_b32_e32 v2, s6260; VI-NEXT: v_mov_b32_e32 v0, s0261; VI-NEXT: v_mov_b32_e32 v1, s8262; VI-NEXT: v_mov_b32_e32 v3, s7263; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]264; VI-NEXT: s_endpgm265;266; GFX9-LABEL: fshl_v2i32:267; GFX9: ; %bb.0: ; %entry268; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c269; GFX9-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24270; GFX9-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x3c271; GFX9-NEXT: v_mov_b32_e32 v2, 0272; GFX9-NEXT: s_waitcnt lgkmcnt(0)273; GFX9-NEXT: s_mov_b32 s4, s3274; GFX9-NEXT: s_mov_b32 s5, s1275; GFX9-NEXT: s_lshr_b32 s10, s1, 1276; GFX9-NEXT: s_lshr_b64 s[4:5], s[4:5], 1277; GFX9-NEXT: s_not_b32 s1, s9278; GFX9-NEXT: s_mov_b32 s5, s10279; GFX9-NEXT: s_and_b32 s1, s1, 31280; GFX9-NEXT: s_lshr_b64 s[4:5], s[4:5], s1281; GFX9-NEXT: s_mov_b32 s3, s0282; GFX9-NEXT: s_lshr_b32 s5, s0, 1283; GFX9-NEXT: s_lshr_b64 s[0:1], s[2:3], 1284; GFX9-NEXT: s_not_b32 s2, s8285; GFX9-NEXT: s_mov_b32 s1, s5286; GFX9-NEXT: s_and_b32 s2, s2, 31287; GFX9-NEXT: s_lshr_b64 s[0:1], s[0:1], s2288; GFX9-NEXT: v_mov_b32_e32 v0, s0289; GFX9-NEXT: v_mov_b32_e32 v1, s4290; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[6:7]291; GFX9-NEXT: s_endpgm292;293; R600-LABEL: fshl_v2i32:294; R600: ; %bb.0: ; %entry295; R600-NEXT: ALU 9, @4, KC0[CB0:0-32], KC1[]296; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1297; R600-NEXT: CF_END298; R600-NEXT: PAD299; R600-NEXT: ALU clause starting at 4:300; R600-NEXT: LSHR T0.Z, KC0[3].X, 1,301; R600-NEXT: BIT_ALIGN_INT * T0.W, KC0[3].X, KC0[3].Z, 1,302; R600-NEXT: NOT_INT * T1.W, KC0[4].X,303; R600-NEXT: BIT_ALIGN_INT T0.Y, T0.Z, T0.W, PV.W,304; R600-NEXT: LSHR T0.Z, KC0[2].W, 1,305; R600-NEXT: BIT_ALIGN_INT * T0.W, KC0[2].W, KC0[3].Y, 1,306; R600-NEXT: NOT_INT * T1.W, KC0[3].W,307; R600-NEXT: BIT_ALIGN_INT T0.X, T0.Z, T0.W, PV.W,308; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,309; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)310;311; GFX10-LABEL: fshl_v2i32:312; GFX10: ; %bb.0: ; %entry313; GFX10-NEXT: s_clause 0x2314; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c315; GFX10-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x3c316; GFX10-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x24317; GFX10-NEXT: v_mov_b32_e32 v2, 0318; GFX10-NEXT: s_waitcnt lgkmcnt(0)319; GFX10-NEXT: s_mov_b32 s4, s3320; GFX10-NEXT: s_mov_b32 s5, s1321; GFX10-NEXT: s_mov_b32 s3, s0322; GFX10-NEXT: s_lshr_b32 s10, s1, 1323; GFX10-NEXT: s_not_b32 s7, s7324; GFX10-NEXT: s_lshr_b32 s11, s0, 1325; GFX10-NEXT: s_not_b32 s6, s6326; GFX10-NEXT: s_lshr_b64 s[0:1], s[4:5], 1327; GFX10-NEXT: s_lshr_b64 s[2:3], s[2:3], 1328; GFX10-NEXT: s_and_b32 s4, s7, 31329; GFX10-NEXT: s_and_b32 s5, s6, 31330; GFX10-NEXT: s_mov_b32 s3, s11331; GFX10-NEXT: s_mov_b32 s1, s10332; GFX10-NEXT: s_lshr_b64 s[2:3], s[2:3], s5333; GFX10-NEXT: s_lshr_b64 s[0:1], s[0:1], s4334; GFX10-NEXT: v_mov_b32_e32 v0, s2335; GFX10-NEXT: v_mov_b32_e32 v1, s0336; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[8:9]337; GFX10-NEXT: s_endpgm338;339; GFX11-LABEL: fshl_v2i32:340; GFX11: ; %bb.0: ; %entry341; GFX11-NEXT: s_clause 0x2342; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x2c343; GFX11-NEXT: s_load_b64 s[6:7], s[4:5], 0x3c344; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x24345; GFX11-NEXT: s_waitcnt lgkmcnt(0)346; GFX11-NEXT: s_mov_b32 s8, s3347; GFX11-NEXT: s_mov_b32 s9, s1348; GFX11-NEXT: s_mov_b32 s3, s0349; GFX11-NEXT: s_lshr_b32 s10, s1, 1350; GFX11-NEXT: s_not_b32 s7, s7351; GFX11-NEXT: s_lshr_b32 s11, s0, 1352; GFX11-NEXT: s_not_b32 s6, s6353; GFX11-NEXT: s_lshr_b64 s[0:1], s[8:9], 1354; GFX11-NEXT: s_lshr_b64 s[2:3], s[2:3], 1355; GFX11-NEXT: s_and_b32 s7, s7, 31356; GFX11-NEXT: s_and_b32 s6, s6, 31357; GFX11-NEXT: s_mov_b32 s3, s11358; GFX11-NEXT: s_mov_b32 s1, s10359; GFX11-NEXT: s_lshr_b64 s[2:3], s[2:3], s6360; GFX11-NEXT: s_lshr_b64 s[0:1], s[0:1], s7361; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)362; GFX11-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s0363; GFX11-NEXT: v_mov_b32_e32 v0, s2364; GFX11-NEXT: global_store_b64 v2, v[0:1], s[4:5]365; GFX11-NEXT: s_endpgm366entry:367 %0 = call <2 x i32> @llvm.fshl.v2i32(<2 x i32> %x, <2 x i32> %y, <2 x i32> %z)368 store <2 x i32> %0, ptr addrspace(1) %in369 ret void370}371 372define amdgpu_kernel void @fshl_v2i32_imm(ptr addrspace(1) %in, <2 x i32> %x, <2 x i32> %y) {373; SI-LABEL: fshl_v2i32_imm:374; SI: ; %bb.0: ; %entry375; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xb376; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9377; SI-NEXT: s_mov_b32 s7, 0xf000378; SI-NEXT: s_mov_b32 s6, -1379; SI-NEXT: s_waitcnt lgkmcnt(0)380; SI-NEXT: s_mov_b32 s8, s3381; SI-NEXT: s_mov_b32 s9, s1382; SI-NEXT: s_mov_b32 s3, s0383; SI-NEXT: s_lshr_b64 s[8:9], s[8:9], 23384; SI-NEXT: s_lshr_b64 s[0:1], s[2:3], 25385; SI-NEXT: v_mov_b32_e32 v0, s0386; SI-NEXT: v_mov_b32_e32 v1, s8387; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0388; SI-NEXT: s_endpgm389;390; VI-LABEL: fshl_v2i32_imm:391; VI: ; %bb.0: ; %entry392; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c393; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24394; VI-NEXT: s_waitcnt lgkmcnt(0)395; VI-NEXT: s_mov_b32 s6, s3396; VI-NEXT: s_mov_b32 s7, s1397; VI-NEXT: s_mov_b32 s3, s0398; VI-NEXT: s_lshr_b64 s[0:1], s[6:7], 23399; VI-NEXT: s_lshr_b64 s[2:3], s[2:3], 25400; VI-NEXT: v_mov_b32_e32 v2, s4401; VI-NEXT: v_mov_b32_e32 v0, s2402; VI-NEXT: v_mov_b32_e32 v1, s0403; VI-NEXT: v_mov_b32_e32 v3, s5404; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]405; VI-NEXT: s_endpgm406;407; GFX9-LABEL: fshl_v2i32_imm:408; GFX9: ; %bb.0: ; %entry409; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c410; GFX9-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24411; GFX9-NEXT: v_mov_b32_e32 v2, 0412; GFX9-NEXT: s_waitcnt lgkmcnt(0)413; GFX9-NEXT: s_mov_b32 s4, s3414; GFX9-NEXT: s_mov_b32 s5, s1415; GFX9-NEXT: s_mov_b32 s3, s0416; GFX9-NEXT: s_lshr_b64 s[0:1], s[4:5], 23417; GFX9-NEXT: s_lshr_b64 s[2:3], s[2:3], 25418; GFX9-NEXT: v_mov_b32_e32 v0, s2419; GFX9-NEXT: v_mov_b32_e32 v1, s0420; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[6:7]421; GFX9-NEXT: s_endpgm422;423; R600-LABEL: fshl_v2i32_imm:424; R600: ; %bb.0: ; %entry425; R600-NEXT: ALU 5, @4, KC0[CB0:0-32], KC1[]426; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1427; R600-NEXT: CF_END428; R600-NEXT: PAD429; R600-NEXT: ALU clause starting at 4:430; R600-NEXT: BIT_ALIGN_INT * T0.Y, KC0[3].X, KC0[3].Z, literal.x,431; R600-NEXT: 23(3.222986e-44), 0(0.000000e+00)432; R600-NEXT: BIT_ALIGN_INT * T0.X, KC0[2].W, KC0[3].Y, literal.x,433; R600-NEXT: 25(3.503246e-44), 0(0.000000e+00)434; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,435; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)436;437; GFX10-LABEL: fshl_v2i32_imm:438; GFX10: ; %bb.0: ; %entry439; GFX10-NEXT: s_clause 0x1440; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c441; GFX10-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24442; GFX10-NEXT: v_mov_b32_e32 v2, 0443; GFX10-NEXT: s_waitcnt lgkmcnt(0)444; GFX10-NEXT: s_mov_b32 s4, s3445; GFX10-NEXT: s_mov_b32 s3, s0446; GFX10-NEXT: s_mov_b32 s5, s1447; GFX10-NEXT: s_lshr_b64 s[0:1], s[2:3], 25448; GFX10-NEXT: s_lshr_b64 s[2:3], s[4:5], 23449; GFX10-NEXT: v_mov_b32_e32 v0, s0450; GFX10-NEXT: v_mov_b32_e32 v1, s2451; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[6:7]452; GFX10-NEXT: s_endpgm453;454; GFX11-LABEL: fshl_v2i32_imm:455; GFX11: ; %bb.0: ; %entry456; GFX11-NEXT: s_clause 0x1457; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x2c458; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x24459; GFX11-NEXT: s_waitcnt lgkmcnt(0)460; GFX11-NEXT: s_mov_b32 s6, s3461; GFX11-NEXT: s_mov_b32 s3, s0462; GFX11-NEXT: s_mov_b32 s7, s1463; GFX11-NEXT: s_lshr_b64 s[0:1], s[2:3], 25464; GFX11-NEXT: s_lshr_b64 s[2:3], s[6:7], 23465; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)466; GFX11-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s2467; GFX11-NEXT: v_mov_b32_e32 v0, s0468; GFX11-NEXT: global_store_b64 v2, v[0:1], s[4:5]469; GFX11-NEXT: s_endpgm470entry:471 %0 = call <2 x i32> @llvm.fshl.v2i32(<2 x i32> %x, <2 x i32> %y, <2 x i32> <i32 7, i32 9>)472 store <2 x i32> %0, ptr addrspace(1) %in473 ret void474}475 476define amdgpu_kernel void @fshl_v4i32(ptr addrspace(1) %in, <4 x i32> %x, <4 x i32> %y, <4 x i32> %z) {477; SI-LABEL: fshl_v4i32:478; SI: ; %bb.0: ; %entry479; SI-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0xd480; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9481; SI-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x15482; SI-NEXT: s_mov_b32 s3, 0xf000483; SI-NEXT: s_mov_b32 s2, -1484; SI-NEXT: s_waitcnt lgkmcnt(0)485; SI-NEXT: s_mov_b32 s16, s15486; SI-NEXT: s_mov_b32 s17, s11487; SI-NEXT: s_lshr_b32 s18, s11, 1488; SI-NEXT: s_lshr_b64 s[16:17], s[16:17], 1489; SI-NEXT: s_not_b32 s7, s7490; SI-NEXT: s_mov_b32 s17, s18491; SI-NEXT: s_and_b32 s7, s7, 31492; SI-NEXT: s_mov_b32 s15, s10493; SI-NEXT: s_lshr_b64 s[16:17], s[16:17], s7494; SI-NEXT: s_lshr_b32 s7, s10, 1495; SI-NEXT: s_lshr_b64 s[10:11], s[14:15], 1496; SI-NEXT: s_not_b32 s6, s6497; SI-NEXT: s_mov_b32 s11, s7498; SI-NEXT: s_and_b32 s6, s6, 31499; SI-NEXT: s_lshr_b64 s[6:7], s[10:11], s6500; SI-NEXT: s_mov_b32 s10, s13501; SI-NEXT: s_mov_b32 s11, s9502; SI-NEXT: s_lshr_b32 s7, s9, 1503; SI-NEXT: s_lshr_b64 s[10:11], s[10:11], 1504; SI-NEXT: s_not_b32 s5, s5505; SI-NEXT: s_mov_b32 s11, s7506; SI-NEXT: s_and_b32 s5, s5, 31507; SI-NEXT: s_mov_b32 s13, s8508; SI-NEXT: s_lshr_b64 s[10:11], s[10:11], s5509; SI-NEXT: s_lshr_b32 s5, s8, 1510; SI-NEXT: s_lshr_b64 s[8:9], s[12:13], 1511; SI-NEXT: s_not_b32 s4, s4512; SI-NEXT: s_mov_b32 s9, s5513; SI-NEXT: s_and_b32 s4, s4, 31514; SI-NEXT: s_lshr_b64 s[4:5], s[8:9], s4515; SI-NEXT: v_mov_b32_e32 v0, s4516; SI-NEXT: v_mov_b32_e32 v1, s10517; SI-NEXT: v_mov_b32_e32 v2, s6518; SI-NEXT: v_mov_b32_e32 v3, s16519; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0520; SI-NEXT: s_endpgm521;522; VI-LABEL: fshl_v4i32:523; VI: ; %bb.0: ; %entry524; VI-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x34525; VI-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24526; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x54527; VI-NEXT: s_waitcnt lgkmcnt(0)528; VI-NEXT: s_mov_b32 s4, s15529; VI-NEXT: s_mov_b32 s5, s11530; VI-NEXT: s_lshr_b32 s16, s11, 1531; VI-NEXT: s_lshr_b64 s[4:5], s[4:5], 1532; VI-NEXT: s_not_b32 s3, s3533; VI-NEXT: s_mov_b32 s5, s16534; VI-NEXT: s_and_b32 s3, s3, 31535; VI-NEXT: s_mov_b32 s15, s10536; VI-NEXT: s_lshr_b64 s[4:5], s[4:5], s3537; VI-NEXT: s_lshr_b32 s3, s10, 1538; VI-NEXT: s_lshr_b64 s[10:11], s[14:15], 1539; VI-NEXT: s_not_b32 s2, s2540; VI-NEXT: s_mov_b32 s11, s3541; VI-NEXT: s_and_b32 s2, s2, 31542; VI-NEXT: s_lshr_b64 s[2:3], s[10:11], s2543; VI-NEXT: s_mov_b32 s10, s13544; VI-NEXT: s_mov_b32 s11, s9545; VI-NEXT: s_lshr_b32 s3, s9, 1546; VI-NEXT: s_lshr_b64 s[10:11], s[10:11], 1547; VI-NEXT: s_not_b32 s1, s1548; VI-NEXT: s_mov_b32 s11, s3549; VI-NEXT: s_and_b32 s1, s1, 31550; VI-NEXT: s_mov_b32 s13, s8551; VI-NEXT: s_lshr_b64 s[10:11], s[10:11], s1552; VI-NEXT: s_lshr_b32 s1, s8, 1553; VI-NEXT: s_lshr_b64 s[8:9], s[12:13], 1554; VI-NEXT: s_not_b32 s0, s0555; VI-NEXT: s_mov_b32 s9, s1556; VI-NEXT: s_and_b32 s0, s0, 31557; VI-NEXT: s_lshr_b64 s[0:1], s[8:9], s0558; VI-NEXT: v_mov_b32_e32 v4, s6559; VI-NEXT: v_mov_b32_e32 v0, s0560; VI-NEXT: v_mov_b32_e32 v1, s10561; VI-NEXT: v_mov_b32_e32 v2, s2562; VI-NEXT: v_mov_b32_e32 v3, s4563; VI-NEXT: v_mov_b32_e32 v5, s7564; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]565; VI-NEXT: s_endpgm566;567; GFX9-LABEL: fshl_v4i32:568; GFX9: ; %bb.0: ; %entry569; GFX9-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x34570; GFX9-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24571; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x54572; GFX9-NEXT: v_mov_b32_e32 v4, 0573; GFX9-NEXT: s_waitcnt lgkmcnt(0)574; GFX9-NEXT: s_mov_b32 s4, s15575; GFX9-NEXT: s_mov_b32 s5, s11576; GFX9-NEXT: s_lshr_b32 s16, s11, 1577; GFX9-NEXT: s_lshr_b64 s[4:5], s[4:5], 1578; GFX9-NEXT: s_not_b32 s3, s3579; GFX9-NEXT: s_mov_b32 s5, s16580; GFX9-NEXT: s_and_b32 s3, s3, 31581; GFX9-NEXT: s_mov_b32 s15, s10582; GFX9-NEXT: s_lshr_b64 s[4:5], s[4:5], s3583; GFX9-NEXT: s_lshr_b32 s3, s10, 1584; GFX9-NEXT: s_lshr_b64 s[10:11], s[14:15], 1585; GFX9-NEXT: s_not_b32 s2, s2586; GFX9-NEXT: s_mov_b32 s11, s3587; GFX9-NEXT: s_and_b32 s2, s2, 31588; GFX9-NEXT: s_lshr_b64 s[2:3], s[10:11], s2589; GFX9-NEXT: s_mov_b32 s10, s13590; GFX9-NEXT: s_mov_b32 s11, s9591; GFX9-NEXT: s_lshr_b32 s3, s9, 1592; GFX9-NEXT: s_lshr_b64 s[10:11], s[10:11], 1593; GFX9-NEXT: s_not_b32 s1, s1594; GFX9-NEXT: s_mov_b32 s11, s3595; GFX9-NEXT: s_and_b32 s1, s1, 31596; GFX9-NEXT: s_mov_b32 s13, s8597; GFX9-NEXT: s_lshr_b64 s[10:11], s[10:11], s1598; GFX9-NEXT: s_lshr_b32 s1, s8, 1599; GFX9-NEXT: s_lshr_b64 s[8:9], s[12:13], 1600; GFX9-NEXT: s_not_b32 s0, s0601; GFX9-NEXT: s_mov_b32 s9, s1602; GFX9-NEXT: s_and_b32 s0, s0, 31603; GFX9-NEXT: s_lshr_b64 s[0:1], s[8:9], s0604; GFX9-NEXT: v_mov_b32_e32 v0, s0605; GFX9-NEXT: v_mov_b32_e32 v1, s10606; GFX9-NEXT: v_mov_b32_e32 v2, s2607; GFX9-NEXT: v_mov_b32_e32 v3, s4608; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[6:7]609; GFX9-NEXT: s_endpgm610;611; R600-LABEL: fshl_v4i32:612; R600: ; %bb.0: ; %entry613; R600-NEXT: ALU 17, @4, KC0[CB0:0-32], KC1[]614; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1615; R600-NEXT: CF_END616; R600-NEXT: PAD617; R600-NEXT: ALU clause starting at 4:618; R600-NEXT: LSHR T0.Z, KC0[4].X, 1,619; R600-NEXT: BIT_ALIGN_INT * T0.W, KC0[4].X, KC0[5].X, 1,620; R600-NEXT: NOT_INT * T1.W, KC0[6].X,621; R600-NEXT: LSHR T0.Y, KC0[3].W, 1,622; R600-NEXT: BIT_ALIGN_INT T1.Z, KC0[3].W, KC0[4].W, 1,623; R600-NEXT: BIT_ALIGN_INT * T0.W, T0.Z, T0.W, PV.W,624; R600-NEXT: NOT_INT * T1.W, KC0[5].W,625; R600-NEXT: LSHR T1.Y, KC0[3].Z, 1,626; R600-NEXT: BIT_ALIGN_INT T0.Z, T0.Y, T1.Z, PV.W,627; R600-NEXT: BIT_ALIGN_INT * T1.W, KC0[3].Z, KC0[4].Z, 1,628; R600-NEXT: NOT_INT * T2.W, KC0[5].Z,629; R600-NEXT: BIT_ALIGN_INT T0.Y, T1.Y, T1.W, PV.W,630; R600-NEXT: LSHR T1.Z, KC0[3].Y, 1,631; R600-NEXT: BIT_ALIGN_INT * T1.W, KC0[3].Y, KC0[4].Y, 1,632; R600-NEXT: NOT_INT * T2.W, KC0[5].Y,633; R600-NEXT: BIT_ALIGN_INT T0.X, T1.Z, T1.W, PV.W,634; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,635; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)636;637; GFX10-LABEL: fshl_v4i32:638; GFX10: ; %bb.0: ; %entry639; GFX10-NEXT: s_clause 0x2640; GFX10-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x34641; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x54642; GFX10-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24643; GFX10-NEXT: v_mov_b32_e32 v4, 0644; GFX10-NEXT: s_waitcnt lgkmcnt(0)645; GFX10-NEXT: s_mov_b32 s4, s15646; GFX10-NEXT: s_mov_b32 s5, s11647; GFX10-NEXT: s_mov_b32 s15, s10648; GFX10-NEXT: s_lshr_b32 s16, s11, 1649; GFX10-NEXT: s_not_b32 s11, s3650; GFX10-NEXT: s_lshr_b32 s17, s10, 1651; GFX10-NEXT: s_not_b32 s10, s2652; GFX10-NEXT: s_lshr_b32 s18, s9, 1653; GFX10-NEXT: s_mov_b32 s2, s13654; GFX10-NEXT: s_mov_b32 s3, s9655; GFX10-NEXT: s_lshr_b32 s19, s8, 1656; GFX10-NEXT: s_mov_b32 s13, s8657; GFX10-NEXT: s_lshr_b64 s[4:5], s[4:5], 1658; GFX10-NEXT: s_lshr_b64 s[8:9], s[14:15], 1659; GFX10-NEXT: s_and_b32 s11, s11, 31660; GFX10-NEXT: s_and_b32 s10, s10, 31661; GFX10-NEXT: s_mov_b32 s5, s16662; GFX10-NEXT: s_mov_b32 s9, s17663; GFX10-NEXT: s_not_b32 s1, s1664; GFX10-NEXT: s_not_b32 s0, s0665; GFX10-NEXT: s_lshr_b64 s[2:3], s[2:3], 1666; GFX10-NEXT: s_lshr_b64 s[4:5], s[4:5], s11667; GFX10-NEXT: s_lshr_b64 s[8:9], s[8:9], s10668; GFX10-NEXT: s_lshr_b64 s[10:11], s[12:13], 1669; GFX10-NEXT: s_mov_b32 s3, s18670; GFX10-NEXT: s_mov_b32 s11, s19671; GFX10-NEXT: s_and_b32 s0, s0, 31672; GFX10-NEXT: s_and_b32 s5, s1, 31673; GFX10-NEXT: s_lshr_b64 s[0:1], s[10:11], s0674; GFX10-NEXT: s_lshr_b64 s[2:3], s[2:3], s5675; GFX10-NEXT: v_mov_b32_e32 v0, s0676; GFX10-NEXT: v_mov_b32_e32 v1, s2677; GFX10-NEXT: v_mov_b32_e32 v2, s8678; GFX10-NEXT: v_mov_b32_e32 v3, s4679; GFX10-NEXT: global_store_dwordx4 v4, v[0:3], s[6:7]680; GFX10-NEXT: s_endpgm681;682; GFX11-LABEL: fshl_v4i32:683; GFX11: ; %bb.0: ; %entry684; GFX11-NEXT: s_clause 0x2685; GFX11-NEXT: s_load_b256 s[8:15], s[4:5], 0x34686; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x54687; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x24688; GFX11-NEXT: s_waitcnt lgkmcnt(0)689; GFX11-NEXT: s_mov_b32 s6, s15690; GFX11-NEXT: s_mov_b32 s7, s11691; GFX11-NEXT: s_mov_b32 s15, s10692; GFX11-NEXT: s_lshr_b32 s16, s11, 1693; GFX11-NEXT: s_not_b32 s11, s3694; GFX11-NEXT: s_lshr_b32 s17, s10, 1695; GFX11-NEXT: s_not_b32 s10, s2696; GFX11-NEXT: s_lshr_b32 s18, s9, 1697; GFX11-NEXT: s_mov_b32 s2, s13698; GFX11-NEXT: s_mov_b32 s3, s9699; GFX11-NEXT: s_lshr_b32 s19, s8, 1700; GFX11-NEXT: s_mov_b32 s13, s8701; GFX11-NEXT: s_lshr_b64 s[6:7], s[6:7], 1702; GFX11-NEXT: s_lshr_b64 s[8:9], s[14:15], 1703; GFX11-NEXT: s_and_b32 s11, s11, 31704; GFX11-NEXT: s_and_b32 s10, s10, 31705; GFX11-NEXT: s_mov_b32 s7, s16706; GFX11-NEXT: s_mov_b32 s9, s17707; GFX11-NEXT: s_not_b32 s1, s1708; GFX11-NEXT: s_not_b32 s0, s0709; GFX11-NEXT: s_lshr_b64 s[2:3], s[2:3], 1710; GFX11-NEXT: s_lshr_b64 s[6:7], s[6:7], s11711; GFX11-NEXT: s_lshr_b64 s[8:9], s[8:9], s10712; GFX11-NEXT: s_lshr_b64 s[10:11], s[12:13], 1713; GFX11-NEXT: s_mov_b32 s3, s18714; GFX11-NEXT: s_mov_b32 s11, s19715; GFX11-NEXT: s_and_b32 s0, s0, 31716; GFX11-NEXT: s_and_b32 s7, s1, 31717; GFX11-NEXT: s_lshr_b64 s[0:1], s[10:11], s0718; GFX11-NEXT: s_lshr_b64 s[2:3], s[2:3], s7719; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)720; GFX11-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v1, s2721; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s6722; GFX11-NEXT: v_mov_b32_e32 v2, s8723; GFX11-NEXT: global_store_b128 v4, v[0:3], s[4:5]724; GFX11-NEXT: s_endpgm725entry:726 %0 = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z)727 store <4 x i32> %0, ptr addrspace(1) %in728 ret void729}730 731define amdgpu_kernel void @fshl_v4i32_imm(ptr addrspace(1) %in, <4 x i32> %x, <4 x i32> %y) {732; SI-LABEL: fshl_v4i32_imm:733; SI: ; %bb.0: ; %entry734; SI-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0xd735; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9736; SI-NEXT: s_mov_b32 s3, 0xf000737; SI-NEXT: s_mov_b32 s2, -1738; SI-NEXT: s_waitcnt lgkmcnt(0)739; SI-NEXT: s_mov_b32 s4, s15740; SI-NEXT: s_mov_b32 s5, s11741; SI-NEXT: s_mov_b32 s15, s10742; SI-NEXT: s_mov_b32 s10, s13743; SI-NEXT: s_mov_b32 s11, s9744; SI-NEXT: s_mov_b32 s13, s8745; SI-NEXT: s_lshr_b64 s[4:5], s[4:5], 31746; SI-NEXT: s_lshr_b64 s[6:7], s[14:15], 23747; SI-NEXT: s_lshr_b64 s[10:11], s[10:11], 25748; SI-NEXT: s_lshr_b64 s[8:9], s[12:13], 31749; SI-NEXT: v_mov_b32_e32 v0, s8750; SI-NEXT: v_mov_b32_e32 v1, s10751; SI-NEXT: v_mov_b32_e32 v2, s6752; SI-NEXT: v_mov_b32_e32 v3, s4753; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0754; SI-NEXT: s_endpgm755;756; VI-LABEL: fshl_v4i32_imm:757; VI: ; %bb.0: ; %entry758; VI-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x34759; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24760; VI-NEXT: s_waitcnt lgkmcnt(0)761; VI-NEXT: s_mov_b32 s2, s15762; VI-NEXT: s_mov_b32 s3, s11763; VI-NEXT: s_mov_b32 s15, s10764; VI-NEXT: s_mov_b32 s6, s13765; VI-NEXT: s_mov_b32 s7, s9766; VI-NEXT: s_mov_b32 s13, s8767; VI-NEXT: s_lshr_b64 s[2:3], s[2:3], 31768; VI-NEXT: s_lshr_b64 s[4:5], s[14:15], 23769; VI-NEXT: s_lshr_b64 s[6:7], s[6:7], 25770; VI-NEXT: s_lshr_b64 s[8:9], s[12:13], 31771; VI-NEXT: v_mov_b32_e32 v5, s1772; VI-NEXT: v_mov_b32_e32 v0, s8773; VI-NEXT: v_mov_b32_e32 v1, s6774; VI-NEXT: v_mov_b32_e32 v2, s4775; VI-NEXT: v_mov_b32_e32 v3, s2776; VI-NEXT: v_mov_b32_e32 v4, s0777; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]778; VI-NEXT: s_endpgm779;780; GFX9-LABEL: fshl_v4i32_imm:781; GFX9: ; %bb.0: ; %entry782; GFX9-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x34783; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24784; GFX9-NEXT: v_mov_b32_e32 v4, 0785; GFX9-NEXT: s_waitcnt lgkmcnt(0)786; GFX9-NEXT: s_mov_b32 s2, s15787; GFX9-NEXT: s_mov_b32 s3, s11788; GFX9-NEXT: s_mov_b32 s15, s10789; GFX9-NEXT: s_mov_b32 s6, s13790; GFX9-NEXT: s_mov_b32 s7, s9791; GFX9-NEXT: s_mov_b32 s13, s8792; GFX9-NEXT: s_lshr_b64 s[2:3], s[2:3], 31793; GFX9-NEXT: s_lshr_b64 s[4:5], s[14:15], 23794; GFX9-NEXT: s_lshr_b64 s[6:7], s[6:7], 25795; GFX9-NEXT: s_lshr_b64 s[8:9], s[12:13], 31796; GFX9-NEXT: v_mov_b32_e32 v0, s8797; GFX9-NEXT: v_mov_b32_e32 v1, s6798; GFX9-NEXT: v_mov_b32_e32 v2, s4799; GFX9-NEXT: v_mov_b32_e32 v3, s2800; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]801; GFX9-NEXT: s_endpgm802;803; R600-LABEL: fshl_v4i32_imm:804; R600: ; %bb.0: ; %entry805; R600-NEXT: ALU 9, @4, KC0[CB0:0-32], KC1[]806; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1807; R600-NEXT: CF_END808; R600-NEXT: PAD809; R600-NEXT: ALU clause starting at 4:810; R600-NEXT: BIT_ALIGN_INT * T0.W, KC0[4].X, KC0[5].X, literal.x,811; R600-NEXT: 31(4.344025e-44), 0(0.000000e+00)812; R600-NEXT: BIT_ALIGN_INT * T0.Z, KC0[3].W, KC0[4].W, literal.x,813; R600-NEXT: 23(3.222986e-44), 0(0.000000e+00)814; R600-NEXT: BIT_ALIGN_INT * T0.Y, KC0[3].Z, KC0[4].Z, literal.x,815; R600-NEXT: 25(3.503246e-44), 0(0.000000e+00)816; R600-NEXT: BIT_ALIGN_INT * T0.X, KC0[3].Y, KC0[4].Y, literal.x,817; R600-NEXT: 31(4.344025e-44), 0(0.000000e+00)818; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,819; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)820;821; GFX10-LABEL: fshl_v4i32_imm:822; GFX10: ; %bb.0: ; %entry823; GFX10-NEXT: s_clause 0x1824; GFX10-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x34825; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24826; GFX10-NEXT: v_mov_b32_e32 v4, 0827; GFX10-NEXT: s_waitcnt lgkmcnt(0)828; GFX10-NEXT: s_mov_b32 s2, s15829; GFX10-NEXT: s_mov_b32 s3, s11830; GFX10-NEXT: s_mov_b32 s15, s10831; GFX10-NEXT: s_mov_b32 s4, s13832; GFX10-NEXT: s_mov_b32 s5, s9833; GFX10-NEXT: s_mov_b32 s13, s8834; GFX10-NEXT: s_lshr_b64 s[2:3], s[2:3], 31835; GFX10-NEXT: s_lshr_b64 s[6:7], s[14:15], 23836; GFX10-NEXT: s_lshr_b64 s[8:9], s[12:13], 31837; GFX10-NEXT: s_lshr_b64 s[4:5], s[4:5], 25838; GFX10-NEXT: v_mov_b32_e32 v0, s8839; GFX10-NEXT: v_mov_b32_e32 v1, s4840; GFX10-NEXT: v_mov_b32_e32 v2, s6841; GFX10-NEXT: v_mov_b32_e32 v3, s2842; GFX10-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]843; GFX10-NEXT: s_endpgm844;845; GFX11-LABEL: fshl_v4i32_imm:846; GFX11: ; %bb.0: ; %entry847; GFX11-NEXT: s_clause 0x1848; GFX11-NEXT: s_load_b256 s[8:15], s[4:5], 0x34849; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24850; GFX11-NEXT: s_waitcnt lgkmcnt(0)851; GFX11-NEXT: s_mov_b32 s2, s15852; GFX11-NEXT: s_mov_b32 s3, s11853; GFX11-NEXT: s_mov_b32 s15, s10854; GFX11-NEXT: s_mov_b32 s4, s13855; GFX11-NEXT: s_mov_b32 s5, s9856; GFX11-NEXT: s_mov_b32 s13, s8857; GFX11-NEXT: s_lshr_b64 s[2:3], s[2:3], 31858; GFX11-NEXT: s_lshr_b64 s[6:7], s[14:15], 23859; GFX11-NEXT: s_lshr_b64 s[8:9], s[12:13], 31860; GFX11-NEXT: s_lshr_b64 s[4:5], s[4:5], 25861; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)862; GFX11-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v1, s4863; GFX11-NEXT: v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v3, s2864; GFX11-NEXT: v_mov_b32_e32 v2, s6865; GFX11-NEXT: global_store_b128 v4, v[0:3], s[0:1]866; GFX11-NEXT: s_endpgm867entry:868 %0 = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i32> <i32 1, i32 7, i32 9, i32 33>)869 store <4 x i32> %0, ptr addrspace(1) %in870 ret void871}872 873; (a ^ b) | a --> a | b874define amdgpu_kernel void @orxor2or1(ptr addrspace(1) %in, i32 %a, i32 %b) {875; SI-LABEL: orxor2or1:876; SI: ; %bb.0:877; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9878; SI-NEXT: s_waitcnt lgkmcnt(0)879; SI-NEXT: s_mov_b64 s[4:5], s[2:3]880; SI-NEXT: s_lshl_b32 s6, s4, 7881; SI-NEXT: s_or_b32 s6, s5, s6882; SI-NEXT: s_cmp_eq_u32 s6, 0883; SI-NEXT: s_cselect_b32 s4, s4, s5884; SI-NEXT: s_mov_b32 s3, 0xf000885; SI-NEXT: s_mov_b32 s2, -1886; SI-NEXT: v_mov_b32_e32 v0, s4887; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0888; SI-NEXT: s_endpgm889;890; VI-LABEL: orxor2or1:891; VI: ; %bb.0:892; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24893; VI-NEXT: s_waitcnt lgkmcnt(0)894; VI-NEXT: s_lshl_b32 s4, s2, 7895; VI-NEXT: s_or_b32 s4, s3, s4896; VI-NEXT: s_cmp_eq_u32 s4, 0897; VI-NEXT: s_cselect_b32 s2, s2, s3898; VI-NEXT: v_mov_b32_e32 v0, s0899; VI-NEXT: v_mov_b32_e32 v1, s1900; VI-NEXT: v_mov_b32_e32 v2, s2901; VI-NEXT: flat_store_dword v[0:1], v2902; VI-NEXT: s_endpgm903;904; GFX9-LABEL: orxor2or1:905; GFX9: ; %bb.0:906; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24907; GFX9-NEXT: v_mov_b32_e32 v0, 0908; GFX9-NEXT: s_waitcnt lgkmcnt(0)909; GFX9-NEXT: s_lshl_b32 s4, s2, 7910; GFX9-NEXT: s_or_b32 s4, s3, s4911; GFX9-NEXT: s_cmp_eq_u32 s4, 0912; GFX9-NEXT: s_cselect_b32 s2, s2, s3913; GFX9-NEXT: v_mov_b32_e32 v1, s2914; GFX9-NEXT: global_store_dword v0, v1, s[0:1]915; GFX9-NEXT: s_endpgm916;917; R600-LABEL: orxor2or1:918; R600: ; %bb.0:919; R600-NEXT: ALU 5, @4, KC0[CB0:0-32], KC1[]920; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1921; R600-NEXT: CF_END922; R600-NEXT: PAD923; R600-NEXT: ALU clause starting at 4:924; R600-NEXT: LSHL * T0.W, KC0[2].Z, literal.x,925; R600-NEXT: 7(9.809089e-45), 0(0.000000e+00)926; R600-NEXT: OR_INT * T0.W, KC0[2].W, PV.W,927; R600-NEXT: CNDE_INT T0.X, PV.W, KC0[2].Z, KC0[2].W,928; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,929; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)930;931; GFX10-LABEL: orxor2or1:932; GFX10: ; %bb.0:933; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24934; GFX10-NEXT: v_mov_b32_e32 v0, 0935; GFX10-NEXT: s_waitcnt lgkmcnt(0)936; GFX10-NEXT: s_lshl_b32 s4, s2, 7937; GFX10-NEXT: s_or_b32 s4, s3, s4938; GFX10-NEXT: s_cmp_eq_u32 s4, 0939; GFX10-NEXT: s_cselect_b32 s2, s2, s3940; GFX10-NEXT: v_mov_b32_e32 v1, s2941; GFX10-NEXT: global_store_dword v0, v1, s[0:1]942; GFX10-NEXT: s_endpgm943;944; GFX11-LABEL: orxor2or1:945; GFX11: ; %bb.0:946; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24947; GFX11-NEXT: s_waitcnt lgkmcnt(0)948; GFX11-NEXT: s_lshl_b32 s4, s2, 7949; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)950; GFX11-NEXT: s_or_b32 s4, s3, s4951; GFX11-NEXT: s_cmp_eq_u32 s4, 0952; GFX11-NEXT: s_cselect_b32 s2, s2, s3953; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)954; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2955; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]956; GFX11-NEXT: s_endpgm957 %shl = shl i32 %a, 7958 %xor = xor i32 %shl, %b959 %or = or i32 %a, %xor960 %fshl = call i32 @llvm.fshl.i32(i32 %or, i32 %xor, i32 7)961 %cond = icmp eq i32 %fshl, 0962 %r = select i1 %cond, i32 %a, i32 %b963 store i32 %r, ptr addrspace(1) %in964 ret void965}966