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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=amdgcn -mcpu=tahiti | FileCheck %s -check-prefixes=GFX89,SI3; RUN: llc < %s -mtriple=amdgcn -mcpu=tonga  | FileCheck %s -check-prefixes=GFX89,VI4; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx900 | FileCheck %s -check-prefixes=GFX89,GFX95; RUN: llc < %s -mtriple=r600 -mcpu=redwood  | FileCheck %s --check-prefix=R6006; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1010 | FileCheck %s -check-prefixes=GFX107; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 | FileCheck %s -check-prefixes=GFX11,GFX11-TRUE168; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 | FileCheck %s -check-prefixes=GFX11,GFX11-FAKE169; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 | FileCheck %s -check-prefixes=GFX12,GFX12-TRUE1610; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 | FileCheck %s -check-prefixes=GFX12,GFX12-FAKE1611 12declare i32 @llvm.fshr.i32(i32, i32, i32)13declare <2 x i32> @llvm.fshr.v2i32(<2 x i32>, <2 x i32>, <2 x i32>)14declare <3 x i32> @llvm.fshr.v3i32(<3 x i32>, <3 x i32>, <3 x i32>)15declare <4 x i32> @llvm.fshr.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)16declare i16 @llvm.fshr.i16(i16, i16, i16)17declare <2 x i16> @llvm.fshr.v2i16(<2 x i16>, <2 x i16>, <2 x i16>)18declare <3 x i16> @llvm.fshr.v3i16(<3 x i16>, <3 x i16>, <3 x i16>)19declare <4 x i16> @llvm.fshr.v4i16(<4 x i16>, <4 x i16>, <4 x i16>)20declare i64 @llvm.fshr.i64(i64, i64, i64)21declare <2 x i64> @llvm.fshr.v2i64(<2 x i64>, <2 x i64>, <2 x i64>)22declare i24 @llvm.fshr.i24(i24, i24, i24)23declare <2 x i24> @llvm.fshr.v2i24(<2 x i24>, <2 x i24>, <2 x i24>)24 25define amdgpu_kernel void @fshr_i32(ptr addrspace(1) %in, i32 %x, i32 %y, i32 %z) {26; SI-LABEL: fshr_i32:27; SI:       ; %bb.0: ; %entry28; SI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0xb29; SI-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x930; SI-NEXT:    s_mov_b32 s7, 0xf00031; SI-NEXT:    s_mov_b32 s6, -132; SI-NEXT:    s_waitcnt lgkmcnt(0)33; SI-NEXT:    s_mov_b32 s8, s134; SI-NEXT:    s_mov_b32 s9, s035; SI-NEXT:    s_and_b32 s0, s2, 3136; SI-NEXT:    s_lshr_b64 s[0:1], s[8:9], s037; SI-NEXT:    v_mov_b32_e32 v0, s038; SI-NEXT:    buffer_store_dword v0, off, s[4:7], 039; SI-NEXT:    s_endpgm40;41; VI-LABEL: fshr_i32:42; VI:       ; %bb.0: ; %entry43; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x2c44; VI-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2445; VI-NEXT:    s_waitcnt lgkmcnt(0)46; VI-NEXT:    s_mov_b32 s6, s147; VI-NEXT:    s_mov_b32 s7, s048; VI-NEXT:    s_and_b32 s0, s2, 3149; VI-NEXT:    s_lshr_b64 s[0:1], s[6:7], s050; VI-NEXT:    v_mov_b32_e32 v0, s451; VI-NEXT:    v_mov_b32_e32 v1, s552; VI-NEXT:    v_mov_b32_e32 v2, s053; VI-NEXT:    flat_store_dword v[0:1], v254; VI-NEXT:    s_endpgm55;56; GFX9-LABEL: fshr_i32:57; GFX9:       ; %bb.0: ; %entry58; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x2c59; GFX9-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x2460; GFX9-NEXT:    v_mov_b32_e32 v0, 061; GFX9-NEXT:    s_waitcnt lgkmcnt(0)62; GFX9-NEXT:    s_mov_b32 s4, s163; GFX9-NEXT:    s_mov_b32 s5, s064; GFX9-NEXT:    s_and_b32 s0, s2, 3165; GFX9-NEXT:    s_lshr_b64 s[0:1], s[4:5], s066; GFX9-NEXT:    v_mov_b32_e32 v1, s067; GFX9-NEXT:    global_store_dword v0, v1, s[6:7]68; GFX9-NEXT:    s_endpgm69;70; R600-LABEL: fshr_i32:71; R600:       ; %bb.0: ; %entry72; R600-NEXT:    ALU 2, @4, KC0[CB0:0-32], KC1[]73; R600-NEXT:    MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 174; R600-NEXT:    CF_END75; R600-NEXT:    PAD76; R600-NEXT:    ALU clause starting at 4:77; R600-NEXT:     LSHR * T0.X, KC0[2].Y, literal.x,78; R600-NEXT:    2(2.802597e-45), 0(0.000000e+00)79; R600-NEXT:     BIT_ALIGN_INT * T1.X, KC0[2].Z, KC0[2].W, KC0[3].X,80;81; GFX10-LABEL: fshr_i32:82; GFX10:       ; %bb.0: ; %entry83; GFX10-NEXT:    s_clause 0x184; GFX10-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x2c85; GFX10-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x2486; GFX10-NEXT:    v_mov_b32_e32 v0, 087; GFX10-NEXT:    s_waitcnt lgkmcnt(0)88; GFX10-NEXT:    s_mov_b32 s4, s189; GFX10-NEXT:    s_mov_b32 s5, s090; GFX10-NEXT:    s_and_b32 s0, s2, 3191; GFX10-NEXT:    s_lshr_b64 s[0:1], s[4:5], s092; GFX10-NEXT:    v_mov_b32_e32 v1, s093; GFX10-NEXT:    global_store_dword v0, v1, s[6:7]94; GFX10-NEXT:    s_endpgm95;96; GFX11-LABEL: fshr_i32:97; GFX11:       ; %bb.0: ; %entry98; GFX11-NEXT:    s_clause 0x199; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x2c100; GFX11-NEXT:    s_load_b64 s[4:5], s[4:5], 0x24101; GFX11-NEXT:    s_waitcnt lgkmcnt(0)102; GFX11-NEXT:    s_mov_b32 s6, s1103; GFX11-NEXT:    s_mov_b32 s7, s0104; GFX11-NEXT:    s_and_b32 s0, s2, 31105; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)106; GFX11-NEXT:    s_lshr_b64 s[0:1], s[6:7], s0107; GFX11-NEXT:    v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0108; GFX11-NEXT:    global_store_b32 v0, v1, s[4:5]109; GFX11-NEXT:    s_endpgm110;111; GFX12-LABEL: fshr_i32:112; GFX12:       ; %bb.0: ; %entry113; GFX12-NEXT:    s_clause 0x1114; GFX12-NEXT:    s_load_b96 s[0:2], s[4:5], 0x2c115; GFX12-NEXT:    s_load_b64 s[4:5], s[4:5], 0x24116; GFX12-NEXT:    s_wait_kmcnt 0x0117; GFX12-NEXT:    s_mov_b32 s6, s1118; GFX12-NEXT:    s_mov_b32 s7, s0119; GFX12-NEXT:    s_and_b32 s0, s2, 31120; GFX12-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)121; GFX12-NEXT:    s_lshr_b64 s[0:1], s[6:7], s0122; GFX12-NEXT:    v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0123; GFX12-NEXT:    global_store_b32 v0, v1, s[4:5]124; GFX12-NEXT:    s_endpgm125entry:126  %0 = call i32 @llvm.fshr.i32(i32 %x, i32 %y, i32 %z)127  store i32 %0, ptr addrspace(1) %in128  ret void129}130 131define amdgpu_kernel void @fshr_i32_imm(ptr addrspace(1) %in, i32 %x, i32 %y) {132; SI-LABEL: fshr_i32_imm:133; SI:       ; %bb.0: ; %entry134; SI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x9135; SI-NEXT:    s_mov_b32 s7, 0xf000136; SI-NEXT:    s_mov_b32 s6, -1137; SI-NEXT:    s_waitcnt lgkmcnt(0)138; SI-NEXT:    s_mov_b32 s4, s0139; SI-NEXT:    s_mov_b32 s5, s1140; SI-NEXT:    s_mov_b32 s0, s3141; SI-NEXT:    s_mov_b32 s1, s2142; SI-NEXT:    s_lshr_b64 s[0:1], s[0:1], 7143; SI-NEXT:    v_mov_b32_e32 v0, s0144; SI-NEXT:    buffer_store_dword v0, off, s[4:7], 0145; SI-NEXT:    s_endpgm146;147; VI-LABEL: fshr_i32_imm:148; VI:       ; %bb.0: ; %entry149; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24150; VI-NEXT:    s_waitcnt lgkmcnt(0)151; VI-NEXT:    s_mov_b32 s4, s3152; VI-NEXT:    s_mov_b32 s5, s2153; VI-NEXT:    s_lshr_b64 s[2:3], s[4:5], 7154; VI-NEXT:    v_mov_b32_e32 v0, s0155; VI-NEXT:    v_mov_b32_e32 v1, s1156; VI-NEXT:    v_mov_b32_e32 v2, s2157; VI-NEXT:    flat_store_dword v[0:1], v2158; VI-NEXT:    s_endpgm159;160; GFX9-LABEL: fshr_i32_imm:161; GFX9:       ; %bb.0: ; %entry162; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24163; GFX9-NEXT:    v_mov_b32_e32 v0, 0164; GFX9-NEXT:    s_waitcnt lgkmcnt(0)165; GFX9-NEXT:    s_mov_b32 s4, s3166; GFX9-NEXT:    s_mov_b32 s5, s2167; GFX9-NEXT:    s_lshr_b64 s[2:3], s[4:5], 7168; GFX9-NEXT:    v_mov_b32_e32 v1, s2169; GFX9-NEXT:    global_store_dword v0, v1, s[0:1]170; GFX9-NEXT:    s_endpgm171;172; R600-LABEL: fshr_i32_imm:173; R600:       ; %bb.0: ; %entry174; R600-NEXT:    ALU 3, @4, KC0[CB0:0-32], KC1[]175; R600-NEXT:    MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1176; R600-NEXT:    CF_END177; R600-NEXT:    PAD178; R600-NEXT:    ALU clause starting at 4:179; R600-NEXT:     LSHR * T0.X, KC0[2].Y, literal.x,180; R600-NEXT:    2(2.802597e-45), 0(0.000000e+00)181; R600-NEXT:     BIT_ALIGN_INT * T1.X, KC0[2].Z, KC0[2].W, literal.x,182; R600-NEXT:    7(9.809089e-45), 0(0.000000e+00)183;184; GFX10-LABEL: fshr_i32_imm:185; GFX10:       ; %bb.0: ; %entry186; GFX10-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24187; GFX10-NEXT:    v_mov_b32_e32 v0, 0188; GFX10-NEXT:    s_waitcnt lgkmcnt(0)189; GFX10-NEXT:    s_mov_b32 s4, s3190; GFX10-NEXT:    s_mov_b32 s5, s2191; GFX10-NEXT:    s_lshr_b64 s[2:3], s[4:5], 7192; GFX10-NEXT:    v_mov_b32_e32 v1, s2193; GFX10-NEXT:    global_store_dword v0, v1, s[0:1]194; GFX10-NEXT:    s_endpgm195;196; GFX11-LABEL: fshr_i32_imm:197; GFX11:       ; %bb.0: ; %entry198; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24199; GFX11-NEXT:    s_waitcnt lgkmcnt(0)200; GFX11-NEXT:    s_mov_b32 s4, s3201; GFX11-NEXT:    s_mov_b32 s5, s2202; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)203; GFX11-NEXT:    s_lshr_b64 s[2:3], s[4:5], 7204; GFX11-NEXT:    v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2205; GFX11-NEXT:    global_store_b32 v0, v1, s[0:1]206; GFX11-NEXT:    s_endpgm207;208; GFX12-LABEL: fshr_i32_imm:209; GFX12:       ; %bb.0: ; %entry210; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24211; GFX12-NEXT:    s_wait_kmcnt 0x0212; GFX12-NEXT:    s_mov_b32 s4, s3213; GFX12-NEXT:    s_mov_b32 s5, s2214; GFX12-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)215; GFX12-NEXT:    s_lshr_b64 s[2:3], s[4:5], 7216; GFX12-NEXT:    v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2217; GFX12-NEXT:    global_store_b32 v0, v1, s[0:1]218; GFX12-NEXT:    s_endpgm219entry:220  %0 = call i32 @llvm.fshr.i32(i32 %x, i32 %y, i32 7)221  store i32 %0, ptr addrspace(1) %in222  ret void223}224 225define amdgpu_kernel void @fshr_i32_imm_src0(ptr addrspace(1) %in, i32 %x, i32 %y) {226; SI-LABEL: fshr_i32_imm_src0:227; SI:       ; %bb.0: ; %entry228; SI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x9229; SI-NEXT:    s_mov_b32 s9, 7230; SI-NEXT:    s_mov_b32 s7, 0xf000231; SI-NEXT:    s_mov_b32 s6, -1232; SI-NEXT:    s_waitcnt lgkmcnt(0)233; SI-NEXT:    s_mov_b32 s4, s0234; SI-NEXT:    s_mov_b32 s8, s3235; SI-NEXT:    s_and_b32 s0, s2, 31236; SI-NEXT:    s_mov_b32 s5, s1237; SI-NEXT:    s_lshr_b64 s[0:1], s[8:9], s0238; SI-NEXT:    v_mov_b32_e32 v0, s0239; SI-NEXT:    buffer_store_dword v0, off, s[4:7], 0240; SI-NEXT:    s_endpgm241;242; VI-LABEL: fshr_i32_imm_src0:243; VI:       ; %bb.0: ; %entry244; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24245; VI-NEXT:    s_mov_b32 s5, 7246; VI-NEXT:    s_waitcnt lgkmcnt(0)247; VI-NEXT:    s_mov_b32 s4, s3248; VI-NEXT:    s_and_b32 s2, s2, 31249; VI-NEXT:    s_lshr_b64 s[2:3], s[4:5], s2250; VI-NEXT:    v_mov_b32_e32 v0, s0251; VI-NEXT:    v_mov_b32_e32 v1, s1252; VI-NEXT:    v_mov_b32_e32 v2, s2253; VI-NEXT:    flat_store_dword v[0:1], v2254; VI-NEXT:    s_endpgm255;256; GFX9-LABEL: fshr_i32_imm_src0:257; GFX9:       ; %bb.0: ; %entry258; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24259; GFX9-NEXT:    s_mov_b32 s5, 7260; GFX9-NEXT:    v_mov_b32_e32 v0, 0261; GFX9-NEXT:    s_waitcnt lgkmcnt(0)262; GFX9-NEXT:    s_mov_b32 s4, s3263; GFX9-NEXT:    s_and_b32 s2, s2, 31264; GFX9-NEXT:    s_lshr_b64 s[2:3], s[4:5], s2265; GFX9-NEXT:    v_mov_b32_e32 v1, s2266; GFX9-NEXT:    global_store_dword v0, v1, s[0:1]267; GFX9-NEXT:    s_endpgm268;269; R600-LABEL: fshr_i32_imm_src0:270; R600:       ; %bb.0: ; %entry271; R600-NEXT:    ALU 3, @4, KC0[CB0:0-32], KC1[]272; R600-NEXT:    MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1273; R600-NEXT:    CF_END274; R600-NEXT:    PAD275; R600-NEXT:    ALU clause starting at 4:276; R600-NEXT:     LSHR * T0.X, KC0[2].Y, literal.x,277; R600-NEXT:    2(2.802597e-45), 0(0.000000e+00)278; R600-NEXT:     BIT_ALIGN_INT * T1.X, literal.x, KC0[2].W, KC0[2].Z,279; R600-NEXT:    7(9.809089e-45), 0(0.000000e+00)280;281; GFX10-LABEL: fshr_i32_imm_src0:282; GFX10:       ; %bb.0: ; %entry283; GFX10-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24284; GFX10-NEXT:    s_mov_b32 s5, 7285; GFX10-NEXT:    v_mov_b32_e32 v0, 0286; GFX10-NEXT:    s_waitcnt lgkmcnt(0)287; GFX10-NEXT:    s_mov_b32 s4, s3288; GFX10-NEXT:    s_and_b32 s2, s2, 31289; GFX10-NEXT:    s_lshr_b64 s[2:3], s[4:5], s2290; GFX10-NEXT:    v_mov_b32_e32 v1, s2291; GFX10-NEXT:    global_store_dword v0, v1, s[0:1]292; GFX10-NEXT:    s_endpgm293;294; GFX11-LABEL: fshr_i32_imm_src0:295; GFX11:       ; %bb.0: ; %entry296; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24297; GFX11-NEXT:    s_mov_b32 s5, 7298; GFX11-NEXT:    s_waitcnt lgkmcnt(0)299; GFX11-NEXT:    s_mov_b32 s4, s3300; GFX11-NEXT:    s_and_b32 s2, s2, 31301; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)302; GFX11-NEXT:    s_lshr_b64 s[2:3], s[4:5], s2303; GFX11-NEXT:    v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2304; GFX11-NEXT:    global_store_b32 v0, v1, s[0:1]305; GFX11-NEXT:    s_endpgm306;307; GFX12-LABEL: fshr_i32_imm_src0:308; GFX12:       ; %bb.0: ; %entry309; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24310; GFX12-NEXT:    s_mov_b32 s5, 7311; GFX12-NEXT:    s_wait_kmcnt 0x0312; GFX12-NEXT:    s_mov_b32 s4, s3313; GFX12-NEXT:    s_and_b32 s2, s2, 31314; GFX12-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)315; GFX12-NEXT:    s_lshr_b64 s[2:3], s[4:5], s2316; GFX12-NEXT:    v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2317; GFX12-NEXT:    global_store_b32 v0, v1, s[0:1]318; GFX12-NEXT:    s_endpgm319entry:320  %0 = call i32 @llvm.fshr.i32(i32 7, i32 %y, i32 %x)321  store i32 %0, ptr addrspace(1) %in322  ret void323}324 325define amdgpu_kernel void @fshr_v2i32(ptr addrspace(1) %in, <2 x i32> %x, <2 x i32> %y, <2 x i32> %z) {326; SI-LABEL: fshr_v2i32:327; SI:       ; %bb.0: ; %entry328; SI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0xb329; SI-NEXT:    s_load_dwordx2 s[8:9], s[4:5], 0x9330; SI-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0xf331; SI-NEXT:    s_mov_b32 s11, 0xf000332; SI-NEXT:    s_mov_b32 s10, -1333; SI-NEXT:    s_waitcnt lgkmcnt(0)334; SI-NEXT:    s_mov_b32 s6, s3335; SI-NEXT:    s_mov_b32 s7, s1336; SI-NEXT:    s_and_b32 s1, s5, 31337; SI-NEXT:    s_mov_b32 s3, s0338; SI-NEXT:    s_and_b32 s0, s4, 31339; SI-NEXT:    s_lshr_b64 s[6:7], s[6:7], s1340; SI-NEXT:    s_lshr_b64 s[0:1], s[2:3], s0341; SI-NEXT:    v_mov_b32_e32 v0, s0342; SI-NEXT:    v_mov_b32_e32 v1, s6343; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[8:11], 0344; SI-NEXT:    s_endpgm345;346; VI-LABEL: fshr_v2i32:347; VI:       ; %bb.0: ; %entry348; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x2c349; VI-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x3c350; VI-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x24351; VI-NEXT:    s_waitcnt lgkmcnt(0)352; VI-NEXT:    s_mov_b32 s8, s3353; VI-NEXT:    s_mov_b32 s9, s1354; VI-NEXT:    s_and_b32 s1, s7, 31355; VI-NEXT:    s_mov_b32 s3, s0356; VI-NEXT:    s_and_b32 s0, s6, 31357; VI-NEXT:    s_lshr_b64 s[8:9], s[8:9], s1358; VI-NEXT:    s_lshr_b64 s[0:1], s[2:3], s0359; VI-NEXT:    v_mov_b32_e32 v2, s4360; VI-NEXT:    v_mov_b32_e32 v0, s0361; VI-NEXT:    v_mov_b32_e32 v1, s8362; VI-NEXT:    v_mov_b32_e32 v3, s5363; VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]364; VI-NEXT:    s_endpgm365;366; GFX9-LABEL: fshr_v2i32:367; GFX9:       ; %bb.0: ; %entry368; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x2c369; GFX9-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x3c370; GFX9-NEXT:    s_load_dwordx2 s[8:9], s[4:5], 0x24371; GFX9-NEXT:    v_mov_b32_e32 v2, 0372; GFX9-NEXT:    s_waitcnt lgkmcnt(0)373; GFX9-NEXT:    s_mov_b32 s4, s3374; GFX9-NEXT:    s_mov_b32 s5, s1375; GFX9-NEXT:    s_and_b32 s1, s7, 31376; GFX9-NEXT:    s_mov_b32 s3, s0377; GFX9-NEXT:    s_and_b32 s0, s6, 31378; GFX9-NEXT:    s_lshr_b64 s[4:5], s[4:5], s1379; GFX9-NEXT:    s_lshr_b64 s[0:1], s[2:3], s0380; GFX9-NEXT:    v_mov_b32_e32 v0, s0381; GFX9-NEXT:    v_mov_b32_e32 v1, s4382; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[8:9]383; GFX9-NEXT:    s_endpgm384;385; R600-LABEL: fshr_v2i32:386; R600:       ; %bb.0: ; %entry387; R600-NEXT:    ALU 5, @4, KC0[CB0:0-32], KC1[]388; R600-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1389; R600-NEXT:    CF_END390; R600-NEXT:    PAD391; R600-NEXT:    ALU clause starting at 4:392; R600-NEXT:     MOV * T0.W, KC0[4].X,393; R600-NEXT:     BIT_ALIGN_INT T0.Y, KC0[3].X, KC0[3].Z, PV.W,394; R600-NEXT:     MOV * T0.W, KC0[3].W,395; R600-NEXT:     BIT_ALIGN_INT * T0.X, KC0[2].W, KC0[3].Y, PV.W,396; R600-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,397; R600-NEXT:    2(2.802597e-45), 0(0.000000e+00)398;399; GFX10-LABEL: fshr_v2i32:400; GFX10:       ; %bb.0: ; %entry401; GFX10-NEXT:    s_clause 0x2402; GFX10-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x2c403; GFX10-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x3c404; GFX10-NEXT:    s_load_dwordx2 s[8:9], s[4:5], 0x24405; GFX10-NEXT:    v_mov_b32_e32 v2, 0406; GFX10-NEXT:    s_waitcnt lgkmcnt(0)407; GFX10-NEXT:    s_mov_b32 s4, s3408; GFX10-NEXT:    s_mov_b32 s5, s1409; GFX10-NEXT:    s_mov_b32 s3, s0410; GFX10-NEXT:    s_and_b32 s0, s6, 31411; GFX10-NEXT:    s_and_b32 s6, s7, 31412; GFX10-NEXT:    s_lshr_b64 s[0:1], s[2:3], s0413; GFX10-NEXT:    s_lshr_b64 s[2:3], s[4:5], s6414; GFX10-NEXT:    v_mov_b32_e32 v0, s0415; GFX10-NEXT:    v_mov_b32_e32 v1, s2416; GFX10-NEXT:    global_store_dwordx2 v2, v[0:1], s[8:9]417; GFX10-NEXT:    s_endpgm418;419; GFX11-LABEL: fshr_v2i32:420; GFX11:       ; %bb.0: ; %entry421; GFX11-NEXT:    s_clause 0x2422; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x2c423; GFX11-NEXT:    s_load_b64 s[6:7], s[4:5], 0x3c424; GFX11-NEXT:    s_load_b64 s[4:5], s[4:5], 0x24425; GFX11-NEXT:    s_waitcnt lgkmcnt(0)426; GFX11-NEXT:    s_mov_b32 s8, s3427; GFX11-NEXT:    s_mov_b32 s9, s1428; GFX11-NEXT:    s_mov_b32 s3, s0429; GFX11-NEXT:    s_and_b32 s0, s6, 31430; GFX11-NEXT:    s_and_b32 s6, s7, 31431; GFX11-NEXT:    s_lshr_b64 s[0:1], s[2:3], s0432; GFX11-NEXT:    s_lshr_b64 s[2:3], s[8:9], s6433; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)434; GFX11-NEXT:    v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s2435; GFX11-NEXT:    v_mov_b32_e32 v0, s0436; GFX11-NEXT:    global_store_b64 v2, v[0:1], s[4:5]437; GFX11-NEXT:    s_endpgm438;439; GFX12-LABEL: fshr_v2i32:440; GFX12:       ; %bb.0: ; %entry441; GFX12-NEXT:    s_clause 0x2442; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x2c443; GFX12-NEXT:    s_load_b64 s[6:7], s[4:5], 0x3c444; GFX12-NEXT:    s_load_b64 s[4:5], s[4:5], 0x24445; GFX12-NEXT:    s_wait_kmcnt 0x0446; GFX12-NEXT:    s_mov_b32 s8, s3447; GFX12-NEXT:    s_mov_b32 s9, s1448; GFX12-NEXT:    s_mov_b32 s3, s0449; GFX12-NEXT:    s_and_b32 s0, s6, 31450; GFX12-NEXT:    s_and_b32 s6, s7, 31451; GFX12-NEXT:    s_lshr_b64 s[0:1], s[2:3], s0452; GFX12-NEXT:    s_lshr_b64 s[2:3], s[8:9], s6453; GFX12-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)454; GFX12-NEXT:    v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s2455; GFX12-NEXT:    v_mov_b32_e32 v0, s0456; GFX12-NEXT:    global_store_b64 v2, v[0:1], s[4:5]457; GFX12-NEXT:    s_endpgm458entry:459  %0 = call <2 x i32> @llvm.fshr.v2i32(<2 x i32> %x, <2 x i32> %y, <2 x i32> %z)460  store <2 x i32> %0, ptr addrspace(1) %in461  ret void462}463 464define amdgpu_kernel void @fshr_v2i32_imm(ptr addrspace(1) %in, <2 x i32> %x, <2 x i32> %y) {465; SI-LABEL: fshr_v2i32_imm:466; SI:       ; %bb.0: ; %entry467; SI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0xb468; SI-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x9469; SI-NEXT:    s_mov_b32 s7, 0xf000470; SI-NEXT:    s_mov_b32 s6, -1471; SI-NEXT:    s_waitcnt lgkmcnt(0)472; SI-NEXT:    s_mov_b32 s8, s3473; SI-NEXT:    s_mov_b32 s9, s1474; SI-NEXT:    s_mov_b32 s3, s0475; SI-NEXT:    s_lshr_b64 s[8:9], s[8:9], 9476; SI-NEXT:    s_lshr_b64 s[0:1], s[2:3], 7477; SI-NEXT:    v_mov_b32_e32 v0, s0478; SI-NEXT:    v_mov_b32_e32 v1, s8479; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0480; SI-NEXT:    s_endpgm481;482; VI-LABEL: fshr_v2i32_imm:483; VI:       ; %bb.0: ; %entry484; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x2c485; VI-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x24486; VI-NEXT:    s_waitcnt lgkmcnt(0)487; VI-NEXT:    s_mov_b32 s6, s3488; VI-NEXT:    s_mov_b32 s7, s1489; VI-NEXT:    s_mov_b32 s3, s0490; VI-NEXT:    s_lshr_b64 s[0:1], s[6:7], 9491; VI-NEXT:    s_lshr_b64 s[2:3], s[2:3], 7492; VI-NEXT:    v_mov_b32_e32 v2, s4493; VI-NEXT:    v_mov_b32_e32 v0, s2494; VI-NEXT:    v_mov_b32_e32 v1, s0495; VI-NEXT:    v_mov_b32_e32 v3, s5496; VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]497; VI-NEXT:    s_endpgm498;499; GFX9-LABEL: fshr_v2i32_imm:500; GFX9:       ; %bb.0: ; %entry501; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x2c502; GFX9-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x24503; GFX9-NEXT:    v_mov_b32_e32 v2, 0504; GFX9-NEXT:    s_waitcnt lgkmcnt(0)505; GFX9-NEXT:    s_mov_b32 s4, s3506; GFX9-NEXT:    s_mov_b32 s5, s1507; GFX9-NEXT:    s_mov_b32 s3, s0508; GFX9-NEXT:    s_lshr_b64 s[0:1], s[4:5], 9509; GFX9-NEXT:    s_lshr_b64 s[2:3], s[2:3], 7510; GFX9-NEXT:    v_mov_b32_e32 v0, s2511; GFX9-NEXT:    v_mov_b32_e32 v1, s0512; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[6:7]513; GFX9-NEXT:    s_endpgm514;515; R600-LABEL: fshr_v2i32_imm:516; R600:       ; %bb.0: ; %entry517; R600-NEXT:    ALU 5, @4, KC0[CB0:0-32], KC1[]518; R600-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1519; R600-NEXT:    CF_END520; R600-NEXT:    PAD521; R600-NEXT:    ALU clause starting at 4:522; R600-NEXT:     BIT_ALIGN_INT * T0.Y, KC0[3].X, KC0[3].Z, literal.x,523; R600-NEXT:    9(1.261169e-44), 0(0.000000e+00)524; R600-NEXT:     BIT_ALIGN_INT * T0.X, KC0[2].W, KC0[3].Y, literal.x,525; R600-NEXT:    7(9.809089e-45), 0(0.000000e+00)526; R600-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,527; R600-NEXT:    2(2.802597e-45), 0(0.000000e+00)528;529; GFX10-LABEL: fshr_v2i32_imm:530; GFX10:       ; %bb.0: ; %entry531; GFX10-NEXT:    s_clause 0x1532; GFX10-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x2c533; GFX10-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x24534; GFX10-NEXT:    v_mov_b32_e32 v2, 0535; GFX10-NEXT:    s_waitcnt lgkmcnt(0)536; GFX10-NEXT:    s_mov_b32 s4, s3537; GFX10-NEXT:    s_mov_b32 s3, s0538; GFX10-NEXT:    s_mov_b32 s5, s1539; GFX10-NEXT:    s_lshr_b64 s[0:1], s[2:3], 7540; GFX10-NEXT:    s_lshr_b64 s[2:3], s[4:5], 9541; GFX10-NEXT:    v_mov_b32_e32 v0, s0542; GFX10-NEXT:    v_mov_b32_e32 v1, s2543; GFX10-NEXT:    global_store_dwordx2 v2, v[0:1], s[6:7]544; GFX10-NEXT:    s_endpgm545;546; GFX11-LABEL: fshr_v2i32_imm:547; GFX11:       ; %bb.0: ; %entry548; GFX11-NEXT:    s_clause 0x1549; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x2c550; GFX11-NEXT:    s_load_b64 s[4:5], s[4:5], 0x24551; GFX11-NEXT:    s_waitcnt lgkmcnt(0)552; GFX11-NEXT:    s_mov_b32 s6, s3553; GFX11-NEXT:    s_mov_b32 s3, s0554; GFX11-NEXT:    s_mov_b32 s7, s1555; GFX11-NEXT:    s_lshr_b64 s[0:1], s[2:3], 7556; GFX11-NEXT:    s_lshr_b64 s[2:3], s[6:7], 9557; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)558; GFX11-NEXT:    v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s2559; GFX11-NEXT:    v_mov_b32_e32 v0, s0560; GFX11-NEXT:    global_store_b64 v2, v[0:1], s[4:5]561; GFX11-NEXT:    s_endpgm562;563; GFX12-LABEL: fshr_v2i32_imm:564; GFX12:       ; %bb.0: ; %entry565; GFX12-NEXT:    s_clause 0x1566; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x2c567; GFX12-NEXT:    s_load_b64 s[4:5], s[4:5], 0x24568; GFX12-NEXT:    s_wait_kmcnt 0x0569; GFX12-NEXT:    s_mov_b32 s6, s3570; GFX12-NEXT:    s_mov_b32 s3, s0571; GFX12-NEXT:    s_mov_b32 s7, s1572; GFX12-NEXT:    s_lshr_b64 s[0:1], s[2:3], 7573; GFX12-NEXT:    s_lshr_b64 s[2:3], s[6:7], 9574; GFX12-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)575; GFX12-NEXT:    v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s2576; GFX12-NEXT:    v_mov_b32_e32 v0, s0577; GFX12-NEXT:    global_store_b64 v2, v[0:1], s[4:5]578; GFX12-NEXT:    s_endpgm579entry:580  %0 = call <2 x i32> @llvm.fshr.v2i32(<2 x i32> %x, <2 x i32> %y, <2 x i32> <i32 7, i32 9>)581  store <2 x i32> %0, ptr addrspace(1) %in582  ret void583}584 585define amdgpu_kernel void @fshr_v2i32_imm_src1(ptr addrspace(1) %in, <2 x i32> %x, <2 x i32> %y) {586; SI-LABEL: fshr_v2i32_imm_src1:587; SI:       ; %bb.0: ; %entry588; SI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0xb589; SI-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x9590; SI-NEXT:    s_mov_b32 s8, 9591; SI-NEXT:    s_mov_b32 s10, 7592; SI-NEXT:    s_mov_b32 s7, 0xf000593; SI-NEXT:    s_waitcnt lgkmcnt(0)594; SI-NEXT:    s_mov_b32 s9, s1595; SI-NEXT:    s_and_b32 s1, s3, 31596; SI-NEXT:    s_mov_b32 s11, s0597; SI-NEXT:    s_and_b32 s0, s2, 31598; SI-NEXT:    s_lshr_b64 s[8:9], s[8:9], s1599; SI-NEXT:    s_lshr_b64 s[0:1], s[10:11], s0600; SI-NEXT:    s_mov_b32 s6, -1601; SI-NEXT:    v_mov_b32_e32 v0, s0602; SI-NEXT:    v_mov_b32_e32 v1, s8603; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0604; SI-NEXT:    s_endpgm605;606; VI-LABEL: fshr_v2i32_imm_src1:607; VI:       ; %bb.0: ; %entry608; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x2c609; VI-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x24610; VI-NEXT:    s_mov_b32 s6, 9611; VI-NEXT:    s_mov_b32 s8, 7612; VI-NEXT:    s_waitcnt lgkmcnt(0)613; VI-NEXT:    s_mov_b32 s7, s1614; VI-NEXT:    s_and_b32 s1, s3, 31615; VI-NEXT:    s_mov_b32 s9, s0616; VI-NEXT:    s_and_b32 s0, s2, 31617; VI-NEXT:    s_lshr_b64 s[6:7], s[6:7], s1618; VI-NEXT:    s_lshr_b64 s[0:1], s[8:9], s0619; VI-NEXT:    v_mov_b32_e32 v2, s4620; VI-NEXT:    v_mov_b32_e32 v0, s0621; VI-NEXT:    v_mov_b32_e32 v1, s6622; VI-NEXT:    v_mov_b32_e32 v3, s5623; VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]624; VI-NEXT:    s_endpgm625;626; GFX9-LABEL: fshr_v2i32_imm_src1:627; GFX9:       ; %bb.0: ; %entry628; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x2c629; GFX9-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x24630; GFX9-NEXT:    s_mov_b32 s4, 9631; GFX9-NEXT:    s_mov_b32 s8, 7632; GFX9-NEXT:    v_mov_b32_e32 v2, 0633; GFX9-NEXT:    s_waitcnt lgkmcnt(0)634; GFX9-NEXT:    s_mov_b32 s5, s1635; GFX9-NEXT:    s_and_b32 s1, s3, 31636; GFX9-NEXT:    s_mov_b32 s9, s0637; GFX9-NEXT:    s_and_b32 s0, s2, 31638; GFX9-NEXT:    s_lshr_b64 s[4:5], s[4:5], s1639; GFX9-NEXT:    s_lshr_b64 s[0:1], s[8:9], s0640; GFX9-NEXT:    v_mov_b32_e32 v0, s0641; GFX9-NEXT:    v_mov_b32_e32 v1, s4642; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[6:7]643; GFX9-NEXT:    s_endpgm644;645; R600-LABEL: fshr_v2i32_imm_src1:646; R600:       ; %bb.0: ; %entry647; R600-NEXT:    ALU 5, @4, KC0[CB0:0-32], KC1[]648; R600-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1649; R600-NEXT:    CF_END650; R600-NEXT:    PAD651; R600-NEXT:    ALU clause starting at 4:652; R600-NEXT:     BIT_ALIGN_INT * T0.Y, KC0[3].X, literal.x, KC0[3].Z,653; R600-NEXT:    9(1.261169e-44), 0(0.000000e+00)654; R600-NEXT:     BIT_ALIGN_INT * T0.X, KC0[2].W, literal.x, KC0[3].Y,655; R600-NEXT:    7(9.809089e-45), 0(0.000000e+00)656; R600-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,657; R600-NEXT:    2(2.802597e-45), 0(0.000000e+00)658;659; GFX10-LABEL: fshr_v2i32_imm_src1:660; GFX10:       ; %bb.0: ; %entry661; GFX10-NEXT:    s_clause 0x1662; GFX10-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x2c663; GFX10-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x24664; GFX10-NEXT:    s_mov_b32 s4, 9665; GFX10-NEXT:    s_mov_b32 s8, 7666; GFX10-NEXT:    v_mov_b32_e32 v2, 0667; GFX10-NEXT:    s_waitcnt lgkmcnt(0)668; GFX10-NEXT:    s_mov_b32 s5, s1669; GFX10-NEXT:    s_mov_b32 s9, s0670; GFX10-NEXT:    s_and_b32 s0, s2, 31671; GFX10-NEXT:    s_and_b32 s2, s3, 31672; GFX10-NEXT:    s_lshr_b64 s[0:1], s[8:9], s0673; GFX10-NEXT:    s_lshr_b64 s[2:3], s[4:5], s2674; GFX10-NEXT:    v_mov_b32_e32 v0, s0675; GFX10-NEXT:    v_mov_b32_e32 v1, s2676; GFX10-NEXT:    global_store_dwordx2 v2, v[0:1], s[6:7]677; GFX10-NEXT:    s_endpgm678;679; GFX11-LABEL: fshr_v2i32_imm_src1:680; GFX11:       ; %bb.0: ; %entry681; GFX11-NEXT:    s_clause 0x1682; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x2c683; GFX11-NEXT:    s_load_b64 s[4:5], s[4:5], 0x24684; GFX11-NEXT:    s_mov_b32 s6, 9685; GFX11-NEXT:    s_mov_b32 s8, 7686; GFX11-NEXT:    s_waitcnt lgkmcnt(0)687; GFX11-NEXT:    s_mov_b32 s7, s1688; GFX11-NEXT:    s_mov_b32 s9, s0689; GFX11-NEXT:    s_and_b32 s0, s2, 31690; GFX11-NEXT:    s_and_b32 s2, s3, 31691; GFX11-NEXT:    s_lshr_b64 s[0:1], s[8:9], s0692; GFX11-NEXT:    s_lshr_b64 s[2:3], s[6:7], s2693; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)694; GFX11-NEXT:    v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s2695; GFX11-NEXT:    v_mov_b32_e32 v0, s0696; GFX11-NEXT:    global_store_b64 v2, v[0:1], s[4:5]697; GFX11-NEXT:    s_endpgm698;699; GFX12-LABEL: fshr_v2i32_imm_src1:700; GFX12:       ; %bb.0: ; %entry701; GFX12-NEXT:    s_clause 0x1702; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x2c703; GFX12-NEXT:    s_load_b64 s[4:5], s[4:5], 0x24704; GFX12-NEXT:    s_mov_b32 s6, 9705; GFX12-NEXT:    s_mov_b32 s8, 7706; GFX12-NEXT:    s_wait_kmcnt 0x0707; GFX12-NEXT:    s_mov_b32 s7, s1708; GFX12-NEXT:    s_mov_b32 s9, s0709; GFX12-NEXT:    s_and_b32 s0, s2, 31710; GFX12-NEXT:    s_and_b32 s2, s3, 31711; GFX12-NEXT:    s_lshr_b64 s[0:1], s[8:9], s0712; GFX12-NEXT:    s_lshr_b64 s[2:3], s[6:7], s2713; GFX12-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)714; GFX12-NEXT:    v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s2715; GFX12-NEXT:    v_mov_b32_e32 v0, s0716; GFX12-NEXT:    global_store_b64 v2, v[0:1], s[4:5]717; GFX12-NEXT:    s_endpgm718entry:719  %0 = call <2 x i32> @llvm.fshr.v2i32(<2 x i32> %x, <2 x i32> <i32 7, i32 9>, <2 x i32> %y)720  store <2 x i32> %0, ptr addrspace(1) %in721  ret void722}723 724define amdgpu_kernel void @fshr_v4i32(ptr addrspace(1) %in, <4 x i32> %x, <4 x i32> %y, <4 x i32> %z) {725; SI-LABEL: fshr_v4i32:726; SI:       ; %bb.0: ; %entry727; SI-NEXT:    s_load_dwordx8 s[8:15], s[4:5], 0xd728; SI-NEXT:    s_load_dwordx4 s[16:19], s[4:5], 0x15729; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x9730; SI-NEXT:    s_mov_b32 s3, 0xf000731; SI-NEXT:    s_mov_b32 s2, -1732; SI-NEXT:    s_waitcnt lgkmcnt(0)733; SI-NEXT:    s_mov_b32 s4, s15734; SI-NEXT:    s_mov_b32 s5, s11735; SI-NEXT:    s_and_b32 s6, s19, 31736; SI-NEXT:    s_lshr_b64 s[4:5], s[4:5], s6737; SI-NEXT:    s_mov_b32 s15, s10738; SI-NEXT:    s_and_b32 s5, s18, 31739; SI-NEXT:    s_lshr_b64 s[6:7], s[14:15], s5740; SI-NEXT:    s_mov_b32 s10, s13741; SI-NEXT:    s_mov_b32 s11, s9742; SI-NEXT:    s_and_b32 s5, s17, 31743; SI-NEXT:    s_lshr_b64 s[10:11], s[10:11], s5744; SI-NEXT:    s_mov_b32 s13, s8745; SI-NEXT:    s_and_b32 s5, s16, 31746; SI-NEXT:    s_lshr_b64 s[8:9], s[12:13], s5747; SI-NEXT:    v_mov_b32_e32 v0, s8748; SI-NEXT:    v_mov_b32_e32 v1, s10749; SI-NEXT:    v_mov_b32_e32 v2, s6750; SI-NEXT:    v_mov_b32_e32 v3, s4751; SI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0752; SI-NEXT:    s_endpgm753;754; VI-LABEL: fshr_v4i32:755; VI:       ; %bb.0: ; %entry756; VI-NEXT:    s_load_dwordx8 s[8:15], s[4:5], 0x34757; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x54758; VI-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x24759; VI-NEXT:    s_waitcnt lgkmcnt(0)760; VI-NEXT:    s_mov_b32 s6, s15761; VI-NEXT:    s_mov_b32 s7, s11762; VI-NEXT:    s_and_b32 s3, s3, 31763; VI-NEXT:    s_mov_b32 s15, s10764; VI-NEXT:    s_and_b32 s2, s2, 31765; VI-NEXT:    s_mov_b32 s10, s13766; VI-NEXT:    s_mov_b32 s11, s9767; VI-NEXT:    s_and_b32 s1, s1, 31768; VI-NEXT:    s_mov_b32 s13, s8769; VI-NEXT:    s_and_b32 s0, s0, 31770; VI-NEXT:    s_lshr_b64 s[6:7], s[6:7], s3771; VI-NEXT:    s_lshr_b64 s[2:3], s[14:15], s2772; VI-NEXT:    s_lshr_b64 s[10:11], s[10:11], s1773; VI-NEXT:    s_lshr_b64 s[0:1], s[12:13], s0774; VI-NEXT:    v_mov_b32_e32 v4, s4775; VI-NEXT:    v_mov_b32_e32 v0, s0776; VI-NEXT:    v_mov_b32_e32 v1, s10777; VI-NEXT:    v_mov_b32_e32 v2, s2778; VI-NEXT:    v_mov_b32_e32 v3, s6779; VI-NEXT:    v_mov_b32_e32 v5, s5780; VI-NEXT:    flat_store_dwordx4 v[4:5], v[0:3]781; VI-NEXT:    s_endpgm782;783; GFX9-LABEL: fshr_v4i32:784; GFX9:       ; %bb.0: ; %entry785; GFX9-NEXT:    s_load_dwordx8 s[8:15], s[4:5], 0x34786; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x54787; GFX9-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x24788; GFX9-NEXT:    v_mov_b32_e32 v4, 0789; GFX9-NEXT:    s_waitcnt lgkmcnt(0)790; GFX9-NEXT:    s_mov_b32 s4, s15791; GFX9-NEXT:    s_mov_b32 s5, s11792; GFX9-NEXT:    s_and_b32 s3, s3, 31793; GFX9-NEXT:    s_mov_b32 s15, s10794; GFX9-NEXT:    s_and_b32 s2, s2, 31795; GFX9-NEXT:    s_mov_b32 s10, s13796; GFX9-NEXT:    s_mov_b32 s11, s9797; GFX9-NEXT:    s_and_b32 s1, s1, 31798; GFX9-NEXT:    s_mov_b32 s13, s8799; GFX9-NEXT:    s_and_b32 s0, s0, 31800; GFX9-NEXT:    s_lshr_b64 s[4:5], s[4:5], s3801; GFX9-NEXT:    s_lshr_b64 s[2:3], s[14:15], s2802; GFX9-NEXT:    s_lshr_b64 s[10:11], s[10:11], s1803; GFX9-NEXT:    s_lshr_b64 s[0:1], s[12:13], s0804; GFX9-NEXT:    v_mov_b32_e32 v0, s0805; GFX9-NEXT:    v_mov_b32_e32 v1, s10806; GFX9-NEXT:    v_mov_b32_e32 v2, s2807; GFX9-NEXT:    v_mov_b32_e32 v3, s4808; GFX9-NEXT:    global_store_dwordx4 v4, v[0:3], s[6:7]809; GFX9-NEXT:    s_endpgm810;811; R600-LABEL: fshr_v4i32:812; R600:       ; %bb.0: ; %entry813; R600-NEXT:    ALU 9, @4, KC0[CB0:0-32], KC1[]814; R600-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1815; R600-NEXT:    CF_END816; R600-NEXT:    PAD817; R600-NEXT:    ALU clause starting at 4:818; R600-NEXT:     MOV * T0.W, KC0[6].X,819; R600-NEXT:     BIT_ALIGN_INT * T0.W, KC0[4].X, KC0[5].X, PV.W,820; R600-NEXT:     MOV * T1.W, KC0[5].W,821; R600-NEXT:     BIT_ALIGN_INT * T0.Z, KC0[3].W, KC0[4].W, PV.W,822; R600-NEXT:     MOV * T1.W, KC0[5].Z,823; R600-NEXT:     BIT_ALIGN_INT * T0.Y, KC0[3].Z, KC0[4].Z, PV.W,824; R600-NEXT:     MOV * T1.W, KC0[5].Y,825; R600-NEXT:     BIT_ALIGN_INT * T0.X, KC0[3].Y, KC0[4].Y, PV.W,826; R600-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,827; R600-NEXT:    2(2.802597e-45), 0(0.000000e+00)828;829; GFX10-LABEL: fshr_v4i32:830; GFX10:       ; %bb.0: ; %entry831; GFX10-NEXT:    s_clause 0x2832; GFX10-NEXT:    s_load_dwordx8 s[8:15], s[4:5], 0x34833; GFX10-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x54834; GFX10-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x24835; GFX10-NEXT:    v_mov_b32_e32 v4, 0836; GFX10-NEXT:    s_waitcnt lgkmcnt(0)837; GFX10-NEXT:    s_mov_b32 s4, s15838; GFX10-NEXT:    s_mov_b32 s5, s11839; GFX10-NEXT:    s_and_b32 s11, s3, 31840; GFX10-NEXT:    s_mov_b32 s15, s10841; GFX10-NEXT:    s_and_b32 s10, s2, 31842; GFX10-NEXT:    s_mov_b32 s2, s13843; GFX10-NEXT:    s_mov_b32 s3, s9844; GFX10-NEXT:    s_and_b32 s16, s1, 31845; GFX10-NEXT:    s_mov_b32 s13, s8846; GFX10-NEXT:    s_and_b32 s8, s0, 31847; GFX10-NEXT:    s_lshr_b64 s[0:1], s[4:5], s11848; GFX10-NEXT:    s_lshr_b64 s[4:5], s[14:15], s10849; GFX10-NEXT:    s_lshr_b64 s[8:9], s[12:13], s8850; GFX10-NEXT:    s_lshr_b64 s[2:3], s[2:3], s16851; GFX10-NEXT:    v_mov_b32_e32 v0, s8852; GFX10-NEXT:    v_mov_b32_e32 v1, s2853; GFX10-NEXT:    v_mov_b32_e32 v2, s4854; GFX10-NEXT:    v_mov_b32_e32 v3, s0855; GFX10-NEXT:    global_store_dwordx4 v4, v[0:3], s[6:7]856; GFX10-NEXT:    s_endpgm857;858; GFX11-LABEL: fshr_v4i32:859; GFX11:       ; %bb.0: ; %entry860; GFX11-NEXT:    s_clause 0x2861; GFX11-NEXT:    s_load_b256 s[8:15], s[4:5], 0x34862; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x54863; GFX11-NEXT:    s_load_b64 s[4:5], s[4:5], 0x24864; GFX11-NEXT:    s_waitcnt lgkmcnt(0)865; GFX11-NEXT:    s_mov_b32 s6, s15866; GFX11-NEXT:    s_mov_b32 s7, s11867; GFX11-NEXT:    s_and_b32 s11, s3, 31868; GFX11-NEXT:    s_mov_b32 s15, s10869; GFX11-NEXT:    s_and_b32 s10, s2, 31870; GFX11-NEXT:    s_mov_b32 s2, s13871; GFX11-NEXT:    s_mov_b32 s3, s9872; GFX11-NEXT:    s_and_b32 s16, s1, 31873; GFX11-NEXT:    s_mov_b32 s13, s8874; GFX11-NEXT:    s_and_b32 s8, s0, 31875; GFX11-NEXT:    s_lshr_b64 s[0:1], s[6:7], s11876; GFX11-NEXT:    s_lshr_b64 s[6:7], s[14:15], s10877; GFX11-NEXT:    s_lshr_b64 s[8:9], s[12:13], s8878; GFX11-NEXT:    s_lshr_b64 s[2:3], s[2:3], s16879; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)880; GFX11-NEXT:    v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v1, s2881; GFX11-NEXT:    v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v3, s0882; GFX11-NEXT:    v_mov_b32_e32 v2, s6883; GFX11-NEXT:    global_store_b128 v4, v[0:3], s[4:5]884; GFX11-NEXT:    s_endpgm885;886; GFX12-LABEL: fshr_v4i32:887; GFX12:       ; %bb.0: ; %entry888; GFX12-NEXT:    s_clause 0x2889; GFX12-NEXT:    s_load_b256 s[8:15], s[4:5], 0x34890; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x54891; GFX12-NEXT:    s_load_b64 s[4:5], s[4:5], 0x24892; GFX12-NEXT:    s_wait_kmcnt 0x0893; GFX12-NEXT:    s_mov_b32 s6, s15894; GFX12-NEXT:    s_mov_b32 s7, s11895; GFX12-NEXT:    s_and_b32 s11, s3, 31896; GFX12-NEXT:    s_mov_b32 s15, s10897; GFX12-NEXT:    s_and_b32 s10, s2, 31898; GFX12-NEXT:    s_mov_b32 s2, s13899; GFX12-NEXT:    s_mov_b32 s3, s9900; GFX12-NEXT:    s_and_b32 s16, s1, 31901; GFX12-NEXT:    s_mov_b32 s13, s8902; GFX12-NEXT:    s_and_b32 s8, s0, 31903; GFX12-NEXT:    s_lshr_b64 s[0:1], s[6:7], s11904; GFX12-NEXT:    s_lshr_b64 s[6:7], s[14:15], s10905; GFX12-NEXT:    s_lshr_b64 s[8:9], s[12:13], s8906; GFX12-NEXT:    s_lshr_b64 s[2:3], s[2:3], s16907; GFX12-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)908; GFX12-NEXT:    v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v1, s2909; GFX12-NEXT:    v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v3, s0910; GFX12-NEXT:    v_mov_b32_e32 v2, s6911; GFX12-NEXT:    global_store_b128 v4, v[0:3], s[4:5]912; GFX12-NEXT:    s_endpgm913entry:914  %0 = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z)915  store <4 x i32> %0, ptr addrspace(1) %in916  ret void917}918 919define amdgpu_kernel void @fshr_v4i32_imm(ptr addrspace(1) %in, <4 x i32> %x, <4 x i32> %y) {920; SI-LABEL: fshr_v4i32_imm:921; SI:       ; %bb.0: ; %entry922; SI-NEXT:    s_load_dwordx8 s[8:15], s[4:5], 0xd923; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x9924; SI-NEXT:    s_mov_b32 s3, 0xf000925; SI-NEXT:    s_mov_b32 s2, -1926; SI-NEXT:    s_waitcnt lgkmcnt(0)927; SI-NEXT:    s_mov_b32 s4, s15928; SI-NEXT:    s_mov_b32 s5, s11929; SI-NEXT:    s_mov_b32 s15, s10930; SI-NEXT:    s_mov_b32 s10, s13931; SI-NEXT:    s_mov_b32 s11, s9932; SI-NEXT:    s_mov_b32 s13, s8933; SI-NEXT:    s_lshr_b64 s[4:5], s[4:5], 1934; SI-NEXT:    s_lshr_b64 s[6:7], s[14:15], 9935; SI-NEXT:    s_lshr_b64 s[10:11], s[10:11], 7936; SI-NEXT:    s_lshr_b64 s[8:9], s[12:13], 1937; SI-NEXT:    v_mov_b32_e32 v0, s8938; SI-NEXT:    v_mov_b32_e32 v1, s10939; SI-NEXT:    v_mov_b32_e32 v2, s6940; SI-NEXT:    v_mov_b32_e32 v3, s4941; SI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0942; SI-NEXT:    s_endpgm943;944; VI-LABEL: fshr_v4i32_imm:945; VI:       ; %bb.0: ; %entry946; VI-NEXT:    s_load_dwordx8 s[8:15], s[4:5], 0x34947; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24948; VI-NEXT:    s_waitcnt lgkmcnt(0)949; VI-NEXT:    s_mov_b32 s2, s15950; VI-NEXT:    s_mov_b32 s3, s11951; VI-NEXT:    s_mov_b32 s15, s10952; VI-NEXT:    s_mov_b32 s6, s13953; VI-NEXT:    s_mov_b32 s7, s9954; VI-NEXT:    s_mov_b32 s13, s8955; VI-NEXT:    s_lshr_b64 s[2:3], s[2:3], 1956; VI-NEXT:    s_lshr_b64 s[4:5], s[14:15], 9957; VI-NEXT:    s_lshr_b64 s[6:7], s[6:7], 7958; VI-NEXT:    s_lshr_b64 s[8:9], s[12:13], 1959; VI-NEXT:    v_mov_b32_e32 v5, s1960; VI-NEXT:    v_mov_b32_e32 v0, s8961; VI-NEXT:    v_mov_b32_e32 v1, s6962; VI-NEXT:    v_mov_b32_e32 v2, s4963; VI-NEXT:    v_mov_b32_e32 v3, s2964; VI-NEXT:    v_mov_b32_e32 v4, s0965; VI-NEXT:    flat_store_dwordx4 v[4:5], v[0:3]966; VI-NEXT:    s_endpgm967;968; GFX9-LABEL: fshr_v4i32_imm:969; GFX9:       ; %bb.0: ; %entry970; GFX9-NEXT:    s_load_dwordx8 s[8:15], s[4:5], 0x34971; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24972; GFX9-NEXT:    v_mov_b32_e32 v4, 0973; GFX9-NEXT:    s_waitcnt lgkmcnt(0)974; GFX9-NEXT:    s_mov_b32 s2, s15975; GFX9-NEXT:    s_mov_b32 s3, s11976; GFX9-NEXT:    s_mov_b32 s15, s10977; GFX9-NEXT:    s_mov_b32 s6, s13978; GFX9-NEXT:    s_mov_b32 s7, s9979; GFX9-NEXT:    s_mov_b32 s13, s8980; GFX9-NEXT:    s_lshr_b64 s[2:3], s[2:3], 1981; GFX9-NEXT:    s_lshr_b64 s[4:5], s[14:15], 9982; GFX9-NEXT:    s_lshr_b64 s[6:7], s[6:7], 7983; GFX9-NEXT:    s_lshr_b64 s[8:9], s[12:13], 1984; GFX9-NEXT:    v_mov_b32_e32 v0, s8985; GFX9-NEXT:    v_mov_b32_e32 v1, s6986; GFX9-NEXT:    v_mov_b32_e32 v2, s4987; GFX9-NEXT:    v_mov_b32_e32 v3, s2988; GFX9-NEXT:    global_store_dwordx4 v4, v[0:3], s[0:1]989; GFX9-NEXT:    s_endpgm990;991; R600-LABEL: fshr_v4i32_imm:992; R600:       ; %bb.0: ; %entry993; R600-NEXT:    ALU 7, @4, KC0[CB0:0-32], KC1[]994; R600-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1995; R600-NEXT:    CF_END996; R600-NEXT:    PAD997; R600-NEXT:    ALU clause starting at 4:998; R600-NEXT:     BIT_ALIGN_INT * T0.W, KC0[4].X, KC0[5].X, 1,999; R600-NEXT:     BIT_ALIGN_INT * T0.Z, KC0[3].W, KC0[4].W, literal.x,1000; R600-NEXT:    9(1.261169e-44), 0(0.000000e+00)1001; R600-NEXT:     BIT_ALIGN_INT * T0.Y, KC0[3].Z, KC0[4].Z, literal.x,1002; R600-NEXT:    7(9.809089e-45), 0(0.000000e+00)1003; R600-NEXT:     BIT_ALIGN_INT * T0.X, KC0[3].Y, KC0[4].Y, 1,1004; R600-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,1005; R600-NEXT:    2(2.802597e-45), 0(0.000000e+00)1006;1007; GFX10-LABEL: fshr_v4i32_imm:1008; GFX10:       ; %bb.0: ; %entry1009; GFX10-NEXT:    s_clause 0x11010; GFX10-NEXT:    s_load_dwordx8 s[8:15], s[4:5], 0x341011; GFX10-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x241012; GFX10-NEXT:    v_mov_b32_e32 v4, 01013; GFX10-NEXT:    s_waitcnt lgkmcnt(0)1014; GFX10-NEXT:    s_mov_b32 s2, s151015; GFX10-NEXT:    s_mov_b32 s3, s111016; GFX10-NEXT:    s_mov_b32 s15, s101017; GFX10-NEXT:    s_mov_b32 s4, s131018; GFX10-NEXT:    s_mov_b32 s5, s91019; GFX10-NEXT:    s_mov_b32 s13, s81020; GFX10-NEXT:    s_lshr_b64 s[2:3], s[2:3], 11021; GFX10-NEXT:    s_lshr_b64 s[6:7], s[14:15], 91022; GFX10-NEXT:    s_lshr_b64 s[8:9], s[12:13], 11023; GFX10-NEXT:    s_lshr_b64 s[4:5], s[4:5], 71024; GFX10-NEXT:    v_mov_b32_e32 v0, s81025; GFX10-NEXT:    v_mov_b32_e32 v1, s41026; GFX10-NEXT:    v_mov_b32_e32 v2, s61027; GFX10-NEXT:    v_mov_b32_e32 v3, s21028; GFX10-NEXT:    global_store_dwordx4 v4, v[0:3], s[0:1]1029; GFX10-NEXT:    s_endpgm1030;1031; GFX11-LABEL: fshr_v4i32_imm:1032; GFX11:       ; %bb.0: ; %entry1033; GFX11-NEXT:    s_clause 0x11034; GFX11-NEXT:    s_load_b256 s[8:15], s[4:5], 0x341035; GFX11-NEXT:    s_load_b64 s[0:1], s[4:5], 0x241036; GFX11-NEXT:    s_waitcnt lgkmcnt(0)1037; GFX11-NEXT:    s_mov_b32 s2, s151038; GFX11-NEXT:    s_mov_b32 s3, s111039; GFX11-NEXT:    s_mov_b32 s15, s101040; GFX11-NEXT:    s_mov_b32 s4, s131041; GFX11-NEXT:    s_mov_b32 s5, s91042; GFX11-NEXT:    s_mov_b32 s13, s81043; GFX11-NEXT:    s_lshr_b64 s[2:3], s[2:3], 11044; GFX11-NEXT:    s_lshr_b64 s[6:7], s[14:15], 91045; GFX11-NEXT:    s_lshr_b64 s[8:9], s[12:13], 11046; GFX11-NEXT:    s_lshr_b64 s[4:5], s[4:5], 71047; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)1048; GFX11-NEXT:    v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v1, s41049; GFX11-NEXT:    v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v3, s21050; GFX11-NEXT:    v_mov_b32_e32 v2, s61051; GFX11-NEXT:    global_store_b128 v4, v[0:3], s[0:1]1052; GFX11-NEXT:    s_endpgm1053;1054; GFX12-LABEL: fshr_v4i32_imm:1055; GFX12:       ; %bb.0: ; %entry1056; GFX12-NEXT:    s_clause 0x11057; GFX12-NEXT:    s_load_b256 s[8:15], s[4:5], 0x341058; GFX12-NEXT:    s_load_b64 s[0:1], s[4:5], 0x241059; GFX12-NEXT:    s_wait_kmcnt 0x01060; GFX12-NEXT:    s_mov_b32 s2, s151061; GFX12-NEXT:    s_mov_b32 s3, s111062; GFX12-NEXT:    s_mov_b32 s15, s101063; GFX12-NEXT:    s_mov_b32 s4, s131064; GFX12-NEXT:    s_mov_b32 s5, s91065; GFX12-NEXT:    s_mov_b32 s13, s81066; GFX12-NEXT:    s_lshr_b64 s[2:3], s[2:3], 11067; GFX12-NEXT:    s_lshr_b64 s[6:7], s[14:15], 91068; GFX12-NEXT:    s_lshr_b64 s[8:9], s[12:13], 11069; GFX12-NEXT:    s_lshr_b64 s[4:5], s[4:5], 71070; GFX12-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)1071; GFX12-NEXT:    v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v1, s41072; GFX12-NEXT:    v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v3, s21073; GFX12-NEXT:    v_mov_b32_e32 v2, s61074; GFX12-NEXT:    global_store_b128 v4, v[0:3], s[0:1]1075; GFX12-NEXT:    s_endpgm1076entry:1077  %0 = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i32> <i32 1, i32 7, i32 9, i32 33>)1078  store <4 x i32> %0, ptr addrspace(1) %in1079  ret void1080}1081 1082define amdgpu_kernel void @fshr_v4i32_imm_src0(ptr addrspace(1) %in, <4 x i32> %x, <4 x i32> %y) {1083; SI-LABEL: fshr_v4i32_imm_src0:1084; SI:       ; %bb.0: ; %entry1085; SI-NEXT:    s_load_dwordx8 s[8:15], s[4:5], 0xd1086; SI-NEXT:    s_mov_b32 s7, 331087; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x91088; SI-NEXT:    s_mov_b32 s3, 0xf0001089; SI-NEXT:    s_mov_b32 s2, -11090; SI-NEXT:    s_waitcnt lgkmcnt(0)1091; SI-NEXT:    s_mov_b32 s6, s111092; SI-NEXT:    s_and_b32 s4, s15, 311093; SI-NEXT:    s_lshr_b64 s[4:5], s[6:7], s41094; SI-NEXT:    s_mov_b32 s11, 91095; SI-NEXT:    s_and_b32 s5, s14, 311096; SI-NEXT:    s_lshr_b64 s[6:7], s[10:11], s51097; SI-NEXT:    s_mov_b32 s11, 71098; SI-NEXT:    s_mov_b32 s10, s91099; SI-NEXT:    s_and_b32 s5, s13, 311100; SI-NEXT:    s_lshr_b64 s[10:11], s[10:11], s51101; SI-NEXT:    s_mov_b32 s9, 11102; SI-NEXT:    s_and_b32 s5, s12, 311103; SI-NEXT:    s_lshr_b64 s[8:9], s[8:9], s51104; SI-NEXT:    v_mov_b32_e32 v0, s81105; SI-NEXT:    v_mov_b32_e32 v1, s101106; SI-NEXT:    v_mov_b32_e32 v2, s61107; SI-NEXT:    v_mov_b32_e32 v3, s41108; SI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 01109; SI-NEXT:    s_endpgm1110;1111; VI-LABEL: fshr_v4i32_imm_src0:1112; VI:       ; %bb.0: ; %entry1113; VI-NEXT:    s_load_dwordx8 s[8:15], s[4:5], 0x341114; VI-NEXT:    s_mov_b32 s1, 331115; VI-NEXT:    s_load_dwordx2 s[2:3], s[4:5], 0x241116; VI-NEXT:    s_mov_b32 s7, 71117; VI-NEXT:    s_waitcnt lgkmcnt(0)1118; VI-NEXT:    s_mov_b32 s0, s111119; VI-NEXT:    s_and_b32 s4, s15, 311120; VI-NEXT:    s_lshr_b64 s[0:1], s[0:1], s41121; VI-NEXT:    s_mov_b32 s11, 91122; VI-NEXT:    s_and_b32 s1, s14, 311123; VI-NEXT:    s_lshr_b64 s[4:5], s[10:11], s11124; VI-NEXT:    s_mov_b32 s6, s91125; VI-NEXT:    s_and_b32 s1, s13, 311126; VI-NEXT:    s_lshr_b64 s[6:7], s[6:7], s11127; VI-NEXT:    s_mov_b32 s9, 11128; VI-NEXT:    s_and_b32 s1, s12, 311129; VI-NEXT:    s_lshr_b64 s[8:9], s[8:9], s11130; VI-NEXT:    v_mov_b32_e32 v5, s31131; VI-NEXT:    v_mov_b32_e32 v0, s81132; VI-NEXT:    v_mov_b32_e32 v1, s61133; VI-NEXT:    v_mov_b32_e32 v2, s41134; VI-NEXT:    v_mov_b32_e32 v3, s01135; VI-NEXT:    v_mov_b32_e32 v4, s21136; VI-NEXT:    flat_store_dwordx4 v[4:5], v[0:3]1137; VI-NEXT:    s_endpgm1138;1139; GFX9-LABEL: fshr_v4i32_imm_src0:1140; GFX9:       ; %bb.0: ; %entry1141; GFX9-NEXT:    s_load_dwordx8 s[8:15], s[4:5], 0x341142; GFX9-NEXT:    s_mov_b32 s1, 331143; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[4:5], 0x241144; GFX9-NEXT:    s_mov_b32 s7, 71145; GFX9-NEXT:    v_mov_b32_e32 v4, 01146; GFX9-NEXT:    s_waitcnt lgkmcnt(0)1147; GFX9-NEXT:    s_mov_b32 s0, s111148; GFX9-NEXT:    s_and_b32 s4, s15, 311149; GFX9-NEXT:    s_lshr_b64 s[0:1], s[0:1], s41150; GFX9-NEXT:    s_mov_b32 s11, 91151; GFX9-NEXT:    s_and_b32 s1, s14, 311152; GFX9-NEXT:    s_lshr_b64 s[4:5], s[10:11], s11153; GFX9-NEXT:    s_mov_b32 s6, s91154; GFX9-NEXT:    s_and_b32 s1, s13, 311155; GFX9-NEXT:    s_lshr_b64 s[6:7], s[6:7], s11156; GFX9-NEXT:    s_mov_b32 s9, 11157; GFX9-NEXT:    s_and_b32 s1, s12, 311158; GFX9-NEXT:    s_lshr_b64 s[8:9], s[8:9], s11159; GFX9-NEXT:    v_mov_b32_e32 v0, s81160; GFX9-NEXT:    v_mov_b32_e32 v1, s61161; GFX9-NEXT:    v_mov_b32_e32 v2, s41162; GFX9-NEXT:    v_mov_b32_e32 v3, s01163; GFX9-NEXT:    global_store_dwordx4 v4, v[0:3], s[2:3]1164; GFX9-NEXT:    s_endpgm1165;1166; R600-LABEL: fshr_v4i32_imm_src0:1167; R600:       ; %bb.0: ; %entry1168; R600-NEXT:    ALU 8, @4, KC0[CB0:0-32], KC1[]1169; R600-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 11170; R600-NEXT:    CF_END1171; R600-NEXT:    PAD1172; R600-NEXT:    ALU clause starting at 4:1173; R600-NEXT:     BIT_ALIGN_INT * T0.W, literal.x, KC0[4].X, KC0[5].X,1174; R600-NEXT:    33(4.624285e-44), 0(0.000000e+00)1175; R600-NEXT:     BIT_ALIGN_INT * T0.Z, literal.x, KC0[3].W, KC0[4].W,1176; R600-NEXT:    9(1.261169e-44), 0(0.000000e+00)1177; R600-NEXT:     BIT_ALIGN_INT * T0.Y, literal.x, KC0[3].Z, KC0[4].Z,1178; R600-NEXT:    7(9.809089e-45), 0(0.000000e+00)1179; R600-NEXT:     BIT_ALIGN_INT * T0.X, 1, KC0[3].Y, KC0[4].Y,1180; R600-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,1181; R600-NEXT:    2(2.802597e-45), 0(0.000000e+00)1182;1183; GFX10-LABEL: fshr_v4i32_imm_src0:1184; GFX10:       ; %bb.0: ; %entry1185; GFX10-NEXT:    s_clause 0x11186; GFX10-NEXT:    s_load_dwordx8 s[8:15], s[4:5], 0x341187; GFX10-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x241188; GFX10-NEXT:    s_mov_b32 s1, 331189; GFX10-NEXT:    s_mov_b32 s3, 71190; GFX10-NEXT:    v_mov_b32_e32 v4, 01191; GFX10-NEXT:    s_waitcnt lgkmcnt(0)1192; GFX10-NEXT:    s_mov_b32 s0, s111193; GFX10-NEXT:    s_and_b32 s4, s15, 311194; GFX10-NEXT:    s_mov_b32 s11, 91195; GFX10-NEXT:    s_and_b32 s5, s14, 311196; GFX10-NEXT:    s_mov_b32 s2, s91197; GFX10-NEXT:    s_and_b32 s13, s13, 311198; GFX10-NEXT:    s_mov_b32 s9, 11199; GFX10-NEXT:    s_and_b32 s12, s12, 311200; GFX10-NEXT:    s_lshr_b64 s[0:1], s[0:1], s41201; GFX10-NEXT:    s_lshr_b64 s[4:5], s[10:11], s51202; GFX10-NEXT:    s_lshr_b64 s[8:9], s[8:9], s121203; GFX10-NEXT:    s_lshr_b64 s[2:3], s[2:3], s131204; GFX10-NEXT:    v_mov_b32_e32 v0, s81205; GFX10-NEXT:    v_mov_b32_e32 v1, s21206; GFX10-NEXT:    v_mov_b32_e32 v2, s41207; GFX10-NEXT:    v_mov_b32_e32 v3, s01208; GFX10-NEXT:    global_store_dwordx4 v4, v[0:3], s[6:7]1209; GFX10-NEXT:    s_endpgm1210;1211; GFX11-LABEL: fshr_v4i32_imm_src0:1212; GFX11:       ; %bb.0: ; %entry1213; GFX11-NEXT:    s_clause 0x11214; GFX11-NEXT:    s_load_b256 s[8:15], s[4:5], 0x341215; GFX11-NEXT:    s_load_b64 s[4:5], s[4:5], 0x241216; GFX11-NEXT:    s_mov_b32 s1, 331217; GFX11-NEXT:    s_mov_b32 s3, 71218; GFX11-NEXT:    s_waitcnt lgkmcnt(0)1219; GFX11-NEXT:    s_mov_b32 s0, s111220; GFX11-NEXT:    s_and_b32 s6, s15, 311221; GFX11-NEXT:    s_mov_b32 s11, 91222; GFX11-NEXT:    s_and_b32 s7, s14, 311223; GFX11-NEXT:    s_mov_b32 s2, s91224; GFX11-NEXT:    s_and_b32 s13, s13, 311225; GFX11-NEXT:    s_mov_b32 s9, 11226; GFX11-NEXT:    s_and_b32 s12, s12, 311227; GFX11-NEXT:    s_lshr_b64 s[0:1], s[0:1], s61228; GFX11-NEXT:    s_lshr_b64 s[6:7], s[10:11], s71229; GFX11-NEXT:    s_lshr_b64 s[8:9], s[8:9], s121230; GFX11-NEXT:    s_lshr_b64 s[2:3], s[2:3], s131231; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)1232; GFX11-NEXT:    v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v1, s21233; GFX11-NEXT:    v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v3, s01234; GFX11-NEXT:    v_mov_b32_e32 v2, s61235; GFX11-NEXT:    global_store_b128 v4, v[0:3], s[4:5]1236; GFX11-NEXT:    s_endpgm1237;1238; GFX12-LABEL: fshr_v4i32_imm_src0:1239; GFX12:       ; %bb.0: ; %entry1240; GFX12-NEXT:    s_clause 0x11241; GFX12-NEXT:    s_load_b256 s[8:15], s[4:5], 0x341242; GFX12-NEXT:    s_load_b64 s[4:5], s[4:5], 0x241243; GFX12-NEXT:    s_mov_b32 s1, 331244; GFX12-NEXT:    s_mov_b32 s3, 71245; GFX12-NEXT:    s_wait_kmcnt 0x01246; GFX12-NEXT:    s_mov_b32 s0, s111247; GFX12-NEXT:    s_and_b32 s6, s15, 311248; GFX12-NEXT:    s_mov_b32 s11, 91249; GFX12-NEXT:    s_and_b32 s7, s14, 311250; GFX12-NEXT:    s_mov_b32 s2, s91251; GFX12-NEXT:    s_and_b32 s13, s13, 311252; GFX12-NEXT:    s_mov_b32 s9, 11253; GFX12-NEXT:    s_and_b32 s12, s12, 311254; GFX12-NEXT:    s_lshr_b64 s[0:1], s[0:1], s61255; GFX12-NEXT:    s_lshr_b64 s[6:7], s[10:11], s71256; GFX12-NEXT:    s_lshr_b64 s[8:9], s[8:9], s121257; GFX12-NEXT:    s_lshr_b64 s[2:3], s[2:3], s131258; GFX12-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)1259; GFX12-NEXT:    v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v1, s21260; GFX12-NEXT:    v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v3, s01261; GFX12-NEXT:    v_mov_b32_e32 v2, s61262; GFX12-NEXT:    global_store_b128 v4, v[0:3], s[4:5]1263; GFX12-NEXT:    s_endpgm1264entry:1265  %0 = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> <i32 1, i32 7, i32 9, i32 33>, <4 x i32> %x, <4 x i32> %y)1266  store <4 x i32> %0, ptr addrspace(1) %in1267  ret void1268}1269 1270define i32 @v_fshr_i32(i32 %src0, i32 %src1, i32 %src2) {1271; GFX89-LABEL: v_fshr_i32:1272; GFX89:       ; %bb.0:1273; GFX89-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1274; GFX89-NEXT:    v_alignbit_b32 v0, v0, v1, v21275; GFX89-NEXT:    s_setpc_b64 s[30:31]1276;1277; R600-LABEL: v_fshr_i32:1278; R600:       ; %bb.0:1279; R600-NEXT:    CF_END1280; R600-NEXT:    PAD1281;1282; GFX10-LABEL: v_fshr_i32:1283; GFX10:       ; %bb.0:1284; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1285; GFX10-NEXT:    v_alignbit_b32 v0, v0, v1, v21286; GFX10-NEXT:    s_setpc_b64 s[30:31]1287;1288; GFX11-TRUE16-LABEL: v_fshr_i32:1289; GFX11-TRUE16:       ; %bb.0:1290; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1291; GFX11-TRUE16-NEXT:    v_alignbit_b32 v0, v0, v1, v2.l1292; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]1293;1294; GFX11-FAKE16-LABEL: v_fshr_i32:1295; GFX11-FAKE16:       ; %bb.0:1296; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1297; GFX11-FAKE16-NEXT:    v_alignbit_b32 v0, v0, v1, v21298; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]1299;1300; GFX12-TRUE16-LABEL: v_fshr_i32:1301; GFX12-TRUE16:       ; %bb.0:1302; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x01303; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x01304; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x01305; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x01306; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x01307; GFX12-TRUE16-NEXT:    v_alignbit_b32 v0, v0, v1, v2.l1308; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]1309;1310; GFX12-FAKE16-LABEL: v_fshr_i32:1311; GFX12-FAKE16:       ; %bb.0:1312; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x01313; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x01314; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x01315; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x01316; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x01317; GFX12-FAKE16-NEXT:    v_alignbit_b32 v0, v0, v1, v21318; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]1319  %ret = call i32 @llvm.fshr.i32(i32 %src0, i32 %src1, i32 %src2)1320  ret i32 %ret1321}1322 1323define <2 x i32> @v_fshr_v2i32(<2 x i32> %src0, <2 x i32> %src1, <2 x i32> %src2) {1324; GFX89-LABEL: v_fshr_v2i32:1325; GFX89:       ; %bb.0:1326; GFX89-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1327; GFX89-NEXT:    v_alignbit_b32 v0, v0, v2, v41328; GFX89-NEXT:    v_alignbit_b32 v1, v1, v3, v51329; GFX89-NEXT:    s_setpc_b64 s[30:31]1330;1331; R600-LABEL: v_fshr_v2i32:1332; R600:       ; %bb.0:1333; R600-NEXT:    CF_END1334; R600-NEXT:    PAD1335;1336; GFX10-LABEL: v_fshr_v2i32:1337; GFX10:       ; %bb.0:1338; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1339; GFX10-NEXT:    v_alignbit_b32 v0, v0, v2, v41340; GFX10-NEXT:    v_alignbit_b32 v1, v1, v3, v51341; GFX10-NEXT:    s_setpc_b64 s[30:31]1342;1343; GFX11-TRUE16-LABEL: v_fshr_v2i32:1344; GFX11-TRUE16:       ; %bb.0:1345; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1346; GFX11-TRUE16-NEXT:    v_alignbit_b32 v0, v0, v2, v4.l1347; GFX11-TRUE16-NEXT:    v_alignbit_b32 v1, v1, v3, v5.l1348; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]1349;1350; GFX11-FAKE16-LABEL: v_fshr_v2i32:1351; GFX11-FAKE16:       ; %bb.0:1352; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1353; GFX11-FAKE16-NEXT:    v_alignbit_b32 v0, v0, v2, v41354; GFX11-FAKE16-NEXT:    v_alignbit_b32 v1, v1, v3, v51355; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]1356;1357; GFX12-TRUE16-LABEL: v_fshr_v2i32:1358; GFX12-TRUE16:       ; %bb.0:1359; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x01360; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x01361; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x01362; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x01363; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x01364; GFX12-TRUE16-NEXT:    v_alignbit_b32 v0, v0, v2, v4.l1365; GFX12-TRUE16-NEXT:    v_alignbit_b32 v1, v1, v3, v5.l1366; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]1367;1368; GFX12-FAKE16-LABEL: v_fshr_v2i32:1369; GFX12-FAKE16:       ; %bb.0:1370; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x01371; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x01372; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x01373; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x01374; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x01375; GFX12-FAKE16-NEXT:    v_alignbit_b32 v0, v0, v2, v41376; GFX12-FAKE16-NEXT:    v_alignbit_b32 v1, v1, v3, v51377; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]1378  %ret = call <2 x i32> @llvm.fshr.v2i32(<2 x i32> %src0, <2 x i32> %src1, <2 x i32> %src2)1379  ret <2 x i32> %ret1380}1381 1382define <3 x i32> @v_fshr_v3i32(<3 x i32> %src0, <3 x i32> %src1, <3 x i32> %src2) {1383; GFX89-LABEL: v_fshr_v3i32:1384; GFX89:       ; %bb.0:1385; GFX89-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1386; GFX89-NEXT:    v_alignbit_b32 v0, v0, v3, v61387; GFX89-NEXT:    v_alignbit_b32 v1, v1, v4, v71388; GFX89-NEXT:    v_alignbit_b32 v2, v2, v5, v81389; GFX89-NEXT:    s_setpc_b64 s[30:31]1390;1391; R600-LABEL: v_fshr_v3i32:1392; R600:       ; %bb.0:1393; R600-NEXT:    CF_END1394; R600-NEXT:    PAD1395;1396; GFX10-LABEL: v_fshr_v3i32:1397; GFX10:       ; %bb.0:1398; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1399; GFX10-NEXT:    v_alignbit_b32 v0, v0, v3, v61400; GFX10-NEXT:    v_alignbit_b32 v1, v1, v4, v71401; GFX10-NEXT:    v_alignbit_b32 v2, v2, v5, v81402; GFX10-NEXT:    s_setpc_b64 s[30:31]1403;1404; GFX11-TRUE16-LABEL: v_fshr_v3i32:1405; GFX11-TRUE16:       ; %bb.0:1406; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1407; GFX11-TRUE16-NEXT:    v_alignbit_b32 v0, v0, v3, v6.l1408; GFX11-TRUE16-NEXT:    v_alignbit_b32 v1, v1, v4, v7.l1409; GFX11-TRUE16-NEXT:    v_alignbit_b32 v2, v2, v5, v8.l1410; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]1411;1412; GFX11-FAKE16-LABEL: v_fshr_v3i32:1413; GFX11-FAKE16:       ; %bb.0:1414; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1415; GFX11-FAKE16-NEXT:    v_alignbit_b32 v0, v0, v3, v61416; GFX11-FAKE16-NEXT:    v_alignbit_b32 v1, v1, v4, v71417; GFX11-FAKE16-NEXT:    v_alignbit_b32 v2, v2, v5, v81418; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]1419;1420; GFX12-TRUE16-LABEL: v_fshr_v3i32:1421; GFX12-TRUE16:       ; %bb.0:1422; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x01423; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x01424; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x01425; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x01426; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x01427; GFX12-TRUE16-NEXT:    v_alignbit_b32 v0, v0, v3, v6.l1428; GFX12-TRUE16-NEXT:    v_alignbit_b32 v1, v1, v4, v7.l1429; GFX12-TRUE16-NEXT:    v_alignbit_b32 v2, v2, v5, v8.l1430; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]1431;1432; GFX12-FAKE16-LABEL: v_fshr_v3i32:1433; GFX12-FAKE16:       ; %bb.0:1434; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x01435; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x01436; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x01437; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x01438; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x01439; GFX12-FAKE16-NEXT:    v_alignbit_b32 v0, v0, v3, v61440; GFX12-FAKE16-NEXT:    v_alignbit_b32 v1, v1, v4, v71441; GFX12-FAKE16-NEXT:    v_alignbit_b32 v2, v2, v5, v81442; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]1443  %ret = call <3 x i32> @llvm.fshr.v3i32(<3 x i32> %src0, <3 x i32> %src1, <3 x i32> %src2)1444  ret <3 x i32> %ret1445}1446 1447define <4 x i32> @v_fshr_v4i32(<4 x i32> %src0, <4 x i32> %src1, <4 x i32> %src2) {1448; GFX89-LABEL: v_fshr_v4i32:1449; GFX89:       ; %bb.0:1450; GFX89-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1451; GFX89-NEXT:    v_alignbit_b32 v0, v0, v4, v81452; GFX89-NEXT:    v_alignbit_b32 v1, v1, v5, v91453; GFX89-NEXT:    v_alignbit_b32 v2, v2, v6, v101454; GFX89-NEXT:    v_alignbit_b32 v3, v3, v7, v111455; GFX89-NEXT:    s_setpc_b64 s[30:31]1456;1457; R600-LABEL: v_fshr_v4i32:1458; R600:       ; %bb.0:1459; R600-NEXT:    CF_END1460; R600-NEXT:    PAD1461;1462; GFX10-LABEL: v_fshr_v4i32:1463; GFX10:       ; %bb.0:1464; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1465; GFX10-NEXT:    v_alignbit_b32 v0, v0, v4, v81466; GFX10-NEXT:    v_alignbit_b32 v1, v1, v5, v91467; GFX10-NEXT:    v_alignbit_b32 v2, v2, v6, v101468; GFX10-NEXT:    v_alignbit_b32 v3, v3, v7, v111469; GFX10-NEXT:    s_setpc_b64 s[30:31]1470;1471; GFX11-TRUE16-LABEL: v_fshr_v4i32:1472; GFX11-TRUE16:       ; %bb.0:1473; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1474; GFX11-TRUE16-NEXT:    v_alignbit_b32 v0, v0, v4, v8.l1475; GFX11-TRUE16-NEXT:    v_alignbit_b32 v1, v1, v5, v9.l1476; GFX11-TRUE16-NEXT:    v_alignbit_b32 v2, v2, v6, v10.l1477; GFX11-TRUE16-NEXT:    v_alignbit_b32 v3, v3, v7, v11.l1478; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]1479;1480; GFX11-FAKE16-LABEL: v_fshr_v4i32:1481; GFX11-FAKE16:       ; %bb.0:1482; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1483; GFX11-FAKE16-NEXT:    v_alignbit_b32 v0, v0, v4, v81484; GFX11-FAKE16-NEXT:    v_alignbit_b32 v1, v1, v5, v91485; GFX11-FAKE16-NEXT:    v_alignbit_b32 v2, v2, v6, v101486; GFX11-FAKE16-NEXT:    v_alignbit_b32 v3, v3, v7, v111487; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]1488;1489; GFX12-TRUE16-LABEL: v_fshr_v4i32:1490; GFX12-TRUE16:       ; %bb.0:1491; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x01492; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x01493; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x01494; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x01495; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x01496; GFX12-TRUE16-NEXT:    v_alignbit_b32 v0, v0, v4, v8.l1497; GFX12-TRUE16-NEXT:    v_alignbit_b32 v1, v1, v5, v9.l1498; GFX12-TRUE16-NEXT:    v_alignbit_b32 v2, v2, v6, v10.l1499; GFX12-TRUE16-NEXT:    v_alignbit_b32 v3, v3, v7, v11.l1500; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]1501;1502; GFX12-FAKE16-LABEL: v_fshr_v4i32:1503; GFX12-FAKE16:       ; %bb.0:1504; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x01505; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x01506; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x01507; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x01508; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x01509; GFX12-FAKE16-NEXT:    v_alignbit_b32 v0, v0, v4, v81510; GFX12-FAKE16-NEXT:    v_alignbit_b32 v1, v1, v5, v91511; GFX12-FAKE16-NEXT:    v_alignbit_b32 v2, v2, v6, v101512; GFX12-FAKE16-NEXT:    v_alignbit_b32 v3, v3, v7, v111513; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]1514  %ret = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %src0, <4 x i32> %src1, <4 x i32> %src2)1515  ret <4 x i32> %ret1516}1517 1518define i16 @v_fshr_i16(i16 %src0, i16 %src1, i16 %src2) {1519; SI-LABEL: v_fshr_i16:1520; SI:       ; %bb.0:1521; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1522; SI-NEXT:    v_or_b32_e32 v2, 16, v21523; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v11524; SI-NEXT:    v_alignbit_b32 v0, v0, v1, v21525; SI-NEXT:    s_setpc_b64 s[30:31]1526;1527; VI-LABEL: v_fshr_i16:1528; VI:       ; %bb.0:1529; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1530; VI-NEXT:    v_lshlrev_b16_e32 v0, 1, v01531; VI-NEXT:    v_xor_b32_e32 v3, -1, v21532; VI-NEXT:    v_lshlrev_b16_e32 v0, v3, v01533; VI-NEXT:    v_lshrrev_b16_e32 v1, v2, v11534; VI-NEXT:    v_or_b32_e32 v0, v0, v11535; VI-NEXT:    s_setpc_b64 s[30:31]1536;1537; GFX9-LABEL: v_fshr_i16:1538; GFX9:       ; %bb.0:1539; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1540; GFX9-NEXT:    v_lshlrev_b16_e32 v0, 1, v01541; GFX9-NEXT:    v_xor_b32_e32 v3, -1, v21542; GFX9-NEXT:    v_lshlrev_b16_e32 v0, v3, v01543; GFX9-NEXT:    v_lshrrev_b16_e32 v1, v2, v11544; GFX9-NEXT:    v_or_b32_e32 v0, v0, v11545; GFX9-NEXT:    s_setpc_b64 s[30:31]1546;1547; R600-LABEL: v_fshr_i16:1548; R600:       ; %bb.0:1549; R600-NEXT:    CF_END1550; R600-NEXT:    PAD1551;1552; GFX10-LABEL: v_fshr_i16:1553; GFX10:       ; %bb.0:1554; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1555; GFX10-NEXT:    v_lshlrev_b16 v0, 1, v01556; GFX10-NEXT:    v_xor_b32_e32 v3, -1, v21557; GFX10-NEXT:    v_lshrrev_b16 v1, v2, v11558; GFX10-NEXT:    v_lshlrev_b16 v0, v3, v01559; GFX10-NEXT:    v_or_b32_e32 v0, v0, v11560; GFX10-NEXT:    s_setpc_b64 s[30:31]1561;1562; GFX11-TRUE16-LABEL: v_fshr_i16:1563; GFX11-TRUE16:       ; %bb.0:1564; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1565; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v0.l, 1, v0.l1566; GFX11-TRUE16-NEXT:    v_xor_b16 v0.h, v2.l, -11567; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)1568; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v0.l, v0.h, v0.l1569; GFX11-TRUE16-NEXT:    v_lshrrev_b16 v0.h, v2.l, v1.l1570; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v0.h1571; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]1572;1573; GFX11-FAKE16-LABEL: v_fshr_i16:1574; GFX11-FAKE16:       ; %bb.0:1575; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1576; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v0, 1, v01577; GFX11-FAKE16-NEXT:    v_xor_b32_e32 v3, -1, v21578; GFX11-FAKE16-NEXT:    v_lshrrev_b16 v1, v2, v11579; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)1580; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v0, v3, v01581; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v11582; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]1583;1584; GFX12-TRUE16-LABEL: v_fshr_i16:1585; GFX12-TRUE16:       ; %bb.0:1586; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x01587; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x01588; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x01589; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x01590; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x01591; GFX12-TRUE16-NEXT:    v_lshlrev_b16 v0.l, 1, v0.l1592; GFX12-TRUE16-NEXT:    v_xor_b16 v0.h, v2.l, -11593; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)1594; GFX12-TRUE16-NEXT:    v_lshlrev_b16 v0.l, v0.h, v0.l1595; GFX12-TRUE16-NEXT:    v_lshrrev_b16 v0.h, v2.l, v1.l1596; GFX12-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v0.h1597; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]1598;1599; GFX12-FAKE16-LABEL: v_fshr_i16:1600; GFX12-FAKE16:       ; %bb.0:1601; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x01602; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x01603; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x01604; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x01605; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x01606; GFX12-FAKE16-NEXT:    v_lshlrev_b16 v0, 1, v01607; GFX12-FAKE16-NEXT:    v_xor_b32_e32 v3, -1, v21608; GFX12-FAKE16-NEXT:    v_lshrrev_b16 v1, v2, v11609; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)1610; GFX12-FAKE16-NEXT:    v_lshlrev_b16 v0, v3, v01611; GFX12-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v11612; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]1613  %ret = call i16 @llvm.fshr.i16(i16 %src0, i16 %src1, i16 %src2)1614  ret i16 %ret1615}1616 1617define <2 x i16> @v_fshr_v2i16(<2 x i16> %src0, <2 x i16> %src1, <2 x i16> %src2) {1618; SI-LABEL: v_fshr_v2i16:1619; SI:       ; %bb.0:1620; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1621; SI-NEXT:    v_or_b32_e32 v5, 16, v51622; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v31623; SI-NEXT:    v_or_b32_e32 v4, 16, v41624; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v21625; SI-NEXT:    v_alignbit_b32 v1, v1, v3, v51626; SI-NEXT:    v_alignbit_b32 v0, v0, v2, v41627; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v11628; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v01629; SI-NEXT:    v_or_b32_e32 v0, v0, v31630; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v11631; SI-NEXT:    s_setpc_b64 s[30:31]1632;1633; VI-LABEL: v_fshr_v2i16:1634; VI:       ; %bb.0:1635; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1636; VI-NEXT:    v_mov_b32_e32 v4, 11637; VI-NEXT:    v_mov_b32_e32 v5, -11638; VI-NEXT:    v_lshlrev_b16_sdwa v4, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_11639; VI-NEXT:    v_xor_b32_sdwa v5, v2, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1640; VI-NEXT:    v_lshrrev_b16_sdwa v3, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_11641; VI-NEXT:    v_lshlrev_b16_e32 v4, v5, v41642; VI-NEXT:    v_or_b32_sdwa v3, v4, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD1643; VI-NEXT:    v_lshlrev_b16_e32 v0, 1, v01644; VI-NEXT:    v_xor_b32_e32 v4, -1, v21645; VI-NEXT:    v_lshlrev_b16_e32 v0, v4, v01646; VI-NEXT:    v_lshrrev_b16_e32 v1, v2, v11647; VI-NEXT:    v_or_b32_e32 v0, v0, v11648; VI-NEXT:    v_or_b32_sdwa v0, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD1649; VI-NEXT:    s_setpc_b64 s[30:31]1650;1651; GFX9-LABEL: v_fshr_v2i16:1652; GFX9:       ; %bb.0:1653; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1654; GFX9-NEXT:    v_xor_b32_e32 v3, -1, v21655; GFX9-NEXT:    v_pk_lshlrev_b16 v0, 1, v0 op_sel_hi:[0,1]1656; GFX9-NEXT:    v_and_b32_e32 v3, 0xf000f, v31657; GFX9-NEXT:    v_and_b32_e32 v2, 0xf000f, v21658; GFX9-NEXT:    v_pk_lshlrev_b16 v0, v3, v01659; GFX9-NEXT:    v_pk_lshrrev_b16 v1, v2, v11660; GFX9-NEXT:    v_or_b32_e32 v0, v0, v11661; GFX9-NEXT:    s_setpc_b64 s[30:31]1662;1663; R600-LABEL: v_fshr_v2i16:1664; R600:       ; %bb.0:1665; R600-NEXT:    CF_END1666; R600-NEXT:    PAD1667;1668; GFX10-LABEL: v_fshr_v2i16:1669; GFX10:       ; %bb.0:1670; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1671; GFX10-NEXT:    v_xor_b32_e32 v3, -1, v21672; GFX10-NEXT:    v_pk_lshlrev_b16 v0, 1, v0 op_sel_hi:[0,1]1673; GFX10-NEXT:    v_and_b32_e32 v2, 0xf000f, v21674; GFX10-NEXT:    v_and_b32_e32 v3, 0xf000f, v31675; GFX10-NEXT:    v_pk_lshrrev_b16 v1, v2, v11676; GFX10-NEXT:    v_pk_lshlrev_b16 v0, v3, v01677; GFX10-NEXT:    v_or_b32_e32 v0, v0, v11678; GFX10-NEXT:    s_setpc_b64 s[30:31]1679;1680; GFX11-LABEL: v_fshr_v2i16:1681; GFX11:       ; %bb.0:1682; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1683; GFX11-NEXT:    v_xor_b32_e32 v3, -1, v21684; GFX11-NEXT:    v_pk_lshlrev_b16 v0, 1, v0 op_sel_hi:[0,1]1685; GFX11-NEXT:    v_and_b32_e32 v2, 0xf000f, v21686; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)1687; GFX11-NEXT:    v_and_b32_e32 v3, 0xf000f, v31688; GFX11-NEXT:    v_pk_lshrrev_b16 v1, v2, v11689; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)1690; GFX11-NEXT:    v_pk_lshlrev_b16 v0, v3, v01691; GFX11-NEXT:    v_or_b32_e32 v0, v0, v11692; GFX11-NEXT:    s_setpc_b64 s[30:31]1693;1694; GFX12-LABEL: v_fshr_v2i16:1695; GFX12:       ; %bb.0:1696; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x01697; GFX12-NEXT:    s_wait_expcnt 0x01698; GFX12-NEXT:    s_wait_samplecnt 0x01699; GFX12-NEXT:    s_wait_bvhcnt 0x01700; GFX12-NEXT:    s_wait_kmcnt 0x01701; GFX12-NEXT:    v_xor_b32_e32 v3, -1, v21702; GFX12-NEXT:    v_pk_lshlrev_b16 v0, 1, v0 op_sel_hi:[0,1]1703; GFX12-NEXT:    v_and_b32_e32 v2, 0xf000f, v21704; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)1705; GFX12-NEXT:    v_and_b32_e32 v3, 0xf000f, v31706; GFX12-NEXT:    v_pk_lshrrev_b16 v1, v2, v11707; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)1708; GFX12-NEXT:    v_pk_lshlrev_b16 v0, v3, v01709; GFX12-NEXT:    v_or_b32_e32 v0, v0, v11710; GFX12-NEXT:    s_setpc_b64 s[30:31]1711  %ret = call <2 x i16> @llvm.fshr.v2i16(<2 x i16> %src0, <2 x i16> %src1, <2 x i16> %src2)1712  ret <2 x i16> %ret1713}1714 1715define <3 x i16> @v_fshr_v3i16(<3 x i16> %src0, <3 x i16> %src1, <3 x i16> %src2) {1716; SI-LABEL: v_fshr_v3i16:1717; SI:       ; %bb.0:1718; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1719; SI-NEXT:    v_or_b32_e32 v7, 16, v71720; SI-NEXT:    v_lshlrev_b32_e32 v4, 16, v41721; SI-NEXT:    v_alignbit_b32 v1, v1, v4, v71722; SI-NEXT:    v_or_b32_e32 v4, 16, v61723; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v31724; SI-NEXT:    v_alignbit_b32 v0, v0, v3, v41725; SI-NEXT:    v_or_b32_e32 v3, 16, v81726; SI-NEXT:    v_lshlrev_b32_e32 v4, 16, v51727; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v11728; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v01729; SI-NEXT:    v_alignbit_b32 v3, v2, v4, v31730; SI-NEXT:    v_or_b32_e32 v0, v0, v11731; SI-NEXT:    v_and_b32_e32 v2, 0xffff, v31732; SI-NEXT:    v_alignbit_b32 v1, v3, v1, 161733; SI-NEXT:    s_setpc_b64 s[30:31]1734;1735; VI-LABEL: v_fshr_v3i16:1736; VI:       ; %bb.0:1737; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1738; VI-NEXT:    v_mov_b32_e32 v7, 11739; VI-NEXT:    v_mov_b32_e32 v8, -11740; VI-NEXT:    v_lshlrev_b16_sdwa v7, v7, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_11741; VI-NEXT:    v_xor_b32_sdwa v8, v4, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1742; VI-NEXT:    v_lshrrev_b16_sdwa v6, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_11743; VI-NEXT:    v_lshlrev_b16_e32 v7, v8, v71744; VI-NEXT:    v_or_b32_sdwa v6, v7, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD1745; VI-NEXT:    v_lshlrev_b16_e32 v1, 1, v11746; VI-NEXT:    v_xor_b32_e32 v7, -1, v51747; VI-NEXT:    v_lshlrev_b16_e32 v1, v7, v11748; VI-NEXT:    v_lshrrev_b16_e32 v3, v5, v31749; VI-NEXT:    v_or_b32_e32 v1, v1, v31750; VI-NEXT:    v_lshlrev_b16_e32 v0, 1, v01751; VI-NEXT:    v_xor_b32_e32 v3, -1, v41752; VI-NEXT:    v_lshlrev_b16_e32 v0, v3, v01753; VI-NEXT:    v_lshrrev_b16_e32 v2, v4, v21754; VI-NEXT:    v_or_b32_e32 v0, v0, v21755; VI-NEXT:    v_or_b32_sdwa v0, v0, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD1756; VI-NEXT:    s_setpc_b64 s[30:31]1757;1758; GFX9-LABEL: v_fshr_v3i16:1759; GFX9:       ; %bb.0:1760; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1761; GFX9-NEXT:    v_mov_b32_e32 v7, 11762; GFX9-NEXT:    v_mov_b32_e32 v8, -11763; GFX9-NEXT:    v_lshlrev_b16_sdwa v7, v7, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_11764; GFX9-NEXT:    v_xor_b32_sdwa v8, v4, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1765; GFX9-NEXT:    v_lshrrev_b16_sdwa v6, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_11766; GFX9-NEXT:    v_lshlrev_b16_e32 v7, v8, v71767; GFX9-NEXT:    v_or_b32_e32 v6, v7, v61768; GFX9-NEXT:    v_lshlrev_b16_e32 v1, 1, v11769; GFX9-NEXT:    v_xor_b32_e32 v7, -1, v51770; GFX9-NEXT:    v_lshlrev_b16_e32 v1, v7, v11771; GFX9-NEXT:    v_lshrrev_b16_e32 v3, v5, v31772; GFX9-NEXT:    v_or_b32_e32 v1, v1, v31773; GFX9-NEXT:    v_lshlrev_b16_e32 v0, 1, v01774; GFX9-NEXT:    v_xor_b32_e32 v3, -1, v41775; GFX9-NEXT:    v_lshlrev_b16_e32 v0, v3, v01776; GFX9-NEXT:    v_lshrrev_b16_e32 v2, v4, v21777; GFX9-NEXT:    v_or_b32_e32 v0, v0, v21778; GFX9-NEXT:    s_mov_b32 s4, 0x50401001779; GFX9-NEXT:    v_perm_b32 v0, v6, v0, s41780; GFX9-NEXT:    s_setpc_b64 s[30:31]1781;1782; R600-LABEL: v_fshr_v3i16:1783; R600:       ; %bb.0:1784; R600-NEXT:    CF_END1785; R600-NEXT:    PAD1786;1787; GFX10-LABEL: v_fshr_v3i16:1788; GFX10:       ; %bb.0:1789; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1790; GFX10-NEXT:    v_lshrrev_b32_e32 v6, 16, v01791; GFX10-NEXT:    v_lshrrev_b32_e32 v7, 16, v41792; GFX10-NEXT:    v_lshrrev_b32_e32 v8, 16, v21793; GFX10-NEXT:    v_lshlrev_b16 v0, 1, v01794; GFX10-NEXT:    v_xor_b32_e32 v10, -1, v41795; GFX10-NEXT:    v_lshlrev_b16 v6, 1, v61796; GFX10-NEXT:    v_xor_b32_e32 v9, -1, v71797; GFX10-NEXT:    v_lshlrev_b16 v1, 1, v11798; GFX10-NEXT:    v_lshrrev_b16 v7, v7, v81799; GFX10-NEXT:    v_lshlrev_b16 v0, v10, v01800; GFX10-NEXT:    v_lshrrev_b16 v2, v4, v21801; GFX10-NEXT:    v_lshlrev_b16 v6, v9, v61802; GFX10-NEXT:    v_xor_b32_e32 v4, -1, v51803; GFX10-NEXT:    v_lshrrev_b16 v3, v5, v31804; GFX10-NEXT:    v_or_b32_e32 v0, v0, v21805; GFX10-NEXT:    v_or_b32_e32 v5, v6, v71806; GFX10-NEXT:    v_lshlrev_b16 v1, v4, v11807; GFX10-NEXT:    v_perm_b32 v0, v5, v0, 0x50401001808; GFX10-NEXT:    v_or_b32_e32 v1, v1, v31809; GFX10-NEXT:    s_setpc_b64 s[30:31]1810;1811; GFX11-TRUE16-LABEL: v_fshr_v3i16:1812; GFX11-TRUE16:       ; %bb.0:1813; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1814; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v0.h, 1, v0.h1815; GFX11-TRUE16-NEXT:    v_xor_b16 v1.h, v4.h, -11816; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v1.l, 1, v1.l1817; GFX11-TRUE16-NEXT:    v_xor_b16 v3.h, v5.l, -11818; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v0.l, 1, v0.l1819; GFX11-TRUE16-NEXT:    v_xor_b16 v5.h, v4.l, -11820; GFX11-TRUE16-NEXT:    v_lshrrev_b16 v2.h, v4.h, v2.h1821; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v0.h, v1.h, v0.h1822; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v1.l, v3.h, v1.l1823; GFX11-TRUE16-NEXT:    v_lshrrev_b16 v1.h, v4.l, v2.l1824; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v0.l, v5.h, v0.l1825; GFX11-TRUE16-NEXT:    v_lshrrev_b16 v2.l, v5.l, v3.l1826; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v0.h, v2.h1827; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)1828; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v1.h1829; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v2.l1830; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]1831;1832; GFX11-FAKE16-LABEL: v_fshr_v3i16:1833; GFX11-FAKE16:       ; %bb.0:1834; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1835; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v01836; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 16, v41837; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v8, 16, v21838; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v0, 1, v01839; GFX11-FAKE16-NEXT:    v_xor_b32_e32 v10, -1, v41840; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v6, 1, v61841; GFX11-FAKE16-NEXT:    v_xor_b32_e32 v9, -1, v71842; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v1, 1, v11843; GFX11-FAKE16-NEXT:    v_lshrrev_b16 v7, v7, v81844; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v0, v10, v01845; GFX11-FAKE16-NEXT:    v_lshrrev_b16 v2, v4, v21846; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v6, v9, v61847; GFX11-FAKE16-NEXT:    v_xor_b32_e32 v4, -1, v51848; GFX11-FAKE16-NEXT:    v_lshrrev_b16 v3, v5, v31849; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)1850; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v21851; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v6, v71852; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)1853; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v1, v4, v11854; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v5, v0, 0x50401001855; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)1856; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v31857; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]1858;1859; GFX12-TRUE16-LABEL: v_fshr_v3i16:1860; GFX12-TRUE16:       ; %bb.0:1861; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x01862; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x01863; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x01864; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x01865; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x01866; GFX12-TRUE16-NEXT:    v_lshlrev_b16 v0.h, 1, v0.h1867; GFX12-TRUE16-NEXT:    v_xor_b16 v1.h, v4.h, -11868; GFX12-TRUE16-NEXT:    v_lshlrev_b16 v1.l, 1, v1.l1869; GFX12-TRUE16-NEXT:    v_xor_b16 v3.h, v5.l, -11870; GFX12-TRUE16-NEXT:    v_lshlrev_b16 v0.l, 1, v0.l1871; GFX12-TRUE16-NEXT:    v_xor_b16 v5.h, v4.l, -11872; GFX12-TRUE16-NEXT:    v_lshrrev_b16 v2.h, v4.h, v2.h1873; GFX12-TRUE16-NEXT:    v_lshlrev_b16 v0.h, v1.h, v0.h1874; GFX12-TRUE16-NEXT:    v_lshlrev_b16 v1.l, v3.h, v1.l1875; GFX12-TRUE16-NEXT:    v_lshrrev_b16 v1.h, v4.l, v2.l1876; GFX12-TRUE16-NEXT:    v_lshlrev_b16 v0.l, v5.h, v0.l1877; GFX12-TRUE16-NEXT:    v_lshrrev_b16 v2.l, v5.l, v3.l1878; GFX12-TRUE16-NEXT:    v_or_b16 v0.h, v0.h, v2.h1879; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)1880; GFX12-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v1.h1881; GFX12-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v2.l1882; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]1883;1884; GFX12-FAKE16-LABEL: v_fshr_v3i16:1885; GFX12-FAKE16:       ; %bb.0:1886; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x01887; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x01888; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x01889; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x01890; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x01891; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v01892; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 16, v41893; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v8, 16, v21894; GFX12-FAKE16-NEXT:    v_lshlrev_b16 v0, 1, v01895; GFX12-FAKE16-NEXT:    v_xor_b32_e32 v10, -1, v41896; GFX12-FAKE16-NEXT:    v_lshlrev_b16 v6, 1, v61897; GFX12-FAKE16-NEXT:    v_xor_b32_e32 v9, -1, v71898; GFX12-FAKE16-NEXT:    v_lshlrev_b16 v1, 1, v11899; GFX12-FAKE16-NEXT:    v_lshrrev_b16 v7, v7, v81900; GFX12-FAKE16-NEXT:    v_lshlrev_b16 v0, v10, v01901; GFX12-FAKE16-NEXT:    v_lshrrev_b16 v2, v4, v21902; GFX12-FAKE16-NEXT:    v_lshlrev_b16 v6, v9, v61903; GFX12-FAKE16-NEXT:    v_xor_b32_e32 v4, -1, v51904; GFX12-FAKE16-NEXT:    v_lshrrev_b16 v3, v5, v31905; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)1906; GFX12-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v21907; GFX12-FAKE16-NEXT:    v_or_b32_e32 v5, v6, v71908; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)1909; GFX12-FAKE16-NEXT:    v_lshlrev_b16 v1, v4, v11910; GFX12-FAKE16-NEXT:    v_perm_b32 v0, v5, v0, 0x50401001911; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)1912; GFX12-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v31913; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]1914  %ret = call <3 x i16> @llvm.fshr.v3i16(<3 x i16> %src0, <3 x i16> %src1, <3 x i16> %src2)1915  ret <3 x i16> %ret1916}1917 1918define <4 x i16> @v_fshr_v4i16(<4 x i16> %src0, <4 x i16> %src1, <4 x i16> %src2) {1919; SI-LABEL: v_fshr_v4i16:1920; SI:       ; %bb.0:1921; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1922; SI-NEXT:    v_or_b32_e32 v9, 16, v91923; SI-NEXT:    v_lshlrev_b32_e32 v5, 16, v51924; SI-NEXT:    v_alignbit_b32 v1, v1, v5, v91925; SI-NEXT:    v_or_b32_e32 v5, 16, v81926; SI-NEXT:    v_lshlrev_b32_e32 v4, 16, v41927; SI-NEXT:    v_alignbit_b32 v0, v0, v4, v51928; SI-NEXT:    v_or_b32_e32 v4, 16, v111929; SI-NEXT:    v_lshlrev_b32_e32 v5, 16, v71930; SI-NEXT:    v_alignbit_b32 v3, v3, v5, v41931; SI-NEXT:    v_or_b32_e32 v5, 16, v101932; SI-NEXT:    v_lshlrev_b32_e32 v6, 16, v61933; SI-NEXT:    v_alignbit_b32 v2, v2, v6, v51934; SI-NEXT:    v_lshlrev_b32_e32 v4, 16, v31935; SI-NEXT:    v_and_b32_e32 v2, 0xffff, v21936; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v11937; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v01938; SI-NEXT:    v_or_b32_e32 v2, v2, v41939; SI-NEXT:    v_or_b32_e32 v0, v0, v11940; SI-NEXT:    v_alignbit_b32 v1, v2, v1, 161941; SI-NEXT:    v_and_b32_e32 v3, 0xffff, v31942; SI-NEXT:    s_setpc_b64 s[30:31]1943;1944; VI-LABEL: v_fshr_v4i16:1945; VI:       ; %bb.0:1946; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1947; VI-NEXT:    v_mov_b32_e32 v7, 11948; VI-NEXT:    v_mov_b32_e32 v9, -11949; VI-NEXT:    v_lshlrev_b16_sdwa v8, v7, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_11950; VI-NEXT:    v_xor_b32_sdwa v10, v5, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1951; VI-NEXT:    v_lshrrev_b16_sdwa v6, v5, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_11952; VI-NEXT:    v_lshlrev_b16_e32 v8, v10, v81953; VI-NEXT:    v_lshlrev_b16_sdwa v7, v7, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_11954; VI-NEXT:    v_xor_b32_sdwa v9, v4, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1955; VI-NEXT:    v_or_b32_sdwa v6, v8, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD1956; VI-NEXT:    v_lshrrev_b16_sdwa v8, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_11957; VI-NEXT:    v_lshlrev_b16_e32 v7, v9, v71958; VI-NEXT:    v_or_b32_sdwa v7, v7, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD1959; VI-NEXT:    v_lshlrev_b16_e32 v1, 1, v11960; VI-NEXT:    v_xor_b32_e32 v8, -1, v51961; VI-NEXT:    v_lshlrev_b16_e32 v1, v8, v11962; VI-NEXT:    v_lshrrev_b16_e32 v3, v5, v31963; VI-NEXT:    v_or_b32_e32 v1, v1, v31964; VI-NEXT:    v_lshlrev_b16_e32 v0, 1, v01965; VI-NEXT:    v_xor_b32_e32 v3, -1, v41966; VI-NEXT:    v_lshlrev_b16_e32 v0, v3, v01967; VI-NEXT:    v_lshrrev_b16_e32 v2, v4, v21968; VI-NEXT:    v_or_b32_e32 v0, v0, v21969; VI-NEXT:    v_or_b32_sdwa v0, v0, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD1970; VI-NEXT:    v_or_b32_sdwa v1, v1, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD1971; VI-NEXT:    s_setpc_b64 s[30:31]1972;1973; GFX9-LABEL: v_fshr_v4i16:1974; GFX9:       ; %bb.0:1975; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1976; GFX9-NEXT:    v_mov_b32_e32 v7, 11977; GFX9-NEXT:    v_mov_b32_e32 v9, -11978; GFX9-NEXT:    v_lshlrev_b16_sdwa v8, v7, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_11979; GFX9-NEXT:    v_xor_b32_sdwa v10, v5, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1980; GFX9-NEXT:    v_lshrrev_b16_sdwa v6, v5, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_11981; GFX9-NEXT:    v_lshlrev_b16_e32 v8, v10, v81982; GFX9-NEXT:    v_lshlrev_b16_sdwa v7, v7, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_11983; GFX9-NEXT:    v_xor_b32_sdwa v9, v4, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1984; GFX9-NEXT:    v_or_b32_e32 v6, v8, v61985; GFX9-NEXT:    v_lshrrev_b16_sdwa v8, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_11986; GFX9-NEXT:    v_lshlrev_b16_e32 v7, v9, v71987; GFX9-NEXT:    v_or_b32_e32 v7, v7, v81988; GFX9-NEXT:    v_lshlrev_b16_e32 v1, 1, v11989; GFX9-NEXT:    v_xor_b32_e32 v8, -1, v51990; GFX9-NEXT:    v_lshlrev_b16_e32 v1, v8, v11991; GFX9-NEXT:    v_lshrrev_b16_e32 v3, v5, v31992; GFX9-NEXT:    v_or_b32_e32 v1, v1, v31993; GFX9-NEXT:    v_lshlrev_b16_e32 v0, 1, v01994; GFX9-NEXT:    v_xor_b32_e32 v3, -1, v41995; GFX9-NEXT:    v_lshlrev_b16_e32 v0, v3, v01996; GFX9-NEXT:    v_lshrrev_b16_e32 v2, v4, v21997; GFX9-NEXT:    v_or_b32_e32 v0, v0, v21998; GFX9-NEXT:    s_mov_b32 s4, 0x50401001999; GFX9-NEXT:    v_perm_b32 v0, v7, v0, s42000; GFX9-NEXT:    v_perm_b32 v1, v6, v1, s42001; GFX9-NEXT:    s_setpc_b64 s[30:31]2002;2003; R600-LABEL: v_fshr_v4i16:2004; R600:       ; %bb.0:2005; R600-NEXT:    CF_END2006; R600-NEXT:    PAD2007;2008; GFX10-LABEL: v_fshr_v4i16:2009; GFX10:       ; %bb.0:2010; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2011; GFX10-NEXT:    v_lshrrev_b32_e32 v6, 16, v32012; GFX10-NEXT:    v_lshrrev_b32_e32 v7, 16, v52013; GFX10-NEXT:    v_lshrrev_b32_e32 v8, 16, v12014; GFX10-NEXT:    v_lshrrev_b32_e32 v9, 16, v02015; GFX10-NEXT:    v_lshrrev_b32_e32 v10, 16, v42016; GFX10-NEXT:    v_lshrrev_b32_e32 v11, 16, v22017; GFX10-NEXT:    v_lshrrev_b16 v6, v7, v62018; GFX10-NEXT:    v_lshlrev_b16 v8, 1, v82019; GFX10-NEXT:    v_xor_b32_e32 v7, -1, v72020; GFX10-NEXT:    v_lshlrev_b16 v9, 1, v92021; GFX10-NEXT:    v_xor_b32_e32 v12, -1, v102022; GFX10-NEXT:    v_lshlrev_b16 v1, 1, v12023; GFX10-NEXT:    v_xor_b32_e32 v13, -1, v52024; GFX10-NEXT:    v_lshlrev_b16 v0, 1, v02025; GFX10-NEXT:    v_xor_b32_e32 v14, -1, v42026; GFX10-NEXT:    v_lshlrev_b16 v7, v7, v82027; GFX10-NEXT:    v_lshrrev_b16 v8, v10, v112028; GFX10-NEXT:    v_lshlrev_b16 v9, v12, v92029; GFX10-NEXT:    v_lshlrev_b16 v1, v13, v12030; GFX10-NEXT:    v_lshlrev_b16 v0, v14, v02031; GFX10-NEXT:    v_lshrrev_b16 v2, v4, v22032; GFX10-NEXT:    v_lshrrev_b16 v3, v5, v32033; GFX10-NEXT:    v_or_b32_e32 v4, v7, v62034; GFX10-NEXT:    v_or_b32_e32 v5, v9, v82035; GFX10-NEXT:    v_or_b32_e32 v0, v0, v22036; GFX10-NEXT:    v_or_b32_e32 v1, v1, v32037; GFX10-NEXT:    v_perm_b32 v0, v5, v0, 0x50401002038; GFX10-NEXT:    v_perm_b32 v1, v4, v1, 0x50401002039; GFX10-NEXT:    s_setpc_b64 s[30:31]2040;2041; GFX11-TRUE16-LABEL: v_fshr_v4i16:2042; GFX11-TRUE16:       ; %bb.0:2043; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2044; GFX11-TRUE16-NEXT:    v_lshrrev_b16 v3.h, v5.h, v3.h2045; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v1.h, 1, v1.h2046; GFX11-TRUE16-NEXT:    v_xor_b16 v5.h, v5.h, -12047; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v0.h, 1, v0.h2048; GFX11-TRUE16-NEXT:    v_xor_b16 v6.l, v4.h, -12049; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v1.l, 1, v1.l2050; GFX11-TRUE16-NEXT:    v_xor_b16 v6.h, v5.l, -12051; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v0.l, 1, v0.l2052; GFX11-TRUE16-NEXT:    v_xor_b16 v7.l, v4.l, -12053; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v1.h, v5.h, v1.h2054; GFX11-TRUE16-NEXT:    v_lshrrev_b16 v2.h, v4.h, v2.h2055; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v0.h, v6.l, v0.h2056; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v1.l, v6.h, v1.l2057; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v0.l, v7.l, v0.l2058; GFX11-TRUE16-NEXT:    v_lshrrev_b16 v2.l, v4.l, v2.l2059; GFX11-TRUE16-NEXT:    v_lshrrev_b16 v3.l, v5.l, v3.l2060; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v1.h, v3.h2061; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v0.h, v2.h2062; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)2063; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v2.l2064; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v3.l2065; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]2066;2067; GFX11-FAKE16-LABEL: v_fshr_v4i16:2068; GFX11-FAKE16:       ; %bb.0:2069; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2070; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v32071; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 16, v52072; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v8, 16, v12073; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v9, 16, v02074; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v10, 16, v42075; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v11, 16, v22076; GFX11-FAKE16-NEXT:    v_lshrrev_b16 v6, v7, v62077; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v8, 1, v82078; GFX11-FAKE16-NEXT:    v_xor_b32_e32 v7, -1, v72079; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v9, 1, v92080; GFX11-FAKE16-NEXT:    v_xor_b32_e32 v12, -1, v102081; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v1, 1, v12082; GFX11-FAKE16-NEXT:    v_xor_b32_e32 v13, -1, v52083; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v0, 1, v02084; GFX11-FAKE16-NEXT:    v_xor_b32_e32 v14, -1, v42085; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v7, v7, v82086; GFX11-FAKE16-NEXT:    v_lshrrev_b16 v8, v10, v112087; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v9, v12, v92088; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v1, v13, v12089; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v0, v14, v02090; GFX11-FAKE16-NEXT:    v_lshrrev_b16 v2, v4, v22091; GFX11-FAKE16-NEXT:    v_lshrrev_b16 v3, v5, v32092; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v7, v62093; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v9, v82094; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)2095; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v22096; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v32097; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)2098; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v5, v0, 0x50401002099; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v4, v1, 0x50401002100; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]2101;2102; GFX12-TRUE16-LABEL: v_fshr_v4i16:2103; GFX12-TRUE16:       ; %bb.0:2104; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x02105; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x02106; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x02107; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x02108; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x02109; GFX12-TRUE16-NEXT:    v_lshrrev_b16 v3.h, v5.h, v3.h2110; GFX12-TRUE16-NEXT:    v_lshlrev_b16 v1.h, 1, v1.h2111; GFX12-TRUE16-NEXT:    v_xor_b16 v5.h, v5.h, -12112; GFX12-TRUE16-NEXT:    v_lshlrev_b16 v0.h, 1, v0.h2113; GFX12-TRUE16-NEXT:    v_xor_b16 v6.l, v4.h, -12114; GFX12-TRUE16-NEXT:    v_lshlrev_b16 v1.l, 1, v1.l2115; GFX12-TRUE16-NEXT:    v_xor_b16 v6.h, v5.l, -12116; GFX12-TRUE16-NEXT:    v_lshlrev_b16 v0.l, 1, v0.l2117; GFX12-TRUE16-NEXT:    v_xor_b16 v7.l, v4.l, -12118; GFX12-TRUE16-NEXT:    v_lshlrev_b16 v1.h, v5.h, v1.h2119; GFX12-TRUE16-NEXT:    v_lshrrev_b16 v2.h, v4.h, v2.h2120; GFX12-TRUE16-NEXT:    v_lshlrev_b16 v0.h, v6.l, v0.h2121; GFX12-TRUE16-NEXT:    v_lshlrev_b16 v1.l, v6.h, v1.l2122; GFX12-TRUE16-NEXT:    v_lshlrev_b16 v0.l, v7.l, v0.l2123; GFX12-TRUE16-NEXT:    v_lshrrev_b16 v2.l, v4.l, v2.l2124; GFX12-TRUE16-NEXT:    v_lshrrev_b16 v3.l, v5.l, v3.l2125; GFX12-TRUE16-NEXT:    v_or_b16 v1.h, v1.h, v3.h2126; GFX12-TRUE16-NEXT:    v_or_b16 v0.h, v0.h, v2.h2127; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)2128; GFX12-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v2.l2129; GFX12-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v3.l2130; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]2131;2132; GFX12-FAKE16-LABEL: v_fshr_v4i16:2133; GFX12-FAKE16:       ; %bb.0:2134; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x02135; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x02136; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x02137; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x02138; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x02139; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v32140; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 16, v52141; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v8, 16, v12142; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v9, 16, v02143; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v10, 16, v42144; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v11, 16, v22145; GFX12-FAKE16-NEXT:    v_lshrrev_b16 v6, v7, v62146; GFX12-FAKE16-NEXT:    v_lshlrev_b16 v8, 1, v82147; GFX12-FAKE16-NEXT:    v_xor_b32_e32 v7, -1, v72148; GFX12-FAKE16-NEXT:    v_lshlrev_b16 v9, 1, v92149; GFX12-FAKE16-NEXT:    v_xor_b32_e32 v12, -1, v102150; GFX12-FAKE16-NEXT:    v_lshlrev_b16 v1, 1, v12151; GFX12-FAKE16-NEXT:    v_xor_b32_e32 v13, -1, v52152; GFX12-FAKE16-NEXT:    v_lshlrev_b16 v0, 1, v02153; GFX12-FAKE16-NEXT:    v_xor_b32_e32 v14, -1, v42154; GFX12-FAKE16-NEXT:    v_lshlrev_b16 v7, v7, v82155; GFX12-FAKE16-NEXT:    v_lshrrev_b16 v8, v10, v112156; GFX12-FAKE16-NEXT:    v_lshlrev_b16 v9, v12, v92157; GFX12-FAKE16-NEXT:    v_lshlrev_b16 v1, v13, v12158; GFX12-FAKE16-NEXT:    v_lshlrev_b16 v0, v14, v02159; GFX12-FAKE16-NEXT:    v_lshrrev_b16 v2, v4, v22160; GFX12-FAKE16-NEXT:    v_lshrrev_b16 v3, v5, v32161; GFX12-FAKE16-NEXT:    v_or_b32_e32 v4, v7, v62162; GFX12-FAKE16-NEXT:    v_or_b32_e32 v5, v9, v82163; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)2164; GFX12-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v22165; GFX12-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v32166; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)2167; GFX12-FAKE16-NEXT:    v_perm_b32 v0, v5, v0, 0x50401002168; GFX12-FAKE16-NEXT:    v_perm_b32 v1, v4, v1, 0x50401002169; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]2170  %ret = call <4 x i16> @llvm.fshr.v4i16(<4 x i16> %src0, <4 x i16> %src1, <4 x i16> %src2)2171  ret <4 x i16> %ret2172}2173 2174define i64 @v_fshr_i64(i64 %src0, i64 %src1, i64 %src2) {2175; SI-LABEL: v_fshr_i64:2176; SI:       ; %bb.0:2177; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2178; SI-NEXT:    v_lshl_b64 v[0:1], v[0:1], 12179; SI-NEXT:    v_lshr_b64 v[2:3], v[2:3], v42180; SI-NEXT:    v_not_b32_e32 v4, v42181; SI-NEXT:    v_lshl_b64 v[0:1], v[0:1], v42182; SI-NEXT:    v_or_b32_e32 v1, v1, v32183; SI-NEXT:    v_or_b32_e32 v0, v0, v22184; SI-NEXT:    s_setpc_b64 s[30:31]2185;2186; VI-LABEL: v_fshr_i64:2187; VI:       ; %bb.0:2188; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2189; VI-NEXT:    v_lshlrev_b64 v[0:1], 1, v[0:1]2190; VI-NEXT:    v_lshrrev_b64 v[2:3], v4, v[2:3]2191; VI-NEXT:    v_not_b32_e32 v4, v42192; VI-NEXT:    v_lshlrev_b64 v[0:1], v4, v[0:1]2193; VI-NEXT:    v_or_b32_e32 v1, v1, v32194; VI-NEXT:    v_or_b32_e32 v0, v0, v22195; VI-NEXT:    s_setpc_b64 s[30:31]2196;2197; GFX9-LABEL: v_fshr_i64:2198; GFX9:       ; %bb.0:2199; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2200; GFX9-NEXT:    v_lshlrev_b64 v[0:1], 1, v[0:1]2201; GFX9-NEXT:    v_lshrrev_b64 v[2:3], v4, v[2:3]2202; GFX9-NEXT:    v_not_b32_e32 v4, v42203; GFX9-NEXT:    v_lshlrev_b64 v[0:1], v4, v[0:1]2204; GFX9-NEXT:    v_or_b32_e32 v1, v1, v32205; GFX9-NEXT:    v_or_b32_e32 v0, v0, v22206; GFX9-NEXT:    s_setpc_b64 s[30:31]2207;2208; R600-LABEL: v_fshr_i64:2209; R600:       ; %bb.0:2210; R600-NEXT:    CF_END2211; R600-NEXT:    PAD2212;2213; GFX10-LABEL: v_fshr_i64:2214; GFX10:       ; %bb.0:2215; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2216; GFX10-NEXT:    v_lshlrev_b64 v[0:1], 1, v[0:1]2217; GFX10-NEXT:    v_not_b32_e32 v5, v42218; GFX10-NEXT:    v_lshrrev_b64 v[2:3], v4, v[2:3]2219; GFX10-NEXT:    v_lshlrev_b64 v[0:1], v5, v[0:1]2220; GFX10-NEXT:    v_or_b32_e32 v0, v0, v22221; GFX10-NEXT:    v_or_b32_e32 v1, v1, v32222; GFX10-NEXT:    s_setpc_b64 s[30:31]2223;2224; GFX11-LABEL: v_fshr_i64:2225; GFX11:       ; %bb.0:2226; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2227; GFX11-NEXT:    v_lshlrev_b64 v[0:1], 1, v[0:1]2228; GFX11-NEXT:    v_not_b32_e32 v5, v42229; GFX11-NEXT:    v_lshrrev_b64 v[2:3], v4, v[2:3]2230; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)2231; GFX11-NEXT:    v_lshlrev_b64 v[0:1], v5, v[0:1]2232; GFX11-NEXT:    v_or_b32_e32 v0, v0, v22233; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)2234; GFX11-NEXT:    v_or_b32_e32 v1, v1, v32235; GFX11-NEXT:    s_setpc_b64 s[30:31]2236;2237; GFX12-LABEL: v_fshr_i64:2238; GFX12:       ; %bb.0:2239; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x02240; GFX12-NEXT:    s_wait_expcnt 0x02241; GFX12-NEXT:    s_wait_samplecnt 0x02242; GFX12-NEXT:    s_wait_bvhcnt 0x02243; GFX12-NEXT:    s_wait_kmcnt 0x02244; GFX12-NEXT:    v_lshlrev_b64_e32 v[0:1], 1, v[0:1]2245; GFX12-NEXT:    v_not_b32_e32 v5, v42246; GFX12-NEXT:    v_lshrrev_b64 v[2:3], v4, v[2:3]2247; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)2248; GFX12-NEXT:    v_lshlrev_b64_e32 v[0:1], v5, v[0:1]2249; GFX12-NEXT:    v_or_b32_e32 v0, v0, v22250; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_2)2251; GFX12-NEXT:    v_or_b32_e32 v1, v1, v32252; GFX12-NEXT:    s_setpc_b64 s[30:31]2253  %ret = call i64 @llvm.fshr.i64(i64 %src0, i64 %src1, i64 %src2)2254  ret i64 %ret2255}2256 2257define <2 x i64> @v_fshr_v2i64(<2 x i64> %src0, <2 x i64> %src1, <2 x i64> %src2) {2258; SI-LABEL: v_fshr_v2i64:2259; SI:       ; %bb.0:2260; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2261; SI-NEXT:    v_lshl_b64 v[0:1], v[0:1], 12262; SI-NEXT:    v_lshr_b64 v[4:5], v[4:5], v82263; SI-NEXT:    v_not_b32_e32 v8, v82264; SI-NEXT:    v_lshl_b64 v[0:1], v[0:1], v82265; SI-NEXT:    v_lshl_b64 v[2:3], v[2:3], 12266; SI-NEXT:    v_or_b32_e32 v1, v1, v52267; SI-NEXT:    v_lshr_b64 v[5:6], v[6:7], v102268; SI-NEXT:    v_not_b32_e32 v7, v102269; SI-NEXT:    v_lshl_b64 v[2:3], v[2:3], v72270; SI-NEXT:    v_or_b32_e32 v0, v0, v42271; SI-NEXT:    v_or_b32_e32 v3, v3, v62272; SI-NEXT:    v_or_b32_e32 v2, v2, v52273; SI-NEXT:    s_setpc_b64 s[30:31]2274;2275; VI-LABEL: v_fshr_v2i64:2276; VI:       ; %bb.0:2277; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2278; VI-NEXT:    v_lshlrev_b64 v[0:1], 1, v[0:1]2279; VI-NEXT:    v_lshrrev_b64 v[4:5], v8, v[4:5]2280; VI-NEXT:    v_not_b32_e32 v8, v82281; VI-NEXT:    v_lshlrev_b64 v[0:1], v8, v[0:1]2282; VI-NEXT:    v_lshlrev_b64 v[2:3], 1, v[2:3]2283; VI-NEXT:    v_or_b32_e32 v1, v1, v52284; VI-NEXT:    v_lshrrev_b64 v[5:6], v10, v[6:7]2285; VI-NEXT:    v_not_b32_e32 v7, v102286; VI-NEXT:    v_lshlrev_b64 v[2:3], v7, v[2:3]2287; VI-NEXT:    v_or_b32_e32 v0, v0, v42288; VI-NEXT:    v_or_b32_e32 v3, v3, v62289; VI-NEXT:    v_or_b32_e32 v2, v2, v52290; VI-NEXT:    s_setpc_b64 s[30:31]2291;2292; GFX9-LABEL: v_fshr_v2i64:2293; GFX9:       ; %bb.0:2294; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2295; GFX9-NEXT:    v_lshlrev_b64 v[0:1], 1, v[0:1]2296; GFX9-NEXT:    v_lshrrev_b64 v[4:5], v8, v[4:5]2297; GFX9-NEXT:    v_not_b32_e32 v8, v82298; GFX9-NEXT:    v_lshlrev_b64 v[0:1], v8, v[0:1]2299; GFX9-NEXT:    v_lshlrev_b64 v[2:3], 1, v[2:3]2300; GFX9-NEXT:    v_or_b32_e32 v1, v1, v52301; GFX9-NEXT:    v_lshrrev_b64 v[5:6], v10, v[6:7]2302; GFX9-NEXT:    v_not_b32_e32 v7, v102303; GFX9-NEXT:    v_lshlrev_b64 v[2:3], v7, v[2:3]2304; GFX9-NEXT:    v_or_b32_e32 v0, v0, v42305; GFX9-NEXT:    v_or_b32_e32 v3, v3, v62306; GFX9-NEXT:    v_or_b32_e32 v2, v2, v52307; GFX9-NEXT:    s_setpc_b64 s[30:31]2308;2309; R600-LABEL: v_fshr_v2i64:2310; R600:       ; %bb.0:2311; R600-NEXT:    CF_END2312; R600-NEXT:    PAD2313;2314; GFX10-LABEL: v_fshr_v2i64:2315; GFX10:       ; %bb.0:2316; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2317; GFX10-NEXT:    v_lshlrev_b64 v[0:1], 1, v[0:1]2318; GFX10-NEXT:    v_lshlrev_b64 v[2:3], 1, v[2:3]2319; GFX10-NEXT:    v_not_b32_e32 v9, v82320; GFX10-NEXT:    v_not_b32_e32 v11, v102321; GFX10-NEXT:    v_lshrrev_b64 v[4:5], v8, v[4:5]2322; GFX10-NEXT:    v_lshrrev_b64 v[6:7], v10, v[6:7]2323; GFX10-NEXT:    v_lshlrev_b64 v[0:1], v9, v[0:1]2324; GFX10-NEXT:    v_lshlrev_b64 v[2:3], v11, v[2:3]2325; GFX10-NEXT:    v_or_b32_e32 v0, v0, v42326; GFX10-NEXT:    v_or_b32_e32 v1, v1, v52327; GFX10-NEXT:    v_or_b32_e32 v2, v2, v62328; GFX10-NEXT:    v_or_b32_e32 v3, v3, v72329; GFX10-NEXT:    s_setpc_b64 s[30:31]2330;2331; GFX11-LABEL: v_fshr_v2i64:2332; GFX11:       ; %bb.0:2333; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2334; GFX11-NEXT:    v_lshlrev_b64 v[0:1], 1, v[0:1]2335; GFX11-NEXT:    v_lshlrev_b64 v[2:3], 1, v[2:3]2336; GFX11-NEXT:    v_not_b32_e32 v9, v82337; GFX11-NEXT:    v_not_b32_e32 v11, v102338; GFX11-NEXT:    v_lshrrev_b64 v[4:5], v8, v[4:5]2339; GFX11-NEXT:    v_lshrrev_b64 v[6:7], v10, v[6:7]2340; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)2341; GFX11-NEXT:    v_lshlrev_b64 v[0:1], v9, v[0:1]2342; GFX11-NEXT:    v_lshlrev_b64 v[2:3], v11, v[2:3]2343; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)2344; GFX11-NEXT:    v_or_b32_e32 v0, v0, v42345; GFX11-NEXT:    v_or_b32_e32 v1, v1, v52346; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)2347; GFX11-NEXT:    v_or_b32_e32 v2, v2, v62348; GFX11-NEXT:    v_or_b32_e32 v3, v3, v72349; GFX11-NEXT:    s_setpc_b64 s[30:31]2350;2351; GFX12-LABEL: v_fshr_v2i64:2352; GFX12:       ; %bb.0:2353; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x02354; GFX12-NEXT:    s_wait_expcnt 0x02355; GFX12-NEXT:    s_wait_samplecnt 0x02356; GFX12-NEXT:    s_wait_bvhcnt 0x02357; GFX12-NEXT:    s_wait_kmcnt 0x02358; GFX12-NEXT:    v_lshlrev_b64_e32 v[0:1], 1, v[0:1]2359; GFX12-NEXT:    v_lshlrev_b64_e32 v[2:3], 1, v[2:3]2360; GFX12-NEXT:    v_not_b32_e32 v9, v82361; GFX12-NEXT:    v_not_b32_e32 v11, v102362; GFX12-NEXT:    v_lshrrev_b64 v[4:5], v8, v[4:5]2363; GFX12-NEXT:    v_lshrrev_b64 v[6:7], v10, v[6:7]2364; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)2365; GFX12-NEXT:    v_lshlrev_b64_e32 v[0:1], v9, v[0:1]2366; GFX12-NEXT:    v_lshlrev_b64_e32 v[2:3], v11, v[2:3]2367; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)2368; GFX12-NEXT:    v_or_b32_e32 v0, v0, v42369; GFX12-NEXT:    v_or_b32_e32 v1, v1, v52370; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)2371; GFX12-NEXT:    v_or_b32_e32 v2, v2, v62372; GFX12-NEXT:    v_or_b32_e32 v3, v3, v72373; GFX12-NEXT:    s_setpc_b64 s[30:31]2374  %ret = call <2 x i64> @llvm.fshr.v2i64(<2 x i64> %src0, <2 x i64> %src1, <2 x i64> %src2)2375  ret <2 x i64> %ret2376}2377 2378define i24 @v_fshr_i24(i24 %src0, i24 %src1, i24 %src2) {2379; SI-LABEL: v_fshr_i24:2380; SI:       ; %bb.0:2381; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2382; SI-NEXT:    v_and_b32_e32 v3, 0xffffff, v22383; SI-NEXT:    s_mov_b32 s4, 0xaaaaaab2384; SI-NEXT:    v_mul_hi_u32 v3, v3, s42385; SI-NEXT:    v_lshlrev_b32_e32 v1, 8, v12386; SI-NEXT:    v_mul_u32_u24_e32 v3, 24, v32387; SI-NEXT:    v_sub_i32_e32 v2, vcc, v2, v32388; SI-NEXT:    v_add_i32_e32 v2, vcc, 8, v22389; SI-NEXT:    v_alignbit_b32 v0, v0, v1, v22390; SI-NEXT:    s_setpc_b64 s[30:31]2391;2392; VI-LABEL: v_fshr_i24:2393; VI:       ; %bb.0:2394; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2395; VI-NEXT:    v_and_b32_e32 v3, 0xffffff, v22396; VI-NEXT:    s_mov_b32 s4, 0xaaaaaab2397; VI-NEXT:    v_mul_hi_u32 v3, v3, s42398; VI-NEXT:    v_lshlrev_b32_e32 v1, 8, v12399; VI-NEXT:    v_mul_u32_u24_e32 v3, 24, v32400; VI-NEXT:    v_sub_u32_e32 v2, vcc, v2, v32401; VI-NEXT:    v_add_u32_e32 v2, vcc, 8, v22402; VI-NEXT:    v_alignbit_b32 v0, v0, v1, v22403; VI-NEXT:    s_setpc_b64 s[30:31]2404;2405; GFX9-LABEL: v_fshr_i24:2406; GFX9:       ; %bb.0:2407; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2408; GFX9-NEXT:    v_and_b32_e32 v3, 0xffffff, v22409; GFX9-NEXT:    s_mov_b32 s4, 0xaaaaaab2410; GFX9-NEXT:    v_mul_hi_u32 v3, v3, s42411; GFX9-NEXT:    v_lshlrev_b32_e32 v1, 8, v12412; GFX9-NEXT:    v_mul_u32_u24_e32 v3, 24, v32413; GFX9-NEXT:    v_sub_u32_e32 v2, v2, v32414; GFX9-NEXT:    v_add_u32_e32 v2, 8, v22415; GFX9-NEXT:    v_alignbit_b32 v0, v0, v1, v22416; GFX9-NEXT:    s_setpc_b64 s[30:31]2417;2418; R600-LABEL: v_fshr_i24:2419; R600:       ; %bb.0:2420; R600-NEXT:    CF_END2421; R600-NEXT:    PAD2422;2423; GFX10-LABEL: v_fshr_i24:2424; GFX10:       ; %bb.0:2425; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2426; GFX10-NEXT:    v_and_b32_e32 v3, 0xffffff, v22427; GFX10-NEXT:    v_lshlrev_b32_e32 v1, 8, v12428; GFX10-NEXT:    v_mul_hi_u32 v3, 0xaaaaaab, v32429; GFX10-NEXT:    v_mul_u32_u24_e32 v3, 24, v32430; GFX10-NEXT:    v_sub_nc_u32_e32 v2, v2, v32431; GFX10-NEXT:    v_add_nc_u32_e32 v2, 8, v22432; GFX10-NEXT:    v_alignbit_b32 v0, v0, v1, v22433; GFX10-NEXT:    s_setpc_b64 s[30:31]2434;2435; GFX11-TRUE16-LABEL: v_fshr_i24:2436; GFX11-TRUE16:       ; %bb.0:2437; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2438; GFX11-TRUE16-NEXT:    v_and_b32_e32 v3, 0xffffff, v22439; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 8, v12440; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)2441; GFX11-TRUE16-NEXT:    v_mul_hi_u32 v3, 0xaaaaaab, v32442; GFX11-TRUE16-NEXT:    v_mul_u32_u24_e32 v3, 24, v32443; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)2444; GFX11-TRUE16-NEXT:    v_sub_nc_u32_e32 v2, v2, v32445; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v2, 8, v22446; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)2447; GFX11-TRUE16-NEXT:    v_alignbit_b32 v0, v0, v1, v2.l2448; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]2449;2450; GFX11-FAKE16-LABEL: v_fshr_i24:2451; GFX11-FAKE16:       ; %bb.0:2452; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2453; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffffff, v22454; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 8, v12455; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)2456; GFX11-FAKE16-NEXT:    v_mul_hi_u32 v3, 0xaaaaaab, v32457; GFX11-FAKE16-NEXT:    v_mul_u32_u24_e32 v3, 24, v32458; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)2459; GFX11-FAKE16-NEXT:    v_sub_nc_u32_e32 v2, v2, v32460; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v2, 8, v22461; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)2462; GFX11-FAKE16-NEXT:    v_alignbit_b32 v0, v0, v1, v22463; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]2464;2465; GFX12-TRUE16-LABEL: v_fshr_i24:2466; GFX12-TRUE16:       ; %bb.0:2467; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x02468; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x02469; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x02470; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x02471; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x02472; GFX12-TRUE16-NEXT:    v_and_b32_e32 v3, 0xffffff, v22473; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 8, v12474; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)2475; GFX12-TRUE16-NEXT:    v_mul_hi_u32 v3, 0xaaaaaab, v32476; GFX12-TRUE16-NEXT:    v_mul_u32_u24_e32 v3, 24, v32477; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)2478; GFX12-TRUE16-NEXT:    v_sub_nc_u32_e32 v2, v2, v32479; GFX12-TRUE16-NEXT:    v_add_nc_u32_e32 v2, 8, v22480; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)2481; GFX12-TRUE16-NEXT:    v_alignbit_b32 v0, v0, v1, v2.l2482; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]2483;2484; GFX12-FAKE16-LABEL: v_fshr_i24:2485; GFX12-FAKE16:       ; %bb.0:2486; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x02487; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x02488; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x02489; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x02490; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x02491; GFX12-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffffff, v22492; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 8, v12493; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)2494; GFX12-FAKE16-NEXT:    v_mul_hi_u32 v3, 0xaaaaaab, v32495; GFX12-FAKE16-NEXT:    v_mul_u32_u24_e32 v3, 24, v32496; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)2497; GFX12-FAKE16-NEXT:    v_sub_nc_u32_e32 v2, v2, v32498; GFX12-FAKE16-NEXT:    v_add_nc_u32_e32 v2, 8, v22499; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)2500; GFX12-FAKE16-NEXT:    v_alignbit_b32 v0, v0, v1, v22501; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]2502  %ret = call i24 @llvm.fshr.i24(i24 %src0, i24 %src1, i24 %src2)2503  ret i24 %ret2504}2505 2506define <2 x i24> @v_fshr_v2i24(<2 x i24> %src0, <2 x i24> %src1, <2 x i24> %src2) {2507; SI-LABEL: v_fshr_v2i24:2508; SI:       ; %bb.0:2509; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2510; SI-NEXT:    v_and_b32_e32 v4, 0xffffff, v42511; SI-NEXT:    s_mov_b32 s4, 0xaaaaaab2512; SI-NEXT:    v_mul_hi_u32 v6, v4, s42513; SI-NEXT:    v_and_b32_e32 v5, 0xffffff, v52514; SI-NEXT:    v_lshlrev_b32_e32 v2, 8, v22515; SI-NEXT:    v_lshlrev_b32_e32 v3, 8, v32516; SI-NEXT:    v_mul_u32_u24_e32 v6, 24, v62517; SI-NEXT:    v_sub_i32_e32 v4, vcc, v4, v62518; SI-NEXT:    v_mul_hi_u32 v6, v5, s42519; SI-NEXT:    v_add_i32_e32 v4, vcc, 8, v42520; SI-NEXT:    v_alignbit_b32 v0, v0, v2, v42521; SI-NEXT:    v_mul_u32_u24_e32 v2, 24, v62522; SI-NEXT:    v_sub_i32_e32 v2, vcc, v5, v22523; SI-NEXT:    v_add_i32_e32 v2, vcc, 8, v22524; SI-NEXT:    v_alignbit_b32 v1, v1, v3, v22525; SI-NEXT:    s_setpc_b64 s[30:31]2526;2527; VI-LABEL: v_fshr_v2i24:2528; VI:       ; %bb.0:2529; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2530; VI-NEXT:    v_and_b32_e32 v4, 0xffffff, v42531; VI-NEXT:    s_mov_b32 s4, 0xaaaaaab2532; VI-NEXT:    v_mul_hi_u32 v6, v4, s42533; VI-NEXT:    v_and_b32_e32 v5, 0xffffff, v52534; VI-NEXT:    v_lshlrev_b32_e32 v2, 8, v22535; VI-NEXT:    v_lshlrev_b32_e32 v3, 8, v32536; VI-NEXT:    v_mul_u32_u24_e32 v6, 24, v62537; VI-NEXT:    v_sub_u32_e32 v4, vcc, v4, v62538; VI-NEXT:    v_mul_hi_u32 v6, v5, s42539; VI-NEXT:    v_add_u32_e32 v4, vcc, 8, v42540; VI-NEXT:    v_alignbit_b32 v0, v0, v2, v42541; VI-NEXT:    v_mul_u32_u24_e32 v2, 24, v62542; VI-NEXT:    v_sub_u32_e32 v2, vcc, v5, v22543; VI-NEXT:    v_add_u32_e32 v2, vcc, 8, v22544; VI-NEXT:    v_alignbit_b32 v1, v1, v3, v22545; VI-NEXT:    s_setpc_b64 s[30:31]2546;2547; GFX9-LABEL: v_fshr_v2i24:2548; GFX9:       ; %bb.0:2549; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2550; GFX9-NEXT:    v_and_b32_e32 v4, 0xffffff, v42551; GFX9-NEXT:    s_mov_b32 s4, 0xaaaaaab2552; GFX9-NEXT:    v_mul_hi_u32 v6, v4, s42553; GFX9-NEXT:    v_and_b32_e32 v5, 0xffffff, v52554; GFX9-NEXT:    v_lshlrev_b32_e32 v2, 8, v22555; GFX9-NEXT:    v_lshlrev_b32_e32 v3, 8, v32556; GFX9-NEXT:    v_mul_u32_u24_e32 v6, 24, v62557; GFX9-NEXT:    v_sub_u32_e32 v4, v4, v62558; GFX9-NEXT:    v_mul_hi_u32 v6, v5, s42559; GFX9-NEXT:    v_add_u32_e32 v4, 8, v42560; GFX9-NEXT:    v_alignbit_b32 v0, v0, v2, v42561; GFX9-NEXT:    v_mul_u32_u24_e32 v2, 24, v62562; GFX9-NEXT:    v_sub_u32_e32 v2, v5, v22563; GFX9-NEXT:    v_add_u32_e32 v2, 8, v22564; GFX9-NEXT:    v_alignbit_b32 v1, v1, v3, v22565; GFX9-NEXT:    s_setpc_b64 s[30:31]2566;2567; R600-LABEL: v_fshr_v2i24:2568; R600:       ; %bb.0:2569; R600-NEXT:    CF_END2570; R600-NEXT:    PAD2571;2572; GFX10-LABEL: v_fshr_v2i24:2573; GFX10:       ; %bb.0:2574; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2575; GFX10-NEXT:    v_and_b32_e32 v4, 0xffffff, v42576; GFX10-NEXT:    v_and_b32_e32 v5, 0xffffff, v52577; GFX10-NEXT:    v_lshlrev_b32_e32 v2, 8, v22578; GFX10-NEXT:    v_lshlrev_b32_e32 v3, 8, v32579; GFX10-NEXT:    v_mul_hi_u32 v6, 0xaaaaaab, v42580; GFX10-NEXT:    v_mul_hi_u32 v7, 0xaaaaaab, v52581; GFX10-NEXT:    v_mul_u32_u24_e32 v6, 24, v62582; GFX10-NEXT:    v_mul_u32_u24_e32 v7, 24, v72583; GFX10-NEXT:    v_sub_nc_u32_e32 v4, v4, v62584; GFX10-NEXT:    v_sub_nc_u32_e32 v5, v5, v72585; GFX10-NEXT:    v_add_nc_u32_e32 v4, 8, v42586; GFX10-NEXT:    v_add_nc_u32_e32 v5, 8, v52587; GFX10-NEXT:    v_alignbit_b32 v0, v0, v2, v42588; GFX10-NEXT:    v_alignbit_b32 v1, v1, v3, v52589; GFX10-NEXT:    s_setpc_b64 s[30:31]2590;2591; GFX11-TRUE16-LABEL: v_fshr_v2i24:2592; GFX11-TRUE16:       ; %bb.0:2593; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2594; GFX11-TRUE16-NEXT:    v_and_b32_e32 v4, 0xffffff, v42595; GFX11-TRUE16-NEXT:    v_and_b32_e32 v5, 0xffffff, v52596; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v2, 8, v22597; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 8, v32598; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)2599; GFX11-TRUE16-NEXT:    v_mul_hi_u32 v6, 0xaaaaaab, v42600; GFX11-TRUE16-NEXT:    v_mul_hi_u32 v7, 0xaaaaaab, v52601; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)2602; GFX11-TRUE16-NEXT:    v_mul_u32_u24_e32 v6, 24, v62603; GFX11-TRUE16-NEXT:    v_mul_u32_u24_e32 v7, 24, v72604; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)2605; GFX11-TRUE16-NEXT:    v_sub_nc_u32_e32 v4, v4, v62606; GFX11-TRUE16-NEXT:    v_sub_nc_u32_e32 v5, v5, v72607; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)2608; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v4, 8, v42609; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v5, 8, v52610; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)2611; GFX11-TRUE16-NEXT:    v_alignbit_b32 v0, v0, v2, v4.l2612; GFX11-TRUE16-NEXT:    v_alignbit_b32 v1, v1, v3, v5.l2613; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]2614;2615; GFX11-FAKE16-LABEL: v_fshr_v2i24:2616; GFX11-FAKE16:       ; %bb.0:2617; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2618; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffffff, v42619; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xffffff, v52620; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v2, 8, v22621; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 8, v32622; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)2623; GFX11-FAKE16-NEXT:    v_mul_hi_u32 v6, 0xaaaaaab, v42624; GFX11-FAKE16-NEXT:    v_mul_hi_u32 v7, 0xaaaaaab, v52625; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)2626; GFX11-FAKE16-NEXT:    v_mul_u32_u24_e32 v6, 24, v62627; GFX11-FAKE16-NEXT:    v_mul_u32_u24_e32 v7, 24, v72628; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)2629; GFX11-FAKE16-NEXT:    v_sub_nc_u32_e32 v4, v4, v62630; GFX11-FAKE16-NEXT:    v_sub_nc_u32_e32 v5, v5, v72631; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)2632; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v4, 8, v42633; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v5, 8, v52634; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)2635; GFX11-FAKE16-NEXT:    v_alignbit_b32 v0, v0, v2, v42636; GFX11-FAKE16-NEXT:    v_alignbit_b32 v1, v1, v3, v52637; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]2638;2639; GFX12-TRUE16-LABEL: v_fshr_v2i24:2640; GFX12-TRUE16:       ; %bb.0:2641; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x02642; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x02643; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x02644; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x02645; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x02646; GFX12-TRUE16-NEXT:    v_and_b32_e32 v4, 0xffffff, v42647; GFX12-TRUE16-NEXT:    v_and_b32_e32 v5, 0xffffff, v52648; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v2, 8, v22649; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 8, v32650; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)2651; GFX12-TRUE16-NEXT:    v_mul_hi_u32 v6, 0xaaaaaab, v42652; GFX12-TRUE16-NEXT:    v_mul_hi_u32 v7, 0xaaaaaab, v52653; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)2654; GFX12-TRUE16-NEXT:    v_mul_u32_u24_e32 v6, 24, v62655; GFX12-TRUE16-NEXT:    v_mul_u32_u24_e32 v7, 24, v72656; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)2657; GFX12-TRUE16-NEXT:    v_sub_nc_u32_e32 v4, v4, v62658; GFX12-TRUE16-NEXT:    v_sub_nc_u32_e32 v5, v5, v72659; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)2660; GFX12-TRUE16-NEXT:    v_add_nc_u32_e32 v4, 8, v42661; GFX12-TRUE16-NEXT:    v_add_nc_u32_e32 v5, 8, v52662; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)2663; GFX12-TRUE16-NEXT:    v_alignbit_b32 v0, v0, v2, v4.l2664; GFX12-TRUE16-NEXT:    v_alignbit_b32 v1, v1, v3, v5.l2665; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]2666;2667; GFX12-FAKE16-LABEL: v_fshr_v2i24:2668; GFX12-FAKE16:       ; %bb.0:2669; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x02670; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x02671; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x02672; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x02673; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x02674; GFX12-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffffff, v42675; GFX12-FAKE16-NEXT:    v_and_b32_e32 v5, 0xffffff, v52676; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v2, 8, v22677; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 8, v32678; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)2679; GFX12-FAKE16-NEXT:    v_mul_hi_u32 v6, 0xaaaaaab, v42680; GFX12-FAKE16-NEXT:    v_mul_hi_u32 v7, 0xaaaaaab, v52681; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)2682; GFX12-FAKE16-NEXT:    v_mul_u32_u24_e32 v6, 24, v62683; GFX12-FAKE16-NEXT:    v_mul_u32_u24_e32 v7, 24, v72684; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)2685; GFX12-FAKE16-NEXT:    v_sub_nc_u32_e32 v4, v4, v62686; GFX12-FAKE16-NEXT:    v_sub_nc_u32_e32 v5, v5, v72687; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)2688; GFX12-FAKE16-NEXT:    v_add_nc_u32_e32 v4, 8, v42689; GFX12-FAKE16-NEXT:    v_add_nc_u32_e32 v5, 8, v52690; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)2691; GFX12-FAKE16-NEXT:    v_alignbit_b32 v0, v0, v2, v42692; GFX12-FAKE16-NEXT:    v_alignbit_b32 v1, v1, v3, v52693; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]2694  %ret = call <2 x i24> @llvm.fshr.v2i24(<2 x i24> %src0, <2 x i24> %src1, <2 x i24> %src2)2695  ret <2 x i24> %ret2696}2697