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1; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s2; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s3; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s4 5; FUNC-LABEL: {{^}}v_fsub_f32:6; SI: v_sub_f32_e32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}7define amdgpu_kernel void @v_fsub_f32(ptr addrspace(1) %out, ptr addrspace(1) %in) {8 %b_ptr = getelementptr float, ptr addrspace(1) %in, i32 19 %a = load float, ptr addrspace(1) %in, align 410 %b = load float, ptr addrspace(1) %b_ptr, align 411 %result = fsub float %a, %b12 store float %result, ptr addrspace(1) %out, align 413 ret void14}15 16; FUNC-LABEL: {{^}}s_fsub_f32:17; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, -KC0[2].W18 19; SI: v_sub_f32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}20define amdgpu_kernel void @s_fsub_f32(ptr addrspace(1) %out, float %a, float %b) {21 %sub = fsub float %a, %b22 store float %sub, ptr addrspace(1) %out, align 423 ret void24}25 26; FUNC-LABEL: {{^}}fsub_v2f32:27; R600-DAG: ADD {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[3].X, -KC0[3].Z28; R600-DAG: ADD {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].W, -KC0[3].Y29 30; SI: v_sub_f32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}31; SI: v_sub_f32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}32define amdgpu_kernel void @fsub_v2f32(ptr addrspace(1) %out, <2 x float> %a, <2 x float> %b) {33 %sub = fsub <2 x float> %a, %b34 store <2 x float> %sub, ptr addrspace(1) %out, align 835 ret void36}37 38; FUNC-LABEL: {{^}}v_fsub_v4f32:39; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}}40; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}}41; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}}42; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}}43 44; SI: v_sub_f32_e32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}45; SI: v_sub_f32_e32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}46; SI: v_sub_f32_e32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}47; SI: v_sub_f32_e32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}48define amdgpu_kernel void @v_fsub_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %in) {49 %b_ptr = getelementptr <4 x float>, ptr addrspace(1) %in, i32 150 %a = load <4 x float>, ptr addrspace(1) %in, align 1651 %b = load <4 x float>, ptr addrspace(1) %b_ptr, align 1652 %result = fsub <4 x float> %a, %b53 store <4 x float> %result, ptr addrspace(1) %out, align 1654 ret void55}56 57; FUNC-LABEL: {{^}}s_fsub_v4f32:58; SI: v_sub_f32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}59; SI: v_sub_f32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}60; SI: v_sub_f32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}61; SI: v_sub_f32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}62; SI: s_endpgm63define amdgpu_kernel void @s_fsub_v4f32(ptr addrspace(1) %out, <4 x float> %a, <4 x float> %b) {64 %result = fsub <4 x float> %a, %b65 store <4 x float> %result, ptr addrspace(1) %out, align 1666 ret void67}68 69; FUNC-LABEL: {{^}}v_fneg_fsub_f32:70; SI: v_sub_f32_e32 [[SUB:v[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}71; SI: v_xor_b32_e32 v{{[0-9]+}}, 0x80000000, [[SUB]]72define amdgpu_kernel void @v_fneg_fsub_f32(ptr addrspace(1) %out, ptr addrspace(1) %in) {73 %b_ptr = getelementptr float, ptr addrspace(1) %in, i32 174 %a = load float, ptr addrspace(1) %in, align 475 %b = load float, ptr addrspace(1) %b_ptr, align 476 %result = fsub float %a, %b77 %neg.result = fsub float -0.0, %result78 store float %neg.result, ptr addrspace(1) %out, align 479 ret void80}81 82; FUNC-LABEL: {{^}}v_fneg_fsub_nsz_f32:83; SI: v_sub_f32_e32 [[SUB:v[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}84; SI-NOT: xor85define amdgpu_kernel void @v_fneg_fsub_nsz_f32(ptr addrspace(1) %out, ptr addrspace(1) %in) {86 %b_ptr = getelementptr float, ptr addrspace(1) %in, i32 187 %a = load float, ptr addrspace(1) %in, align 488 %b = load float, ptr addrspace(1) %b_ptr, align 489 %result = fsub nsz float %a, %b90 %neg.result = fsub float -0.0, %result91 store float %neg.result, ptr addrspace(1) %out, align 492 ret void93}94 95; FUNC-LABEL: {{^}}v_fsub_0_nsz_flag_f32:96; SI-NOT: v_sub97define amdgpu_kernel void @v_fsub_0_nsz_flag_f32(ptr addrspace(1) %out, ptr addrspace(1) %in) {98 %a = load float, ptr addrspace(1) %in, align 499 %result = fsub nsz float %a, 0.0100 store float %result, ptr addrspace(1) %out, align 4101 ret void102}103