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1; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefix=SI %s2; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=SI %s3 4declare double @llvm.fabs.f64(double) #05 6; SI-LABEL: {{^}}fsub_f64:7; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], -v\[[0-9]+:[0-9]+\]}}8define amdgpu_kernel void @fsub_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1,9 ptr addrspace(1) %in2) {10 %r0 = load double, ptr addrspace(1) %in111 %r1 = load double, ptr addrspace(1) %in212 %r2 = fsub double %r0, %r113 store double %r2, ptr addrspace(1) %out14 ret void15}16 17; SI-LABEL: {{^}}fsub_fabs_f64:18; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], -\|v\[[0-9]+:[0-9]+\]\|}}19define amdgpu_kernel void @fsub_fabs_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1,20 ptr addrspace(1) %in2) {21 %r0 = load double, ptr addrspace(1) %in122 %r1 = load double, ptr addrspace(1) %in223 %r1.fabs = call double @llvm.fabs.f64(double %r1) #024 %r2 = fsub double %r0, %r1.fabs25 store double %r2, ptr addrspace(1) %out26 ret void27}28 29; SI-LABEL: {{^}}fsub_fabs_inv_f64:30; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], |v\[[0-9]+:[0-9]+\]|, -v\[[0-9]+:[0-9]+\]}}31define amdgpu_kernel void @fsub_fabs_inv_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1,32 ptr addrspace(1) %in2) {33 %r0 = load double, ptr addrspace(1) %in134 %r1 = load double, ptr addrspace(1) %in235 %r0.fabs = call double @llvm.fabs.f64(double %r0) #036 %r2 = fsub double %r0.fabs, %r137 store double %r2, ptr addrspace(1) %out38 ret void39}40 41; SI-LABEL: {{^}}s_fsub_f64:42; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], s\[[0-9]+:[0-9]+\], -v\[[0-9]+:[0-9]+\]}}43define amdgpu_kernel void @s_fsub_f64(ptr addrspace(1) %out, double %a, double %b) {44 %sub = fsub double %a, %b45 store double %sub, ptr addrspace(1) %out46 ret void47}48 49; SI-LABEL: {{^}}s_fsub_imm_f64:50; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], -s\[[0-9]+:[0-9]+\]}}, 4.051define amdgpu_kernel void @s_fsub_imm_f64(ptr addrspace(1) %out, double %a, double %b) {52 %sub = fsub double 4.0, %a53 store double %sub, ptr addrspace(1) %out54 ret void55}56 57; SI-LABEL: {{^}}s_fsub_imm_inv_f64:58; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], s\[[0-9]+:[0-9]+\]}}, -4.059define amdgpu_kernel void @s_fsub_imm_inv_f64(ptr addrspace(1) %out, double %a, double %b) {60 %sub = fsub double %a, 4.061 store double %sub, ptr addrspace(1) %out62 ret void63}64 65; SI-LABEL: {{^}}s_fsub_self_f64:66; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], s\[[0-9]+:[0-9]+\], -s\[[0-9]+:[0-9]+\]}}67define amdgpu_kernel void @s_fsub_self_f64(ptr addrspace(1) %out, double %a) {68 %sub = fsub double %a, %a69 store double %sub, ptr addrspace(1) %out70 ret void71}72 73; SI-LABEL: {{^}}fsub_v2f64:74; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], s\[[0-9]+:[0-9]+\], -v\[[0-9]+:[0-9]+\]}}75; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], s\[[0-9]+:[0-9]+\], -v\[[0-9]+:[0-9]+\]}}76define amdgpu_kernel void @fsub_v2f64(ptr addrspace(1) %out, <2 x double> %a, <2 x double> %b) {77 %sub = fsub <2 x double> %a, %b78 store <2 x double> %sub, ptr addrspace(1) %out79 ret void80}81 82; SI-LABEL: {{^}}fsub_v4f64:83; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], -v\[[0-9]+:[0-9]+\]}}84; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], -v\[[0-9]+:[0-9]+\]}}85; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], -v\[[0-9]+:[0-9]+\]}}86; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], -v\[[0-9]+:[0-9]+\]}}87define amdgpu_kernel void @fsub_v4f64(ptr addrspace(1) %out, ptr addrspace(1) %in) {88 %b_ptr = getelementptr <4 x double>, ptr addrspace(1) %in, i32 189 %a = load <4 x double>, ptr addrspace(1) %in90 %b = load <4 x double>, ptr addrspace(1) %b_ptr91 %result = fsub <4 x double> %a, %b92 store <4 x double> %result, ptr addrspace(1) %out93 ret void94}95 96; SI-LABEL: {{^}}s_fsub_v4f64:97; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], s\[[0-9]+:[0-9]+\], -v\[[0-9]+:[0-9]+\]}}98; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], s\[[0-9]+:[0-9]+\], -v\[[0-9]+:[0-9]+\]}}99; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], s\[[0-9]+:[0-9]+\], -v\[[0-9]+:[0-9]+\]}}100; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], s\[[0-9]+:[0-9]+\], -v\[[0-9]+:[0-9]+\]}}101define amdgpu_kernel void @s_fsub_v4f64(ptr addrspace(1) %out, <4 x double> %a, <4 x double> %b) {102 %result = fsub <4 x double> %a, %b103 store <4 x double> %result, ptr addrspace(1) %out, align 16104 ret void105}106 107attributes #0 = { nounwind readnone }108