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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn -mcpu=gfx908 < %s | FileCheck --check-prefix=GCN %s3 4define amdgpu_kernel void @divergent_or3_b32(ptr addrspace(1) %arg) {5; GCN-LABEL: divergent_or3_b32:6; GCN: ; %bb.0: ; %bb7; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x248; GCN-NEXT: v_lshlrev_b32_e32 v3, 4, v09; GCN-NEXT: s_waitcnt lgkmcnt(0)10; GCN-NEXT: global_load_dwordx3 v[0:2], v3, s[0:1]11; GCN-NEXT: s_waitcnt vmcnt(0)12; GCN-NEXT: v_or3_b32 v0, v1, v0, v213; GCN-NEXT: v_not_b32_e32 v0, v014; GCN-NEXT: global_store_dword v3, v0, s[0:1]15; GCN-NEXT: s_endpgm16bb:17 %i = tail call i32 @llvm.amdgcn.workitem.id.x()18 %i1 = zext i32 %i to i6419 %i2 = getelementptr inbounds <3 x i32>, ptr addrspace(1) %arg, i64 %i120 %i3 = load <3 x i32>, ptr addrspace(1) %i2, align 1621 %i4 = extractelement <3 x i32> %i3, i64 022 %i5 = extractelement <3 x i32> %i3, i64 123 %i6 = extractelement <3 x i32> %i3, i64 224 %i7 = or i32 %i5, %i425 %i8 = or i32 %i7, %i626 %i9 = xor i32 %i8, -127 store i32 %i9, ptr addrspace(1) %i2, align 1628 ret void29}30 31define amdgpu_kernel void @divergent_or3_b64(ptr addrspace(1) %arg) {32; GCN-LABEL: divergent_or3_b64:33; GCN: ; %bb.0: ; %bb34; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2435; GCN-NEXT: v_lshlrev_b32_e32 v6, 5, v036; GCN-NEXT: s_waitcnt lgkmcnt(0)37; GCN-NEXT: global_load_dwordx2 v[4:5], v6, s[0:1] offset:1638; GCN-NEXT: global_load_dwordx4 v[0:3], v6, s[0:1]39; GCN-NEXT: s_waitcnt vmcnt(0)40; GCN-NEXT: v_or3_b32 v1, v3, v1, v541; GCN-NEXT: v_or3_b32 v0, v2, v0, v442; GCN-NEXT: v_not_b32_e32 v1, v143; GCN-NEXT: v_not_b32_e32 v0, v044; GCN-NEXT: global_store_dwordx2 v6, v[0:1], s[0:1]45; GCN-NEXT: s_endpgm46bb:47 %i = tail call i32 @llvm.amdgcn.workitem.id.x()48 %i1 = zext i32 %i to i6449 %i2 = getelementptr inbounds <3 x i64>, ptr addrspace(1) %arg, i64 %i150 %i3 = load <3 x i64>, ptr addrspace(1) %i2, align 3251 %i4 = extractelement <3 x i64> %i3, i64 052 %i5 = extractelement <3 x i64> %i3, i64 153 %i6 = extractelement <3 x i64> %i3, i64 254 %i7 = or i64 %i5, %i455 %i8 = or i64 %i7, %i656 %i9 = xor i64 %i8, -157 store i64 %i9, ptr addrspace(1) %i2, align 3258 ret void59}60 61define amdgpu_kernel void @divergent_and3_b32(ptr addrspace(1) %arg) {62; GCN-LABEL: divergent_and3_b32:63; GCN: ; %bb.0: ; %bb64; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2465; GCN-NEXT: v_lshlrev_b32_e32 v3, 4, v066; GCN-NEXT: s_waitcnt lgkmcnt(0)67; GCN-NEXT: global_load_dwordx3 v[0:2], v3, s[0:1]68; GCN-NEXT: s_waitcnt vmcnt(0)69; GCN-NEXT: v_and_b32_e32 v0, v1, v070; GCN-NEXT: v_and_b32_e32 v0, v0, v271; GCN-NEXT: v_not_b32_e32 v0, v072; GCN-NEXT: global_store_dword v3, v0, s[0:1]73; GCN-NEXT: s_endpgm74bb:75 %i = tail call i32 @llvm.amdgcn.workitem.id.x()76 %i1 = zext i32 %i to i6477 %i2 = getelementptr inbounds <3 x i32>, ptr addrspace(1) %arg, i64 %i178 %i3 = load <3 x i32>, ptr addrspace(1) %i2, align 1679 %i4 = extractelement <3 x i32> %i3, i64 080 %i5 = extractelement <3 x i32> %i3, i64 181 %i6 = extractelement <3 x i32> %i3, i64 282 %i7 = and i32 %i5, %i483 %i8 = and i32 %i7, %i684 %i9 = xor i32 %i8, -185 store i32 %i9, ptr addrspace(1) %i2, align 1686 ret void87}88 89define amdgpu_kernel void @divergent_and3_b64(ptr addrspace(1) %arg) {90; GCN-LABEL: divergent_and3_b64:91; GCN: ; %bb.0: ; %bb92; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2493; GCN-NEXT: v_lshlrev_b32_e32 v6, 5, v094; GCN-NEXT: s_waitcnt lgkmcnt(0)95; GCN-NEXT: global_load_dwordx4 v[0:3], v6, s[0:1]96; GCN-NEXT: global_load_dwordx2 v[4:5], v6, s[0:1] offset:1697; GCN-NEXT: s_waitcnt vmcnt(1)98; GCN-NEXT: v_and_b32_e32 v1, v3, v199; GCN-NEXT: v_and_b32_e32 v0, v2, v0100; GCN-NEXT: s_waitcnt vmcnt(0)101; GCN-NEXT: v_and_b32_e32 v1, v1, v5102; GCN-NEXT: v_and_b32_e32 v0, v0, v4103; GCN-NEXT: v_not_b32_e32 v1, v1104; GCN-NEXT: v_not_b32_e32 v0, v0105; GCN-NEXT: global_store_dwordx2 v6, v[0:1], s[0:1]106; GCN-NEXT: s_endpgm107bb:108 %i = tail call i32 @llvm.amdgcn.workitem.id.x()109 %i1 = zext i32 %i to i64110 %i2 = getelementptr inbounds <3 x i64>, ptr addrspace(1) %arg, i64 %i1111 %i3 = load <3 x i64>, ptr addrspace(1) %i2, align 32112 %i4 = extractelement <3 x i64> %i3, i64 0113 %i5 = extractelement <3 x i64> %i3, i64 1114 %i6 = extractelement <3 x i64> %i3, i64 2115 %i7 = and i64 %i5, %i4116 %i8 = and i64 %i7, %i6117 %i9 = xor i64 %i8, -1118 store i64 %i9, ptr addrspace(1) %i2, align 32119 ret void120}121 122define amdgpu_kernel void @divergent_xor3_b32(ptr addrspace(1) %arg) {123; GCN-LABEL: divergent_xor3_b32:124; GCN: ; %bb.0: ; %bb125; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24126; GCN-NEXT: v_lshlrev_b32_e32 v3, 4, v0127; GCN-NEXT: s_waitcnt lgkmcnt(0)128; GCN-NEXT: global_load_dwordx3 v[0:2], v3, s[0:1]129; GCN-NEXT: s_waitcnt vmcnt(0)130; GCN-NEXT: v_xor_b32_e32 v0, v1, v0131; GCN-NEXT: v_xnor_b32_e32 v0, v0, v2132; GCN-NEXT: global_store_dword v3, v0, s[0:1]133; GCN-NEXT: s_endpgm134bb:135 %i = tail call i32 @llvm.amdgcn.workitem.id.x()136 %i1 = zext i32 %i to i64137 %i2 = getelementptr inbounds <3 x i32>, ptr addrspace(1) %arg, i64 %i1138 %i3 = load <3 x i32>, ptr addrspace(1) %i2, align 16139 %i4 = extractelement <3 x i32> %i3, i64 0140 %i5 = extractelement <3 x i32> %i3, i64 1141 %i6 = extractelement <3 x i32> %i3, i64 2142 %i7 = xor i32 %i5, %i4143 %i8 = xor i32 %i7, %i6144 %i9 = xor i32 %i8, -1145 store i32 %i9, ptr addrspace(1) %i2, align 16146 ret void147}148 149define amdgpu_kernel void @divergent_xor3_b64(ptr addrspace(1) %arg) {150; GCN-LABEL: divergent_xor3_b64:151; GCN: ; %bb.0: ; %bb152; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24153; GCN-NEXT: v_lshlrev_b32_e32 v6, 5, v0154; GCN-NEXT: s_waitcnt lgkmcnt(0)155; GCN-NEXT: global_load_dwordx4 v[0:3], v6, s[0:1]156; GCN-NEXT: global_load_dwordx2 v[4:5], v6, s[0:1] offset:16157; GCN-NEXT: s_waitcnt vmcnt(1)158; GCN-NEXT: v_xor_b32_e32 v1, v3, v1159; GCN-NEXT: v_xor_b32_e32 v0, v2, v0160; GCN-NEXT: s_waitcnt vmcnt(0)161; GCN-NEXT: v_xnor_b32_e32 v1, v1, v5162; GCN-NEXT: v_xnor_b32_e32 v0, v0, v4163; GCN-NEXT: global_store_dwordx2 v6, v[0:1], s[0:1]164; GCN-NEXT: s_endpgm165bb:166 %i = tail call i32 @llvm.amdgcn.workitem.id.x()167 %i1 = zext i32 %i to i64168 %i2 = getelementptr inbounds <3 x i64>, ptr addrspace(1) %arg, i64 %i1169 %i3 = load <3 x i64>, ptr addrspace(1) %i2, align 32170 %i4 = extractelement <3 x i64> %i3, i64 0171 %i5 = extractelement <3 x i64> %i3, i64 1172 %i6 = extractelement <3 x i64> %i3, i64 2173 %i7 = xor i64 %i5, %i4174 %i8 = xor i64 %i7, %i6175 %i9 = xor i64 %i8, -1176 store i64 %i9, ptr addrspace(1) %i2, align 32177 ret void178}179 180define amdgpu_kernel void @uniform_or3_b32(ptr addrspace(1) %arg) {181; GCN-LABEL: uniform_or3_b32:182; GCN: ; %bb.0: ; %bb183; GCN-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24184; GCN-NEXT: v_mov_b32_e32 v0, 0185; GCN-NEXT: s_waitcnt lgkmcnt(0)186; GCN-NEXT: s_load_dwordx4 s[0:3], s[6:7], 0x0187; GCN-NEXT: s_waitcnt lgkmcnt(0)188; GCN-NEXT: s_or_b32 s0, s1, s0189; GCN-NEXT: s_nor_b32 s0, s0, s2190; GCN-NEXT: v_mov_b32_e32 v1, s0191; GCN-NEXT: global_store_dword v0, v1, s[6:7]192; GCN-NEXT: s_endpgm193bb:194 %i3 = load <3 x i32>, ptr addrspace(1) %arg, align 16195 %i4 = extractelement <3 x i32> %i3, i64 0196 %i5 = extractelement <3 x i32> %i3, i64 1197 %i6 = extractelement <3 x i32> %i3, i64 2198 %i7 = or i32 %i5, %i4199 %i8 = or i32 %i7, %i6200 %i9 = xor i32 %i8, -1201 store i32 %i9, ptr addrspace(1) %arg, align 16202 ret void203}204 205define amdgpu_kernel void @uniform_or3_b64(ptr addrspace(1) %arg) {206; GCN-LABEL: uniform_or3_b64:207; GCN: ; %bb.0: ; %bb208; GCN-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24209; GCN-NEXT: v_mov_b32_e32 v2, 0210; GCN-NEXT: s_waitcnt lgkmcnt(0)211; GCN-NEXT: s_load_dwordx4 s[0:3], s[6:7], 0x0212; GCN-NEXT: s_load_dwordx2 s[4:5], s[6:7], 0x10213; GCN-NEXT: s_waitcnt lgkmcnt(0)214; GCN-NEXT: s_or_b64 s[0:1], s[2:3], s[0:1]215; GCN-NEXT: s_nor_b64 s[0:1], s[0:1], s[4:5]216; GCN-NEXT: v_mov_b32_e32 v0, s0217; GCN-NEXT: v_mov_b32_e32 v1, s1218; GCN-NEXT: global_store_dwordx2 v2, v[0:1], s[6:7]219; GCN-NEXT: s_endpgm220bb:221 %i3 = load <3 x i64>, ptr addrspace(1) %arg, align 32222 %i4 = extractelement <3 x i64> %i3, i64 0223 %i5 = extractelement <3 x i64> %i3, i64 1224 %i6 = extractelement <3 x i64> %i3, i64 2225 %i7 = or i64 %i5, %i4226 %i8 = or i64 %i7, %i6227 %i9 = xor i64 %i8, -1228 store i64 %i9, ptr addrspace(1) %arg, align 32229 ret void230}231 232define amdgpu_kernel void @uniform_and3_b32(ptr addrspace(1) %arg) {233; GCN-LABEL: uniform_and3_b32:234; GCN: ; %bb.0: ; %bb235; GCN-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24236; GCN-NEXT: v_mov_b32_e32 v0, 0237; GCN-NEXT: s_waitcnt lgkmcnt(0)238; GCN-NEXT: s_load_dwordx4 s[0:3], s[6:7], 0x0239; GCN-NEXT: s_waitcnt lgkmcnt(0)240; GCN-NEXT: s_and_b32 s0, s1, s0241; GCN-NEXT: s_nand_b32 s0, s0, s2242; GCN-NEXT: v_mov_b32_e32 v1, s0243; GCN-NEXT: global_store_dword v0, v1, s[6:7]244; GCN-NEXT: s_endpgm245bb:246 %i3 = load <3 x i32>, ptr addrspace(1) %arg, align 16247 %i4 = extractelement <3 x i32> %i3, i64 0248 %i5 = extractelement <3 x i32> %i3, i64 1249 %i6 = extractelement <3 x i32> %i3, i64 2250 %i7 = and i32 %i5, %i4251 %i8 = and i32 %i7, %i6252 %i9 = xor i32 %i8, -1253 store i32 %i9, ptr addrspace(1) %arg, align 16254 ret void255}256 257define amdgpu_kernel void @uniform_and3_b64(ptr addrspace(1) %arg) {258; GCN-LABEL: uniform_and3_b64:259; GCN: ; %bb.0: ; %bb260; GCN-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24261; GCN-NEXT: v_mov_b32_e32 v2, 0262; GCN-NEXT: s_waitcnt lgkmcnt(0)263; GCN-NEXT: s_load_dwordx4 s[0:3], s[6:7], 0x0264; GCN-NEXT: s_load_dwordx2 s[4:5], s[6:7], 0x10265; GCN-NEXT: s_waitcnt lgkmcnt(0)266; GCN-NEXT: s_and_b64 s[0:1], s[2:3], s[0:1]267; GCN-NEXT: s_nand_b64 s[0:1], s[0:1], s[4:5]268; GCN-NEXT: v_mov_b32_e32 v0, s0269; GCN-NEXT: v_mov_b32_e32 v1, s1270; GCN-NEXT: global_store_dwordx2 v2, v[0:1], s[6:7]271; GCN-NEXT: s_endpgm272bb:273 %i3 = load <3 x i64>, ptr addrspace(1) %arg, align 32274 %i4 = extractelement <3 x i64> %i3, i64 0275 %i5 = extractelement <3 x i64> %i3, i64 1276 %i6 = extractelement <3 x i64> %i3, i64 2277 %i7 = and i64 %i5, %i4278 %i8 = and i64 %i7, %i6279 %i9 = xor i64 %i8, -1280 store i64 %i9, ptr addrspace(1) %arg, align 32281 ret void282}283 284define amdgpu_kernel void @uniform_xor3_b32(ptr addrspace(1) %arg) {285; GCN-LABEL: uniform_xor3_b32:286; GCN: ; %bb.0: ; %bb287; GCN-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24288; GCN-NEXT: v_mov_b32_e32 v0, 0289; GCN-NEXT: s_waitcnt lgkmcnt(0)290; GCN-NEXT: s_load_dwordx4 s[0:3], s[6:7], 0x0291; GCN-NEXT: s_waitcnt lgkmcnt(0)292; GCN-NEXT: s_xor_b32 s0, s1, s0293; GCN-NEXT: s_xnor_b32 s0, s0, s2294; GCN-NEXT: v_mov_b32_e32 v1, s0295; GCN-NEXT: global_store_dword v0, v1, s[6:7]296; GCN-NEXT: s_endpgm297bb:298 %i3 = load <3 x i32>, ptr addrspace(1) %arg, align 16299 %i4 = extractelement <3 x i32> %i3, i64 0300 %i5 = extractelement <3 x i32> %i3, i64 1301 %i6 = extractelement <3 x i32> %i3, i64 2302 %i7 = xor i32 %i5, %i4303 %i8 = xor i32 %i7, %i6304 %i9 = xor i32 %i8, -1305 store i32 %i9, ptr addrspace(1) %arg, align 16306 ret void307}308 309define amdgpu_kernel void @uniform_xor3_b64(ptr addrspace(1) %arg) {310; GCN-LABEL: uniform_xor3_b64:311; GCN: ; %bb.0: ; %bb312; GCN-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24313; GCN-NEXT: v_mov_b32_e32 v2, 0314; GCN-NEXT: s_waitcnt lgkmcnt(0)315; GCN-NEXT: s_load_dwordx4 s[0:3], s[6:7], 0x0316; GCN-NEXT: s_load_dwordx2 s[4:5], s[6:7], 0x10317; GCN-NEXT: s_waitcnt lgkmcnt(0)318; GCN-NEXT: s_xor_b64 s[0:1], s[2:3], s[0:1]319; GCN-NEXT: s_xnor_b64 s[0:1], s[0:1], s[4:5]320; GCN-NEXT: v_mov_b32_e32 v0, s0321; GCN-NEXT: v_mov_b32_e32 v1, s1322; GCN-NEXT: global_store_dwordx2 v2, v[0:1], s[6:7]323; GCN-NEXT: s_endpgm324bb:325 %i3 = load <3 x i64>, ptr addrspace(1) %arg, align 32326 %i4 = extractelement <3 x i64> %i3, i64 0327 %i5 = extractelement <3 x i64> %i3, i64 1328 %i6 = extractelement <3 x i64> %i3, i64 2329 %i7 = xor i64 %i5, %i4330 %i8 = xor i64 %i7, %i6331 %i9 = xor i64 %i8, -1332 store i64 %i9, ptr addrspace(1) %arg, align 32333 ret void334}335 336declare i32 @llvm.amdgcn.workitem.id.x()337