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1; RUN: llc -mtriple=amdgcn < %s | FileCheck --check-prefix=SI --check-prefix=CHECK %s2; RUN: llc -mtriple=amdgcn -mcpu=bonaire < %s | FileCheck --check-prefix=CI --check-prefix=CHECK %s3; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck --check-prefix=CI --check-prefix=CHECK %s4 5define amdgpu_kernel void @use_gep_address_space(ptr addrspace(3) %array) nounwind {6; CHECK-LABEL: {{^}}use_gep_address_space:7; CHECK: v_mov_b32_e32 [[PTR:v[0-9]+]], s{{[0-9]+}}8; CHECK: ds_write_b32 [[PTR]], v{{[0-9]+}} offset:649 %p = getelementptr [1024 x i32], ptr addrspace(3) %array, i16 0, i16 1610 store i32 99, ptr addrspace(3) %p11 ret void12}13 14; CHECK-LABEL: {{^}}use_gep_address_space_large_offset:15; The LDS offset will be 65536 bytes, which is larger than the size of LDS on16; SI, which is why it is being OR'd with the base pointer.17; SI: s_bitset1_b3218; CI: s_add_i3219; CHECK: ds_write_b3220define amdgpu_kernel void @use_gep_address_space_large_offset(ptr addrspace(3) %array) nounwind {21 %p = getelementptr [1024 x i32], ptr addrspace(3) %array, i16 0, i16 1638422 store i32 99, ptr addrspace(3) %p23 ret void24}25 26; CHECK-LABEL: {{^}}gep_as_vector_v4:27; SI: s_add_i3228; SI: s_add_i3229; SI: s_add_i3230; SI: s_add_i3231 32; CHECK-DAG: v_mov_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}33; CHECK-DAG: v_mov_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}34; CHECK-DAG: v_mov_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}35; CHECK-DAG: v_mov_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}36 37; CI-DAG: ds_write_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:6438; CI-DAG: ds_write_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:6439; CI-DAG: ds_write_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:6440; CI-DAG: ds_write_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:6441; CHECK: s_endpgm42define amdgpu_kernel void @gep_as_vector_v4(<4 x ptr addrspace(3)> %array) nounwind {43 %p = getelementptr [1024 x i32], <4 x ptr addrspace(3)> %array, <4 x i16> zeroinitializer, <4 x i16> <i16 16, i16 16, i16 16, i16 16>44 %p0 = extractelement <4 x ptr addrspace(3)> %p, i32 045 %p1 = extractelement <4 x ptr addrspace(3)> %p, i32 146 %p2 = extractelement <4 x ptr addrspace(3)> %p, i32 247 %p3 = extractelement <4 x ptr addrspace(3)> %p, i32 348 store i32 99, ptr addrspace(3) %p049 store i32 99, ptr addrspace(3) %p150 store i32 99, ptr addrspace(3) %p251 store i32 99, ptr addrspace(3) %p352 ret void53}54 55; CHECK-LABEL: {{^}}gep_as_vector_v2:56; SI: s_add_i3257; SI: s_add_i3258; CHECK-DAG: v_mov_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}59; CHECK-DAG: v_mov_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}60; CI-DAG: ds_write_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:6461; CI-DAG: ds_write_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:6462; CHECK: s_endpgm63define amdgpu_kernel void @gep_as_vector_v2(<2 x ptr addrspace(3)> %array) nounwind {64 %p = getelementptr [1024 x i32], <2 x ptr addrspace(3)> %array, <2 x i16> zeroinitializer, <2 x i16> <i16 16, i16 16>65 %p0 = extractelement <2 x ptr addrspace(3)> %p, i32 066 %p1 = extractelement <2 x ptr addrspace(3)> %p, i32 167 store i32 99, ptr addrspace(3) %p068 store i32 99, ptr addrspace(3) %p169 ret void70}71 72