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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GCN,DAG %s3; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -global-isel=1 < %s | FileCheck -check-prefixes=GCN,GISEL %s4 5define amdgpu_ps void @test_s_load_i8(ptr addrspace(4) inreg %in, ptr addrspace(1) %out) {6; GCN-LABEL: test_s_load_i8:7; GCN: ; %bb.0:8; GCN-NEXT: s_load_i8 s0, s[0:1], 0x09; GCN-NEXT: s_wait_kmcnt 0x010; GCN-NEXT: v_mov_b32_e32 v2, s011; GCN-NEXT: global_store_b32 v[0:1], v2, off12; GCN-NEXT: s_endpgm13 %ld = load i8, ptr addrspace(4) %in14 %sext = sext i8 %ld to i3215 store i32 %sext, ptr addrspace(1) %out16 ret void17}18 19define amdgpu_ps void @test_s_load_i8_imm(ptr addrspace(4) inreg %in, ptr addrspace(1) %out) {20; DAG-LABEL: test_s_load_i8_imm:21; DAG: ; %bb.0:22; DAG-NEXT: s_movk_i32 s2, 0xff9c23; DAG-NEXT: s_mov_b32 s3, -124; DAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)25; DAG-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[2:3]26; DAG-NEXT: s_load_i8 s0, s[0:1], 0x027; DAG-NEXT: s_wait_kmcnt 0x028; DAG-NEXT: v_mov_b32_e32 v2, s029; DAG-NEXT: global_store_b32 v[0:1], v2, off30; DAG-NEXT: s_endpgm31;32; GISEL-LABEL: test_s_load_i8_imm:33; GISEL: ; %bb.0:34; GISEL-NEXT: s_add_co_u32 s0, s0, 0xffffff9c35; GISEL-NEXT: s_add_co_ci_u32 s1, s1, -136; GISEL-NEXT: s_load_i8 s0, s[0:1], 0x037; GISEL-NEXT: s_wait_kmcnt 0x038; GISEL-NEXT: v_mov_b32_e32 v2, s039; GISEL-NEXT: global_store_b32 v[0:1], v2, off40; GISEL-NEXT: s_endpgm41 %gep = getelementptr i8, ptr addrspace(4) %in, i64 -10042 %ld = load i8, ptr addrspace(4) %gep43 %sext = sext i8 %ld to i3244 store i32 %sext, ptr addrspace(1) %out45 ret void46}47 48define amdgpu_ps void @test_s_load_i8_sgpr(ptr addrspace(4) inreg %in, i32 inreg %offset, ptr addrspace(1) %out) {49; GCN-LABEL: test_s_load_i8_sgpr:50; GCN: ; %bb.0:51; GCN-NEXT: s_load_i8 s0, s[0:1], s2 offset:0x052; GCN-NEXT: s_wait_kmcnt 0x053; GCN-NEXT: v_mov_b32_e32 v2, s054; GCN-NEXT: global_store_b32 v[0:1], v2, off55; GCN-NEXT: s_endpgm56 %zext = zext i32 %offset to i6457 %gep = getelementptr i8, ptr addrspace(4) %in, i64 %zext58 %ld = load i8, ptr addrspace(4) %gep59 %sext = sext i8 %ld to i3260 store i32 %sext, ptr addrspace(1) %out61 ret void62}63 64define amdgpu_ps void @test_s_load_i8_sgpr_imm(ptr addrspace(4) inreg %in, i32 inreg %offset, ptr addrspace(1) %out) {65; GCN-LABEL: test_s_load_i8_sgpr_imm:66; GCN: ; %bb.0:67; GCN-NEXT: s_load_i8 s0, s[0:1], s2 offset:0x1068; GCN-NEXT: s_wait_kmcnt 0x069; GCN-NEXT: v_mov_b32_e32 v2, s070; GCN-NEXT: global_store_b32 v[0:1], v2, off71; GCN-NEXT: s_endpgm72 %gep1 = getelementptr i8, ptr addrspace(4) %in, i64 1673 %zext = zext i32 %offset to i6474 %gep2 = getelementptr i8, ptr addrspace(4) %gep1, i64 %zext75 %ld = load i8, ptr addrspace(4) %gep276 %sext = sext i8 %ld to i3277 store i32 %sext, ptr addrspace(1) %out78 ret void79}80 81define amdgpu_ps void @test_s_load_i8_divergent(ptr addrspace(4) inreg %in, i32 %offset, ptr addrspace(1) %out) {82; GCN-LABEL: test_s_load_i8_divergent:83; GCN: ; %bb.0:84; GCN-NEXT: global_load_i8 v0, v0, s[0:1] offset:1685; GCN-NEXT: s_wait_loadcnt 0x086; GCN-NEXT: global_store_b32 v[1:2], v0, off87; GCN-NEXT: s_endpgm88 %gep1 = getelementptr i8, ptr addrspace(4) %in, i64 1689 %zext = zext i32 %offset to i6490 %gep2 = getelementptr i8, ptr addrspace(4) %gep1, i64 %zext91 %ld = load i8, ptr addrspace(4) %gep292 %sext = sext i8 %ld to i3293 store i32 %sext, ptr addrspace(1) %out94 ret void95}96 97define amdgpu_ps void @test_s_load_u8(ptr addrspace(4) inreg %in, ptr addrspace(1) %out) {98; GCN-LABEL: test_s_load_u8:99; GCN: ; %bb.0:100; GCN-NEXT: s_load_u8 s0, s[0:1], 0x0101; GCN-NEXT: s_wait_kmcnt 0x0102; GCN-NEXT: v_mov_b32_e32 v2, s0103; GCN-NEXT: global_store_b32 v[0:1], v2, off104; GCN-NEXT: s_endpgm105 %ld = load i8, ptr addrspace(4) %in106 %zext = zext i8 %ld to i32107 store i32 %zext, ptr addrspace(1) %out108 ret void109}110 111define amdgpu_ps void @test_s_load_u8_imm(ptr addrspace(4) inreg %in, ptr addrspace(1) %out) {112; GCN-LABEL: test_s_load_u8_imm:113; GCN: ; %bb.0:114; GCN-NEXT: s_load_u8 s0, s[0:1], 0xff115; GCN-NEXT: s_wait_kmcnt 0x0116; GCN-NEXT: v_mov_b32_e32 v2, s0117; GCN-NEXT: global_store_b32 v[0:1], v2, off118; GCN-NEXT: s_endpgm119 %gep = getelementptr i8, ptr addrspace(4) %in, i64 255120 %ld = load i8, ptr addrspace(4) %gep121 %zext = zext i8 %ld to i32122 store i32 %zext, ptr addrspace(1) %out123 ret void124}125 126define amdgpu_ps void @test_s_load_u8_sgpr(ptr addrspace(4) inreg %in, i32 inreg %offset, ptr addrspace(1) %out) {127; GCN-LABEL: test_s_load_u8_sgpr:128; GCN: ; %bb.0:129; GCN-NEXT: s_load_u8 s0, s[0:1], s2 offset:0x0130; GCN-NEXT: s_wait_kmcnt 0x0131; GCN-NEXT: v_mov_b32_e32 v2, s0132; GCN-NEXT: global_store_b32 v[0:1], v2, off133; GCN-NEXT: s_endpgm134 %zext1 = zext i32 %offset to i64135 %gep = getelementptr i8, ptr addrspace(4) %in, i64 %zext1136 %ld = load i8, ptr addrspace(4) %gep137 %zext2 = zext i8 %ld to i32138 store i32 %zext2, ptr addrspace(1) %out139 ret void140}141 142define amdgpu_ps void @test_s_load_u8_sgpr_imm(ptr addrspace(4) inreg %in, i32 inreg %offset, ptr addrspace(1) %out) {143; GCN-LABEL: test_s_load_u8_sgpr_imm:144; GCN: ; %bb.0:145; GCN-NEXT: s_load_u8 s0, s[0:1], s2 offset:0x10146; GCN-NEXT: s_wait_kmcnt 0x0147; GCN-NEXT: v_mov_b32_e32 v2, s0148; GCN-NEXT: global_store_b32 v[0:1], v2, off149; GCN-NEXT: s_endpgm150 %gep1 = getelementptr i8, ptr addrspace(4) %in, i64 16151 %zext1= zext i32 %offset to i64152 %gep2 = getelementptr i8, ptr addrspace(4) %gep1, i64 %zext1153 %ld = load i8, ptr addrspace(4) %gep2154 %zext2= zext i8 %ld to i32155 store i32 %zext2, ptr addrspace(1) %out156 ret void157}158 159define amdgpu_ps void @test_s_load_u8_divergent(ptr addrspace(4) inreg %in, i32 %offset, ptr addrspace(1) %out) {160; GCN-LABEL: test_s_load_u8_divergent:161; GCN: ; %bb.0:162; GCN-NEXT: global_load_u8 v0, v0, s[0:1] offset:16163; GCN-NEXT: s_wait_loadcnt 0x0164; GCN-NEXT: global_store_b32 v[1:2], v0, off165; GCN-NEXT: s_endpgm166 %gep1 = getelementptr i8, ptr addrspace(4) %in, i64 16167 %zext1= zext i32 %offset to i64168 %gep2 = getelementptr i8, ptr addrspace(4) %gep1, i64 %zext1169 %ld = load i8, ptr addrspace(4) %gep2170 %zext2= zext i8 %ld to i32171 store i32 %zext2, ptr addrspace(1) %out172 ret void173}174 175define amdgpu_ps void @test_s_load_i16(ptr addrspace(4) inreg %in, ptr addrspace(1) %out) {176; GCN-LABEL: test_s_load_i16:177; GCN: ; %bb.0:178; GCN-NEXT: s_load_i16 s0, s[0:1], 0x0179; GCN-NEXT: s_wait_kmcnt 0x0180; GCN-NEXT: v_mov_b32_e32 v2, s0181; GCN-NEXT: global_store_b32 v[0:1], v2, off182; GCN-NEXT: s_endpgm183 %ld = load i16, ptr addrspace(4) %in184 %sext = sext i16 %ld to i32185 store i32 %sext, ptr addrspace(1) %out186 ret void187}188 189define amdgpu_ps void @test_s_load_i16_imm(ptr addrspace(4) inreg %in, ptr addrspace(1) %out) {190; DAG-LABEL: test_s_load_i16_imm:191; DAG: ; %bb.0:192; DAG-NEXT: s_movk_i32 s2, 0xff38193; DAG-NEXT: s_mov_b32 s3, -1194; DAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)195; DAG-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[2:3]196; DAG-NEXT: s_load_i16 s0, s[0:1], 0x0197; DAG-NEXT: s_wait_kmcnt 0x0198; DAG-NEXT: v_mov_b32_e32 v2, s0199; DAG-NEXT: global_store_b32 v[0:1], v2, off200; DAG-NEXT: s_endpgm201;202; GISEL-LABEL: test_s_load_i16_imm:203; GISEL: ; %bb.0:204; GISEL-NEXT: s_add_co_u32 s0, s0, 0xffffff38205; GISEL-NEXT: s_add_co_ci_u32 s1, s1, -1206; GISEL-NEXT: s_load_i16 s0, s[0:1], 0x0207; GISEL-NEXT: s_wait_kmcnt 0x0208; GISEL-NEXT: v_mov_b32_e32 v2, s0209; GISEL-NEXT: global_store_b32 v[0:1], v2, off210; GISEL-NEXT: s_endpgm211 %gep = getelementptr i16, ptr addrspace(4) %in, i64 -100212 %ld = load i16, ptr addrspace(4) %gep213 %sext = sext i16 %ld to i32214 store i32 %sext, ptr addrspace(1) %out215 ret void216}217 218define amdgpu_ps void @test_s_load_i16_sgpr(ptr addrspace(4) inreg %in, i32 inreg %offset, ptr addrspace(1) %out) {219; GCN-LABEL: test_s_load_i16_sgpr:220; GCN: ; %bb.0:221; GCN-NEXT: s_load_i16 s0, s[0:1], s2 offset:0x0222; GCN-NEXT: s_wait_kmcnt 0x0223; GCN-NEXT: v_mov_b32_e32 v2, s0224; GCN-NEXT: global_store_b32 v[0:1], v2, off225; GCN-NEXT: s_endpgm226 %zext = zext i32 %offset to i64227 %gep = getelementptr i8, ptr addrspace(4) %in, i64 %zext228 %ld = load i16, ptr addrspace(4) %gep229 %sext = sext i16 %ld to i32230 store i32 %sext, ptr addrspace(1) %out231 ret void232}233 234define amdgpu_ps void @test_s_load_i16_sgpr_imm(ptr addrspace(4) inreg %in, i32 inreg %offset, ptr addrspace(1) %out) {235; DAG-LABEL: test_s_load_i16_sgpr_imm:236; DAG: ; %bb.0:237; DAG-NEXT: s_mov_b32 s3, 0238; DAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)239; DAG-NEXT: s_lshl_b64 s[2:3], s[2:3], 1240; DAG-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[2:3]241; DAG-NEXT: s_load_i16 s0, s[0:1], 0x20242; DAG-NEXT: s_wait_kmcnt 0x0243; DAG-NEXT: v_mov_b32_e32 v2, s0244; DAG-NEXT: global_store_b32 v[0:1], v2, off245; DAG-NEXT: s_endpgm246;247; GISEL-LABEL: test_s_load_i16_sgpr_imm:248; GISEL: ; %bb.0:249; GISEL-NEXT: s_mov_b32 s3, 0250; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)251; GISEL-NEXT: s_lshl_b64 s[2:3], s[2:3], 1252; GISEL-NEXT: s_add_co_u32 s0, s0, s2253; GISEL-NEXT: s_add_co_ci_u32 s1, s1, s3254; GISEL-NEXT: s_load_i16 s0, s[0:1], 0x20255; GISEL-NEXT: s_wait_kmcnt 0x0256; GISEL-NEXT: v_mov_b32_e32 v2, s0257; GISEL-NEXT: global_store_b32 v[0:1], v2, off258; GISEL-NEXT: s_endpgm259 %gep1 = getelementptr i16, ptr addrspace(4) %in, i64 16260 %zext = zext i32 %offset to i64261 %gep2 = getelementptr i16, ptr addrspace(4) %gep1, i64 %zext262 %ld = load i16, ptr addrspace(4) %gep2263 %sext = sext i16 %ld to i32264 store i32 %sext, ptr addrspace(1) %out265 ret void266}267 268define amdgpu_ps void @test_s_load_i16_divergent(ptr addrspace(4) inreg %in, i32 %offset, ptr addrspace(1) %out) {269; DAG-LABEL: test_s_load_i16_divergent:270; DAG: ; %bb.0:271; DAG-NEXT: v_dual_mov_b32 v3, v0 :: v_dual_mov_b32 v4, 0272; DAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)273; DAG-NEXT: v_lshlrev_b64_e32 v[3:4], 1, v[3:4]274; DAG-NEXT: v_add_co_u32 v3, vcc_lo, s0, v3275; DAG-NEXT: s_delay_alu instid0(VALU_DEP_1)276; DAG-NEXT: v_add_co_ci_u32_e64 v4, null, s1, v4, vcc_lo277; DAG-NEXT: global_load_i16 v0, v[3:4], off offset:32278; DAG-NEXT: s_wait_loadcnt 0x0279; DAG-NEXT: global_store_b32 v[1:2], v0, off280; DAG-NEXT: s_endpgm281;282; GISEL-LABEL: test_s_load_i16_divergent:283; GISEL: ; %bb.0:284; GISEL-NEXT: v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v4, v2285; GISEL-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v6, s1286; GISEL-NEXT: v_mov_b32_e32 v5, s0287; GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)288; GISEL-NEXT: v_lshlrev_b64_e32 v[0:1], 1, v[0:1]289; GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v5, v0290; GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)291; GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, v6, v1, vcc_lo292; GISEL-NEXT: global_load_i16 v0, v[0:1], off offset:32293; GISEL-NEXT: s_wait_loadcnt 0x0294; GISEL-NEXT: global_store_b32 v[3:4], v0, off295; GISEL-NEXT: s_endpgm296 %gep1 = getelementptr i16, ptr addrspace(4) %in, i64 16297 %zext = zext i32 %offset to i64298 %gep2 = getelementptr i16, ptr addrspace(4) %gep1, i64 %zext299 %ld = load i16, ptr addrspace(4) %gep2300 %sext = sext i16 %ld to i32301 store i32 %sext, ptr addrspace(1) %out302 ret void303}304 305define amdgpu_ps void @test_s_load_u16(ptr addrspace(4) inreg %in, ptr addrspace(1) %out) {306; GCN-LABEL: test_s_load_u16:307; GCN: ; %bb.0:308; GCN-NEXT: s_load_u16 s0, s[0:1], 0x0309; GCN-NEXT: s_wait_kmcnt 0x0310; GCN-NEXT: v_mov_b32_e32 v2, s0311; GCN-NEXT: global_store_b32 v[0:1], v2, off312; GCN-NEXT: s_endpgm313 %ld = load i16, ptr addrspace(4) %in314 %zext = zext i16 %ld to i32315 store i32 %zext, ptr addrspace(1) %out316 ret void317}318 319define amdgpu_ps void @test_s_load_u16_imm(ptr addrspace(4) inreg %in, ptr addrspace(1) %out) {320; GCN-LABEL: test_s_load_u16_imm:321; GCN: ; %bb.0:322; GCN-NEXT: s_load_u16 s0, s[0:1], 0x1fe323; GCN-NEXT: s_wait_kmcnt 0x0324; GCN-NEXT: v_mov_b32_e32 v2, s0325; GCN-NEXT: global_store_b32 v[0:1], v2, off326; GCN-NEXT: s_endpgm327 %gep = getelementptr i16, ptr addrspace(4) %in, i64 255328 %ld = load i16, ptr addrspace(4) %gep329 %zext = zext i16 %ld to i32330 store i32 %zext, ptr addrspace(1) %out331 ret void332}333 334define amdgpu_ps void @test_s_load_u16_sgpr(ptr addrspace(4) inreg %in, i32 inreg %offset, ptr addrspace(1) %out) {335; GCN-LABEL: test_s_load_u16_sgpr:336; GCN: ; %bb.0:337; GCN-NEXT: s_load_u16 s0, s[0:1], s2 offset:0x0338; GCN-NEXT: s_wait_kmcnt 0x0339; GCN-NEXT: v_mov_b32_e32 v2, s0340; GCN-NEXT: global_store_b32 v[0:1], v2, off341; GCN-NEXT: s_endpgm342 %zext1 = zext i32 %offset to i64343 %gep = getelementptr i8, ptr addrspace(4) %in, i64 %zext1344 %ld = load i16, ptr addrspace(4) %gep345 %zext2 = zext i16 %ld to i32346 store i32 %zext2, ptr addrspace(1) %out347 ret void348}349 350define amdgpu_ps void @test_s_load_u16_sgpr_imm(ptr addrspace(4) inreg %in, i32 inreg %offset, ptr addrspace(1) %out) {351; DAG-LABEL: test_s_load_u16_sgpr_imm:352; DAG: ; %bb.0:353; DAG-NEXT: s_mov_b32 s3, 0354; DAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)355; DAG-NEXT: s_lshl_b64 s[2:3], s[2:3], 1356; DAG-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[2:3]357; DAG-NEXT: s_load_u16 s0, s[0:1], 0x20358; DAG-NEXT: s_wait_kmcnt 0x0359; DAG-NEXT: v_mov_b32_e32 v2, s0360; DAG-NEXT: global_store_b32 v[0:1], v2, off361; DAG-NEXT: s_endpgm362;363; GISEL-LABEL: test_s_load_u16_sgpr_imm:364; GISEL: ; %bb.0:365; GISEL-NEXT: s_mov_b32 s3, 0366; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)367; GISEL-NEXT: s_lshl_b64 s[2:3], s[2:3], 1368; GISEL-NEXT: s_add_co_u32 s0, s0, s2369; GISEL-NEXT: s_add_co_ci_u32 s1, s1, s3370; GISEL-NEXT: s_load_u16 s0, s[0:1], 0x20371; GISEL-NEXT: s_wait_kmcnt 0x0372; GISEL-NEXT: v_mov_b32_e32 v2, s0373; GISEL-NEXT: global_store_b32 v[0:1], v2, off374; GISEL-NEXT: s_endpgm375 %gep1 = getelementptr i16, ptr addrspace(4) %in, i64 16376 %zext1= zext i32 %offset to i64377 %gep2 = getelementptr i16, ptr addrspace(4) %gep1, i64 %zext1378 %ld = load i16, ptr addrspace(4) %gep2379 %zext2= zext i16 %ld to i32380 store i32 %zext2, ptr addrspace(1) %out381 ret void382}383 384define amdgpu_ps void @test_s_load_u16_divergent(ptr addrspace(4) inreg %in, i32 %offset, ptr addrspace(1) %out) {385; DAG-LABEL: test_s_load_u16_divergent:386; DAG: ; %bb.0:387; DAG-NEXT: v_dual_mov_b32 v3, v0 :: v_dual_mov_b32 v4, 0388; DAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)389; DAG-NEXT: v_lshlrev_b64_e32 v[3:4], 1, v[3:4]390; DAG-NEXT: v_add_co_u32 v3, vcc_lo, s0, v3391; DAG-NEXT: s_delay_alu instid0(VALU_DEP_1)392; DAG-NEXT: v_add_co_ci_u32_e64 v4, null, s1, v4, vcc_lo393; DAG-NEXT: global_load_u16 v0, v[3:4], off offset:32394; DAG-NEXT: s_wait_loadcnt 0x0395; DAG-NEXT: global_store_b32 v[1:2], v0, off396; DAG-NEXT: s_endpgm397;398; GISEL-LABEL: test_s_load_u16_divergent:399; GISEL: ; %bb.0:400; GISEL-NEXT: v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v4, v2401; GISEL-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v6, s1402; GISEL-NEXT: v_mov_b32_e32 v5, s0403; GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)404; GISEL-NEXT: v_lshlrev_b64_e32 v[0:1], 1, v[0:1]405; GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v5, v0406; GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)407; GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, v6, v1, vcc_lo408; GISEL-NEXT: global_load_u16 v0, v[0:1], off offset:32409; GISEL-NEXT: s_wait_loadcnt 0x0410; GISEL-NEXT: global_store_b32 v[3:4], v0, off411; GISEL-NEXT: s_endpgm412 %gep1 = getelementptr i16, ptr addrspace(4) %in, i64 16413 %zext1= zext i32 %offset to i64414 %gep2 = getelementptr i16, ptr addrspace(4) %gep1, i64 %zext1415 %ld = load i16, ptr addrspace(4) %gep2416 %zext2= zext i16 %ld to i32417 store i32 %zext2, ptr addrspace(1) %out418 ret void419}420 421define amdgpu_ps void @s_buffer_load_byte_imm_offset(<4 x i32> inreg %src, ptr addrspace(1) nocapture %out) {422; GCN-LABEL: s_buffer_load_byte_imm_offset:423; GCN: ; %bb.0: ; %main_body424; GCN-NEXT: s_buffer_load_i8 s0, s[0:3], 0x4425; GCN-NEXT: s_wait_kmcnt 0x0426; GCN-NEXT: v_mov_b32_e32 v2, s0427; GCN-NEXT: global_store_b32 v[0:1], v2, off428; GCN-NEXT: s_endpgm429main_body:430 %ld = call i8 @llvm.amdgcn.s.buffer.load.i8(<4 x i32> %src, i32 4, i32 0)431 %sext = sext i8 %ld to i32432 store i32 %sext, ptr addrspace(1) %out433 ret void434}435 436define amdgpu_ps void @s_buffer_load_byte_sgpr(<4 x i32> inreg %src, ptr addrspace(1) nocapture %out, i32 inreg %offset) {437; GCN-LABEL: s_buffer_load_byte_sgpr:438; GCN: ; %bb.0: ; %main_body439; GCN-NEXT: s_buffer_load_i8 s0, s[0:3], s4 offset:0x0440; GCN-NEXT: s_wait_kmcnt 0x0441; GCN-NEXT: v_mov_b32_e32 v2, s0442; GCN-NEXT: global_store_b32 v[0:1], v2, off443; GCN-NEXT: s_endpgm444main_body:445 %ld = call i8 @llvm.amdgcn.s.buffer.load.i8(<4 x i32> %src, i32 %offset, i32 0)446 %sext = sext i8 %ld to i32447 store i32 %sext, ptr addrspace(1) %out448 ret void449}450 451define amdgpu_ps void @s_buffer_load_byte_sgpr_or_imm_offset(<4 x i32> inreg %src, ptr addrspace(1) nocapture %out, i32 inreg %in) {452; GCN-LABEL: s_buffer_load_byte_sgpr_or_imm_offset:453; GCN: ; %bb.0: ; %main_body454; GCN-NEXT: s_buffer_load_i8 s0, s[0:3], s4 offset:0x64455; GCN-NEXT: s_wait_kmcnt 0x0456; GCN-NEXT: v_mov_b32_e32 v2, s0457; GCN-NEXT: global_store_b32 v[0:1], v2, off458; GCN-NEXT: s_endpgm459main_body:460 %off = add nuw nsw i32 %in, 100461 %ld = call i8 @llvm.amdgcn.s.buffer.load.i8(<4 x i32> %src, i32 %off, i32 0)462 %sext = sext i8 %ld to i32463 store i32 %sext, ptr addrspace(1) %out464 ret void465}466 467define amdgpu_ps void @s_buffer_load_byte_sgpr_or_imm_offset_divergent(<4 x i32> inreg %src, ptr addrspace(1) nocapture %out, i32 %offset) {468; GCN-LABEL: s_buffer_load_byte_sgpr_or_imm_offset_divergent:469; GCN: ; %bb.0: ; %main_body470; GCN-NEXT: buffer_load_i8 v2, v2, s[0:3], null offen471; GCN-NEXT: s_wait_loadcnt 0x0472; GCN-NEXT: global_store_b32 v[0:1], v2, off473; GCN-NEXT: s_endpgm474main_body:475 %ld = call i8 @llvm.amdgcn.s.buffer.load.i8(<4 x i32> %src, i32 %offset, i32 0)476 %sext = sext i8 %ld to i32477 store i32 %sext, ptr addrspace(1) %out478 ret void479}480 481define amdgpu_ps void @s_buffer_load_ubyte_imm_offset(<4 x i32> inreg %src, ptr addrspace(1) nocapture %out) {482; GCN-LABEL: s_buffer_load_ubyte_imm_offset:483; GCN: ; %bb.0: ; %main_body484; GCN-NEXT: s_buffer_load_u8 s0, s[0:3], 0x4485; GCN-NEXT: s_wait_kmcnt 0x0486; GCN-NEXT: s_and_b32 s0, s0, 0xff487; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_1)488; GCN-NEXT: v_mov_b32_e32 v2, s0489; GCN-NEXT: global_store_b32 v[0:1], v2, off490; GCN-NEXT: s_endpgm491main_body:492 %ld = call i8 @llvm.amdgcn.s.buffer.load.u8(<4 x i32> %src, i32 4, i32 0)493 %zext = zext i8 %ld to i32494 store i32 %zext, ptr addrspace(1) %out495 ret void496}497 498define amdgpu_ps void @s_buffer_load_ubyte_sgpr(<4 x i32> inreg %src, ptr addrspace(1) nocapture %out, i32 inreg %offset) {499; GCN-LABEL: s_buffer_load_ubyte_sgpr:500; GCN: ; %bb.0: ; %main_body501; GCN-NEXT: s_buffer_load_u8 s0, s[0:3], s4 offset:0x0502; GCN-NEXT: s_wait_kmcnt 0x0503; GCN-NEXT: s_and_b32 s0, s0, 0xff504; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_1)505; GCN-NEXT: v_mov_b32_e32 v2, s0506; GCN-NEXT: global_store_b32 v[0:1], v2, off507; GCN-NEXT: s_endpgm508main_body:509 %ld = call i8 @llvm.amdgcn.s.buffer.load.u8(<4 x i32> %src, i32 %offset, i32 0)510 %zext = zext i8 %ld to i32511 store i32 %zext, ptr addrspace(1) %out512 ret void513}514 515define amdgpu_ps void @s_buffer_load_ubyte_sgpr_or_imm_offset(<4 x i32> inreg %src, ptr addrspace(1) nocapture %out, i32 inreg %in) {516; GCN-LABEL: s_buffer_load_ubyte_sgpr_or_imm_offset:517; GCN: ; %bb.0: ; %main_body518; GCN-NEXT: s_buffer_load_u8 s0, s[0:3], s4 offset:0x64519; GCN-NEXT: s_wait_kmcnt 0x0520; GCN-NEXT: s_and_b32 s0, s0, 0xff521; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_1)522; GCN-NEXT: v_mov_b32_e32 v2, s0523; GCN-NEXT: global_store_b32 v[0:1], v2, off524; GCN-NEXT: s_endpgm525main_body:526 %off = add nuw nsw i32 %in, 100527 %ld = call i8 @llvm.amdgcn.s.buffer.load.u8(<4 x i32> %src, i32 %off, i32 0)528 %zext = zext i8 %ld to i32529 store i32 %zext, ptr addrspace(1) %out530 ret void531}532 533define amdgpu_ps void @s_buffer_load_ubyte_sgpr_or_imm_offset_divergent(<4 x i32> inreg %src, ptr addrspace(1) nocapture %out, i32 %offset) {534; GCN-LABEL: s_buffer_load_ubyte_sgpr_or_imm_offset_divergent:535; GCN: ; %bb.0: ; %main_body536; GCN-NEXT: buffer_load_u8 v2, v2, s[0:3], null offen537; GCN-NEXT: s_wait_loadcnt 0x0538; GCN-NEXT: global_store_b32 v[0:1], v2, off539; GCN-NEXT: s_endpgm540main_body:541 %ld = call i8 @llvm.amdgcn.s.buffer.load.u8(<4 x i32> %src, i32 %offset, i32 0)542 %zext = zext i8 %ld to i32543 store i32 %zext, ptr addrspace(1) %out544 ret void545}546 547define amdgpu_ps void @s_buffer_load_short_imm_offset(<4 x i32> inreg %src, ptr addrspace(1) nocapture %out) {548; GCN-LABEL: s_buffer_load_short_imm_offset:549; GCN: ; %bb.0: ; %main_body550; GCN-NEXT: s_buffer_load_i16 s0, s[0:3], 0x4551; GCN-NEXT: s_wait_kmcnt 0x0552; GCN-NEXT: v_mov_b32_e32 v2, s0553; GCN-NEXT: global_store_b32 v[0:1], v2, off554; GCN-NEXT: s_endpgm555main_body:556 %ld = call i16 @llvm.amdgcn.s.buffer.load.i16(<4 x i32> %src, i32 4, i32 0)557 %sext = sext i16 %ld to i32558 store i32 %sext, ptr addrspace(1) %out559 ret void560}561 562define amdgpu_ps void @s_buffer_load_short_sgpr(<4 x i32> inreg %src, ptr addrspace(1) nocapture %out, i32 inreg %offset) {563; GCN-LABEL: s_buffer_load_short_sgpr:564; GCN: ; %bb.0: ; %main_body565; GCN-NEXT: s_buffer_load_i16 s0, s[0:3], s4 offset:0x0566; GCN-NEXT: s_wait_kmcnt 0x0567; GCN-NEXT: v_mov_b32_e32 v2, s0568; GCN-NEXT: global_store_b32 v[0:1], v2, off569; GCN-NEXT: s_endpgm570main_body:571 %ld = call i16 @llvm.amdgcn.s.buffer.load.i16(<4 x i32> %src, i32 %offset, i32 0)572 %sext = sext i16 %ld to i32573 store i32 %sext, ptr addrspace(1) %out574 ret void575}576 577define amdgpu_ps void @s_buffer_load_short_sgpr_or_imm_offset(<4 x i32> inreg %src, ptr addrspace(1) nocapture %out, i32 inreg %in) {578; GCN-LABEL: s_buffer_load_short_sgpr_or_imm_offset:579; GCN: ; %bb.0: ; %main_body580; GCN-NEXT: s_buffer_load_i16 s0, s[0:3], s4 offset:0x64581; GCN-NEXT: s_wait_kmcnt 0x0582; GCN-NEXT: v_mov_b32_e32 v2, s0583; GCN-NEXT: global_store_b32 v[0:1], v2, off584; GCN-NEXT: s_endpgm585main_body:586 %off = add nuw nsw i32 %in, 100587 %ld = call i16 @llvm.amdgcn.s.buffer.load.i16(<4 x i32> %src, i32 %off, i32 0)588 %sext = sext i16 %ld to i32589 store i32 %sext, ptr addrspace(1) %out590 ret void591}592 593define amdgpu_ps void @s_buffer_load_short_sgpr_or_imm_offset_divergent(<4 x i32> inreg %src, ptr addrspace(1) nocapture %out, i32 %offset) {594; GCN-LABEL: s_buffer_load_short_sgpr_or_imm_offset_divergent:595; GCN: ; %bb.0: ; %main_body596; GCN-NEXT: buffer_load_i16 v2, v2, s[0:3], null offen597; GCN-NEXT: s_wait_loadcnt 0x0598; GCN-NEXT: global_store_b32 v[0:1], v2, off599; GCN-NEXT: s_endpgm600main_body:601 %ld = call i16 @llvm.amdgcn.s.buffer.load.i16(<4 x i32> %src, i32 %offset, i32 0)602 %sext = sext i16 %ld to i32603 store i32 %sext, ptr addrspace(1) %out604 ret void605}606 607define amdgpu_ps void @s_buffer_load_ushort_imm_offset(<4 x i32> inreg %src, ptr addrspace(1) nocapture %out) {608; GCN-LABEL: s_buffer_load_ushort_imm_offset:609; GCN: ; %bb.0: ; %main_body610; GCN-NEXT: s_buffer_load_u16 s0, s[0:3], 0x4611; GCN-NEXT: s_wait_kmcnt 0x0612; GCN-NEXT: s_and_b32 s0, s0, 0xffff613; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_1)614; GCN-NEXT: v_mov_b32_e32 v2, s0615; GCN-NEXT: global_store_b32 v[0:1], v2, off616; GCN-NEXT: s_endpgm617main_body:618 %ld = call i16 @llvm.amdgcn.s.buffer.load.u16(<4 x i32> %src, i32 4, i32 0)619 %zext = zext i16 %ld to i32620 store i32 %zext, ptr addrspace(1) %out621 ret void622}623 624define amdgpu_ps void @s_buffer_load_ushort_sgpr(<4 x i32> inreg %src, ptr addrspace(1) nocapture %out, i32 inreg %offset) {625; GCN-LABEL: s_buffer_load_ushort_sgpr:626; GCN: ; %bb.0: ; %main_body627; GCN-NEXT: s_buffer_load_u16 s0, s[0:3], s4 offset:0x0628; GCN-NEXT: s_wait_kmcnt 0x0629; GCN-NEXT: s_and_b32 s0, s0, 0xffff630; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_1)631; GCN-NEXT: v_mov_b32_e32 v2, s0632; GCN-NEXT: global_store_b32 v[0:1], v2, off633; GCN-NEXT: s_endpgm634main_body:635 %ld = call i16 @llvm.amdgcn.s.buffer.load.u16(<4 x i32> %src, i32 %offset, i32 0)636 %zext = zext i16 %ld to i32637 store i32 %zext, ptr addrspace(1) %out638 ret void639}640 641define amdgpu_ps void @s_buffer_load_ushort_sgpr_or_imm_offset(<4 x i32> inreg %src, ptr addrspace(1) nocapture %out, i32 inreg %in) {642; GCN-LABEL: s_buffer_load_ushort_sgpr_or_imm_offset:643; GCN: ; %bb.0: ; %main_body644; GCN-NEXT: s_buffer_load_u16 s0, s[0:3], s4 offset:0x64645; GCN-NEXT: s_wait_kmcnt 0x0646; GCN-NEXT: s_and_b32 s0, s0, 0xffff647; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_1)648; GCN-NEXT: v_mov_b32_e32 v2, s0649; GCN-NEXT: global_store_b32 v[0:1], v2, off650; GCN-NEXT: s_endpgm651main_body:652 %off = add nuw nsw i32 %in, 100653 %ld = call i16 @llvm.amdgcn.s.buffer.load.u16(<4 x i32> %src, i32 %off, i32 0)654 %zext = zext i16 %ld to i32655 store i32 %zext, ptr addrspace(1) %out656 ret void657}658 659define amdgpu_ps void @s_buffer_load_ushort_sgpr_or_imm_offset_divergent(<4 x i32> inreg %src, ptr addrspace(1) nocapture %out, i32 %offset) {660; GCN-LABEL: s_buffer_load_ushort_sgpr_or_imm_offset_divergent:661; GCN: ; %bb.0: ; %main_body662; GCN-NEXT: buffer_load_u16 v2, v2, s[0:3], null offen663; GCN-NEXT: s_wait_loadcnt 0x0664; GCN-NEXT: global_store_b32 v[0:1], v2, off665; GCN-NEXT: s_endpgm666main_body:667 %ld = call i16 @llvm.amdgcn.s.buffer.load.u16(<4 x i32> %src, i32 %offset, i32 0)668 %zext = zext i16 %ld to i32669 store i32 %zext, ptr addrspace(1) %out670 ret void671}672 673declare i8 @llvm.amdgcn.s.buffer.load.i8(<4 x i32>, i32, i32)674declare i8 @llvm.amdgcn.s.buffer.load.u8(<4 x i32>, i32, i32)675declare i16 @llvm.amdgcn.s.buffer.load.i16(<4 x i32>, i32, i32)676declare i16 @llvm.amdgcn.s.buffer.load.u16(<4 x i32>, i32, i32)677