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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9 %s3; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GCN,GFX10 %s4; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX11 %s5; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX12 %s6 7; Test using saddr addressing mode of global_*store_* flat instructions.8 9define amdgpu_ps void @global_store_saddr_i8_zext_vgpr(ptr addrspace(1) inreg %sbase, ptr addrspace(1) %voffset.ptr, i8 %data) {10; GCN-LABEL: global_store_saddr_i8_zext_vgpr:11; GCN: ; %bb.0:12; GCN-NEXT: global_load_dword v0, v[0:1], off13; GCN-NEXT: s_waitcnt vmcnt(0)14; GCN-NEXT: global_store_byte v0, v2, s[2:3]15; GCN-NEXT: s_endpgm16;17; GFX11-LABEL: global_store_saddr_i8_zext_vgpr:18; GFX11: ; %bb.0:19; GFX11-NEXT: global_load_b32 v0, v[0:1], off20; GFX11-NEXT: s_waitcnt vmcnt(0)21; GFX11-NEXT: global_store_b8 v0, v2, s[2:3]22; GFX11-NEXT: s_endpgm23;24; GFX12-LABEL: global_store_saddr_i8_zext_vgpr:25; GFX12: ; %bb.0:26; GFX12-NEXT: global_load_b32 v0, v[0:1], off27; GFX12-NEXT: s_wait_loadcnt 0x028; GFX12-NEXT: global_store_b8 v0, v2, s[2:3]29; GFX12-NEXT: s_endpgm30 %voffset = load i32, ptr addrspace(1) %voffset.ptr31 %zext.offset = zext i32 %voffset to i6432 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset33 store i8 %data, ptr addrspace(1) %gep034 ret void35}36 37; Maximum positive offset on gfx1038define amdgpu_ps void @global_store_saddr_i8_zext_vgpr_offset_2047(ptr addrspace(1) inreg %sbase, ptr addrspace(1) %voffset.ptr, i8 %data) {39; GCN-LABEL: global_store_saddr_i8_zext_vgpr_offset_2047:40; GCN: ; %bb.0:41; GCN-NEXT: global_load_dword v0, v[0:1], off42; GCN-NEXT: s_waitcnt vmcnt(0)43; GCN-NEXT: global_store_byte v0, v2, s[2:3] offset:204744; GCN-NEXT: s_endpgm45;46; GFX11-LABEL: global_store_saddr_i8_zext_vgpr_offset_2047:47; GFX11: ; %bb.0:48; GFX11-NEXT: global_load_b32 v0, v[0:1], off49; GFX11-NEXT: s_waitcnt vmcnt(0)50; GFX11-NEXT: global_store_b8 v0, v2, s[2:3] offset:204751; GFX11-NEXT: s_endpgm52;53; GFX12-LABEL: global_store_saddr_i8_zext_vgpr_offset_2047:54; GFX12: ; %bb.0:55; GFX12-NEXT: global_load_b32 v0, v[0:1], off56; GFX12-NEXT: s_wait_loadcnt 0x057; GFX12-NEXT: global_store_b8 v0, v2, s[2:3] offset:204758; GFX12-NEXT: s_endpgm59 %voffset = load i32, ptr addrspace(1) %voffset.ptr60 %zext.offset = zext i32 %voffset to i6461 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset62 %gep1 = getelementptr inbounds i8, ptr addrspace(1) %gep0, i64 204763 store i8 %data, ptr addrspace(1) %gep164 ret void65}66 67; Maximum negative offset on gfx1068define amdgpu_ps void @global_store_saddr_i8_zext_vgpr_offset_neg2048(ptr addrspace(1) inreg %sbase, ptr addrspace(1) %voffset.ptr, i8 %data) {69; GCN-LABEL: global_store_saddr_i8_zext_vgpr_offset_neg2048:70; GCN: ; %bb.0:71; GCN-NEXT: global_load_dword v0, v[0:1], off72; GCN-NEXT: s_waitcnt vmcnt(0)73; GCN-NEXT: global_store_byte v0, v2, s[2:3] offset:-204874; GCN-NEXT: s_endpgm75;76; GFX11-LABEL: global_store_saddr_i8_zext_vgpr_offset_neg2048:77; GFX11: ; %bb.0:78; GFX11-NEXT: global_load_b32 v0, v[0:1], off79; GFX11-NEXT: s_waitcnt vmcnt(0)80; GFX11-NEXT: global_store_b8 v0, v2, s[2:3] offset:-204881; GFX11-NEXT: s_endpgm82;83; GFX12-LABEL: global_store_saddr_i8_zext_vgpr_offset_neg2048:84; GFX12: ; %bb.0:85; GFX12-NEXT: global_load_b32 v0, v[0:1], off86; GFX12-NEXT: s_wait_loadcnt 0x087; GFX12-NEXT: global_store_b8 v0, v2, s[2:3] offset:-204888; GFX12-NEXT: s_endpgm89 %voffset = load i32, ptr addrspace(1) %voffset.ptr90 %zext.offset = zext i32 %voffset to i6491 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset92 %gep1 = getelementptr inbounds i8, ptr addrspace(1) %gep0, i64 -204893 store i8 %data, ptr addrspace(1) %gep194 ret void95}96 97; --------------------------------------------------------------------------------98; Uniformity edge cases99; --------------------------------------------------------------------------------100 101@ptr.in.lds = internal addrspace(3) global ptr addrspace(1) poison102 103; Base pointer is uniform, but also in VGPRs104define amdgpu_ps void @global_store_saddr_uniform_ptr_in_vgprs(i32 %voffset, i8 %data) {105; GFX9-LABEL: global_store_saddr_uniform_ptr_in_vgprs:106; GFX9: ; %bb.0:107; GFX9-NEXT: v_mov_b32_e32 v2, 0108; GFX9-NEXT: ds_read_b64 v[2:3], v2109; GFX9-NEXT: s_waitcnt lgkmcnt(0)110; GFX9-NEXT: v_readfirstlane_b32 s0, v2111; GFX9-NEXT: v_readfirstlane_b32 s1, v3112; GFX9-NEXT: s_nop 4113; GFX9-NEXT: global_store_byte v0, v1, s[0:1]114; GFX9-NEXT: s_endpgm115;116; GFX10-LABEL: global_store_saddr_uniform_ptr_in_vgprs:117; GFX10: ; %bb.0:118; GFX10-NEXT: v_mov_b32_e32 v2, 0119; GFX10-NEXT: ds_read_b64 v[2:3], v2120; GFX10-NEXT: s_waitcnt lgkmcnt(0)121; GFX10-NEXT: v_readfirstlane_b32 s0, v2122; GFX10-NEXT: v_readfirstlane_b32 s1, v3123; GFX10-NEXT: global_store_byte v0, v1, s[0:1]124; GFX10-NEXT: s_endpgm125;126; GFX11-LABEL: global_store_saddr_uniform_ptr_in_vgprs:127; GFX11: ; %bb.0:128; GFX11-NEXT: v_mov_b32_e32 v2, 0129; GFX11-NEXT: ds_load_b64 v[2:3], v2130; GFX11-NEXT: s_waitcnt lgkmcnt(0)131; GFX11-NEXT: v_readfirstlane_b32 s0, v2132; GFX11-NEXT: v_readfirstlane_b32 s1, v3133; GFX11-NEXT: global_store_b8 v0, v1, s[0:1]134; GFX11-NEXT: s_endpgm135;136; GFX12-LABEL: global_store_saddr_uniform_ptr_in_vgprs:137; GFX12: ; %bb.0:138; GFX12-NEXT: v_mov_b32_e32 v2, 0139; GFX12-NEXT: ds_load_b64 v[2:3], v2140; GFX12-NEXT: s_wait_dscnt 0x0141; GFX12-NEXT: v_readfirstlane_b32 s0, v2142; GFX12-NEXT: v_readfirstlane_b32 s1, v3143; GFX12-NEXT: global_store_b8 v0, v1, s[0:1]144; GFX12-NEXT: s_endpgm145 %sbase = load ptr addrspace(1), ptr addrspace(3) @ptr.in.lds146 %zext.offset = zext i32 %voffset to i64147 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset148 store i8 %data, ptr addrspace(1) %gep0149 ret void150}151 152; Base pointer is uniform, but also in VGPRs, with imm offset153define amdgpu_ps void @global_store_saddr_uniform_ptr_in_vgprs_immoffset(i32 %voffset, i8 %data) {154; GFX9-LABEL: global_store_saddr_uniform_ptr_in_vgprs_immoffset:155; GFX9: ; %bb.0:156; GFX9-NEXT: v_mov_b32_e32 v2, 0157; GFX9-NEXT: ds_read_b64 v[2:3], v2158; GFX9-NEXT: s_waitcnt lgkmcnt(0)159; GFX9-NEXT: v_readfirstlane_b32 s0, v2160; GFX9-NEXT: v_readfirstlane_b32 s1, v3161; GFX9-NEXT: s_nop 4162; GFX9-NEXT: global_store_byte v0, v1, s[0:1] offset:-120163; GFX9-NEXT: s_endpgm164;165; GFX10-LABEL: global_store_saddr_uniform_ptr_in_vgprs_immoffset:166; GFX10: ; %bb.0:167; GFX10-NEXT: v_mov_b32_e32 v2, 0168; GFX10-NEXT: ds_read_b64 v[2:3], v2169; GFX10-NEXT: s_waitcnt lgkmcnt(0)170; GFX10-NEXT: v_readfirstlane_b32 s0, v2171; GFX10-NEXT: v_readfirstlane_b32 s1, v3172; GFX10-NEXT: global_store_byte v0, v1, s[0:1] offset:-120173; GFX10-NEXT: s_endpgm174;175; GFX11-LABEL: global_store_saddr_uniform_ptr_in_vgprs_immoffset:176; GFX11: ; %bb.0:177; GFX11-NEXT: v_mov_b32_e32 v2, 0178; GFX11-NEXT: ds_load_b64 v[2:3], v2179; GFX11-NEXT: s_waitcnt lgkmcnt(0)180; GFX11-NEXT: v_readfirstlane_b32 s0, v2181; GFX11-NEXT: v_readfirstlane_b32 s1, v3182; GFX11-NEXT: global_store_b8 v0, v1, s[0:1] offset:-120183; GFX11-NEXT: s_endpgm184;185; GFX12-LABEL: global_store_saddr_uniform_ptr_in_vgprs_immoffset:186; GFX12: ; %bb.0:187; GFX12-NEXT: v_mov_b32_e32 v2, 0188; GFX12-NEXT: ds_load_b64 v[2:3], v2189; GFX12-NEXT: s_wait_dscnt 0x0190; GFX12-NEXT: v_readfirstlane_b32 s0, v2191; GFX12-NEXT: v_readfirstlane_b32 s1, v3192; GFX12-NEXT: global_store_b8 v0, v1, s[0:1] offset:-120193; GFX12-NEXT: s_endpgm194 %sbase = load ptr addrspace(1), ptr addrspace(3) @ptr.in.lds195 %zext.offset = zext i32 %voffset to i64196 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset197 %gep1 = getelementptr inbounds i8, ptr addrspace(1) %gep0, i64 -120198 store i8 %data, ptr addrspace(1) %gep1199 ret void200}201 202; --------------------------------------------------------------------------------203; Stress various type stores204; --------------------------------------------------------------------------------205 206define amdgpu_ps void @global_store_saddr_i16_zext_vgpr(ptr addrspace(1) inreg %sbase, i32 %voffset, i16 %data) {207; GCN-LABEL: global_store_saddr_i16_zext_vgpr:208; GCN: ; %bb.0:209; GCN-NEXT: global_store_short v0, v1, s[2:3]210; GCN-NEXT: s_endpgm211;212; GFX11-LABEL: global_store_saddr_i16_zext_vgpr:213; GFX11: ; %bb.0:214; GFX11-NEXT: global_store_b16 v0, v1, s[2:3]215; GFX11-NEXT: s_endpgm216;217; GFX12-LABEL: global_store_saddr_i16_zext_vgpr:218; GFX12: ; %bb.0:219; GFX12-NEXT: global_store_b16 v0, v1, s[2:3]220; GFX12-NEXT: s_endpgm221 %zext.offset = zext i32 %voffset to i64222 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset223 store i16 %data, ptr addrspace(1) %gep0224 ret void225}226 227define amdgpu_ps void @global_store_saddr_i16_zext_vgpr_offset_neg128(ptr addrspace(1) inreg %sbase, i32 %voffset, i16 %data) {228; GCN-LABEL: global_store_saddr_i16_zext_vgpr_offset_neg128:229; GCN: ; %bb.0:230; GCN-NEXT: global_store_short v0, v1, s[2:3] offset:-128231; GCN-NEXT: s_endpgm232;233; GFX11-LABEL: global_store_saddr_i16_zext_vgpr_offset_neg128:234; GFX11: ; %bb.0:235; GFX11-NEXT: global_store_b16 v0, v1, s[2:3] offset:-128236; GFX11-NEXT: s_endpgm237;238; GFX12-LABEL: global_store_saddr_i16_zext_vgpr_offset_neg128:239; GFX12: ; %bb.0:240; GFX12-NEXT: global_store_b16 v0, v1, s[2:3] offset:-128241; GFX12-NEXT: s_endpgm242 %zext.offset = zext i32 %voffset to i64243 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset244 %gep1 = getelementptr inbounds i8, ptr addrspace(1) %gep0, i64 -128245 store i16 %data, ptr addrspace(1) %gep1246 ret void247}248 249define amdgpu_ps void @global_store_saddr_f16_zext_vgpr(ptr addrspace(1) inreg %sbase, i32 %voffset, half %data) {250; GCN-LABEL: global_store_saddr_f16_zext_vgpr:251; GCN: ; %bb.0:252; GCN-NEXT: global_store_short v0, v1, s[2:3]253; GCN-NEXT: s_endpgm254;255; GFX11-LABEL: global_store_saddr_f16_zext_vgpr:256; GFX11: ; %bb.0:257; GFX11-NEXT: global_store_b16 v0, v1, s[2:3]258; GFX11-NEXT: s_endpgm259;260; GFX12-LABEL: global_store_saddr_f16_zext_vgpr:261; GFX12: ; %bb.0:262; GFX12-NEXT: global_store_b16 v0, v1, s[2:3]263; GFX12-NEXT: s_endpgm264 %zext.offset = zext i32 %voffset to i64265 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset266 store half %data, ptr addrspace(1) %gep0267 ret void268}269 270define amdgpu_ps void @global_store_saddr_f16_zext_vgpr_offset_neg128(ptr addrspace(1) inreg %sbase, i32 %voffset, half %data) {271; GCN-LABEL: global_store_saddr_f16_zext_vgpr_offset_neg128:272; GCN: ; %bb.0:273; GCN-NEXT: global_store_short v0, v1, s[2:3] offset:-128274; GCN-NEXT: s_endpgm275;276; GFX11-LABEL: global_store_saddr_f16_zext_vgpr_offset_neg128:277; GFX11: ; %bb.0:278; GFX11-NEXT: global_store_b16 v0, v1, s[2:3] offset:-128279; GFX11-NEXT: s_endpgm280;281; GFX12-LABEL: global_store_saddr_f16_zext_vgpr_offset_neg128:282; GFX12: ; %bb.0:283; GFX12-NEXT: global_store_b16 v0, v1, s[2:3] offset:-128284; GFX12-NEXT: s_endpgm285 %zext.offset = zext i32 %voffset to i64286 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset287 %gep1 = getelementptr inbounds i8, ptr addrspace(1) %gep0, i64 -128288 store half %data, ptr addrspace(1) %gep1289 ret void290}291 292define amdgpu_ps void @global_store_saddr_i32_zext_vgpr(ptr addrspace(1) inreg %sbase, i32 %voffset, i32 %data) {293; GCN-LABEL: global_store_saddr_i32_zext_vgpr:294; GCN: ; %bb.0:295; GCN-NEXT: global_store_dword v0, v1, s[2:3]296; GCN-NEXT: s_endpgm297;298; GFX11-LABEL: global_store_saddr_i32_zext_vgpr:299; GFX11: ; %bb.0:300; GFX11-NEXT: global_store_b32 v0, v1, s[2:3]301; GFX11-NEXT: s_endpgm302;303; GFX12-LABEL: global_store_saddr_i32_zext_vgpr:304; GFX12: ; %bb.0:305; GFX12-NEXT: global_store_b32 v0, v1, s[2:3]306; GFX12-NEXT: s_endpgm307 %zext.offset = zext i32 %voffset to i64308 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset309 store i32 %data, ptr addrspace(1) %gep0310 ret void311}312 313define amdgpu_ps void @global_store_saddr_i32_zext_vgpr_offset_neg128(ptr addrspace(1) inreg %sbase, i32 %voffset, i32 %data) {314; GCN-LABEL: global_store_saddr_i32_zext_vgpr_offset_neg128:315; GCN: ; %bb.0:316; GCN-NEXT: global_store_dword v0, v1, s[2:3] offset:-128317; GCN-NEXT: s_endpgm318;319; GFX11-LABEL: global_store_saddr_i32_zext_vgpr_offset_neg128:320; GFX11: ; %bb.0:321; GFX11-NEXT: global_store_b32 v0, v1, s[2:3] offset:-128322; GFX11-NEXT: s_endpgm323;324; GFX12-LABEL: global_store_saddr_i32_zext_vgpr_offset_neg128:325; GFX12: ; %bb.0:326; GFX12-NEXT: global_store_b32 v0, v1, s[2:3] offset:-128327; GFX12-NEXT: s_endpgm328 %zext.offset = zext i32 %voffset to i64329 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset330 %gep1 = getelementptr inbounds i8, ptr addrspace(1) %gep0, i64 -128331 store i32 %data, ptr addrspace(1) %gep1332 ret void333}334 335define amdgpu_ps void @global_store_saddr_f32_zext_vgpr(ptr addrspace(1) inreg %sbase, i32 %voffset, float %data) {336; GCN-LABEL: global_store_saddr_f32_zext_vgpr:337; GCN: ; %bb.0:338; GCN-NEXT: global_store_dword v0, v1, s[2:3]339; GCN-NEXT: s_endpgm340;341; GFX11-LABEL: global_store_saddr_f32_zext_vgpr:342; GFX11: ; %bb.0:343; GFX11-NEXT: global_store_b32 v0, v1, s[2:3]344; GFX11-NEXT: s_endpgm345;346; GFX12-LABEL: global_store_saddr_f32_zext_vgpr:347; GFX12: ; %bb.0:348; GFX12-NEXT: global_store_b32 v0, v1, s[2:3]349; GFX12-NEXT: s_endpgm350 %zext.offset = zext i32 %voffset to i64351 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset352 store float %data, ptr addrspace(1) %gep0353 ret void354}355 356define amdgpu_ps void @global_store_saddr_f32_zext_vgpr_offset_neg128(ptr addrspace(1) inreg %sbase, i32 %voffset, float %data) {357; GCN-LABEL: global_store_saddr_f32_zext_vgpr_offset_neg128:358; GCN: ; %bb.0:359; GCN-NEXT: global_store_dword v0, v1, s[2:3] offset:-128360; GCN-NEXT: s_endpgm361;362; GFX11-LABEL: global_store_saddr_f32_zext_vgpr_offset_neg128:363; GFX11: ; %bb.0:364; GFX11-NEXT: global_store_b32 v0, v1, s[2:3] offset:-128365; GFX11-NEXT: s_endpgm366;367; GFX12-LABEL: global_store_saddr_f32_zext_vgpr_offset_neg128:368; GFX12: ; %bb.0:369; GFX12-NEXT: global_store_b32 v0, v1, s[2:3] offset:-128370; GFX12-NEXT: s_endpgm371 %zext.offset = zext i32 %voffset to i64372 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset373 %gep1 = getelementptr inbounds i8, ptr addrspace(1) %gep0, i64 -128374 store float %data, ptr addrspace(1) %gep1375 ret void376}377 378define amdgpu_ps void @global_store_saddr_p3_zext_vgpr(ptr addrspace(1) inreg %sbase, i32 %voffset, ptr addrspace(3) %data) {379; GCN-LABEL: global_store_saddr_p3_zext_vgpr:380; GCN: ; %bb.0:381; GCN-NEXT: global_store_dword v0, v1, s[2:3]382; GCN-NEXT: s_endpgm383;384; GFX11-LABEL: global_store_saddr_p3_zext_vgpr:385; GFX11: ; %bb.0:386; GFX11-NEXT: global_store_b32 v0, v1, s[2:3]387; GFX11-NEXT: s_endpgm388;389; GFX12-LABEL: global_store_saddr_p3_zext_vgpr:390; GFX12: ; %bb.0:391; GFX12-NEXT: global_store_b32 v0, v1, s[2:3]392; GFX12-NEXT: s_endpgm393 %zext.offset = zext i32 %voffset to i64394 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset395 store ptr addrspace(3) %data, ptr addrspace(1) %gep0396 ret void397}398 399define amdgpu_ps void @global_store_saddr_p3_zext_vgpr_offset_neg128(ptr addrspace(1) inreg %sbase, i32 %voffset, ptr addrspace(3) %data) {400; GCN-LABEL: global_store_saddr_p3_zext_vgpr_offset_neg128:401; GCN: ; %bb.0:402; GCN-NEXT: global_store_dword v0, v1, s[2:3] offset:-128403; GCN-NEXT: s_endpgm404;405; GFX11-LABEL: global_store_saddr_p3_zext_vgpr_offset_neg128:406; GFX11: ; %bb.0:407; GFX11-NEXT: global_store_b32 v0, v1, s[2:3] offset:-128408; GFX11-NEXT: s_endpgm409;410; GFX12-LABEL: global_store_saddr_p3_zext_vgpr_offset_neg128:411; GFX12: ; %bb.0:412; GFX12-NEXT: global_store_b32 v0, v1, s[2:3] offset:-128413; GFX12-NEXT: s_endpgm414 %zext.offset = zext i32 %voffset to i64415 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset416 %gep1 = getelementptr inbounds i8, ptr addrspace(1) %gep0, i64 -128417 store ptr addrspace(3) %data, ptr addrspace(1) %gep1418 ret void419}420 421define amdgpu_ps void @global_store_saddr_i64_zext_vgpr(ptr addrspace(1) inreg %sbase, i32 %voffset, i64 %data) {422; GCN-LABEL: global_store_saddr_i64_zext_vgpr:423; GCN: ; %bb.0:424; GCN-NEXT: global_store_dwordx2 v0, v[1:2], s[2:3]425; GCN-NEXT: s_endpgm426;427; GFX11-LABEL: global_store_saddr_i64_zext_vgpr:428; GFX11: ; %bb.0:429; GFX11-NEXT: global_store_b64 v0, v[1:2], s[2:3]430; GFX11-NEXT: s_endpgm431;432; GFX12-LABEL: global_store_saddr_i64_zext_vgpr:433; GFX12: ; %bb.0:434; GFX12-NEXT: global_store_b64 v0, v[1:2], s[2:3]435; GFX12-NEXT: s_endpgm436 %zext.offset = zext i32 %voffset to i64437 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset438 store i64 %data, ptr addrspace(1) %gep0439 ret void440}441 442define amdgpu_ps void @global_store_saddr_i64_zext_vgpr_offset_neg128(ptr addrspace(1) inreg %sbase, i32 %voffset, i64 %data) {443; GCN-LABEL: global_store_saddr_i64_zext_vgpr_offset_neg128:444; GCN: ; %bb.0:445; GCN-NEXT: global_store_dwordx2 v0, v[1:2], s[2:3] offset:-128446; GCN-NEXT: s_endpgm447;448; GFX11-LABEL: global_store_saddr_i64_zext_vgpr_offset_neg128:449; GFX11: ; %bb.0:450; GFX11-NEXT: global_store_b64 v0, v[1:2], s[2:3] offset:-128451; GFX11-NEXT: s_endpgm452;453; GFX12-LABEL: global_store_saddr_i64_zext_vgpr_offset_neg128:454; GFX12: ; %bb.0:455; GFX12-NEXT: global_store_b64 v0, v[1:2], s[2:3] offset:-128456; GFX12-NEXT: s_endpgm457 %zext.offset = zext i32 %voffset to i64458 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset459 %gep1 = getelementptr inbounds i8, ptr addrspace(1) %gep0, i64 -128460 store i64 %data, ptr addrspace(1) %gep1461 ret void462}463 464define amdgpu_ps void @global_store_saddr_f64_zext_vgpr(ptr addrspace(1) inreg %sbase, i32 %voffset, double %data) {465; GCN-LABEL: global_store_saddr_f64_zext_vgpr:466; GCN: ; %bb.0:467; GCN-NEXT: global_store_dwordx2 v0, v[1:2], s[2:3]468; GCN-NEXT: s_endpgm469;470; GFX11-LABEL: global_store_saddr_f64_zext_vgpr:471; GFX11: ; %bb.0:472; GFX11-NEXT: global_store_b64 v0, v[1:2], s[2:3]473; GFX11-NEXT: s_endpgm474;475; GFX12-LABEL: global_store_saddr_f64_zext_vgpr:476; GFX12: ; %bb.0:477; GFX12-NEXT: global_store_b64 v0, v[1:2], s[2:3]478; GFX12-NEXT: s_endpgm479 %zext.offset = zext i32 %voffset to i64480 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset481 store double %data, ptr addrspace(1) %gep0482 ret void483}484 485define amdgpu_ps void @global_store_saddr_f64_zext_vgpr_offset_neg128(ptr addrspace(1) inreg %sbase, i32 %voffset, double %data) {486; GCN-LABEL: global_store_saddr_f64_zext_vgpr_offset_neg128:487; GCN: ; %bb.0:488; GCN-NEXT: global_store_dwordx2 v0, v[1:2], s[2:3] offset:-128489; GCN-NEXT: s_endpgm490;491; GFX11-LABEL: global_store_saddr_f64_zext_vgpr_offset_neg128:492; GFX11: ; %bb.0:493; GFX11-NEXT: global_store_b64 v0, v[1:2], s[2:3] offset:-128494; GFX11-NEXT: s_endpgm495;496; GFX12-LABEL: global_store_saddr_f64_zext_vgpr_offset_neg128:497; GFX12: ; %bb.0:498; GFX12-NEXT: global_store_b64 v0, v[1:2], s[2:3] offset:-128499; GFX12-NEXT: s_endpgm500 %zext.offset = zext i32 %voffset to i64501 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset502 %gep1 = getelementptr inbounds i8, ptr addrspace(1) %gep0, i64 -128503 store double %data, ptr addrspace(1) %gep1504 ret void505}506 507define amdgpu_ps void @global_store_saddr_v2i32_zext_vgpr(ptr addrspace(1) inreg %sbase, i32 %voffset, <2 x i32> %data) {508; GCN-LABEL: global_store_saddr_v2i32_zext_vgpr:509; GCN: ; %bb.0:510; GCN-NEXT: global_store_dwordx2 v0, v[1:2], s[2:3]511; GCN-NEXT: s_endpgm512;513; GFX11-LABEL: global_store_saddr_v2i32_zext_vgpr:514; GFX11: ; %bb.0:515; GFX11-NEXT: global_store_b64 v0, v[1:2], s[2:3]516; GFX11-NEXT: s_endpgm517;518; GFX12-LABEL: global_store_saddr_v2i32_zext_vgpr:519; GFX12: ; %bb.0:520; GFX12-NEXT: global_store_b64 v0, v[1:2], s[2:3]521; GFX12-NEXT: s_endpgm522 %zext.offset = zext i32 %voffset to i64523 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset524 store <2 x i32> %data, ptr addrspace(1) %gep0525 ret void526}527 528define amdgpu_ps void @global_store_saddr_v2i32_zext_vgpr_offset_neg128(ptr addrspace(1) inreg %sbase, i32 %voffset, <2 x i32> %data) {529; GCN-LABEL: global_store_saddr_v2i32_zext_vgpr_offset_neg128:530; GCN: ; %bb.0:531; GCN-NEXT: global_store_dwordx2 v0, v[1:2], s[2:3] offset:-128532; GCN-NEXT: s_endpgm533;534; GFX11-LABEL: global_store_saddr_v2i32_zext_vgpr_offset_neg128:535; GFX11: ; %bb.0:536; GFX11-NEXT: global_store_b64 v0, v[1:2], s[2:3] offset:-128537; GFX11-NEXT: s_endpgm538;539; GFX12-LABEL: global_store_saddr_v2i32_zext_vgpr_offset_neg128:540; GFX12: ; %bb.0:541; GFX12-NEXT: global_store_b64 v0, v[1:2], s[2:3] offset:-128542; GFX12-NEXT: s_endpgm543 %zext.offset = zext i32 %voffset to i64544 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset545 %gep1 = getelementptr inbounds i8, ptr addrspace(1) %gep0, i64 -128546 store <2 x i32> %data, ptr addrspace(1) %gep1547 ret void548}549 550define amdgpu_ps void @global_store_saddr_v2f32_zext_vgpr(ptr addrspace(1) inreg %sbase, i32 %voffset, <2 x float> %data) {551; GCN-LABEL: global_store_saddr_v2f32_zext_vgpr:552; GCN: ; %bb.0:553; GCN-NEXT: global_store_dwordx2 v0, v[1:2], s[2:3]554; GCN-NEXT: s_endpgm555;556; GFX11-LABEL: global_store_saddr_v2f32_zext_vgpr:557; GFX11: ; %bb.0:558; GFX11-NEXT: global_store_b64 v0, v[1:2], s[2:3]559; GFX11-NEXT: s_endpgm560;561; GFX12-LABEL: global_store_saddr_v2f32_zext_vgpr:562; GFX12: ; %bb.0:563; GFX12-NEXT: global_store_b64 v0, v[1:2], s[2:3]564; GFX12-NEXT: s_endpgm565 %zext.offset = zext i32 %voffset to i64566 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset567 store <2 x float> %data, ptr addrspace(1) %gep0568 ret void569}570 571define amdgpu_ps void @global_store_saddr_v2f32_zext_vgpr_offset_neg128(ptr addrspace(1) inreg %sbase, i32 %voffset, <2 x float> %data) {572; GCN-LABEL: global_store_saddr_v2f32_zext_vgpr_offset_neg128:573; GCN: ; %bb.0:574; GCN-NEXT: global_store_dwordx2 v0, v[1:2], s[2:3] offset:-128575; GCN-NEXT: s_endpgm576;577; GFX11-LABEL: global_store_saddr_v2f32_zext_vgpr_offset_neg128:578; GFX11: ; %bb.0:579; GFX11-NEXT: global_store_b64 v0, v[1:2], s[2:3] offset:-128580; GFX11-NEXT: s_endpgm581;582; GFX12-LABEL: global_store_saddr_v2f32_zext_vgpr_offset_neg128:583; GFX12: ; %bb.0:584; GFX12-NEXT: global_store_b64 v0, v[1:2], s[2:3] offset:-128585; GFX12-NEXT: s_endpgm586 %zext.offset = zext i32 %voffset to i64587 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset588 %gep1 = getelementptr inbounds i8, ptr addrspace(1) %gep0, i64 -128589 store <2 x float> %data, ptr addrspace(1) %gep1590 ret void591}592 593define amdgpu_ps void @global_store_saddr_v4i16_zext_vgpr(ptr addrspace(1) inreg %sbase, i32 %voffset, <4 x i16> %data) {594; GCN-LABEL: global_store_saddr_v4i16_zext_vgpr:595; GCN: ; %bb.0:596; GCN-NEXT: global_store_dwordx2 v0, v[1:2], s[2:3]597; GCN-NEXT: s_endpgm598;599; GFX11-LABEL: global_store_saddr_v4i16_zext_vgpr:600; GFX11: ; %bb.0:601; GFX11-NEXT: global_store_b64 v0, v[1:2], s[2:3]602; GFX11-NEXT: s_endpgm603;604; GFX12-LABEL: global_store_saddr_v4i16_zext_vgpr:605; GFX12: ; %bb.0:606; GFX12-NEXT: global_store_b64 v0, v[1:2], s[2:3]607; GFX12-NEXT: s_endpgm608 %zext.offset = zext i32 %voffset to i64609 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset610 store <4 x i16> %data, ptr addrspace(1) %gep0611 ret void612}613 614define amdgpu_ps void @global_store_saddr_v4i16_zext_vgpr_offset_neg128(ptr addrspace(1) inreg %sbase, i32 %voffset, <4 x i16> %data) {615; GCN-LABEL: global_store_saddr_v4i16_zext_vgpr_offset_neg128:616; GCN: ; %bb.0:617; GCN-NEXT: global_store_dwordx2 v0, v[1:2], s[2:3] offset:-128618; GCN-NEXT: s_endpgm619;620; GFX11-LABEL: global_store_saddr_v4i16_zext_vgpr_offset_neg128:621; GFX11: ; %bb.0:622; GFX11-NEXT: global_store_b64 v0, v[1:2], s[2:3] offset:-128623; GFX11-NEXT: s_endpgm624;625; GFX12-LABEL: global_store_saddr_v4i16_zext_vgpr_offset_neg128:626; GFX12: ; %bb.0:627; GFX12-NEXT: global_store_b64 v0, v[1:2], s[2:3] offset:-128628; GFX12-NEXT: s_endpgm629 %zext.offset = zext i32 %voffset to i64630 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset631 %gep1 = getelementptr inbounds i8, ptr addrspace(1) %gep0, i64 -128632 store <4 x i16> %data, ptr addrspace(1) %gep1633 ret void634}635 636define amdgpu_ps void @global_store_saddr_v4f16_zext_vgpr(ptr addrspace(1) inreg %sbase, i32 %voffset, <4 x half> %data) {637; GCN-LABEL: global_store_saddr_v4f16_zext_vgpr:638; GCN: ; %bb.0:639; GCN-NEXT: global_store_dwordx2 v0, v[1:2], s[2:3]640; GCN-NEXT: s_endpgm641;642; GFX11-LABEL: global_store_saddr_v4f16_zext_vgpr:643; GFX11: ; %bb.0:644; GFX11-NEXT: global_store_b64 v0, v[1:2], s[2:3]645; GFX11-NEXT: s_endpgm646;647; GFX12-LABEL: global_store_saddr_v4f16_zext_vgpr:648; GFX12: ; %bb.0:649; GFX12-NEXT: global_store_b64 v0, v[1:2], s[2:3]650; GFX12-NEXT: s_endpgm651 %zext.offset = zext i32 %voffset to i64652 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset653 store <4 x half> %data, ptr addrspace(1) %gep0654 ret void655}656 657define amdgpu_ps void @global_store_saddr_v4f16_zext_vgpr_offset_neg128(ptr addrspace(1) inreg %sbase, i32 %voffset, <4 x half> %data) {658; GCN-LABEL: global_store_saddr_v4f16_zext_vgpr_offset_neg128:659; GCN: ; %bb.0:660; GCN-NEXT: global_store_dwordx2 v0, v[1:2], s[2:3] offset:-128661; GCN-NEXT: s_endpgm662;663; GFX11-LABEL: global_store_saddr_v4f16_zext_vgpr_offset_neg128:664; GFX11: ; %bb.0:665; GFX11-NEXT: global_store_b64 v0, v[1:2], s[2:3] offset:-128666; GFX11-NEXT: s_endpgm667;668; GFX12-LABEL: global_store_saddr_v4f16_zext_vgpr_offset_neg128:669; GFX12: ; %bb.0:670; GFX12-NEXT: global_store_b64 v0, v[1:2], s[2:3] offset:-128671; GFX12-NEXT: s_endpgm672 %zext.offset = zext i32 %voffset to i64673 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset674 %gep1 = getelementptr inbounds i8, ptr addrspace(1) %gep0, i64 -128675 store <4 x half> %data, ptr addrspace(1) %gep1676 ret void677}678 679define amdgpu_ps void @global_store_saddr_p1_zext_vgpr(ptr addrspace(1) inreg %sbase, i32 %voffset, ptr addrspace(1) %data) {680; GCN-LABEL: global_store_saddr_p1_zext_vgpr:681; GCN: ; %bb.0:682; GCN-NEXT: global_store_dwordx2 v0, v[1:2], s[2:3]683; GCN-NEXT: s_endpgm684;685; GFX11-LABEL: global_store_saddr_p1_zext_vgpr:686; GFX11: ; %bb.0:687; GFX11-NEXT: global_store_b64 v0, v[1:2], s[2:3]688; GFX11-NEXT: s_endpgm689;690; GFX12-LABEL: global_store_saddr_p1_zext_vgpr:691; GFX12: ; %bb.0:692; GFX12-NEXT: global_store_b64 v0, v[1:2], s[2:3]693; GFX12-NEXT: s_endpgm694 %zext.offset = zext i32 %voffset to i64695 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset696 store ptr addrspace(1) %data, ptr addrspace(1) %gep0697 ret void698}699 700define amdgpu_ps void @global_store_saddr_p1_zext_vgpr_offset_neg128(ptr addrspace(1) inreg %sbase, i32 %voffset, ptr addrspace(1) %data) {701; GCN-LABEL: global_store_saddr_p1_zext_vgpr_offset_neg128:702; GCN: ; %bb.0:703; GCN-NEXT: global_store_dwordx2 v0, v[1:2], s[2:3] offset:-128704; GCN-NEXT: s_endpgm705;706; GFX11-LABEL: global_store_saddr_p1_zext_vgpr_offset_neg128:707; GFX11: ; %bb.0:708; GFX11-NEXT: global_store_b64 v0, v[1:2], s[2:3] offset:-128709; GFX11-NEXT: s_endpgm710;711; GFX12-LABEL: global_store_saddr_p1_zext_vgpr_offset_neg128:712; GFX12: ; %bb.0:713; GFX12-NEXT: global_store_b64 v0, v[1:2], s[2:3] offset:-128714; GFX12-NEXT: s_endpgm715 %zext.offset = zext i32 %voffset to i64716 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset717 %gep1 = getelementptr inbounds i8, ptr addrspace(1) %gep0, i64 -128718 store ptr addrspace(1) %data, ptr addrspace(1) %gep1719 ret void720}721 722define amdgpu_ps void @global_store_saddr_v3i32_zext_vgpr(ptr addrspace(1) inreg %sbase, i32 %voffset, <3 x i32> %data) {723; GCN-LABEL: global_store_saddr_v3i32_zext_vgpr:724; GCN: ; %bb.0:725; GCN-NEXT: global_store_dwordx3 v0, v[1:3], s[2:3]726; GCN-NEXT: s_endpgm727;728; GFX11-LABEL: global_store_saddr_v3i32_zext_vgpr:729; GFX11: ; %bb.0:730; GFX11-NEXT: global_store_b96 v0, v[1:3], s[2:3]731; GFX11-NEXT: s_endpgm732;733; GFX12-LABEL: global_store_saddr_v3i32_zext_vgpr:734; GFX12: ; %bb.0:735; GFX12-NEXT: global_store_b96 v0, v[1:3], s[2:3]736; GFX12-NEXT: s_endpgm737 %zext.offset = zext i32 %voffset to i64738 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset739 store <3 x i32> %data, ptr addrspace(1) %gep0740 ret void741}742 743define amdgpu_ps void @global_store_saddr_v3i32_zext_vgpr_offset_neg128(ptr addrspace(1) inreg %sbase, i32 %voffset, <3 x i32> %data) {744; GCN-LABEL: global_store_saddr_v3i32_zext_vgpr_offset_neg128:745; GCN: ; %bb.0:746; GCN-NEXT: global_store_dwordx3 v0, v[1:3], s[2:3] offset:-128747; GCN-NEXT: s_endpgm748;749; GFX11-LABEL: global_store_saddr_v3i32_zext_vgpr_offset_neg128:750; GFX11: ; %bb.0:751; GFX11-NEXT: global_store_b96 v0, v[1:3], s[2:3] offset:-128752; GFX11-NEXT: s_endpgm753;754; GFX12-LABEL: global_store_saddr_v3i32_zext_vgpr_offset_neg128:755; GFX12: ; %bb.0:756; GFX12-NEXT: global_store_b96 v0, v[1:3], s[2:3] offset:-128757; GFX12-NEXT: s_endpgm758 %zext.offset = zext i32 %voffset to i64759 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset760 %gep1 = getelementptr inbounds i8, ptr addrspace(1) %gep0, i64 -128761 store <3 x i32> %data, ptr addrspace(1) %gep1762 ret void763}764 765define amdgpu_ps void @global_store_saddr_v3f32_zext_vgpr(ptr addrspace(1) inreg %sbase, i32 %voffset, <3 x float> %data) {766; GCN-LABEL: global_store_saddr_v3f32_zext_vgpr:767; GCN: ; %bb.0:768; GCN-NEXT: global_store_dwordx3 v0, v[1:3], s[2:3]769; GCN-NEXT: s_endpgm770;771; GFX11-LABEL: global_store_saddr_v3f32_zext_vgpr:772; GFX11: ; %bb.0:773; GFX11-NEXT: global_store_b96 v0, v[1:3], s[2:3]774; GFX11-NEXT: s_endpgm775;776; GFX12-LABEL: global_store_saddr_v3f32_zext_vgpr:777; GFX12: ; %bb.0:778; GFX12-NEXT: global_store_b96 v0, v[1:3], s[2:3]779; GFX12-NEXT: s_endpgm780 %zext.offset = zext i32 %voffset to i64781 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset782 store <3 x float> %data, ptr addrspace(1) %gep0783 ret void784}785 786define amdgpu_ps void @global_store_saddr_v3f32_zext_vgpr_offset_neg128(ptr addrspace(1) inreg %sbase, i32 %voffset, <3 x float> %data) {787; GCN-LABEL: global_store_saddr_v3f32_zext_vgpr_offset_neg128:788; GCN: ; %bb.0:789; GCN-NEXT: global_store_dwordx3 v0, v[1:3], s[2:3] offset:-128790; GCN-NEXT: s_endpgm791;792; GFX11-LABEL: global_store_saddr_v3f32_zext_vgpr_offset_neg128:793; GFX11: ; %bb.0:794; GFX11-NEXT: global_store_b96 v0, v[1:3], s[2:3] offset:-128795; GFX11-NEXT: s_endpgm796;797; GFX12-LABEL: global_store_saddr_v3f32_zext_vgpr_offset_neg128:798; GFX12: ; %bb.0:799; GFX12-NEXT: global_store_b96 v0, v[1:3], s[2:3] offset:-128800; GFX12-NEXT: s_endpgm801 %zext.offset = zext i32 %voffset to i64802 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset803 %gep1 = getelementptr inbounds i8, ptr addrspace(1) %gep0, i64 -128804 store <3 x float> %data, ptr addrspace(1) %gep1805 ret void806}807 808define amdgpu_ps void @global_store_saddr_v6i16_zext_vgpr(ptr addrspace(1) inreg %sbase, i32 %voffset, <6 x i16> %data) {809; GCN-LABEL: global_store_saddr_v6i16_zext_vgpr:810; GCN: ; %bb.0:811; GCN-NEXT: global_store_dwordx3 v0, v[1:3], s[2:3]812; GCN-NEXT: s_endpgm813;814; GFX11-LABEL: global_store_saddr_v6i16_zext_vgpr:815; GFX11: ; %bb.0:816; GFX11-NEXT: global_store_b96 v0, v[1:3], s[2:3]817; GFX11-NEXT: s_endpgm818;819; GFX12-LABEL: global_store_saddr_v6i16_zext_vgpr:820; GFX12: ; %bb.0:821; GFX12-NEXT: global_store_b96 v0, v[1:3], s[2:3]822; GFX12-NEXT: s_endpgm823 %zext.offset = zext i32 %voffset to i64824 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset825 store <6 x i16> %data, ptr addrspace(1) %gep0826 ret void827}828 829define amdgpu_ps void @global_store_saddr_v6i16_zext_vgpr_offset_neg128(ptr addrspace(1) inreg %sbase, i32 %voffset, <6 x i16> %data) {830; GCN-LABEL: global_store_saddr_v6i16_zext_vgpr_offset_neg128:831; GCN: ; %bb.0:832; GCN-NEXT: global_store_dwordx3 v0, v[1:3], s[2:3] offset:-128833; GCN-NEXT: s_endpgm834;835; GFX11-LABEL: global_store_saddr_v6i16_zext_vgpr_offset_neg128:836; GFX11: ; %bb.0:837; GFX11-NEXT: global_store_b96 v0, v[1:3], s[2:3] offset:-128838; GFX11-NEXT: s_endpgm839;840; GFX12-LABEL: global_store_saddr_v6i16_zext_vgpr_offset_neg128:841; GFX12: ; %bb.0:842; GFX12-NEXT: global_store_b96 v0, v[1:3], s[2:3] offset:-128843; GFX12-NEXT: s_endpgm844 %zext.offset = zext i32 %voffset to i64845 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset846 %gep1 = getelementptr inbounds i8, ptr addrspace(1) %gep0, i64 -128847 store <6 x i16> %data, ptr addrspace(1) %gep1848 ret void849}850 851define amdgpu_ps void @global_store_saddr_v6f16_zext_vgpr(ptr addrspace(1) inreg %sbase, i32 %voffset, <6 x half> %data) {852; GCN-LABEL: global_store_saddr_v6f16_zext_vgpr:853; GCN: ; %bb.0:854; GCN-NEXT: global_store_dwordx3 v0, v[1:3], s[2:3]855; GCN-NEXT: s_endpgm856;857; GFX11-LABEL: global_store_saddr_v6f16_zext_vgpr:858; GFX11: ; %bb.0:859; GFX11-NEXT: global_store_b96 v0, v[1:3], s[2:3]860; GFX11-NEXT: s_endpgm861;862; GFX12-LABEL: global_store_saddr_v6f16_zext_vgpr:863; GFX12: ; %bb.0:864; GFX12-NEXT: global_store_b96 v0, v[1:3], s[2:3]865; GFX12-NEXT: s_endpgm866 %zext.offset = zext i32 %voffset to i64867 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset868 store <6 x half> %data, ptr addrspace(1) %gep0869 ret void870}871 872define amdgpu_ps void @global_store_saddr_v6f16_zext_vgpr_offset_neg128(ptr addrspace(1) inreg %sbase, i32 %voffset, <6 x half> %data) {873; GCN-LABEL: global_store_saddr_v6f16_zext_vgpr_offset_neg128:874; GCN: ; %bb.0:875; GCN-NEXT: global_store_dwordx3 v0, v[1:3], s[2:3] offset:-128876; GCN-NEXT: s_endpgm877;878; GFX11-LABEL: global_store_saddr_v6f16_zext_vgpr_offset_neg128:879; GFX11: ; %bb.0:880; GFX11-NEXT: global_store_b96 v0, v[1:3], s[2:3] offset:-128881; GFX11-NEXT: s_endpgm882;883; GFX12-LABEL: global_store_saddr_v6f16_zext_vgpr_offset_neg128:884; GFX12: ; %bb.0:885; GFX12-NEXT: global_store_b96 v0, v[1:3], s[2:3] offset:-128886; GFX12-NEXT: s_endpgm887 %zext.offset = zext i32 %voffset to i64888 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset889 %gep1 = getelementptr inbounds i8, ptr addrspace(1) %gep0, i64 -128890 store <6 x half> %data, ptr addrspace(1) %gep1891 ret void892}893 894define amdgpu_ps void @global_store_saddr_v4i32_zext_vgpr(ptr addrspace(1) inreg %sbase, i32 %voffset, <4 x i32> %data) {895; GCN-LABEL: global_store_saddr_v4i32_zext_vgpr:896; GCN: ; %bb.0:897; GCN-NEXT: global_store_dwordx4 v0, v[1:4], s[2:3]898; GCN-NEXT: s_endpgm899;900; GFX11-LABEL: global_store_saddr_v4i32_zext_vgpr:901; GFX11: ; %bb.0:902; GFX11-NEXT: global_store_b128 v0, v[1:4], s[2:3]903; GFX11-NEXT: s_endpgm904;905; GFX12-LABEL: global_store_saddr_v4i32_zext_vgpr:906; GFX12: ; %bb.0:907; GFX12-NEXT: global_store_b128 v0, v[1:4], s[2:3]908; GFX12-NEXT: s_endpgm909 %zext.offset = zext i32 %voffset to i64910 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset911 store <4 x i32> %data, ptr addrspace(1) %gep0912 ret void913}914 915define amdgpu_ps void @global_store_saddr_v4i32_zext_vgpr_offset_neg128(ptr addrspace(1) inreg %sbase, i32 %voffset, <4 x i32> %data) {916; GCN-LABEL: global_store_saddr_v4i32_zext_vgpr_offset_neg128:917; GCN: ; %bb.0:918; GCN-NEXT: global_store_dwordx4 v0, v[1:4], s[2:3] offset:-128919; GCN-NEXT: s_endpgm920;921; GFX11-LABEL: global_store_saddr_v4i32_zext_vgpr_offset_neg128:922; GFX11: ; %bb.0:923; GFX11-NEXT: global_store_b128 v0, v[1:4], s[2:3] offset:-128924; GFX11-NEXT: s_endpgm925;926; GFX12-LABEL: global_store_saddr_v4i32_zext_vgpr_offset_neg128:927; GFX12: ; %bb.0:928; GFX12-NEXT: global_store_b128 v0, v[1:4], s[2:3] offset:-128929; GFX12-NEXT: s_endpgm930 %zext.offset = zext i32 %voffset to i64931 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset932 %gep1 = getelementptr inbounds i8, ptr addrspace(1) %gep0, i64 -128933 store <4 x i32> %data, ptr addrspace(1) %gep1934 ret void935}936 937define amdgpu_ps void @global_store_saddr_v4f32_zext_vgpr(ptr addrspace(1) inreg %sbase, i32 %voffset, <4 x float> %data) {938; GCN-LABEL: global_store_saddr_v4f32_zext_vgpr:939; GCN: ; %bb.0:940; GCN-NEXT: global_store_dwordx4 v0, v[1:4], s[2:3]941; GCN-NEXT: s_endpgm942;943; GFX11-LABEL: global_store_saddr_v4f32_zext_vgpr:944; GFX11: ; %bb.0:945; GFX11-NEXT: global_store_b128 v0, v[1:4], s[2:3]946; GFX11-NEXT: s_endpgm947;948; GFX12-LABEL: global_store_saddr_v4f32_zext_vgpr:949; GFX12: ; %bb.0:950; GFX12-NEXT: global_store_b128 v0, v[1:4], s[2:3]951; GFX12-NEXT: s_endpgm952 %zext.offset = zext i32 %voffset to i64953 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset954 store <4 x float> %data, ptr addrspace(1) %gep0955 ret void956}957 958define amdgpu_ps void @global_store_saddr_v4f32_zext_vgpr_offset_neg128(ptr addrspace(1) inreg %sbase, i32 %voffset, <4 x float> %data) {959; GCN-LABEL: global_store_saddr_v4f32_zext_vgpr_offset_neg128:960; GCN: ; %bb.0:961; GCN-NEXT: global_store_dwordx4 v0, v[1:4], s[2:3] offset:-128962; GCN-NEXT: s_endpgm963;964; GFX11-LABEL: global_store_saddr_v4f32_zext_vgpr_offset_neg128:965; GFX11: ; %bb.0:966; GFX11-NEXT: global_store_b128 v0, v[1:4], s[2:3] offset:-128967; GFX11-NEXT: s_endpgm968;969; GFX12-LABEL: global_store_saddr_v4f32_zext_vgpr_offset_neg128:970; GFX12: ; %bb.0:971; GFX12-NEXT: global_store_b128 v0, v[1:4], s[2:3] offset:-128972; GFX12-NEXT: s_endpgm973 %zext.offset = zext i32 %voffset to i64974 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset975 %gep1 = getelementptr inbounds i8, ptr addrspace(1) %gep0, i64 -128976 store <4 x float> %data, ptr addrspace(1) %gep1977 ret void978}979 980define amdgpu_ps void @global_store_saddr_v2i64_zext_vgpr(ptr addrspace(1) inreg %sbase, i32 %voffset, <2 x i64> %data) {981; GCN-LABEL: global_store_saddr_v2i64_zext_vgpr:982; GCN: ; %bb.0:983; GCN-NEXT: global_store_dwordx4 v0, v[1:4], s[2:3]984; GCN-NEXT: s_endpgm985;986; GFX11-LABEL: global_store_saddr_v2i64_zext_vgpr:987; GFX11: ; %bb.0:988; GFX11-NEXT: global_store_b128 v0, v[1:4], s[2:3]989; GFX11-NEXT: s_endpgm990;991; GFX12-LABEL: global_store_saddr_v2i64_zext_vgpr:992; GFX12: ; %bb.0:993; GFX12-NEXT: global_store_b128 v0, v[1:4], s[2:3]994; GFX12-NEXT: s_endpgm995 %zext.offset = zext i32 %voffset to i64996 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset997 store <2 x i64> %data, ptr addrspace(1) %gep0998 ret void999}1000 1001define amdgpu_ps void @global_store_saddr_v2i64_zext_vgpr_offset_neg128(ptr addrspace(1) inreg %sbase, i32 %voffset, <2 x i64> %data) {1002; GCN-LABEL: global_store_saddr_v2i64_zext_vgpr_offset_neg128:1003; GCN: ; %bb.0:1004; GCN-NEXT: global_store_dwordx4 v0, v[1:4], s[2:3] offset:-1281005; GCN-NEXT: s_endpgm1006;1007; GFX11-LABEL: global_store_saddr_v2i64_zext_vgpr_offset_neg128:1008; GFX11: ; %bb.0:1009; GFX11-NEXT: global_store_b128 v0, v[1:4], s[2:3] offset:-1281010; GFX11-NEXT: s_endpgm1011;1012; GFX12-LABEL: global_store_saddr_v2i64_zext_vgpr_offset_neg128:1013; GFX12: ; %bb.0:1014; GFX12-NEXT: global_store_b128 v0, v[1:4], s[2:3] offset:-1281015; GFX12-NEXT: s_endpgm1016 %zext.offset = zext i32 %voffset to i641017 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset1018 %gep1 = getelementptr inbounds i8, ptr addrspace(1) %gep0, i64 -1281019 store <2 x i64> %data, ptr addrspace(1) %gep11020 ret void1021}1022 1023define amdgpu_ps void @global_store_saddr_v2f64_zext_vgpr(ptr addrspace(1) inreg %sbase, i32 %voffset, <2 x double> %data) {1024; GCN-LABEL: global_store_saddr_v2f64_zext_vgpr:1025; GCN: ; %bb.0:1026; GCN-NEXT: global_store_dwordx4 v0, v[1:4], s[2:3]1027; GCN-NEXT: s_endpgm1028;1029; GFX11-LABEL: global_store_saddr_v2f64_zext_vgpr:1030; GFX11: ; %bb.0:1031; GFX11-NEXT: global_store_b128 v0, v[1:4], s[2:3]1032; GFX11-NEXT: s_endpgm1033;1034; GFX12-LABEL: global_store_saddr_v2f64_zext_vgpr:1035; GFX12: ; %bb.0:1036; GFX12-NEXT: global_store_b128 v0, v[1:4], s[2:3]1037; GFX12-NEXT: s_endpgm1038 %zext.offset = zext i32 %voffset to i641039 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset1040 store <2 x double> %data, ptr addrspace(1) %gep01041 ret void1042}1043 1044define amdgpu_ps void @global_store_saddr_v2f64_zext_vgpr_offset_neg128(ptr addrspace(1) inreg %sbase, i32 %voffset, <2 x double> %data) {1045; GCN-LABEL: global_store_saddr_v2f64_zext_vgpr_offset_neg128:1046; GCN: ; %bb.0:1047; GCN-NEXT: global_store_dwordx4 v0, v[1:4], s[2:3] offset:-1281048; GCN-NEXT: s_endpgm1049;1050; GFX11-LABEL: global_store_saddr_v2f64_zext_vgpr_offset_neg128:1051; GFX11: ; %bb.0:1052; GFX11-NEXT: global_store_b128 v0, v[1:4], s[2:3] offset:-1281053; GFX11-NEXT: s_endpgm1054;1055; GFX12-LABEL: global_store_saddr_v2f64_zext_vgpr_offset_neg128:1056; GFX12: ; %bb.0:1057; GFX12-NEXT: global_store_b128 v0, v[1:4], s[2:3] offset:-1281058; GFX12-NEXT: s_endpgm1059 %zext.offset = zext i32 %voffset to i641060 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset1061 %gep1 = getelementptr inbounds i8, ptr addrspace(1) %gep0, i64 -1281062 store <2 x double> %data, ptr addrspace(1) %gep11063 ret void1064}1065 1066define amdgpu_ps void @global_store_saddr_v8i16_zext_vgpr(ptr addrspace(1) inreg %sbase, i32 %voffset, <8 x i16> %data) {1067; GCN-LABEL: global_store_saddr_v8i16_zext_vgpr:1068; GCN: ; %bb.0:1069; GCN-NEXT: global_store_dwordx4 v0, v[1:4], s[2:3]1070; GCN-NEXT: s_endpgm1071;1072; GFX11-LABEL: global_store_saddr_v8i16_zext_vgpr:1073; GFX11: ; %bb.0:1074; GFX11-NEXT: global_store_b128 v0, v[1:4], s[2:3]1075; GFX11-NEXT: s_endpgm1076;1077; GFX12-LABEL: global_store_saddr_v8i16_zext_vgpr:1078; GFX12: ; %bb.0:1079; GFX12-NEXT: global_store_b128 v0, v[1:4], s[2:3]1080; GFX12-NEXT: s_endpgm1081 %zext.offset = zext i32 %voffset to i641082 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset1083 store <8 x i16> %data, ptr addrspace(1) %gep01084 ret void1085}1086 1087define amdgpu_ps void @global_store_saddr_v8i16_zext_vgpr_offset_neg128(ptr addrspace(1) inreg %sbase, i32 %voffset, <8 x i16> %data) {1088; GCN-LABEL: global_store_saddr_v8i16_zext_vgpr_offset_neg128:1089; GCN: ; %bb.0:1090; GCN-NEXT: global_store_dwordx4 v0, v[1:4], s[2:3] offset:-1281091; GCN-NEXT: s_endpgm1092;1093; GFX11-LABEL: global_store_saddr_v8i16_zext_vgpr_offset_neg128:1094; GFX11: ; %bb.0:1095; GFX11-NEXT: global_store_b128 v0, v[1:4], s[2:3] offset:-1281096; GFX11-NEXT: s_endpgm1097;1098; GFX12-LABEL: global_store_saddr_v8i16_zext_vgpr_offset_neg128:1099; GFX12: ; %bb.0:1100; GFX12-NEXT: global_store_b128 v0, v[1:4], s[2:3] offset:-1281101; GFX12-NEXT: s_endpgm1102 %zext.offset = zext i32 %voffset to i641103 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset1104 %gep1 = getelementptr inbounds i8, ptr addrspace(1) %gep0, i64 -1281105 store <8 x i16> %data, ptr addrspace(1) %gep11106 ret void1107}1108 1109define amdgpu_ps void @global_store_saddr_v8f16_zext_vgpr(ptr addrspace(1) inreg %sbase, i32 %voffset, <8 x half> %data) {1110; GCN-LABEL: global_store_saddr_v8f16_zext_vgpr:1111; GCN: ; %bb.0:1112; GCN-NEXT: global_store_dwordx4 v0, v[1:4], s[2:3]1113; GCN-NEXT: s_endpgm1114;1115; GFX11-LABEL: global_store_saddr_v8f16_zext_vgpr:1116; GFX11: ; %bb.0:1117; GFX11-NEXT: global_store_b128 v0, v[1:4], s[2:3]1118; GFX11-NEXT: s_endpgm1119;1120; GFX12-LABEL: global_store_saddr_v8f16_zext_vgpr:1121; GFX12: ; %bb.0:1122; GFX12-NEXT: global_store_b128 v0, v[1:4], s[2:3]1123; GFX12-NEXT: s_endpgm1124 %zext.offset = zext i32 %voffset to i641125 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset1126 store <8 x half> %data, ptr addrspace(1) %gep01127 ret void1128}1129 1130define amdgpu_ps void @global_store_saddr_v8f16_zext_vgpr_offset_neg128(ptr addrspace(1) inreg %sbase, i32 %voffset, <8 x half> %data) {1131; GCN-LABEL: global_store_saddr_v8f16_zext_vgpr_offset_neg128:1132; GCN: ; %bb.0:1133; GCN-NEXT: global_store_dwordx4 v0, v[1:4], s[2:3] offset:-1281134; GCN-NEXT: s_endpgm1135;1136; GFX11-LABEL: global_store_saddr_v8f16_zext_vgpr_offset_neg128:1137; GFX11: ; %bb.0:1138; GFX11-NEXT: global_store_b128 v0, v[1:4], s[2:3] offset:-1281139; GFX11-NEXT: s_endpgm1140;1141; GFX12-LABEL: global_store_saddr_v8f16_zext_vgpr_offset_neg128:1142; GFX12: ; %bb.0:1143; GFX12-NEXT: global_store_b128 v0, v[1:4], s[2:3] offset:-1281144; GFX12-NEXT: s_endpgm1145 %zext.offset = zext i32 %voffset to i641146 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset1147 %gep1 = getelementptr inbounds i8, ptr addrspace(1) %gep0, i64 -1281148 store <8 x half> %data, ptr addrspace(1) %gep11149 ret void1150}1151 1152define amdgpu_ps void @global_store_saddr_v2p1_zext_vgpr(ptr addrspace(1) inreg %sbase, i32 %voffset, <2 x ptr addrspace(1)> %data) {1153; GCN-LABEL: global_store_saddr_v2p1_zext_vgpr:1154; GCN: ; %bb.0:1155; GCN-NEXT: global_store_dwordx4 v0, v[1:4], s[2:3]1156; GCN-NEXT: s_endpgm1157;1158; GFX11-LABEL: global_store_saddr_v2p1_zext_vgpr:1159; GFX11: ; %bb.0:1160; GFX11-NEXT: global_store_b128 v0, v[1:4], s[2:3]1161; GFX11-NEXT: s_endpgm1162;1163; GFX12-LABEL: global_store_saddr_v2p1_zext_vgpr:1164; GFX12: ; %bb.0:1165; GFX12-NEXT: global_store_b128 v0, v[1:4], s[2:3]1166; GFX12-NEXT: s_endpgm1167 %zext.offset = zext i32 %voffset to i641168 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset1169 store <2 x ptr addrspace(1)> %data, ptr addrspace(1) %gep01170 ret void1171}1172 1173define amdgpu_ps void @global_store_saddr_v2p1_zext_vgpr_offset_neg128(ptr addrspace(1) inreg %sbase, i32 %voffset, <2 x ptr addrspace(1)> %data) {1174; GCN-LABEL: global_store_saddr_v2p1_zext_vgpr_offset_neg128:1175; GCN: ; %bb.0:1176; GCN-NEXT: global_store_dwordx4 v0, v[1:4], s[2:3] offset:-1281177; GCN-NEXT: s_endpgm1178;1179; GFX11-LABEL: global_store_saddr_v2p1_zext_vgpr_offset_neg128:1180; GFX11: ; %bb.0:1181; GFX11-NEXT: global_store_b128 v0, v[1:4], s[2:3] offset:-1281182; GFX11-NEXT: s_endpgm1183;1184; GFX12-LABEL: global_store_saddr_v2p1_zext_vgpr_offset_neg128:1185; GFX12: ; %bb.0:1186; GFX12-NEXT: global_store_b128 v0, v[1:4], s[2:3] offset:-1281187; GFX12-NEXT: s_endpgm1188 %zext.offset = zext i32 %voffset to i641189 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset1190 %gep1 = getelementptr inbounds i8, ptr addrspace(1) %gep0, i64 -1281191 store <2 x ptr addrspace(1)> %data, ptr addrspace(1) %gep11192 ret void1193}1194 1195define amdgpu_ps void @global_store_saddr_v4p3_zext_vgpr(ptr addrspace(1) inreg %sbase, i32 %voffset, <4 x ptr addrspace(3)> %data) {1196; GCN-LABEL: global_store_saddr_v4p3_zext_vgpr:1197; GCN: ; %bb.0:1198; GCN-NEXT: global_store_dwordx4 v0, v[1:4], s[2:3]1199; GCN-NEXT: s_endpgm1200;1201; GFX11-LABEL: global_store_saddr_v4p3_zext_vgpr:1202; GFX11: ; %bb.0:1203; GFX11-NEXT: global_store_b128 v0, v[1:4], s[2:3]1204; GFX11-NEXT: s_endpgm1205;1206; GFX12-LABEL: global_store_saddr_v4p3_zext_vgpr:1207; GFX12: ; %bb.0:1208; GFX12-NEXT: global_store_b128 v0, v[1:4], s[2:3]1209; GFX12-NEXT: s_endpgm1210 %zext.offset = zext i32 %voffset to i641211 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset1212 store <4 x ptr addrspace(3)> %data, ptr addrspace(1) %gep01213 ret void1214}1215 1216define amdgpu_ps void @global_store_saddr_v4p3_zext_vgpr_offset_neg128(ptr addrspace(1) inreg %sbase, i32 %voffset, <4 x ptr addrspace(3)> %data) {1217; GCN-LABEL: global_store_saddr_v4p3_zext_vgpr_offset_neg128:1218; GCN: ; %bb.0:1219; GCN-NEXT: global_store_dwordx4 v0, v[1:4], s[2:3] offset:-1281220; GCN-NEXT: s_endpgm1221;1222; GFX11-LABEL: global_store_saddr_v4p3_zext_vgpr_offset_neg128:1223; GFX11: ; %bb.0:1224; GFX11-NEXT: global_store_b128 v0, v[1:4], s[2:3] offset:-1281225; GFX11-NEXT: s_endpgm1226;1227; GFX12-LABEL: global_store_saddr_v4p3_zext_vgpr_offset_neg128:1228; GFX12: ; %bb.0:1229; GFX12-NEXT: global_store_b128 v0, v[1:4], s[2:3] offset:-1281230; GFX12-NEXT: s_endpgm1231 %zext.offset = zext i32 %voffset to i641232 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset1233 %gep1 = getelementptr inbounds i8, ptr addrspace(1) %gep0, i64 -1281234 store <4 x ptr addrspace(3)> %data, ptr addrspace(1) %gep11235 ret void1236}1237 1238; --------------------------------------------------------------------------------1239; Atomic store1240; --------------------------------------------------------------------------------1241 1242define amdgpu_ps void @atomic_global_store_saddr_i32_zext_vgpr(ptr addrspace(1) inreg %sbase, i32 %voffset, i32 %data) {1243; GCN-LABEL: atomic_global_store_saddr_i32_zext_vgpr:1244; GCN: ; %bb.0:1245; GCN-NEXT: global_store_dword v0, v1, s[2:3]1246; GCN-NEXT: s_endpgm1247;1248; GFX11-LABEL: atomic_global_store_saddr_i32_zext_vgpr:1249; GFX11: ; %bb.0:1250; GFX11-NEXT: global_store_b32 v0, v1, s[2:3]1251; GFX11-NEXT: s_endpgm1252;1253; GFX12-LABEL: atomic_global_store_saddr_i32_zext_vgpr:1254; GFX12: ; %bb.0:1255; GFX12-NEXT: global_wb scope:SCOPE_SYS1256; GFX12-NEXT: s_wait_storecnt 0x01257; GFX12-NEXT: global_store_b32 v0, v1, s[2:3] scope:SCOPE_SYS1258; GFX12-NEXT: s_endpgm1259 %zext.offset = zext i32 %voffset to i641260 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset1261 store atomic i32 %data, ptr addrspace(1) %gep0 seq_cst, align 41262 ret void1263}1264 1265define amdgpu_ps void @atomic_global_store_saddr_i32_zext_vgpr_offset_neg128(ptr addrspace(1) inreg %sbase, i32 %voffset, i32 %data) {1266; GCN-LABEL: atomic_global_store_saddr_i32_zext_vgpr_offset_neg128:1267; GCN: ; %bb.0:1268; GCN-NEXT: global_store_dword v0, v1, s[2:3] offset:-1281269; GCN-NEXT: s_endpgm1270;1271; GFX11-LABEL: atomic_global_store_saddr_i32_zext_vgpr_offset_neg128:1272; GFX11: ; %bb.0:1273; GFX11-NEXT: global_store_b32 v0, v1, s[2:3] offset:-1281274; GFX11-NEXT: s_endpgm1275;1276; GFX12-LABEL: atomic_global_store_saddr_i32_zext_vgpr_offset_neg128:1277; GFX12: ; %bb.0:1278; GFX12-NEXT: global_wb scope:SCOPE_SYS1279; GFX12-NEXT: s_wait_storecnt 0x01280; GFX12-NEXT: global_store_b32 v0, v1, s[2:3] offset:-128 scope:SCOPE_SYS1281; GFX12-NEXT: s_endpgm1282 %zext.offset = zext i32 %voffset to i641283 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset1284 %gep1 = getelementptr inbounds i8, ptr addrspace(1) %gep0, i64 -1281285 store atomic i32 %data, ptr addrspace(1) %gep1 seq_cst, align 41286 ret void1287}1288 1289define amdgpu_ps void @atomic_global_store_saddr_i64_zext_vgpr(ptr addrspace(1) inreg %sbase, i32 %voffset, i64 %data) {1290; GCN-LABEL: atomic_global_store_saddr_i64_zext_vgpr:1291; GCN: ; %bb.0:1292; GCN-NEXT: global_store_dwordx2 v0, v[1:2], s[2:3]1293; GCN-NEXT: s_endpgm1294;1295; GFX11-LABEL: atomic_global_store_saddr_i64_zext_vgpr:1296; GFX11: ; %bb.0:1297; GFX11-NEXT: global_store_b64 v0, v[1:2], s[2:3]1298; GFX11-NEXT: s_endpgm1299;1300; GFX12-LABEL: atomic_global_store_saddr_i64_zext_vgpr:1301; GFX12: ; %bb.0:1302; GFX12-NEXT: global_wb scope:SCOPE_SYS1303; GFX12-NEXT: s_wait_storecnt 0x01304; GFX12-NEXT: global_store_b64 v0, v[1:2], s[2:3] scope:SCOPE_SYS1305; GFX12-NEXT: s_endpgm1306 %zext.offset = zext i32 %voffset to i641307 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset1308 store atomic i64 %data, ptr addrspace(1) %gep0 seq_cst, align 81309 ret void1310}1311 1312define amdgpu_ps void @atomic_global_store_saddr_i64_zext_vgpr_offset_neg128(ptr addrspace(1) inreg %sbase, i32 %voffset, i64 %data) {1313; GCN-LABEL: atomic_global_store_saddr_i64_zext_vgpr_offset_neg128:1314; GCN: ; %bb.0:1315; GCN-NEXT: global_store_dwordx2 v0, v[1:2], s[2:3] offset:-1281316; GCN-NEXT: s_endpgm1317;1318; GFX11-LABEL: atomic_global_store_saddr_i64_zext_vgpr_offset_neg128:1319; GFX11: ; %bb.0:1320; GFX11-NEXT: global_store_b64 v0, v[1:2], s[2:3] offset:-1281321; GFX11-NEXT: s_endpgm1322;1323; GFX12-LABEL: atomic_global_store_saddr_i64_zext_vgpr_offset_neg128:1324; GFX12: ; %bb.0:1325; GFX12-NEXT: global_wb scope:SCOPE_SYS1326; GFX12-NEXT: s_wait_storecnt 0x01327; GFX12-NEXT: global_store_b64 v0, v[1:2], s[2:3] offset:-128 scope:SCOPE_SYS1328; GFX12-NEXT: s_endpgm1329 %zext.offset = zext i32 %voffset to i641330 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset1331 %gep1 = getelementptr inbounds i8, ptr addrspace(1) %gep0, i64 -1281332 store atomic i64 %data, ptr addrspace(1) %gep1 seq_cst, align 81333 ret void1334}1335 1336; --------------------------------------------------------------------------------1337; D16 HI store (hi 16)1338; --------------------------------------------------------------------------------1339 1340define amdgpu_ps void @global_store_saddr_i16_d16hi_zext_vgpr(ptr addrspace(1) inreg %sbase, i32 %voffset, <2 x i16> %data) {1341; GCN-LABEL: global_store_saddr_i16_d16hi_zext_vgpr:1342; GCN: ; %bb.0:1343; GCN-NEXT: global_store_short_d16_hi v0, v1, s[2:3]1344; GCN-NEXT: s_endpgm1345;1346; GFX11-LABEL: global_store_saddr_i16_d16hi_zext_vgpr:1347; GFX11: ; %bb.0:1348; GFX11-NEXT: global_store_d16_hi_b16 v0, v1, s[2:3]1349; GFX11-NEXT: s_endpgm1350;1351; GFX12-LABEL: global_store_saddr_i16_d16hi_zext_vgpr:1352; GFX12: ; %bb.0:1353; GFX12-NEXT: global_store_d16_hi_b16 v0, v1, s[2:3]1354; GFX12-NEXT: s_endpgm1355 %zext.offset = zext i32 %voffset to i641356 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset1357 %data.hi = extractelement <2 x i16> %data, i32 11358 store i16 %data.hi, ptr addrspace(1) %gep01359 ret void1360}1361 1362define amdgpu_ps void @global_store_saddr_i16_d16hi_zext_vgpr_offset_neg128(ptr addrspace(1) inreg %sbase, i32 %voffset, <2 x i16> %data) {1363; GCN-LABEL: global_store_saddr_i16_d16hi_zext_vgpr_offset_neg128:1364; GCN: ; %bb.0:1365; GCN-NEXT: global_store_short_d16_hi v0, v1, s[2:3] offset:-1281366; GCN-NEXT: s_endpgm1367;1368; GFX11-LABEL: global_store_saddr_i16_d16hi_zext_vgpr_offset_neg128:1369; GFX11: ; %bb.0:1370; GFX11-NEXT: global_store_d16_hi_b16 v0, v1, s[2:3] offset:-1281371; GFX11-NEXT: s_endpgm1372;1373; GFX12-LABEL: global_store_saddr_i16_d16hi_zext_vgpr_offset_neg128:1374; GFX12: ; %bb.0:1375; GFX12-NEXT: global_store_d16_hi_b16 v0, v1, s[2:3] offset:-1281376; GFX12-NEXT: s_endpgm1377 %zext.offset = zext i32 %voffset to i641378 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset1379 %gep1 = getelementptr inbounds i8, ptr addrspace(1) %gep0, i64 -1281380 %data.hi = extractelement <2 x i16> %data, i32 11381 store i16 %data.hi, ptr addrspace(1) %gep11382 ret void1383}1384 1385define amdgpu_ps void @global_store_saddr_i16_d16hi_trunci8_zext_vgpr(ptr addrspace(1) inreg %sbase, i32 %voffset, <2 x i16> %data) {1386; GCN-LABEL: global_store_saddr_i16_d16hi_trunci8_zext_vgpr:1387; GCN: ; %bb.0:1388; GCN-NEXT: global_store_byte_d16_hi v0, v1, s[2:3]1389; GCN-NEXT: s_endpgm1390;1391; GFX11-LABEL: global_store_saddr_i16_d16hi_trunci8_zext_vgpr:1392; GFX11: ; %bb.0:1393; GFX11-NEXT: global_store_d16_hi_b8 v0, v1, s[2:3]1394; GFX11-NEXT: s_endpgm1395;1396; GFX12-LABEL: global_store_saddr_i16_d16hi_trunci8_zext_vgpr:1397; GFX12: ; %bb.0:1398; GFX12-NEXT: global_store_d16_hi_b8 v0, v1, s[2:3]1399; GFX12-NEXT: s_endpgm1400 %zext.offset = zext i32 %voffset to i641401 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset1402 %data.hi = extractelement <2 x i16> %data, i32 11403 %data.hi.trunc = trunc i16 %data.hi to i81404 store i8 %data.hi.trunc, ptr addrspace(1) %gep01405 ret void1406}1407 1408define amdgpu_ps void @global_store_saddr_i16_d16hi_trunci8_zext_vgpr_offset_neg128(ptr addrspace(1) inreg %sbase, i32 %voffset, <2 x i16> %data) {1409; GCN-LABEL: global_store_saddr_i16_d16hi_trunci8_zext_vgpr_offset_neg128:1410; GCN: ; %bb.0:1411; GCN-NEXT: global_store_byte_d16_hi v0, v1, s[2:3] offset:-1281412; GCN-NEXT: s_endpgm1413;1414; GFX11-LABEL: global_store_saddr_i16_d16hi_trunci8_zext_vgpr_offset_neg128:1415; GFX11: ; %bb.0:1416; GFX11-NEXT: global_store_d16_hi_b8 v0, v1, s[2:3] offset:-1281417; GFX11-NEXT: s_endpgm1418;1419; GFX12-LABEL: global_store_saddr_i16_d16hi_trunci8_zext_vgpr_offset_neg128:1420; GFX12: ; %bb.0:1421; GFX12-NEXT: global_store_d16_hi_b8 v0, v1, s[2:3] offset:-1281422; GFX12-NEXT: s_endpgm1423 %zext.offset = zext i32 %voffset to i641424 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset1425 %gep1 = getelementptr inbounds i8, ptr addrspace(1) %gep0, i64 -1281426 %data.hi = extractelement <2 x i16> %data, i32 11427 %data.hi.trunc = trunc i16 %data.hi to i81428 store i8 %data.hi.trunc, ptr addrspace(1) %gep11429 ret void1430}1431