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1; RUN: llc -mtriple amdgcn--amdhsa -mcpu=fiji -amdgpu-scalarize-global-loads=true < %s | FileCheck %s2 3; uniform loads4; CHECK-LABEL: @uniform_load5; CHECK: s_load_dwordx46; CHECK-NOT: flat_load_dword7 8define amdgpu_kernel void @uniform_load(ptr addrspace(1) %arg, [8 x i32], ptr addrspace(1) %arg1) {9bb:10 %tmp2 = load float, ptr addrspace(1) %arg, align 4, !tbaa !811 %tmp3 = fadd float %tmp2, 0.000000e+0012 %tmp4 = getelementptr inbounds float, ptr addrspace(1) %arg, i64 113 %tmp5 = load float, ptr addrspace(1) %tmp4, align 4, !tbaa !814 %tmp6 = fadd float %tmp3, %tmp515 %tmp7 = getelementptr inbounds float, ptr addrspace(1) %arg, i64 216 %tmp8 = load float, ptr addrspace(1) %tmp7, align 4, !tbaa !817 %tmp9 = fadd float %tmp6, %tmp818 %tmp10 = getelementptr inbounds float, ptr addrspace(1) %arg, i64 319 %tmp11 = load float, ptr addrspace(1) %tmp10, align 4, !tbaa !820 %tmp12 = fadd float %tmp9, %tmp1121 %tmp13 = getelementptr inbounds float, ptr addrspace(1) %arg122 store float %tmp12, ptr addrspace(1) %tmp13, align 4, !tbaa !823 ret void24}25 26; uniform loads before and after an aliasing store27; CHECK-LABEL: @uniform_load_store_load28; CHECK: s_load_dwordx429; CHECK: s_load_dword30; CHECK: flat_store_dword31; CHECK: flat_load_dword32; CHECK: flat_store_dword33 34define amdgpu_kernel void @uniform_load_store_load(ptr addrspace(1) %arg0, ptr addrspace(1) %arg1) {35bb:36 %tmp2 = load float, ptr addrspace(1) %arg0, !tbaa !837 store float %tmp2, ptr addrspace(1) %arg1, !tbaa !838 %tmp3 = load float, ptr addrspace(1) %arg0, !tbaa !839 store float %tmp3, ptr addrspace(1) %arg1, !tbaa !840 ret void41}42 43; non-uniform loads44; CHECK-LABEL: @non-uniform_load45; CHECK: flat_load_dword46; CHECK-NOT: s_load_dwordx447 48define amdgpu_kernel void @non-uniform_load(ptr addrspace(1) %arg, [8 x i32], ptr addrspace(1) %arg1) #0 {49bb:50 %tmp = call i32 @llvm.amdgcn.workitem.id.x() #151 %tmp2 = getelementptr inbounds float, ptr addrspace(1) %arg, i32 %tmp52 %tmp3 = load float, ptr addrspace(1) %tmp2, align 4, !tbaa !853 %tmp4 = fadd float %tmp3, 0.000000e+0054 %tmp5 = add i32 %tmp, 155 %tmp6 = getelementptr inbounds float, ptr addrspace(1) %arg, i32 %tmp556 %tmp7 = load float, ptr addrspace(1) %tmp6, align 4, !tbaa !857 %tmp8 = fadd float %tmp4, %tmp758 %tmp9 = add i32 %tmp, 259 %tmp10 = getelementptr inbounds float, ptr addrspace(1) %arg, i32 %tmp960 %tmp11 = load float, ptr addrspace(1) %tmp10, align 4, !tbaa !861 %tmp12 = fadd float %tmp8, %tmp1162 %tmp13 = add i32 %tmp, 363 %tmp14 = getelementptr inbounds float, ptr addrspace(1) %arg, i32 %tmp1364 %tmp15 = load float, ptr addrspace(1) %tmp14, align 4, !tbaa !865 %tmp16 = fadd float %tmp12, %tmp1566 %tmp17 = getelementptr inbounds float, ptr addrspace(1) %arg1, i32 %tmp67 store float %tmp16, ptr addrspace(1) %tmp17, align 4, !tbaa !868 ret void69}70 71 72; uniform load dominated by no-alias store - scalarize73; CHECK-LABEL: @no_memdep_alias_arg74; CHECK: s_load_dwordx2 s[[[IN_LO:[0-9]+]]:[[IN_HI:[0-9]+]]], s[8:9], 0x075; CHECK: s_load_dword [[SVAL:s[0-9]+]], s[[[IN_LO]]:[[IN_HI]]], 0x076; CHECK: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[SVAL]]77; CHECK: flat_store_dword v[{{[0-9]+:[0-9]+}}], [[VVAL]]78 79define amdgpu_kernel void @no_memdep_alias_arg(ptr addrspace(1) noalias %in, [8 x i32], ptr addrspace(1) %out0, [8 x i32], ptr addrspace(1) %out1) {80 store i32 0, ptr addrspace(1) %out081 %val = load i32, ptr addrspace(1) %in82 store i32 %val, ptr addrspace(1) %out183 ret void84}85 86; uniform load dominated by alias store - vector87; CHECK-LABEL: {{^}}memdep:88; CHECK: flat_store_dword89; CHECK: flat_load_dword [[VVAL:v[0-9]+]]90; CHECK: flat_store_dword v[{{[0-9]+:[0-9]+}}], [[VVAL]]91define amdgpu_kernel void @memdep(ptr addrspace(1) %in, [8 x i32], ptr addrspace(1) %out0, [8 x i32], ptr addrspace(1) %out1) {92 store i32 0, ptr addrspace(1) %out093 %val = load i32, ptr addrspace(1) %in94 store i32 %val, ptr addrspace(1) %out195 ret void96}97 98; uniform load from global array99; CHECK-LABEL: @global_array100; CHECK: s_getpc_b64 [[GET_PC:s\[[0-9]+:[0-9]+\]]]101; CHECK-DAG: s_load_dwordx2 [[A_ADDR:s\[[0-9]+:[0-9]+\]]], [[GET_PC]], 0x0102; CHECK-DAG: s_load_dwordx2 [[A_ADDR1:s\[[0-9]+:[0-9]+\]]], [[A_ADDR]], 0x0103; CHECK-DAG: s_load_dwordx2 [[OUT:s\[[0-9]+:[0-9]+\]]], s[8:9], 0x0104; CHECK-DAG: s_load_dword [[SVAL:s[0-9]+]], [[A_ADDR1]], 0x0105; CHECK: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[SVAL]]106; CHECK: flat_store_dword v[{{[0-9]+:[0-9]+}}], [[VVAL]]107@A = common local_unnamed_addr addrspace(1) global ptr addrspace(1) null, align 4108 109define amdgpu_kernel void @global_array(ptr addrspace(1) nocapture %out) {110entry:111 %load0 = load ptr addrspace(1), ptr addrspace(1) @A, align 4112 %load1 = load i32, ptr addrspace(1) %load0, align 4113 store i32 %load1, ptr addrspace(1) %out, align 4114 ret void115}116 117 118; uniform load from global array dominated by alias store119; CHECK-LABEL: @global_array_alias_store120; CHECK: flat_store_dword121; CHECK: v_mov_b32_e32 v[[ADDR_LO:[0-9]+]], s{{[0-9]+}}122; CHECK: v_mov_b32_e32 v[[ADDR_HI:[0-9]+]], s{{[0-9]+}}123; CHECK: flat_load_dwordx2 [[A_ADDR:v\[[0-9]+:[0-9]+\]]], v[[[ADDR_LO]]:[[ADDR_HI]]]124; CHECK: flat_load_dword [[VVAL:v[0-9]+]], [[A_ADDR]]125; CHECK: flat_store_dword v[{{[0-9]+:[0-9]+}}], [[VVAL]]126define amdgpu_kernel void @global_array_alias_store(ptr addrspace(1) nocapture %out, [8 x i32], i32 %n) {127entry:128 %gep = getelementptr i32, ptr addrspace(1) %out, i32 %n129 store i32 12, ptr addrspace(1) %gep130 %load0 = load ptr addrspace(1), ptr addrspace(1) @A, align 4131 %load1 = load i32, ptr addrspace(1) %load0, align 4132 store i32 %load1, ptr addrspace(1) %out, align 4133 ret void134}135 136 137declare i32 @llvm.amdgcn.workitem.id.x() #1138 139attributes #1 = { nounwind readnone }140 141!8 = !{!9, !9, i64 0}142!9 = !{!"float", !10, i64 0}143!10 = !{!"omnipotent char", !11, i64 0}144!11 = !{!"Simple C/C++ TBAA"}145