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1; RUN: llc -mtriple amdgcn--amdhsa -mcpu=fiji -amdgpu-scalarize-global-loads=true < %s | FileCheck %s2 3; CHECK-LABEL: %bb224 5; Load from %arg has alias store in Loop6 7; CHECK: flat_load_dword8 9; #####################################################################10 11; Load from %arg1 has no-alias store in Loop - arg1[i+1] never alias arg1[i]12; However, our analysis cannot detect this.13 14; CHECK: flat_load_dword15 16; #####################################################################17 18; CHECK-LABEL: %bb1119 20; Load from %arg in a Loop body has alias store21 22; CHECK: flat_load_dword23 24; CHECK-LABEL: %bb2025 26; CHECK: flat_store_dword27 28define amdgpu_kernel void @cfg(ptr addrspace(1) nocapture readonly %arg, ptr addrspace(1) nocapture %arg1, i32 %arg2) #0 {29bb:30 %tmp = sext i32 %arg2 to i6431 %tmp3 = getelementptr inbounds i32, ptr addrspace(1) %arg, i64 %tmp32 %tmp4 = load i32, ptr addrspace(1) %tmp3, align 4, !tbaa !033 %tmp5 = icmp sgt i32 %tmp4, 034 br i1 %tmp5, label %bb6, label %bb835 36bb6: ; preds = %bb37 br label %bb1138 39bb7: ; preds = %bb2240 br label %bb841 42bb8: ; preds = %bb7, %bb43 %tmp9 = phi i32 [ 0, %bb ], [ %tmp30, %bb7 ]44 %tmp10 = getelementptr inbounds i32, ptr addrspace(1) %arg1, i64 %tmp45 store i32 %tmp9, ptr addrspace(1) %tmp10, align 4, !tbaa !046 ret void47 48bb11: ; preds = %bb22, %bb649 %tmp12 = phi i32 [ %tmp30, %bb22 ], [ 0, %bb6 ]50 %tmp13 = phi i32 [ %tmp25, %bb22 ], [ 0, %bb6 ]51 %tmp14 = srem i32 %tmp13, %arg252 %tmp15 = sext i32 %tmp14 to i6453 %tmp16 = getelementptr inbounds i32, ptr addrspace(1) %arg, i64 %tmp1554 %tmp17 = load i32, ptr addrspace(1) %tmp16, align 4, !tbaa !055 %tmp18 = icmp sgt i32 %tmp17, 10056 %tmp19 = sext i32 %tmp13 to i6457 br i1 %tmp18, label %bb20, label %bb2258 59bb20: ; preds = %bb1160 %tmp21 = getelementptr inbounds i32, ptr addrspace(1) %arg1, i64 %tmp1961 store i32 0, ptr addrspace(1) %tmp21, align 4, !tbaa !062 br label %bb2263 64bb22: ; preds = %bb20, %bb1165 %tmp23 = getelementptr inbounds i32, ptr addrspace(1) %arg, i64 %tmp1966 %tmp24 = load i32, ptr addrspace(1) %tmp23, align 4, !tbaa !067 %tmp25 = add nuw nsw i32 %tmp13, 168 %tmp26 = sext i32 %tmp25 to i6469 %tmp27 = getelementptr inbounds i32, ptr addrspace(1) %arg1, i64 %tmp2670 %tmp28 = load i32, ptr addrspace(1) %tmp27, align 4, !tbaa !071 %tmp29 = add i32 %tmp24, %tmp1272 %tmp30 = add i32 %tmp29, %tmp2873 %tmp31 = icmp eq i32 %tmp25, %tmp474 br i1 %tmp31, label %bb7, label %bb1175}76 77; one more test to ensure that aliasing store after the load78; is considered clobbering if load parent block is the same79; as a loop header block.80 81; CHECK-LABEL: %bb182 83; Load from %arg has alias store that is after the load84; but is considered clobbering because of the loop.85 86; CHECK: flat_load_dword87 88define amdgpu_kernel void @cfg_selfloop(ptr addrspace(1) nocapture readonly %arg, ptr addrspace(1) nocapture %arg1, i32 %arg2) #0 {89bb:90 br label %bb191 92bb2:93 ret void94 95bb1:96 %tmp13 = phi i32 [ %tmp25, %bb1 ], [ 0, %bb ]97 %tmp14 = srem i32 %tmp13, %arg298 %tmp15 = sext i32 %tmp14 to i6499 %tmp16 = getelementptr inbounds i32, ptr addrspace(1) %arg, i64 %tmp15100 %tmp17 = load i32, ptr addrspace(1) %tmp16, align 4, !tbaa !0101 %tmp19 = sext i32 %tmp13 to i64102 %tmp21 = getelementptr inbounds i32, ptr addrspace(1) %arg1, i64 %tmp19103 store i32 %tmp17, ptr addrspace(1) %tmp21, align 4, !tbaa !0104 %tmp25 = add nuw nsw i32 %tmp13, 1105 %tmp31 = icmp eq i32 %tmp25, 100106 br i1 %tmp31, label %bb2, label %bb1107}108 109 110attributes #0 = { "target-cpu"="fiji" }111 112!0 = !{!1, !1, i64 0}113!1 = !{!"int", !2, i64 0}114!2 = !{!"omnipotent char", !3, i64 0}115!3 = !{!"Simple C/C++ TBAA"}116