41 lines · plain
1# RUN: llc -mtriple=amdgcn -mcpu=gfx1030 -verify-machineinstrs -run-pass=greedy -stress-regalloc=2 %s -o - | FileCheck -check-prefix=GCN %s2 3# Make sure there's no verifier error after register allocation4# introduces vreg defs when the MIR parser infers SSA.5 6---7name: ra_introduces_vreg_def8tracksRegLiveness: true9machineFunctionInfo:10 scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'11 frameOffsetReg: '$sgpr33'12 stackPtrOffsetReg: '$sgpr32'13 argumentInfo:14 privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' }15body: |16 ; GCN-LABEL: name: ra_introduces_vreg_def17 ; GCN: [[COPY_V0:%[0-9]+]]:vgpr_32 = COPY $vgpr018 ; GCN: [[COPY_V1:%[0-9]+]]:vgpr_32 = COPY $vgpr119 bb.0:20 liveins: $vgpr0, $vgpr121 %0:vgpr_32 = COPY $vgpr022 %1:vgpr_32 = COPY $vgpr123 S_NOP 0, implicit %024 S_NOP 0, implicit %125 26 bb.1:27 $vgpr0 = V_MOV_B32_e32 0, implicit $exec28 $vgpr1 = V_MOV_B32_e32 1, implicit $exec29 S_NOP 0, implicit %030 S_NOP 0, implicit %131 32 bb.2:33 S_CBRANCH_EXECNZ %bb.1, implicit $exec34 35 bb.3:36 $exec_lo = S_OR_B32 $exec_lo, undef $sgpr4, implicit-def $scc37 $vgpr0 = COPY %038 S_SETPC_B64_return undef $sgpr30_sgpr31, implicit $vgpr039 40...41