255 lines · plain
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=greedy -verify-machineinstrs -o - %s |FileCheck %s3 4# Testcase is limited to 24 VGPRs. Only a maximum of 6 vreg_128s can5# be allocated at the same time.6 7# This testcase is intended to stress the heuristic in8# RAGreedy::enqueue to switch from local to global. If an interval is9# in one basic block, the usual preference is to allocate registers in10# instruction order. If the estimated live range length is more than11# twice the number of registers in the class, the global heuristic is12# used which increases the priority of the longest live ranges. By13# accounting for the number of reserved registers in vreg_128, the14# heuristic changes end up avoiding a spill of %0.15 16--- |17 18 define void @use_global_assign() #0 {19 entry:20 unreachable21 }22 23 attributes #0 = { "amdgpu-waves-per-eu"="10,10" }24 25...26---27name: use_global_assign28tracksRegLiveness: true29registers:30 - { id: 0, class: vreg_128, preferred-register: '%0' }31 - { id: 1, class: vreg_128, preferred-register: '%0' }32 - { id: 2, class: vreg_128, preferred-register: '%0' }33 - { id: 3, class: vreg_128, preferred-register: '%0' }34 - { id: 4, class: vreg_128, preferred-register: '%0' }35 - { id: 5, class: vreg_128, preferred-register: '%0' }36 - { id: 6, class: vreg_128, preferred-register: '%0' }37 - { id: 7, class: vreg_128, preferred-register: '%0' }38 - { id: 8, class: vreg_128, preferred-register: '%0' }39 - { id: 9, class: vreg_128, preferred-register: '%0' }40 - { id: 10, class: vreg_128, preferred-register: '%0' }41 - { id: 11, class: vreg_128, preferred-register: '%0' }42 - { id: 12, class: vreg_128, preferred-register: '%0' }43 - { id: 13, class: vreg_128, preferred-register: '%0' }44 - { id: 14, class: vreg_128, preferred-register: '%0' }45 - { id: 15, class: vreg_128, preferred-register: '%0' }46 47machineFunctionInfo:48 waveLimiter: true49 scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'50 stackPtrOffsetReg: '$sgpr32'51body: |52 ; CHECK-LABEL: name: use_global_assign53 ; CHECK: bb.0:54 ; CHECK-NEXT: successors: %bb.1(0x80000000)55 ; CHECK-NEXT: {{ $}}56 ; CHECK-NEXT: S_NOP 0, implicit-def %057 ; CHECK-NEXT: S_NOP 0, implicit-def %1858 ; CHECK-NEXT: SI_SPILL_V128_SAVE %18, %stack.0, $sgpr32, 0, implicit $exec :: (store (s128) into %stack.0, align 4, addrspace 5)59 ; CHECK-NEXT: S_NOP 0, implicit-def %3560 ; CHECK-NEXT: S_NOP 0, implicit-def %2761 ; CHECK-NEXT: S_NOP 0, implicit-def %2962 ; CHECK-NEXT: S_NOP 0, implicit-def %3163 ; CHECK-NEXT: {{ $}}64 ; CHECK-NEXT: bb.1:65 ; CHECK-NEXT: successors: %bb.2(0x80000000)66 ; CHECK-NEXT: {{ $}}67 ; CHECK-NEXT: S_NOP 0, implicit %3168 ; CHECK-NEXT: S_NOP 0, implicit %2969 ; CHECK-NEXT: S_NOP 0, implicit %2770 ; CHECK-NEXT: S_NOP 0, implicit %3571 ; CHECK-NEXT: SI_SPILL_V128_SAVE %35, %stack.1, $sgpr32, 0, implicit $exec :: (store (s128) into %stack.1, align 4, addrspace 5)72 ; CHECK-NEXT: [[SI_SPILL_V128_RESTORE:%[0-9]+]]:vreg_128 = SI_SPILL_V128_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load (s128) from %stack.0, align 4, addrspace 5)73 ; CHECK-NEXT: S_NOP 0, implicit [[SI_SPILL_V128_RESTORE]]74 ; CHECK-NEXT: S_NOP 0, implicit %075 ; CHECK-NEXT: S_NOP 0, implicit-def %1076 ; CHECK-NEXT: S_NOP 077 ; CHECK-NEXT: S_NOP 078 ; CHECK-NEXT: S_NOP 079 ; CHECK-NEXT: S_NOP 080 ; CHECK-NEXT: S_NOP 081 ; CHECK-NEXT: S_NOP 082 ; CHECK-NEXT: S_NOP 083 ; CHECK-NEXT: S_NOP 0, implicit %084 ; CHECK-NEXT: S_NOP 0, implicit-def %3385 ; CHECK-NEXT: SI_SPILL_V128_SAVE %33, %stack.2, $sgpr32, 0, implicit $exec :: (store (s128) into %stack.2, align 4, addrspace 5)86 ; CHECK-NEXT: S_NOP 0, implicit %1087 ; CHECK-NEXT: S_NOP 088 ; CHECK-NEXT: S_NOP 089 ; CHECK-NEXT: S_NOP 090 ; CHECK-NEXT: S_NOP 091 ; CHECK-NEXT: S_NOP 092 ; CHECK-NEXT: S_NOP 093 ; CHECK-NEXT: S_NOP 094 ; CHECK-NEXT: S_NOP 095 ; CHECK-NEXT: S_NOP 096 ; CHECK-NEXT: S_NOP 097 ; CHECK-NEXT: S_NOP 0, implicit-def %4098 ; CHECK-NEXT: SI_SPILL_V128_SAVE %40, %stack.4, $sgpr32, 0, implicit $exec :: (store (s128) into %stack.4, align 4, addrspace 5)99 ; CHECK-NEXT: S_NOP 0, implicit %33100 ; CHECK-NEXT: S_NOP 0101 ; CHECK-NEXT: S_NOP 0102 ; CHECK-NEXT: S_NOP 0103 ; CHECK-NEXT: S_NOP 0104 ; CHECK-NEXT: S_NOP 0105 ; CHECK-NEXT: S_NOP 0106 ; CHECK-NEXT: S_NOP 0107 ; CHECK-NEXT: S_NOP 0108 ; CHECK-NEXT: S_NOP 0109 ; CHECK-NEXT: S_NOP 0110 ; CHECK-NEXT: S_NOP 0111 ; CHECK-NEXT: S_NOP 0112 ; CHECK-NEXT: S_NOP 0113 ; CHECK-NEXT: S_NOP 0114 ; CHECK-NEXT: S_NOP 0, implicit-def %42115 ; CHECK-NEXT: SI_SPILL_V128_SAVE %42, %stack.3, $sgpr32, 0, implicit $exec :: (store (s128) into %stack.3, align 4, addrspace 5)116 ; CHECK-NEXT: S_NOP 0, implicit %40117 ; CHECK-NEXT: S_NOP 0118 ; CHECK-NEXT: S_NOP 0119 ; CHECK-NEXT: S_NOP 0120 ; CHECK-NEXT: S_NOP 0121 ; CHECK-NEXT: S_NOP 0122 ; CHECK-NEXT: S_NOP 0123 ; CHECK-NEXT: S_NOP 0124 ; CHECK-NEXT: S_NOP 0125 ; CHECK-NEXT: S_NOP 0126 ; CHECK-NEXT: S_NOP 0127 ; CHECK-NEXT: S_NOP 0128 ; CHECK-NEXT: S_NOP 0129 ; CHECK-NEXT: S_NOP 0130 ; CHECK-NEXT: S_NOP 0131 ; CHECK-NEXT: S_NOP 0132 ; CHECK-NEXT: S_NOP 0133 ; CHECK-NEXT: S_NOP 0134 ; CHECK-NEXT: S_NOP 0135 ; CHECK-NEXT: S_NOP 0136 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_128 = COPY %31137 ; CHECK-NEXT: S_NOP 0, implicit %31138 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vreg_128 = COPY %29139 ; CHECK-NEXT: S_NOP 0, implicit %29140 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vreg_128 = COPY %27141 ; CHECK-NEXT: S_NOP 0, implicit %27142 ; CHECK-NEXT: [[SI_SPILL_V128_RESTORE1:%[0-9]+]]:vreg_128 = SI_SPILL_V128_RESTORE %stack.1, $sgpr32, 0, implicit $exec :: (load (s128) from %stack.1, align 4, addrspace 5)143 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vreg_128 = COPY [[SI_SPILL_V128_RESTORE1]]144 ; CHECK-NEXT: S_NOP 0, implicit [[SI_SPILL_V128_RESTORE1]]145 ; CHECK-NEXT: [[SI_SPILL_V128_RESTORE2:%[0-9]+]]:vreg_128 = SI_SPILL_V128_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load (s128) from %stack.0, align 4, addrspace 5)146 ; CHECK-NEXT: S_NOP 0, implicit [[SI_SPILL_V128_RESTORE2]]147 ; CHECK-NEXT: S_NOP 0, implicit %0148 ; CHECK-NEXT: [[SI_SPILL_V128_RESTORE3:%[0-9]+]]:vreg_128 = SI_SPILL_V128_RESTORE %stack.2, $sgpr32, 0, implicit $exec :: (load (s128) from %stack.2, align 4, addrspace 5)149 ; CHECK-NEXT: S_NOP 0, implicit [[SI_SPILL_V128_RESTORE3]]150 ; CHECK-NEXT: [[SI_SPILL_V128_RESTORE4:%[0-9]+]]:vreg_128 = SI_SPILL_V128_RESTORE %stack.4, $sgpr32, 0, implicit $exec :: (load (s128) from %stack.4, align 4, addrspace 5)151 ; CHECK-NEXT: S_NOP 0, implicit [[SI_SPILL_V128_RESTORE4]]152 ; CHECK-NEXT: [[SI_SPILL_V128_RESTORE5:%[0-9]+]]:vreg_128 = SI_SPILL_V128_RESTORE %stack.3, $sgpr32, 0, implicit $exec :: (load (s128) from %stack.3, align 4, addrspace 5)153 ; CHECK-NEXT: S_NOP 0, implicit [[SI_SPILL_V128_RESTORE5]]154 ; CHECK-NEXT: {{ $}}155 ; CHECK-NEXT: bb.2:156 ; CHECK-NEXT: S_NOP 0, implicit %0157 ; CHECK-NEXT: [[SI_SPILL_V128_RESTORE6:%[0-9]+]]:vreg_128 = SI_SPILL_V128_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load (s128) from %stack.0, align 4, addrspace 5)158 ; CHECK-NEXT: S_NOP 0, implicit [[SI_SPILL_V128_RESTORE6]]159 ; CHECK-NEXT: S_NOP 0, implicit [[COPY3]]160 ; CHECK-NEXT: S_NOP 0, implicit [[COPY2]]161 ; CHECK-NEXT: S_NOP 0, implicit [[COPY1]]162 ; CHECK-NEXT: S_NOP 0, implicit [[COPY]]163 bb.0:164 S_NOP 0, implicit-def %0:vreg_128165 S_NOP 0, implicit-def %1:vreg_128166 S_NOP 0, implicit-def %2:vreg_128167 S_NOP 0, implicit-def %3:vreg_128168 S_NOP 0, implicit-def %4:vreg_128169 S_NOP 0, implicit-def %5:vreg_128170 171 bb.1:172 S_NOP 0, implicit %5173 S_NOP 0, implicit %4174 S_NOP 0, implicit %3175 S_NOP 0, implicit %2176 S_NOP 0, implicit %1177 S_NOP 0, implicit %0178 S_NOP 0, implicit-def %10:vreg_128179 S_NOP 0180 S_NOP 0181 S_NOP 0182 S_NOP 0183 S_NOP 0184 S_NOP 0185 S_NOP 0186 S_NOP 0, implicit %0187 S_NOP 0, implicit-def %11:vreg_128188 S_NOP 0, implicit %10189 S_NOP 0190 S_NOP 0191 S_NOP 0192 S_NOP 0193 S_NOP 0194 S_NOP 0195 S_NOP 0196 S_NOP 0197 S_NOP 0198 S_NOP 0199 S_NOP 0, implicit-def %12:vreg_128200 S_NOP 0, implicit %11201 S_NOP 0202 S_NOP 0203 S_NOP 0204 S_NOP 0205 S_NOP 0206 S_NOP 0207 S_NOP 0208 S_NOP 0209 S_NOP 0210 S_NOP 0211 S_NOP 0212 S_NOP 0213 S_NOP 0214 S_NOP 0215 S_NOP 0, implicit-def %13:vreg_128216 S_NOP 0, implicit %12217 S_NOP 0218 S_NOP 0219 S_NOP 0220 S_NOP 0221 S_NOP 0222 S_NOP 0223 S_NOP 0224 S_NOP 0225 S_NOP 0226 S_NOP 0227 S_NOP 0228 S_NOP 0229 S_NOP 0230 S_NOP 0231 S_NOP 0232 S_NOP 0233 S_NOP 0234 S_NOP 0235 S_NOP 0236 S_NOP 0, implicit %5237 S_NOP 0, implicit %4238 S_NOP 0, implicit %3239 S_NOP 0, implicit %2240 S_NOP 0, implicit %1241 S_NOP 0, implicit %0242 S_NOP 0, implicit %11243 S_NOP 0, implicit %12244 S_NOP 0, implicit %13245 246 bb.2:247 S_NOP 0, implicit %0248 S_NOP 0, implicit %1249 S_NOP 0, implicit %2250 S_NOP 0, implicit %3251 S_NOP 0, implicit %4252 S_NOP 0, implicit %5253 254...255