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1; RUN: llc -mtriple=amdgcn -disable-block-placement < %s | FileCheck %s2 3; Check that invariant compare is hoisted out of the loop.4; At the same time condition shall not be serialized into a VGPR and deserialized later5; using another v_cmp + v_cndmask, but used directly in s_and_saveexec_b64.6 7; CHECK: v_cmp_{{..}}_u32_e{{32|64}} [[COND:s\[[0-9]+:[0-9]+\]|vcc]]8; CHECK: BB0_1:9; CHECK-NOT: v_cmp10; CHECK-NOT: v_cndmask11; CHECK: s_and_saveexec_b64 s[{{[0-9]+:[0-9]+}}], [[COND]]12; CHECK: ; %bb.2:13 14define amdgpu_kernel void @hoist_cond(ptr addrspace(1) nocapture %arg, ptr addrspace(1) noalias nocapture readonly %arg1, i32 %arg3, i32 %arg4) {15bb:16 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x() #017 %tmp5 = icmp ult i32 %tmp, %arg318 br label %bb119 20bb1: ; preds = %bb3, %bb21 %tmp7 = phi i32 [ %arg4, %bb ], [ %tmp16, %bb3 ]22 %tmp8 = phi float [ 0.000000e+00, %bb ], [ %tmp15, %bb3 ]23 br i1 %tmp5, label %bb2, label %bb324 25bb2: ; preds = %bb126 %tmp10 = zext i32 %tmp7 to i6427 %tmp11 = getelementptr inbounds float, ptr addrspace(1) %arg1, i64 %tmp1028 %tmp12 = load float, ptr addrspace(1) %tmp11, align 429 br label %bb330 31bb3: ; preds = %bb2, %bb132 %tmp14 = phi float [ %tmp12, %bb2 ], [ 0.000000e+00, %bb1 ]33 %tmp15 = fadd float %tmp8, %tmp1434 %tmp16 = add i32 %tmp7, -135 %tmp17 = icmp eq i32 %tmp16, 036 br i1 %tmp17, label %bb4, label %bb137 38bb4: ; preds = %bb339 store float %tmp15, ptr addrspace(1) %arg, align 440 ret void41}42 43; Function Attrs: nounwind readnone44declare i32 @llvm.amdgcn.workitem.id.x() #045 46attributes #0 = { nounwind readnone }47