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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn-- < %s | FileCheck -check-prefix=SI %s3 4define amdgpu_ps void @i1_copy_from_loop(ptr addrspace(8) inreg %rsrc, i32 %tid) {5; SI-LABEL: i1_copy_from_loop:6; SI: ; %bb.0: ; %entry7; SI-NEXT: s_mov_b32 s14, 08; SI-NEXT: s_mov_b64 s[4:5], 09; SI-NEXT: ; implicit-def: $sgpr6_sgpr710; SI-NEXT: ; implicit-def: $sgpr8_sgpr911; SI-NEXT: s_branch .LBB0_312; SI-NEXT: .LBB0_1: ; in Loop: Header=BB0_3 Depth=113; SI-NEXT: ; implicit-def: $sgpr1414; SI-NEXT: .LBB0_2: ; %Flow15; SI-NEXT: ; in Loop: Header=BB0_3 Depth=116; SI-NEXT: s_and_b64 s[12:13], exec, s[8:9]17; SI-NEXT: s_or_b64 s[4:5], s[12:13], s[4:5]18; SI-NEXT: s_andn2_b64 s[6:7], s[6:7], exec19; SI-NEXT: s_and_b64 s[10:11], s[10:11], exec20; SI-NEXT: s_or_b64 s[6:7], s[6:7], s[10:11]21; SI-NEXT: s_andn2_b64 exec, exec, s[4:5]22; SI-NEXT: s_cbranch_execz .LBB0_723; SI-NEXT: .LBB0_3: ; %for.body24; SI-NEXT: ; =>This Inner Loop Header: Depth=125; SI-NEXT: s_cmp_lt_u32 s14, 426; SI-NEXT: s_cselect_b64 s[10:11], -1, 027; SI-NEXT: s_or_b64 s[8:9], s[8:9], exec28; SI-NEXT: s_cmp_gt_u32 s14, 329; SI-NEXT: s_cbranch_scc1 .LBB0_130; SI-NEXT: ; %bb.4: ; %mid.loop31; SI-NEXT: ; in Loop: Header=BB0_3 Depth=132; SI-NEXT: v_mov_b32_e32 v1, s1433; SI-NEXT: buffer_load_dword v1, v[0:1], s[0:3], 0 idxen offen34; SI-NEXT: s_mov_b64 s[10:11], -135; SI-NEXT: s_waitcnt vmcnt(0)36; SI-NEXT: v_cmp_le_f32_e32 vcc, 0, v137; SI-NEXT: s_mov_b64 s[8:9], -138; SI-NEXT: s_and_saveexec_b64 s[12:13], vcc39; SI-NEXT: s_cbranch_execz .LBB0_640; SI-NEXT: ; %bb.5: ; %end.loop41; SI-NEXT: ; in Loop: Header=BB0_3 Depth=142; SI-NEXT: s_add_i32 s14, s14, 143; SI-NEXT: s_xor_b64 s[8:9], exec, -144; SI-NEXT: .LBB0_6: ; %Flow145; SI-NEXT: ; in Loop: Header=BB0_3 Depth=146; SI-NEXT: s_or_b64 exec, exec, s[12:13]47; SI-NEXT: s_branch .LBB0_248; SI-NEXT: .LBB0_7: ; %for.end49; SI-NEXT: s_or_b64 exec, exec, s[4:5]50; SI-NEXT: s_and_saveexec_b64 s[0:1], s[6:7]51; SI-NEXT: s_cbranch_execz .LBB0_952; SI-NEXT: ; %bb.8: ; %if53; SI-NEXT: exp mrt0 v0, v0, v0, v0 done vm54; SI-NEXT: .LBB0_9: ; %end55; SI-NEXT: s_endpgm56entry:57 br label %for.body58 59for.body:60 %i = phi i32 [0, %entry], [%i.inc, %end.loop]61 %cc = icmp ult i32 %i, 462 br i1 %cc, label %mid.loop, label %for.end63 64mid.loop:65 %v = call float @llvm.amdgcn.struct.ptr.buffer.load.f32(ptr addrspace(8) %rsrc, i32 %tid, i32 %i, i32 0, i32 0)66 %cc2 = fcmp oge float %v, 0.067 br i1 %cc2, label %end.loop, label %for.end68 69end.loop:70 %i.inc = add i32 %i, 171 br label %for.body72 73for.end:74 br i1 %cc, label %if, label %end75 76if:77 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float poison, float poison, float poison, float poison, i1 true, i1 true)78 br label %end79 80end:81 ret void82}83 84declare float @llvm.amdgcn.struct.ptr.buffer.load.f32(ptr addrspace(8), i32, i32, i32, i32 immarg) #085declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #186 87attributes #0 = { nounwind memory(argmem: read) }88attributes #1 = { nounwind inaccessiblememonly }89