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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN:  llc -amdgpu-scalarize-global-loads=false  -mtriple=amdgcn -mcpu=verde < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s3; RUN:  llc -amdgpu-scalarize-global-loads=false  -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI %s4; RUN:  llc -amdgpu-scalarize-global-loads=false  -mtriple=amdgcn -mcpu=gfx942 -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=GFX942 %s5 6; Use a 64-bit value with lo bits that can be represented as an inline constant7define amdgpu_kernel void @i64_imm_inline_lo(ptr addrspace(1) %out) {8; SI-LABEL: i64_imm_inline_lo:9; SI:       ; %bb.0: ; %entry10; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x911; SI-NEXT:    s_mov_b32 s3, 0xf00012; SI-NEXT:    s_mov_b32 s2, -113; SI-NEXT:    v_mov_b32_e32 v0, 514; SI-NEXT:    v_mov_b32_e32 v1, 0x1234567815; SI-NEXT:    s_waitcnt lgkmcnt(0)16; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 017; SI-NEXT:    s_endpgm18;19; VI-LABEL: i64_imm_inline_lo:20; VI:       ; %bb.0: ; %entry21; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x2422; VI-NEXT:    s_mov_b32 s3, 0xf00023; VI-NEXT:    s_mov_b32 s2, -124; VI-NEXT:    v_mov_b32_e32 v0, 525; VI-NEXT:    v_mov_b32_e32 v1, 0x1234567826; VI-NEXT:    s_waitcnt lgkmcnt(0)27; VI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 028; VI-NEXT:    s_endpgm29;30; GFX942-LABEL: i64_imm_inline_lo:31; GFX942:       ; %bb.0: ; %entry32; GFX942-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x2433; GFX942-NEXT:    s_mov_b32 s3, 0xf00034; GFX942-NEXT:    s_mov_b32 s2, -135; GFX942-NEXT:    v_mov_b32_e32 v0, 536; GFX942-NEXT:    v_mov_b32_e32 v1, 0x1234567837; GFX942-NEXT:    s_waitcnt lgkmcnt(0)38; GFX942-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 039; GFX942-NEXT:    s_endpgm40entry:41  store i64 1311768464867721221, ptr addrspace(1) %out ; 0x123456780000000542  ret void43}44 45; Use a 64-bit value with hi bits that can be represented as an inline constant46define amdgpu_kernel void @i64_imm_inline_hi(ptr addrspace(1) %out) {47; SI-LABEL: i64_imm_inline_hi:48; SI:       ; %bb.0: ; %entry49; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x950; SI-NEXT:    s_mov_b32 s3, 0xf00051; SI-NEXT:    s_mov_b32 s2, -152; SI-NEXT:    v_mov_b32_e32 v0, 0x1234567853; SI-NEXT:    v_mov_b32_e32 v1, 554; SI-NEXT:    s_waitcnt lgkmcnt(0)55; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 056; SI-NEXT:    s_endpgm57;58; VI-LABEL: i64_imm_inline_hi:59; VI:       ; %bb.0: ; %entry60; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x2461; VI-NEXT:    s_mov_b32 s3, 0xf00062; VI-NEXT:    s_mov_b32 s2, -163; VI-NEXT:    v_mov_b32_e32 v0, 0x1234567864; VI-NEXT:    v_mov_b32_e32 v1, 565; VI-NEXT:    s_waitcnt lgkmcnt(0)66; VI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 067; VI-NEXT:    s_endpgm68;69; GFX942-LABEL: i64_imm_inline_hi:70; GFX942:       ; %bb.0: ; %entry71; GFX942-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x2472; GFX942-NEXT:    s_mov_b32 s3, 0xf00073; GFX942-NEXT:    s_mov_b32 s2, -174; GFX942-NEXT:    v_mov_b32_e32 v0, 0x1234567875; GFX942-NEXT:    v_mov_b32_e32 v1, 576; GFX942-NEXT:    s_waitcnt lgkmcnt(0)77; GFX942-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 078; GFX942-NEXT:    s_endpgm79entry:80  store i64 21780256376, ptr addrspace(1) %out ; 0x000000051234567881  ret void82}83 84define amdgpu_kernel void @store_imm_neg_0.0_i64(ptr addrspace(1) %out) {85; SI-LABEL: store_imm_neg_0.0_i64:86; SI:       ; %bb.0:87; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x988; SI-NEXT:    s_mov_b32 s3, 0xf00089; SI-NEXT:    s_mov_b32 s2, -190; SI-NEXT:    v_mov_b32_e32 v0, 091; SI-NEXT:    v_bfrev_b32_e32 v1, 192; SI-NEXT:    s_waitcnt lgkmcnt(0)93; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 094; SI-NEXT:    s_endpgm95;96; VI-LABEL: store_imm_neg_0.0_i64:97; VI:       ; %bb.0:98; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x2499; VI-NEXT:    s_mov_b32 s3, 0xf000100; VI-NEXT:    s_mov_b32 s2, -1101; VI-NEXT:    v_mov_b32_e32 v0, 0102; VI-NEXT:    v_bfrev_b32_e32 v1, 1103; VI-NEXT:    s_waitcnt lgkmcnt(0)104; VI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0105; VI-NEXT:    s_endpgm106;107; GFX942-LABEL: store_imm_neg_0.0_i64:108; GFX942:       ; %bb.0:109; GFX942-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24110; GFX942-NEXT:    s_mov_b32 s3, 0xf000111; GFX942-NEXT:    s_mov_b32 s2, -1112; GFX942-NEXT:    v_mov_b32_e32 v0, 0113; GFX942-NEXT:    v_bfrev_b32_e32 v1, 1114; GFX942-NEXT:    s_waitcnt lgkmcnt(0)115; GFX942-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0116; GFX942-NEXT:    s_endpgm117  store i64 -9223372036854775808, ptr addrspace(1) %out118  ret void119}120 121define amdgpu_kernel void @store_inline_imm_neg_0.0_i32(ptr addrspace(1) %out) {122; SI-LABEL: store_inline_imm_neg_0.0_i32:123; SI:       ; %bb.0:124; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x9125; SI-NEXT:    s_mov_b32 s3, 0xf000126; SI-NEXT:    s_mov_b32 s2, -1127; SI-NEXT:    v_bfrev_b32_e32 v0, 1128; SI-NEXT:    s_waitcnt lgkmcnt(0)129; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 0130; SI-NEXT:    s_endpgm131;132; VI-LABEL: store_inline_imm_neg_0.0_i32:133; VI:       ; %bb.0:134; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24135; VI-NEXT:    s_mov_b32 s3, 0xf000136; VI-NEXT:    s_mov_b32 s2, -1137; VI-NEXT:    v_bfrev_b32_e32 v0, 1138; VI-NEXT:    s_waitcnt lgkmcnt(0)139; VI-NEXT:    buffer_store_dword v0, off, s[0:3], 0140; VI-NEXT:    s_endpgm141;142; GFX942-LABEL: store_inline_imm_neg_0.0_i32:143; GFX942:       ; %bb.0:144; GFX942-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24145; GFX942-NEXT:    s_mov_b32 s3, 0xf000146; GFX942-NEXT:    s_mov_b32 s2, -1147; GFX942-NEXT:    v_bfrev_b32_e32 v0, 1148; GFX942-NEXT:    s_waitcnt lgkmcnt(0)149; GFX942-NEXT:    buffer_store_dword v0, off, s[0:3], 0150; GFX942-NEXT:    s_endpgm151  store i32 -2147483648, ptr addrspace(1) %out152  ret void153}154 155define amdgpu_kernel void @store_inline_imm_0.0_f32(ptr addrspace(1) %out) {156; SI-LABEL: store_inline_imm_0.0_f32:157; SI:       ; %bb.0:158; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x9159; SI-NEXT:    s_mov_b32 s3, 0xf000160; SI-NEXT:    s_mov_b32 s2, -1161; SI-NEXT:    v_mov_b32_e32 v0, 0162; SI-NEXT:    s_waitcnt lgkmcnt(0)163; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 0164; SI-NEXT:    s_endpgm165;166; VI-LABEL: store_inline_imm_0.0_f32:167; VI:       ; %bb.0:168; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24169; VI-NEXT:    s_mov_b32 s3, 0xf000170; VI-NEXT:    s_mov_b32 s2, -1171; VI-NEXT:    v_mov_b32_e32 v0, 0172; VI-NEXT:    s_waitcnt lgkmcnt(0)173; VI-NEXT:    buffer_store_dword v0, off, s[0:3], 0174; VI-NEXT:    s_endpgm175;176; GFX942-LABEL: store_inline_imm_0.0_f32:177; GFX942:       ; %bb.0:178; GFX942-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24179; GFX942-NEXT:    s_mov_b32 s3, 0xf000180; GFX942-NEXT:    s_mov_b32 s2, -1181; GFX942-NEXT:    v_mov_b32_e32 v0, 0182; GFX942-NEXT:    s_waitcnt lgkmcnt(0)183; GFX942-NEXT:    buffer_store_dword v0, off, s[0:3], 0184; GFX942-NEXT:    s_endpgm185  store float 0.0, ptr addrspace(1) %out186  ret void187}188 189define amdgpu_kernel void @store_imm_neg_0.0_f32(ptr addrspace(1) %out) {190; SI-LABEL: store_imm_neg_0.0_f32:191; SI:       ; %bb.0:192; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x9193; SI-NEXT:    s_mov_b32 s3, 0xf000194; SI-NEXT:    s_mov_b32 s2, -1195; SI-NEXT:    v_bfrev_b32_e32 v0, 1196; SI-NEXT:    s_waitcnt lgkmcnt(0)197; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 0198; SI-NEXT:    s_endpgm199;200; VI-LABEL: store_imm_neg_0.0_f32:201; VI:       ; %bb.0:202; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24203; VI-NEXT:    s_mov_b32 s3, 0xf000204; VI-NEXT:    s_mov_b32 s2, -1205; VI-NEXT:    v_bfrev_b32_e32 v0, 1206; VI-NEXT:    s_waitcnt lgkmcnt(0)207; VI-NEXT:    buffer_store_dword v0, off, s[0:3], 0208; VI-NEXT:    s_endpgm209;210; GFX942-LABEL: store_imm_neg_0.0_f32:211; GFX942:       ; %bb.0:212; GFX942-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24213; GFX942-NEXT:    s_mov_b32 s3, 0xf000214; GFX942-NEXT:    s_mov_b32 s2, -1215; GFX942-NEXT:    v_bfrev_b32_e32 v0, 1216; GFX942-NEXT:    s_waitcnt lgkmcnt(0)217; GFX942-NEXT:    buffer_store_dword v0, off, s[0:3], 0218; GFX942-NEXT:    s_endpgm219  store float -0.0, ptr addrspace(1) %out220  ret void221}222 223define amdgpu_kernel void @store_inline_imm_0.5_f32(ptr addrspace(1) %out) {224; SI-LABEL: store_inline_imm_0.5_f32:225; SI:       ; %bb.0:226; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x9227; SI-NEXT:    s_mov_b32 s3, 0xf000228; SI-NEXT:    s_mov_b32 s2, -1229; SI-NEXT:    v_mov_b32_e32 v0, 0.5230; SI-NEXT:    s_waitcnt lgkmcnt(0)231; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 0232; SI-NEXT:    s_endpgm233;234; VI-LABEL: store_inline_imm_0.5_f32:235; VI:       ; %bb.0:236; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24237; VI-NEXT:    s_mov_b32 s3, 0xf000238; VI-NEXT:    s_mov_b32 s2, -1239; VI-NEXT:    v_mov_b32_e32 v0, 0.5240; VI-NEXT:    s_waitcnt lgkmcnt(0)241; VI-NEXT:    buffer_store_dword v0, off, s[0:3], 0242; VI-NEXT:    s_endpgm243;244; GFX942-LABEL: store_inline_imm_0.5_f32:245; GFX942:       ; %bb.0:246; GFX942-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24247; GFX942-NEXT:    s_mov_b32 s3, 0xf000248; GFX942-NEXT:    s_mov_b32 s2, -1249; GFX942-NEXT:    v_mov_b32_e32 v0, 0.5250; GFX942-NEXT:    s_waitcnt lgkmcnt(0)251; GFX942-NEXT:    buffer_store_dword v0, off, s[0:3], 0252; GFX942-NEXT:    s_endpgm253  store float 0.5, ptr addrspace(1) %out254  ret void255}256 257define amdgpu_kernel void @store_inline_imm_m_0.5_f32(ptr addrspace(1) %out) {258; SI-LABEL: store_inline_imm_m_0.5_f32:259; SI:       ; %bb.0:260; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x9261; SI-NEXT:    s_mov_b32 s3, 0xf000262; SI-NEXT:    s_mov_b32 s2, -1263; SI-NEXT:    v_mov_b32_e32 v0, -0.5264; SI-NEXT:    s_waitcnt lgkmcnt(0)265; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 0266; SI-NEXT:    s_endpgm267;268; VI-LABEL: store_inline_imm_m_0.5_f32:269; VI:       ; %bb.0:270; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24271; VI-NEXT:    s_mov_b32 s3, 0xf000272; VI-NEXT:    s_mov_b32 s2, -1273; VI-NEXT:    v_mov_b32_e32 v0, -0.5274; VI-NEXT:    s_waitcnt lgkmcnt(0)275; VI-NEXT:    buffer_store_dword v0, off, s[0:3], 0276; VI-NEXT:    s_endpgm277;278; GFX942-LABEL: store_inline_imm_m_0.5_f32:279; GFX942:       ; %bb.0:280; GFX942-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24281; GFX942-NEXT:    s_mov_b32 s3, 0xf000282; GFX942-NEXT:    s_mov_b32 s2, -1283; GFX942-NEXT:    v_mov_b32_e32 v0, -0.5284; GFX942-NEXT:    s_waitcnt lgkmcnt(0)285; GFX942-NEXT:    buffer_store_dword v0, off, s[0:3], 0286; GFX942-NEXT:    s_endpgm287  store float -0.5, ptr addrspace(1) %out288  ret void289}290 291define amdgpu_kernel void @store_inline_imm_1.0_f32(ptr addrspace(1) %out) {292; SI-LABEL: store_inline_imm_1.0_f32:293; SI:       ; %bb.0:294; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x9295; SI-NEXT:    s_mov_b32 s3, 0xf000296; SI-NEXT:    s_mov_b32 s2, -1297; SI-NEXT:    v_mov_b32_e32 v0, 1.0298; SI-NEXT:    s_waitcnt lgkmcnt(0)299; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 0300; SI-NEXT:    s_endpgm301;302; VI-LABEL: store_inline_imm_1.0_f32:303; VI:       ; %bb.0:304; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24305; VI-NEXT:    s_mov_b32 s3, 0xf000306; VI-NEXT:    s_mov_b32 s2, -1307; VI-NEXT:    v_mov_b32_e32 v0, 1.0308; VI-NEXT:    s_waitcnt lgkmcnt(0)309; VI-NEXT:    buffer_store_dword v0, off, s[0:3], 0310; VI-NEXT:    s_endpgm311;312; GFX942-LABEL: store_inline_imm_1.0_f32:313; GFX942:       ; %bb.0:314; GFX942-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24315; GFX942-NEXT:    s_mov_b32 s3, 0xf000316; GFX942-NEXT:    s_mov_b32 s2, -1317; GFX942-NEXT:    v_mov_b32_e32 v0, 1.0318; GFX942-NEXT:    s_waitcnt lgkmcnt(0)319; GFX942-NEXT:    buffer_store_dword v0, off, s[0:3], 0320; GFX942-NEXT:    s_endpgm321  store float 1.0, ptr addrspace(1) %out322  ret void323}324 325define amdgpu_kernel void @store_inline_imm_m_1.0_f32(ptr addrspace(1) %out) {326; SI-LABEL: store_inline_imm_m_1.0_f32:327; SI:       ; %bb.0:328; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x9329; SI-NEXT:    s_mov_b32 s3, 0xf000330; SI-NEXT:    s_mov_b32 s2, -1331; SI-NEXT:    v_mov_b32_e32 v0, -1.0332; SI-NEXT:    s_waitcnt lgkmcnt(0)333; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 0334; SI-NEXT:    s_endpgm335;336; VI-LABEL: store_inline_imm_m_1.0_f32:337; VI:       ; %bb.0:338; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24339; VI-NEXT:    s_mov_b32 s3, 0xf000340; VI-NEXT:    s_mov_b32 s2, -1341; VI-NEXT:    v_mov_b32_e32 v0, -1.0342; VI-NEXT:    s_waitcnt lgkmcnt(0)343; VI-NEXT:    buffer_store_dword v0, off, s[0:3], 0344; VI-NEXT:    s_endpgm345;346; GFX942-LABEL: store_inline_imm_m_1.0_f32:347; GFX942:       ; %bb.0:348; GFX942-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24349; GFX942-NEXT:    s_mov_b32 s3, 0xf000350; GFX942-NEXT:    s_mov_b32 s2, -1351; GFX942-NEXT:    v_mov_b32_e32 v0, -1.0352; GFX942-NEXT:    s_waitcnt lgkmcnt(0)353; GFX942-NEXT:    buffer_store_dword v0, off, s[0:3], 0354; GFX942-NEXT:    s_endpgm355  store float -1.0, ptr addrspace(1) %out356  ret void357}358 359define amdgpu_kernel void @store_inline_imm_2.0_f32(ptr addrspace(1) %out) {360; SI-LABEL: store_inline_imm_2.0_f32:361; SI:       ; %bb.0:362; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x9363; SI-NEXT:    s_mov_b32 s3, 0xf000364; SI-NEXT:    s_mov_b32 s2, -1365; SI-NEXT:    v_mov_b32_e32 v0, 2.0366; SI-NEXT:    s_waitcnt lgkmcnt(0)367; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 0368; SI-NEXT:    s_endpgm369;370; VI-LABEL: store_inline_imm_2.0_f32:371; VI:       ; %bb.0:372; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24373; VI-NEXT:    s_mov_b32 s3, 0xf000374; VI-NEXT:    s_mov_b32 s2, -1375; VI-NEXT:    v_mov_b32_e32 v0, 2.0376; VI-NEXT:    s_waitcnt lgkmcnt(0)377; VI-NEXT:    buffer_store_dword v0, off, s[0:3], 0378; VI-NEXT:    s_endpgm379;380; GFX942-LABEL: store_inline_imm_2.0_f32:381; GFX942:       ; %bb.0:382; GFX942-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24383; GFX942-NEXT:    s_mov_b32 s3, 0xf000384; GFX942-NEXT:    s_mov_b32 s2, -1385; GFX942-NEXT:    v_mov_b32_e32 v0, 2.0386; GFX942-NEXT:    s_waitcnt lgkmcnt(0)387; GFX942-NEXT:    buffer_store_dword v0, off, s[0:3], 0388; GFX942-NEXT:    s_endpgm389  store float 2.0, ptr addrspace(1) %out390  ret void391}392 393define amdgpu_kernel void @store_inline_imm_m_2.0_f32(ptr addrspace(1) %out) {394; SI-LABEL: store_inline_imm_m_2.0_f32:395; SI:       ; %bb.0:396; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x9397; SI-NEXT:    s_mov_b32 s3, 0xf000398; SI-NEXT:    s_mov_b32 s2, -1399; SI-NEXT:    v_mov_b32_e32 v0, -2.0400; SI-NEXT:    s_waitcnt lgkmcnt(0)401; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 0402; SI-NEXT:    s_endpgm403;404; VI-LABEL: store_inline_imm_m_2.0_f32:405; VI:       ; %bb.0:406; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24407; VI-NEXT:    s_mov_b32 s3, 0xf000408; VI-NEXT:    s_mov_b32 s2, -1409; VI-NEXT:    v_mov_b32_e32 v0, -2.0410; VI-NEXT:    s_waitcnt lgkmcnt(0)411; VI-NEXT:    buffer_store_dword v0, off, s[0:3], 0412; VI-NEXT:    s_endpgm413;414; GFX942-LABEL: store_inline_imm_m_2.0_f32:415; GFX942:       ; %bb.0:416; GFX942-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24417; GFX942-NEXT:    s_mov_b32 s3, 0xf000418; GFX942-NEXT:    s_mov_b32 s2, -1419; GFX942-NEXT:    v_mov_b32_e32 v0, -2.0420; GFX942-NEXT:    s_waitcnt lgkmcnt(0)421; GFX942-NEXT:    buffer_store_dword v0, off, s[0:3], 0422; GFX942-NEXT:    s_endpgm423  store float -2.0, ptr addrspace(1) %out424  ret void425}426 427define amdgpu_kernel void @store_inline_imm_4.0_f32(ptr addrspace(1) %out) {428; SI-LABEL: store_inline_imm_4.0_f32:429; SI:       ; %bb.0:430; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x9431; SI-NEXT:    s_mov_b32 s3, 0xf000432; SI-NEXT:    s_mov_b32 s2, -1433; SI-NEXT:    v_mov_b32_e32 v0, 4.0434; SI-NEXT:    s_waitcnt lgkmcnt(0)435; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 0436; SI-NEXT:    s_endpgm437;438; VI-LABEL: store_inline_imm_4.0_f32:439; VI:       ; %bb.0:440; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24441; VI-NEXT:    s_mov_b32 s3, 0xf000442; VI-NEXT:    s_mov_b32 s2, -1443; VI-NEXT:    v_mov_b32_e32 v0, 4.0444; VI-NEXT:    s_waitcnt lgkmcnt(0)445; VI-NEXT:    buffer_store_dword v0, off, s[0:3], 0446; VI-NEXT:    s_endpgm447;448; GFX942-LABEL: store_inline_imm_4.0_f32:449; GFX942:       ; %bb.0:450; GFX942-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24451; GFX942-NEXT:    s_mov_b32 s3, 0xf000452; GFX942-NEXT:    s_mov_b32 s2, -1453; GFX942-NEXT:    v_mov_b32_e32 v0, 4.0454; GFX942-NEXT:    s_waitcnt lgkmcnt(0)455; GFX942-NEXT:    buffer_store_dword v0, off, s[0:3], 0456; GFX942-NEXT:    s_endpgm457  store float 4.0, ptr addrspace(1) %out458  ret void459}460 461define amdgpu_kernel void @store_inline_imm_m_4.0_f32(ptr addrspace(1) %out) {462; SI-LABEL: store_inline_imm_m_4.0_f32:463; SI:       ; %bb.0:464; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x9465; SI-NEXT:    s_mov_b32 s3, 0xf000466; SI-NEXT:    s_mov_b32 s2, -1467; SI-NEXT:    v_mov_b32_e32 v0, -4.0468; SI-NEXT:    s_waitcnt lgkmcnt(0)469; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 0470; SI-NEXT:    s_endpgm471;472; VI-LABEL: store_inline_imm_m_4.0_f32:473; VI:       ; %bb.0:474; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24475; VI-NEXT:    s_mov_b32 s3, 0xf000476; VI-NEXT:    s_mov_b32 s2, -1477; VI-NEXT:    v_mov_b32_e32 v0, -4.0478; VI-NEXT:    s_waitcnt lgkmcnt(0)479; VI-NEXT:    buffer_store_dword v0, off, s[0:3], 0480; VI-NEXT:    s_endpgm481;482; GFX942-LABEL: store_inline_imm_m_4.0_f32:483; GFX942:       ; %bb.0:484; GFX942-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24485; GFX942-NEXT:    s_mov_b32 s3, 0xf000486; GFX942-NEXT:    s_mov_b32 s2, -1487; GFX942-NEXT:    v_mov_b32_e32 v0, -4.0488; GFX942-NEXT:    s_waitcnt lgkmcnt(0)489; GFX942-NEXT:    buffer_store_dword v0, off, s[0:3], 0490; GFX942-NEXT:    s_endpgm491  store float -4.0, ptr addrspace(1) %out492  ret void493}494 495define amdgpu_kernel void @store_inline_imm_inv_2pi_f32(ptr addrspace(1) %out) {496; SI-LABEL: store_inline_imm_inv_2pi_f32:497; SI:       ; %bb.0:498; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x9499; SI-NEXT:    s_mov_b32 s3, 0xf000500; SI-NEXT:    s_mov_b32 s2, -1501; SI-NEXT:    v_mov_b32_e32 v0, 0x3e22f983502; SI-NEXT:    s_waitcnt lgkmcnt(0)503; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 0504; SI-NEXT:    s_endpgm505;506; VI-LABEL: store_inline_imm_inv_2pi_f32:507; VI:       ; %bb.0:508; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24509; VI-NEXT:    s_mov_b32 s3, 0xf000510; VI-NEXT:    s_mov_b32 s2, -1511; VI-NEXT:    v_mov_b32_e32 v0, 0.15915494512; VI-NEXT:    s_waitcnt lgkmcnt(0)513; VI-NEXT:    buffer_store_dword v0, off, s[0:3], 0514; VI-NEXT:    s_endpgm515;516; GFX942-LABEL: store_inline_imm_inv_2pi_f32:517; GFX942:       ; %bb.0:518; GFX942-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24519; GFX942-NEXT:    s_mov_b32 s3, 0xf000520; GFX942-NEXT:    s_mov_b32 s2, -1521; GFX942-NEXT:    v_mov_b32_e32 v0, 0.15915494522; GFX942-NEXT:    s_waitcnt lgkmcnt(0)523; GFX942-NEXT:    buffer_store_dword v0, off, s[0:3], 0524; GFX942-NEXT:    s_endpgm525  store float 0x3FC45F3060000000, ptr addrspace(1) %out526  ret void527}528 529define amdgpu_kernel void @store_inline_imm_m_inv_2pi_f32(ptr addrspace(1) %out) {530; SI-LABEL: store_inline_imm_m_inv_2pi_f32:531; SI:       ; %bb.0:532; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x9533; SI-NEXT:    s_mov_b32 s3, 0xf000534; SI-NEXT:    s_mov_b32 s2, -1535; SI-NEXT:    v_mov_b32_e32 v0, 0xbe22f983536; SI-NEXT:    s_waitcnt lgkmcnt(0)537; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 0538; SI-NEXT:    s_endpgm539;540; VI-LABEL: store_inline_imm_m_inv_2pi_f32:541; VI:       ; %bb.0:542; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24543; VI-NEXT:    s_mov_b32 s3, 0xf000544; VI-NEXT:    s_mov_b32 s2, -1545; VI-NEXT:    v_mov_b32_e32 v0, 0xbe22f983546; VI-NEXT:    s_waitcnt lgkmcnt(0)547; VI-NEXT:    buffer_store_dword v0, off, s[0:3], 0548; VI-NEXT:    s_endpgm549;550; GFX942-LABEL: store_inline_imm_m_inv_2pi_f32:551; GFX942:       ; %bb.0:552; GFX942-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24553; GFX942-NEXT:    s_mov_b32 s3, 0xf000554; GFX942-NEXT:    s_mov_b32 s2, -1555; GFX942-NEXT:    v_mov_b32_e32 v0, 0xbe22f983556; GFX942-NEXT:    s_waitcnt lgkmcnt(0)557; GFX942-NEXT:    buffer_store_dword v0, off, s[0:3], 0558; GFX942-NEXT:    s_endpgm559  store float 0xBFC45F3060000000, ptr addrspace(1) %out560  ret void561}562 563define amdgpu_kernel void @store_literal_imm_f32(ptr addrspace(1) %out) {564; SI-LABEL: store_literal_imm_f32:565; SI:       ; %bb.0:566; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x9567; SI-NEXT:    s_mov_b32 s3, 0xf000568; SI-NEXT:    s_mov_b32 s2, -1569; SI-NEXT:    v_mov_b32_e32 v0, 0x45800000570; SI-NEXT:    s_waitcnt lgkmcnt(0)571; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 0572; SI-NEXT:    s_endpgm573;574; VI-LABEL: store_literal_imm_f32:575; VI:       ; %bb.0:576; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24577; VI-NEXT:    s_mov_b32 s3, 0xf000578; VI-NEXT:    s_mov_b32 s2, -1579; VI-NEXT:    v_mov_b32_e32 v0, 0x45800000580; VI-NEXT:    s_waitcnt lgkmcnt(0)581; VI-NEXT:    buffer_store_dword v0, off, s[0:3], 0582; VI-NEXT:    s_endpgm583;584; GFX942-LABEL: store_literal_imm_f32:585; GFX942:       ; %bb.0:586; GFX942-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24587; GFX942-NEXT:    s_mov_b32 s3, 0xf000588; GFX942-NEXT:    s_mov_b32 s2, -1589; GFX942-NEXT:    v_mov_b32_e32 v0, 0x45800000590; GFX942-NEXT:    s_waitcnt lgkmcnt(0)591; GFX942-NEXT:    buffer_store_dword v0, off, s[0:3], 0592; GFX942-NEXT:    s_endpgm593  store float 4096.0, ptr addrspace(1) %out594  ret void595}596 597define amdgpu_kernel void @add_inline_imm_0.0_f32(ptr addrspace(1) %out, float %x) {598; SI-LABEL: add_inline_imm_0.0_f32:599; SI:       ; %bb.0:600; SI-NEXT:    s_load_dword s6, s[4:5], 0xb601; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x9602; SI-NEXT:    s_mov_b32 s3, 0xf000603; SI-NEXT:    s_mov_b32 s2, -1604; SI-NEXT:    s_waitcnt lgkmcnt(0)605; SI-NEXT:    v_add_f32_e64 v0, s6, 0606; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 0607; SI-NEXT:    s_endpgm608;609; VI-LABEL: add_inline_imm_0.0_f32:610; VI:       ; %bb.0:611; VI-NEXT:    s_load_dword s6, s[4:5], 0x2c612; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24613; VI-NEXT:    s_mov_b32 s3, 0xf000614; VI-NEXT:    s_mov_b32 s2, -1615; VI-NEXT:    s_waitcnt lgkmcnt(0)616; VI-NEXT:    v_add_f32_e64 v0, s6, 0617; VI-NEXT:    buffer_store_dword v0, off, s[0:3], 0618; VI-NEXT:    s_endpgm619;620; GFX942-LABEL: add_inline_imm_0.0_f32:621; GFX942:       ; %bb.0:622; GFX942-NEXT:    s_load_dword s6, s[4:5], 0x2c623; GFX942-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24624; GFX942-NEXT:    s_mov_b32 s3, 0xf000625; GFX942-NEXT:    s_mov_b32 s2, -1626; GFX942-NEXT:    s_waitcnt lgkmcnt(0)627; GFX942-NEXT:    v_add_f32_e64 v0, s6, 0628; GFX942-NEXT:    buffer_store_dword v0, off, s[0:3], 0629; GFX942-NEXT:    s_endpgm630  %y = fadd float %x, 0.0631  store float %y, ptr addrspace(1) %out632  ret void633}634 635define amdgpu_kernel void @add_inline_imm_0.5_f32(ptr addrspace(1) %out, float %x) {636; SI-LABEL: add_inline_imm_0.5_f32:637; SI:       ; %bb.0:638; SI-NEXT:    s_load_dword s6, s[4:5], 0xb639; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x9640; SI-NEXT:    s_mov_b32 s3, 0xf000641; SI-NEXT:    s_mov_b32 s2, -1642; SI-NEXT:    s_waitcnt lgkmcnt(0)643; SI-NEXT:    v_add_f32_e64 v0, s6, 0.5644; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 0645; SI-NEXT:    s_endpgm646;647; VI-LABEL: add_inline_imm_0.5_f32:648; VI:       ; %bb.0:649; VI-NEXT:    s_load_dword s6, s[4:5], 0x2c650; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24651; VI-NEXT:    s_mov_b32 s3, 0xf000652; VI-NEXT:    s_mov_b32 s2, -1653; VI-NEXT:    s_waitcnt lgkmcnt(0)654; VI-NEXT:    v_add_f32_e64 v0, s6, 0.5655; VI-NEXT:    buffer_store_dword v0, off, s[0:3], 0656; VI-NEXT:    s_endpgm657;658; GFX942-LABEL: add_inline_imm_0.5_f32:659; GFX942:       ; %bb.0:660; GFX942-NEXT:    s_load_dword s6, s[4:5], 0x2c661; GFX942-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24662; GFX942-NEXT:    s_mov_b32 s3, 0xf000663; GFX942-NEXT:    s_mov_b32 s2, -1664; GFX942-NEXT:    s_waitcnt lgkmcnt(0)665; GFX942-NEXT:    v_add_f32_e64 v0, s6, 0.5666; GFX942-NEXT:    buffer_store_dword v0, off, s[0:3], 0667; GFX942-NEXT:    s_endpgm668  %y = fadd float %x, 0.5669  store float %y, ptr addrspace(1) %out670  ret void671}672 673define amdgpu_kernel void @add_inline_imm_neg_0.5_f32(ptr addrspace(1) %out, float %x) {674; SI-LABEL: add_inline_imm_neg_0.5_f32:675; SI:       ; %bb.0:676; SI-NEXT:    s_load_dword s6, s[4:5], 0xb677; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x9678; SI-NEXT:    s_mov_b32 s3, 0xf000679; SI-NEXT:    s_mov_b32 s2, -1680; SI-NEXT:    s_waitcnt lgkmcnt(0)681; SI-NEXT:    v_add_f32_e64 v0, s6, -0.5682; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 0683; SI-NEXT:    s_endpgm684;685; VI-LABEL: add_inline_imm_neg_0.5_f32:686; VI:       ; %bb.0:687; VI-NEXT:    s_load_dword s6, s[4:5], 0x2c688; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24689; VI-NEXT:    s_mov_b32 s3, 0xf000690; VI-NEXT:    s_mov_b32 s2, -1691; VI-NEXT:    s_waitcnt lgkmcnt(0)692; VI-NEXT:    v_add_f32_e64 v0, s6, -0.5693; VI-NEXT:    buffer_store_dword v0, off, s[0:3], 0694; VI-NEXT:    s_endpgm695;696; GFX942-LABEL: add_inline_imm_neg_0.5_f32:697; GFX942:       ; %bb.0:698; GFX942-NEXT:    s_load_dword s6, s[4:5], 0x2c699; GFX942-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24700; GFX942-NEXT:    s_mov_b32 s3, 0xf000701; GFX942-NEXT:    s_mov_b32 s2, -1702; GFX942-NEXT:    s_waitcnt lgkmcnt(0)703; GFX942-NEXT:    v_add_f32_e64 v0, s6, -0.5704; GFX942-NEXT:    buffer_store_dword v0, off, s[0:3], 0705; GFX942-NEXT:    s_endpgm706  %y = fadd float %x, -0.5707  store float %y, ptr addrspace(1) %out708  ret void709}710 711define amdgpu_kernel void @add_inline_imm_1.0_f32(ptr addrspace(1) %out, float %x) {712; SI-LABEL: add_inline_imm_1.0_f32:713; SI:       ; %bb.0:714; SI-NEXT:    s_load_dword s6, s[4:5], 0xb715; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x9716; SI-NEXT:    s_mov_b32 s3, 0xf000717; SI-NEXT:    s_mov_b32 s2, -1718; SI-NEXT:    s_waitcnt lgkmcnt(0)719; SI-NEXT:    v_add_f32_e64 v0, s6, 1.0720; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 0721; SI-NEXT:    s_endpgm722;723; VI-LABEL: add_inline_imm_1.0_f32:724; VI:       ; %bb.0:725; VI-NEXT:    s_load_dword s6, s[4:5], 0x2c726; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24727; VI-NEXT:    s_mov_b32 s3, 0xf000728; VI-NEXT:    s_mov_b32 s2, -1729; VI-NEXT:    s_waitcnt lgkmcnt(0)730; VI-NEXT:    v_add_f32_e64 v0, s6, 1.0731; VI-NEXT:    buffer_store_dword v0, off, s[0:3], 0732; VI-NEXT:    s_endpgm733;734; GFX942-LABEL: add_inline_imm_1.0_f32:735; GFX942:       ; %bb.0:736; GFX942-NEXT:    s_load_dword s6, s[4:5], 0x2c737; GFX942-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24738; GFX942-NEXT:    s_mov_b32 s3, 0xf000739; GFX942-NEXT:    s_mov_b32 s2, -1740; GFX942-NEXT:    s_waitcnt lgkmcnt(0)741; GFX942-NEXT:    v_add_f32_e64 v0, s6, 1.0742; GFX942-NEXT:    buffer_store_dword v0, off, s[0:3], 0743; GFX942-NEXT:    s_endpgm744  %y = fadd float %x, 1.0745  store float %y, ptr addrspace(1) %out746  ret void747}748 749define amdgpu_kernel void @add_inline_imm_neg_1.0_f32(ptr addrspace(1) %out, float %x) {750; SI-LABEL: add_inline_imm_neg_1.0_f32:751; SI:       ; %bb.0:752; SI-NEXT:    s_load_dword s6, s[4:5], 0xb753; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x9754; SI-NEXT:    s_mov_b32 s3, 0xf000755; SI-NEXT:    s_mov_b32 s2, -1756; SI-NEXT:    s_waitcnt lgkmcnt(0)757; SI-NEXT:    v_add_f32_e64 v0, s6, -1.0758; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 0759; SI-NEXT:    s_endpgm760;761; VI-LABEL: add_inline_imm_neg_1.0_f32:762; VI:       ; %bb.0:763; VI-NEXT:    s_load_dword s6, s[4:5], 0x2c764; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24765; VI-NEXT:    s_mov_b32 s3, 0xf000766; VI-NEXT:    s_mov_b32 s2, -1767; VI-NEXT:    s_waitcnt lgkmcnt(0)768; VI-NEXT:    v_add_f32_e64 v0, s6, -1.0769; VI-NEXT:    buffer_store_dword v0, off, s[0:3], 0770; VI-NEXT:    s_endpgm771;772; GFX942-LABEL: add_inline_imm_neg_1.0_f32:773; GFX942:       ; %bb.0:774; GFX942-NEXT:    s_load_dword s6, s[4:5], 0x2c775; GFX942-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24776; GFX942-NEXT:    s_mov_b32 s3, 0xf000777; GFX942-NEXT:    s_mov_b32 s2, -1778; GFX942-NEXT:    s_waitcnt lgkmcnt(0)779; GFX942-NEXT:    v_add_f32_e64 v0, s6, -1.0780; GFX942-NEXT:    buffer_store_dword v0, off, s[0:3], 0781; GFX942-NEXT:    s_endpgm782  %y = fadd float %x, -1.0783  store float %y, ptr addrspace(1) %out784  ret void785}786 787define amdgpu_kernel void @add_inline_imm_2.0_f32(ptr addrspace(1) %out, float %x) {788; SI-LABEL: add_inline_imm_2.0_f32:789; SI:       ; %bb.0:790; SI-NEXT:    s_load_dword s6, s[4:5], 0xb791; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x9792; SI-NEXT:    s_mov_b32 s3, 0xf000793; SI-NEXT:    s_mov_b32 s2, -1794; SI-NEXT:    s_waitcnt lgkmcnt(0)795; SI-NEXT:    v_add_f32_e64 v0, s6, 2.0796; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 0797; SI-NEXT:    s_endpgm798;799; VI-LABEL: add_inline_imm_2.0_f32:800; VI:       ; %bb.0:801; VI-NEXT:    s_load_dword s6, s[4:5], 0x2c802; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24803; VI-NEXT:    s_mov_b32 s3, 0xf000804; VI-NEXT:    s_mov_b32 s2, -1805; VI-NEXT:    s_waitcnt lgkmcnt(0)806; VI-NEXT:    v_add_f32_e64 v0, s6, 2.0807; VI-NEXT:    buffer_store_dword v0, off, s[0:3], 0808; VI-NEXT:    s_endpgm809;810; GFX942-LABEL: add_inline_imm_2.0_f32:811; GFX942:       ; %bb.0:812; GFX942-NEXT:    s_load_dword s6, s[4:5], 0x2c813; GFX942-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24814; GFX942-NEXT:    s_mov_b32 s3, 0xf000815; GFX942-NEXT:    s_mov_b32 s2, -1816; GFX942-NEXT:    s_waitcnt lgkmcnt(0)817; GFX942-NEXT:    v_add_f32_e64 v0, s6, 2.0818; GFX942-NEXT:    buffer_store_dword v0, off, s[0:3], 0819; GFX942-NEXT:    s_endpgm820  %y = fadd float %x, 2.0821  store float %y, ptr addrspace(1) %out822  ret void823}824 825define amdgpu_kernel void @add_inline_imm_neg_2.0_f32(ptr addrspace(1) %out, float %x) {826; SI-LABEL: add_inline_imm_neg_2.0_f32:827; SI:       ; %bb.0:828; SI-NEXT:    s_load_dword s6, s[4:5], 0xb829; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x9830; SI-NEXT:    s_mov_b32 s3, 0xf000831; SI-NEXT:    s_mov_b32 s2, -1832; SI-NEXT:    s_waitcnt lgkmcnt(0)833; SI-NEXT:    v_add_f32_e64 v0, s6, -2.0834; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 0835; SI-NEXT:    s_endpgm836;837; VI-LABEL: add_inline_imm_neg_2.0_f32:838; VI:       ; %bb.0:839; VI-NEXT:    s_load_dword s6, s[4:5], 0x2c840; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24841; VI-NEXT:    s_mov_b32 s3, 0xf000842; VI-NEXT:    s_mov_b32 s2, -1843; VI-NEXT:    s_waitcnt lgkmcnt(0)844; VI-NEXT:    v_add_f32_e64 v0, s6, -2.0845; VI-NEXT:    buffer_store_dword v0, off, s[0:3], 0846; VI-NEXT:    s_endpgm847;848; GFX942-LABEL: add_inline_imm_neg_2.0_f32:849; GFX942:       ; %bb.0:850; GFX942-NEXT:    s_load_dword s6, s[4:5], 0x2c851; GFX942-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24852; GFX942-NEXT:    s_mov_b32 s3, 0xf000853; GFX942-NEXT:    s_mov_b32 s2, -1854; GFX942-NEXT:    s_waitcnt lgkmcnt(0)855; GFX942-NEXT:    v_add_f32_e64 v0, s6, -2.0856; GFX942-NEXT:    buffer_store_dword v0, off, s[0:3], 0857; GFX942-NEXT:    s_endpgm858  %y = fadd float %x, -2.0859  store float %y, ptr addrspace(1) %out860  ret void861}862 863define amdgpu_kernel void @add_inline_imm_4.0_f32(ptr addrspace(1) %out, float %x) {864; SI-LABEL: add_inline_imm_4.0_f32:865; SI:       ; %bb.0:866; SI-NEXT:    s_load_dword s6, s[4:5], 0xb867; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x9868; SI-NEXT:    s_mov_b32 s3, 0xf000869; SI-NEXT:    s_mov_b32 s2, -1870; SI-NEXT:    s_waitcnt lgkmcnt(0)871; SI-NEXT:    v_add_f32_e64 v0, s6, 4.0872; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 0873; SI-NEXT:    s_endpgm874;875; VI-LABEL: add_inline_imm_4.0_f32:876; VI:       ; %bb.0:877; VI-NEXT:    s_load_dword s6, s[4:5], 0x2c878; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24879; VI-NEXT:    s_mov_b32 s3, 0xf000880; VI-NEXT:    s_mov_b32 s2, -1881; VI-NEXT:    s_waitcnt lgkmcnt(0)882; VI-NEXT:    v_add_f32_e64 v0, s6, 4.0883; VI-NEXT:    buffer_store_dword v0, off, s[0:3], 0884; VI-NEXT:    s_endpgm885;886; GFX942-LABEL: add_inline_imm_4.0_f32:887; GFX942:       ; %bb.0:888; GFX942-NEXT:    s_load_dword s6, s[4:5], 0x2c889; GFX942-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24890; GFX942-NEXT:    s_mov_b32 s3, 0xf000891; GFX942-NEXT:    s_mov_b32 s2, -1892; GFX942-NEXT:    s_waitcnt lgkmcnt(0)893; GFX942-NEXT:    v_add_f32_e64 v0, s6, 4.0894; GFX942-NEXT:    buffer_store_dword v0, off, s[0:3], 0895; GFX942-NEXT:    s_endpgm896  %y = fadd float %x, 4.0897  store float %y, ptr addrspace(1) %out898  ret void899}900 901define amdgpu_kernel void @add_inline_imm_neg_4.0_f32(ptr addrspace(1) %out, float %x) {902; SI-LABEL: add_inline_imm_neg_4.0_f32:903; SI:       ; %bb.0:904; SI-NEXT:    s_load_dword s6, s[4:5], 0xb905; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x9906; SI-NEXT:    s_mov_b32 s3, 0xf000907; SI-NEXT:    s_mov_b32 s2, -1908; SI-NEXT:    s_waitcnt lgkmcnt(0)909; SI-NEXT:    v_add_f32_e64 v0, s6, -4.0910; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 0911; SI-NEXT:    s_endpgm912;913; VI-LABEL: add_inline_imm_neg_4.0_f32:914; VI:       ; %bb.0:915; VI-NEXT:    s_load_dword s6, s[4:5], 0x2c916; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24917; VI-NEXT:    s_mov_b32 s3, 0xf000918; VI-NEXT:    s_mov_b32 s2, -1919; VI-NEXT:    s_waitcnt lgkmcnt(0)920; VI-NEXT:    v_add_f32_e64 v0, s6, -4.0921; VI-NEXT:    buffer_store_dword v0, off, s[0:3], 0922; VI-NEXT:    s_endpgm923;924; GFX942-LABEL: add_inline_imm_neg_4.0_f32:925; GFX942:       ; %bb.0:926; GFX942-NEXT:    s_load_dword s6, s[4:5], 0x2c927; GFX942-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24928; GFX942-NEXT:    s_mov_b32 s3, 0xf000929; GFX942-NEXT:    s_mov_b32 s2, -1930; GFX942-NEXT:    s_waitcnt lgkmcnt(0)931; GFX942-NEXT:    v_add_f32_e64 v0, s6, -4.0932; GFX942-NEXT:    buffer_store_dword v0, off, s[0:3], 0933; GFX942-NEXT:    s_endpgm934  %y = fadd float %x, -4.0935  store float %y, ptr addrspace(1) %out936  ret void937}938 939define amdgpu_kernel void @commute_add_inline_imm_0.5_f32(ptr addrspace(1) %out, ptr addrspace(1) %in) {940; SI-LABEL: commute_add_inline_imm_0.5_f32:941; SI:       ; %bb.0:942; SI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x9943; SI-NEXT:    s_mov_b32 s7, 0xf000944; SI-NEXT:    s_mov_b32 s6, -1945; SI-NEXT:    s_mov_b32 s10, s6946; SI-NEXT:    s_mov_b32 s11, s7947; SI-NEXT:    s_waitcnt lgkmcnt(0)948; SI-NEXT:    s_mov_b32 s8, s2949; SI-NEXT:    s_mov_b32 s9, s3950; SI-NEXT:    buffer_load_dword v0, off, s[8:11], 0951; SI-NEXT:    s_mov_b32 s4, s0952; SI-NEXT:    s_mov_b32 s5, s1953; SI-NEXT:    s_waitcnt vmcnt(0)954; SI-NEXT:    v_add_f32_e32 v0, 0.5, v0955; SI-NEXT:    buffer_store_dword v0, off, s[4:7], 0956; SI-NEXT:    s_endpgm957;958; VI-LABEL: commute_add_inline_imm_0.5_f32:959; VI:       ; %bb.0:960; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24961; VI-NEXT:    s_mov_b32 s7, 0xf000962; VI-NEXT:    s_mov_b32 s6, -1963; VI-NEXT:    s_mov_b32 s10, s6964; VI-NEXT:    s_mov_b32 s11, s7965; VI-NEXT:    s_waitcnt lgkmcnt(0)966; VI-NEXT:    s_mov_b32 s8, s2967; VI-NEXT:    s_mov_b32 s9, s3968; VI-NEXT:    buffer_load_dword v0, off, s[8:11], 0969; VI-NEXT:    s_mov_b32 s4, s0970; VI-NEXT:    s_mov_b32 s5, s1971; VI-NEXT:    s_waitcnt vmcnt(0)972; VI-NEXT:    v_add_f32_e32 v0, 0.5, v0973; VI-NEXT:    buffer_store_dword v0, off, s[4:7], 0974; VI-NEXT:    s_endpgm975;976; GFX942-LABEL: commute_add_inline_imm_0.5_f32:977; GFX942:       ; %bb.0:978; GFX942-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24979; GFX942-NEXT:    s_mov_b32 s7, 0xf000980; GFX942-NEXT:    s_mov_b32 s6, -1981; GFX942-NEXT:    s_mov_b32 s10, s6982; GFX942-NEXT:    s_mov_b32 s11, s7983; GFX942-NEXT:    s_waitcnt lgkmcnt(0)984; GFX942-NEXT:    s_mov_b32 s8, s2985; GFX942-NEXT:    s_mov_b32 s9, s3986; GFX942-NEXT:    buffer_load_dword v0, off, s[8:11], 0987; GFX942-NEXT:    s_mov_b32 s4, s0988; GFX942-NEXT:    s_mov_b32 s5, s1989; GFX942-NEXT:    s_waitcnt vmcnt(0)990; GFX942-NEXT:    v_add_f32_e32 v0, 0.5, v0991; GFX942-NEXT:    buffer_store_dword v0, off, s[4:7], 0992; GFX942-NEXT:    s_endpgm993  %x = load float, ptr addrspace(1) %in994  %y = fadd float %x, 0.5995  store float %y, ptr addrspace(1) %out996  ret void997}998 999define amdgpu_kernel void @commute_add_literal_f32(ptr addrspace(1) %out, ptr addrspace(1) %in) {1000; SI-LABEL: commute_add_literal_f32:1001; SI:       ; %bb.0:1002; SI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x91003; SI-NEXT:    s_mov_b32 s7, 0xf0001004; SI-NEXT:    s_mov_b32 s6, -11005; SI-NEXT:    s_mov_b32 s10, s61006; SI-NEXT:    s_mov_b32 s11, s71007; SI-NEXT:    s_waitcnt lgkmcnt(0)1008; SI-NEXT:    s_mov_b32 s8, s21009; SI-NEXT:    s_mov_b32 s9, s31010; SI-NEXT:    buffer_load_dword v0, off, s[8:11], 01011; SI-NEXT:    s_mov_b32 s4, s01012; SI-NEXT:    s_mov_b32 s5, s11013; SI-NEXT:    s_waitcnt vmcnt(0)1014; SI-NEXT:    v_add_f32_e32 v0, 0x44800000, v01015; SI-NEXT:    buffer_store_dword v0, off, s[4:7], 01016; SI-NEXT:    s_endpgm1017;1018; VI-LABEL: commute_add_literal_f32:1019; VI:       ; %bb.0:1020; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x241021; VI-NEXT:    s_mov_b32 s7, 0xf0001022; VI-NEXT:    s_mov_b32 s6, -11023; VI-NEXT:    s_mov_b32 s10, s61024; VI-NEXT:    s_mov_b32 s11, s71025; VI-NEXT:    s_waitcnt lgkmcnt(0)1026; VI-NEXT:    s_mov_b32 s8, s21027; VI-NEXT:    s_mov_b32 s9, s31028; VI-NEXT:    buffer_load_dword v0, off, s[8:11], 01029; VI-NEXT:    s_mov_b32 s4, s01030; VI-NEXT:    s_mov_b32 s5, s11031; VI-NEXT:    s_waitcnt vmcnt(0)1032; VI-NEXT:    v_add_f32_e32 v0, 0x44800000, v01033; VI-NEXT:    buffer_store_dword v0, off, s[4:7], 01034; VI-NEXT:    s_endpgm1035;1036; GFX942-LABEL: commute_add_literal_f32:1037; GFX942:       ; %bb.0:1038; GFX942-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x241039; GFX942-NEXT:    s_mov_b32 s7, 0xf0001040; GFX942-NEXT:    s_mov_b32 s6, -11041; GFX942-NEXT:    s_mov_b32 s10, s61042; GFX942-NEXT:    s_mov_b32 s11, s71043; GFX942-NEXT:    s_waitcnt lgkmcnt(0)1044; GFX942-NEXT:    s_mov_b32 s8, s21045; GFX942-NEXT:    s_mov_b32 s9, s31046; GFX942-NEXT:    buffer_load_dword v0, off, s[8:11], 01047; GFX942-NEXT:    s_mov_b32 s4, s01048; GFX942-NEXT:    s_mov_b32 s5, s11049; GFX942-NEXT:    s_waitcnt vmcnt(0)1050; GFX942-NEXT:    v_add_f32_e32 v0, 0x44800000, v01051; GFX942-NEXT:    buffer_store_dword v0, off, s[4:7], 01052; GFX942-NEXT:    s_endpgm1053  %x = load float, ptr addrspace(1) %in1054  %y = fadd float %x, 1024.01055  store float %y, ptr addrspace(1) %out1056  ret void1057}1058 1059define amdgpu_kernel void @add_inline_imm_1_f32(ptr addrspace(1) %out, float %x) {1060; SI-LABEL: add_inline_imm_1_f32:1061; SI:       ; %bb.0:1062; SI-NEXT:    s_load_dword s6, s[4:5], 0xb1063; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x91064; SI-NEXT:    s_mov_b32 s3, 0xf0001065; SI-NEXT:    s_mov_b32 s2, -11066; SI-NEXT:    s_waitcnt lgkmcnt(0)1067; SI-NEXT:    v_add_f32_e64 v0, s6, 11068; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 01069; SI-NEXT:    s_endpgm1070;1071; VI-LABEL: add_inline_imm_1_f32:1072; VI:       ; %bb.0:1073; VI-NEXT:    s_load_dword s6, s[4:5], 0x2c1074; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x241075; VI-NEXT:    s_mov_b32 s3, 0xf0001076; VI-NEXT:    s_mov_b32 s2, -11077; VI-NEXT:    s_waitcnt lgkmcnt(0)1078; VI-NEXT:    v_add_f32_e64 v0, s6, 11079; VI-NEXT:    buffer_store_dword v0, off, s[0:3], 01080; VI-NEXT:    s_endpgm1081;1082; GFX942-LABEL: add_inline_imm_1_f32:1083; GFX942:       ; %bb.0:1084; GFX942-NEXT:    s_load_dword s6, s[4:5], 0x2c1085; GFX942-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x241086; GFX942-NEXT:    s_mov_b32 s3, 0xf0001087; GFX942-NEXT:    s_mov_b32 s2, -11088; GFX942-NEXT:    s_waitcnt lgkmcnt(0)1089; GFX942-NEXT:    v_add_f32_e64 v0, s6, 11090; GFX942-NEXT:    buffer_store_dword v0, off, s[0:3], 01091; GFX942-NEXT:    s_endpgm1092  %y = fadd float %x, 0x36a00000000000001093  store float %y, ptr addrspace(1) %out1094  ret void1095}1096 1097define amdgpu_kernel void @add_inline_imm_2_f32(ptr addrspace(1) %out, float %x) {1098; SI-LABEL: add_inline_imm_2_f32:1099; SI:       ; %bb.0:1100; SI-NEXT:    s_load_dword s6, s[4:5], 0xb1101; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x91102; SI-NEXT:    s_mov_b32 s3, 0xf0001103; SI-NEXT:    s_mov_b32 s2, -11104; SI-NEXT:    s_waitcnt lgkmcnt(0)1105; SI-NEXT:    v_add_f32_e64 v0, s6, 21106; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 01107; SI-NEXT:    s_endpgm1108;1109; VI-LABEL: add_inline_imm_2_f32:1110; VI:       ; %bb.0:1111; VI-NEXT:    s_load_dword s6, s[4:5], 0x2c1112; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x241113; VI-NEXT:    s_mov_b32 s3, 0xf0001114; VI-NEXT:    s_mov_b32 s2, -11115; VI-NEXT:    s_waitcnt lgkmcnt(0)1116; VI-NEXT:    v_add_f32_e64 v0, s6, 21117; VI-NEXT:    buffer_store_dword v0, off, s[0:3], 01118; VI-NEXT:    s_endpgm1119;1120; GFX942-LABEL: add_inline_imm_2_f32:1121; GFX942:       ; %bb.0:1122; GFX942-NEXT:    s_load_dword s6, s[4:5], 0x2c1123; GFX942-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x241124; GFX942-NEXT:    s_mov_b32 s3, 0xf0001125; GFX942-NEXT:    s_mov_b32 s2, -11126; GFX942-NEXT:    s_waitcnt lgkmcnt(0)1127; GFX942-NEXT:    v_add_f32_e64 v0, s6, 21128; GFX942-NEXT:    buffer_store_dword v0, off, s[0:3], 01129; GFX942-NEXT:    s_endpgm1130  %y = fadd float %x, 0x36b00000000000001131  store float %y, ptr addrspace(1) %out1132  ret void1133}1134 1135define amdgpu_kernel void @add_inline_imm_16_f32(ptr addrspace(1) %out, float %x) {1136; SI-LABEL: add_inline_imm_16_f32:1137; SI:       ; %bb.0:1138; SI-NEXT:    s_load_dword s6, s[4:5], 0xb1139; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x91140; SI-NEXT:    s_mov_b32 s3, 0xf0001141; SI-NEXT:    s_mov_b32 s2, -11142; SI-NEXT:    s_waitcnt lgkmcnt(0)1143; SI-NEXT:    v_add_f32_e64 v0, s6, 161144; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 01145; SI-NEXT:    s_endpgm1146;1147; VI-LABEL: add_inline_imm_16_f32:1148; VI:       ; %bb.0:1149; VI-NEXT:    s_load_dword s6, s[4:5], 0x2c1150; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x241151; VI-NEXT:    s_mov_b32 s3, 0xf0001152; VI-NEXT:    s_mov_b32 s2, -11153; VI-NEXT:    s_waitcnt lgkmcnt(0)1154; VI-NEXT:    v_add_f32_e64 v0, s6, 161155; VI-NEXT:    buffer_store_dword v0, off, s[0:3], 01156; VI-NEXT:    s_endpgm1157;1158; GFX942-LABEL: add_inline_imm_16_f32:1159; GFX942:       ; %bb.0:1160; GFX942-NEXT:    s_load_dword s6, s[4:5], 0x2c1161; GFX942-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x241162; GFX942-NEXT:    s_mov_b32 s3, 0xf0001163; GFX942-NEXT:    s_mov_b32 s2, -11164; GFX942-NEXT:    s_waitcnt lgkmcnt(0)1165; GFX942-NEXT:    v_add_f32_e64 v0, s6, 161166; GFX942-NEXT:    buffer_store_dword v0, off, s[0:3], 01167; GFX942-NEXT:    s_endpgm1168  %y = fadd float %x, 0x36e00000000000001169  store float %y, ptr addrspace(1) %out1170  ret void1171}1172 1173define amdgpu_kernel void @add_inline_imm_neg_1_f32(ptr addrspace(1) %out, float %x) {1174; SI-LABEL: add_inline_imm_neg_1_f32:1175; SI:       ; %bb.0:1176; SI-NEXT:    s_load_dword s6, s[4:5], 0xb1177; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x91178; SI-NEXT:    s_mov_b32 s3, 0xf0001179; SI-NEXT:    s_mov_b32 s2, -11180; SI-NEXT:    s_waitcnt lgkmcnt(0)1181; SI-NEXT:    s_add_i32 s4, s6, -11182; SI-NEXT:    v_mov_b32_e32 v0, s41183; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 01184; SI-NEXT:    s_endpgm1185;1186; VI-LABEL: add_inline_imm_neg_1_f32:1187; VI:       ; %bb.0:1188; VI-NEXT:    s_load_dword s6, s[4:5], 0x2c1189; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x241190; VI-NEXT:    s_mov_b32 s3, 0xf0001191; VI-NEXT:    s_mov_b32 s2, -11192; VI-NEXT:    s_waitcnt lgkmcnt(0)1193; VI-NEXT:    s_add_i32 s4, s6, -11194; VI-NEXT:    v_mov_b32_e32 v0, s41195; VI-NEXT:    buffer_store_dword v0, off, s[0:3], 01196; VI-NEXT:    s_endpgm1197;1198; GFX942-LABEL: add_inline_imm_neg_1_f32:1199; GFX942:       ; %bb.0:1200; GFX942-NEXT:    s_load_dword s6, s[4:5], 0x2c1201; GFX942-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x241202; GFX942-NEXT:    s_mov_b32 s3, 0xf0001203; GFX942-NEXT:    s_mov_b32 s2, -11204; GFX942-NEXT:    s_waitcnt lgkmcnt(0)1205; GFX942-NEXT:    s_add_i32 s4, s6, -11206; GFX942-NEXT:    v_mov_b32_e32 v0, s41207; GFX942-NEXT:    buffer_store_dword v0, off, s[0:3], 01208; GFX942-NEXT:    s_endpgm1209  %xbc = bitcast float %x to i321210  %y = add i32 %xbc, -11211  %ybc = bitcast i32 %y to float1212  store float %ybc, ptr addrspace(1) %out1213  ret void1214}1215 1216define amdgpu_kernel void @add_inline_imm_neg_2_f32(ptr addrspace(1) %out, float %x) {1217; SI-LABEL: add_inline_imm_neg_2_f32:1218; SI:       ; %bb.0:1219; SI-NEXT:    s_load_dword s6, s[4:5], 0xb1220; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x91221; SI-NEXT:    s_mov_b32 s3, 0xf0001222; SI-NEXT:    s_mov_b32 s2, -11223; SI-NEXT:    s_waitcnt lgkmcnt(0)1224; SI-NEXT:    s_add_i32 s4, s6, -21225; SI-NEXT:    v_mov_b32_e32 v0, s41226; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 01227; SI-NEXT:    s_endpgm1228;1229; VI-LABEL: add_inline_imm_neg_2_f32:1230; VI:       ; %bb.0:1231; VI-NEXT:    s_load_dword s6, s[4:5], 0x2c1232; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x241233; VI-NEXT:    s_mov_b32 s3, 0xf0001234; VI-NEXT:    s_mov_b32 s2, -11235; VI-NEXT:    s_waitcnt lgkmcnt(0)1236; VI-NEXT:    s_add_i32 s4, s6, -21237; VI-NEXT:    v_mov_b32_e32 v0, s41238; VI-NEXT:    buffer_store_dword v0, off, s[0:3], 01239; VI-NEXT:    s_endpgm1240;1241; GFX942-LABEL: add_inline_imm_neg_2_f32:1242; GFX942:       ; %bb.0:1243; GFX942-NEXT:    s_load_dword s6, s[4:5], 0x2c1244; GFX942-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x241245; GFX942-NEXT:    s_mov_b32 s3, 0xf0001246; GFX942-NEXT:    s_mov_b32 s2, -11247; GFX942-NEXT:    s_waitcnt lgkmcnt(0)1248; GFX942-NEXT:    s_add_i32 s4, s6, -21249; GFX942-NEXT:    v_mov_b32_e32 v0, s41250; GFX942-NEXT:    buffer_store_dword v0, off, s[0:3], 01251; GFX942-NEXT:    s_endpgm1252  %xbc = bitcast float %x to i321253  %y = add i32 %xbc, -21254  %ybc = bitcast i32 %y to float1255  store float %ybc, ptr addrspace(1) %out1256  ret void1257}1258 1259define amdgpu_kernel void @add_inline_imm_neg_16_f32(ptr addrspace(1) %out, float %x) {1260; SI-LABEL: add_inline_imm_neg_16_f32:1261; SI:       ; %bb.0:1262; SI-NEXT:    s_load_dword s6, s[4:5], 0xb1263; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x91264; SI-NEXT:    s_mov_b32 s3, 0xf0001265; SI-NEXT:    s_mov_b32 s2, -11266; SI-NEXT:    s_waitcnt lgkmcnt(0)1267; SI-NEXT:    s_add_i32 s4, s6, -161268; SI-NEXT:    v_mov_b32_e32 v0, s41269; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 01270; SI-NEXT:    s_endpgm1271;1272; VI-LABEL: add_inline_imm_neg_16_f32:1273; VI:       ; %bb.0:1274; VI-NEXT:    s_load_dword s6, s[4:5], 0x2c1275; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x241276; VI-NEXT:    s_mov_b32 s3, 0xf0001277; VI-NEXT:    s_mov_b32 s2, -11278; VI-NEXT:    s_waitcnt lgkmcnt(0)1279; VI-NEXT:    s_add_i32 s4, s6, -161280; VI-NEXT:    v_mov_b32_e32 v0, s41281; VI-NEXT:    buffer_store_dword v0, off, s[0:3], 01282; VI-NEXT:    s_endpgm1283;1284; GFX942-LABEL: add_inline_imm_neg_16_f32:1285; GFX942:       ; %bb.0:1286; GFX942-NEXT:    s_load_dword s6, s[4:5], 0x2c1287; GFX942-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x241288; GFX942-NEXT:    s_mov_b32 s3, 0xf0001289; GFX942-NEXT:    s_mov_b32 s2, -11290; GFX942-NEXT:    s_waitcnt lgkmcnt(0)1291; GFX942-NEXT:    s_add_i32 s4, s6, -161292; GFX942-NEXT:    v_mov_b32_e32 v0, s41293; GFX942-NEXT:    buffer_store_dword v0, off, s[0:3], 01294; GFX942-NEXT:    s_endpgm1295  %xbc = bitcast float %x to i321296  %y = add i32 %xbc, -161297  %ybc = bitcast i32 %y to float1298  store float %ybc, ptr addrspace(1) %out1299  ret void1300}1301 1302define amdgpu_kernel void @add_inline_imm_63_f32(ptr addrspace(1) %out, float %x) {1303; SI-LABEL: add_inline_imm_63_f32:1304; SI:       ; %bb.0:1305; SI-NEXT:    s_load_dword s6, s[4:5], 0xb1306; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x91307; SI-NEXT:    s_mov_b32 s3, 0xf0001308; SI-NEXT:    s_mov_b32 s2, -11309; SI-NEXT:    s_waitcnt lgkmcnt(0)1310; SI-NEXT:    v_add_f32_e64 v0, s6, 631311; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 01312; SI-NEXT:    s_endpgm1313;1314; VI-LABEL: add_inline_imm_63_f32:1315; VI:       ; %bb.0:1316; VI-NEXT:    s_load_dword s6, s[4:5], 0x2c1317; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x241318; VI-NEXT:    s_mov_b32 s3, 0xf0001319; VI-NEXT:    s_mov_b32 s2, -11320; VI-NEXT:    s_waitcnt lgkmcnt(0)1321; VI-NEXT:    v_add_f32_e64 v0, s6, 631322; VI-NEXT:    buffer_store_dword v0, off, s[0:3], 01323; VI-NEXT:    s_endpgm1324;1325; GFX942-LABEL: add_inline_imm_63_f32:1326; GFX942:       ; %bb.0:1327; GFX942-NEXT:    s_load_dword s6, s[4:5], 0x2c1328; GFX942-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x241329; GFX942-NEXT:    s_mov_b32 s3, 0xf0001330; GFX942-NEXT:    s_mov_b32 s2, -11331; GFX942-NEXT:    s_waitcnt lgkmcnt(0)1332; GFX942-NEXT:    v_add_f32_e64 v0, s6, 631333; GFX942-NEXT:    buffer_store_dword v0, off, s[0:3], 01334; GFX942-NEXT:    s_endpgm1335  %y = fadd float %x, 0x36ff8000000000001336  store float %y, ptr addrspace(1) %out1337  ret void1338}1339 1340define amdgpu_kernel void @add_inline_imm_64_f32(ptr addrspace(1) %out, float %x) {1341; SI-LABEL: add_inline_imm_64_f32:1342; SI:       ; %bb.0:1343; SI-NEXT:    s_load_dword s6, s[4:5], 0xb1344; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x91345; SI-NEXT:    s_mov_b32 s3, 0xf0001346; SI-NEXT:    s_mov_b32 s2, -11347; SI-NEXT:    s_waitcnt lgkmcnt(0)1348; SI-NEXT:    v_add_f32_e64 v0, s6, 641349; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 01350; SI-NEXT:    s_endpgm1351;1352; VI-LABEL: add_inline_imm_64_f32:1353; VI:       ; %bb.0:1354; VI-NEXT:    s_load_dword s6, s[4:5], 0x2c1355; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x241356; VI-NEXT:    s_mov_b32 s3, 0xf0001357; VI-NEXT:    s_mov_b32 s2, -11358; VI-NEXT:    s_waitcnt lgkmcnt(0)1359; VI-NEXT:    v_add_f32_e64 v0, s6, 641360; VI-NEXT:    buffer_store_dword v0, off, s[0:3], 01361; VI-NEXT:    s_endpgm1362;1363; GFX942-LABEL: add_inline_imm_64_f32:1364; GFX942:       ; %bb.0:1365; GFX942-NEXT:    s_load_dword s6, s[4:5], 0x2c1366; GFX942-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x241367; GFX942-NEXT:    s_mov_b32 s3, 0xf0001368; GFX942-NEXT:    s_mov_b32 s2, -11369; GFX942-NEXT:    s_waitcnt lgkmcnt(0)1370; GFX942-NEXT:    v_add_f32_e64 v0, s6, 641371; GFX942-NEXT:    buffer_store_dword v0, off, s[0:3], 01372; GFX942-NEXT:    s_endpgm1373  %y = fadd float %x, 0x37000000000000001374  store float %y, ptr addrspace(1) %out1375  ret void1376}1377 1378define amdgpu_kernel void @add_inline_imm_0.0_f64(ptr addrspace(1) %out, [8 x i32], double %x) {1379; SI-LABEL: add_inline_imm_0.0_f64:1380; SI:       ; %bb.0:1381; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x131382; SI-NEXT:    s_mov_b32 s3, 0xf0001383; SI-NEXT:    s_mov_b32 s2, -11384; SI-NEXT:    s_waitcnt lgkmcnt(0)1385; SI-NEXT:    v_add_f64 v[0:1], s[0:1], 01386; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x91387; SI-NEXT:    s_waitcnt lgkmcnt(0)1388; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 01389; SI-NEXT:    s_endpgm1390;1391; VI-LABEL: add_inline_imm_0.0_f64:1392; VI:       ; %bb.0:1393; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x4c1394; VI-NEXT:    s_mov_b32 s3, 0xf0001395; VI-NEXT:    s_mov_b32 s2, -11396; VI-NEXT:    s_waitcnt lgkmcnt(0)1397; VI-NEXT:    v_add_f64 v[0:1], s[0:1], 01398; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x241399; VI-NEXT:    s_waitcnt lgkmcnt(0)1400; VI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 01401; VI-NEXT:    s_endpgm1402;1403; GFX942-LABEL: add_inline_imm_0.0_f64:1404; GFX942:       ; %bb.0:1405; GFX942-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x4c1406; GFX942-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x241407; GFX942-NEXT:    s_mov_b32 s3, 0xf0001408; GFX942-NEXT:    s_mov_b32 s2, -11409; GFX942-NEXT:    s_waitcnt lgkmcnt(0)1410; GFX942-NEXT:    v_add_f64 v[0:1], s[6:7], 01411; GFX942-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 01412; GFX942-NEXT:    s_endpgm1413  %y = fadd double %x, 0.01414  store double %y, ptr addrspace(1) %out1415  ret void1416}1417 1418define amdgpu_kernel void @add_inline_imm_0.5_f64(ptr addrspace(1) %out, [8 x i32], double %x) {1419; SI-LABEL: add_inline_imm_0.5_f64:1420; SI:       ; %bb.0:1421; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x131422; SI-NEXT:    s_mov_b32 s3, 0xf0001423; SI-NEXT:    s_mov_b32 s2, -11424; SI-NEXT:    s_waitcnt lgkmcnt(0)1425; SI-NEXT:    v_add_f64 v[0:1], s[0:1], 0.51426; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x91427; SI-NEXT:    s_waitcnt lgkmcnt(0)1428; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 01429; SI-NEXT:    s_endpgm1430;1431; VI-LABEL: add_inline_imm_0.5_f64:1432; VI:       ; %bb.0:1433; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x4c1434; VI-NEXT:    s_mov_b32 s3, 0xf0001435; VI-NEXT:    s_mov_b32 s2, -11436; VI-NEXT:    s_waitcnt lgkmcnt(0)1437; VI-NEXT:    v_add_f64 v[0:1], s[0:1], 0.51438; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x241439; VI-NEXT:    s_waitcnt lgkmcnt(0)1440; VI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 01441; VI-NEXT:    s_endpgm1442;1443; GFX942-LABEL: add_inline_imm_0.5_f64:1444; GFX942:       ; %bb.0:1445; GFX942-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x4c1446; GFX942-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x241447; GFX942-NEXT:    s_mov_b32 s3, 0xf0001448; GFX942-NEXT:    s_mov_b32 s2, -11449; GFX942-NEXT:    s_waitcnt lgkmcnt(0)1450; GFX942-NEXT:    v_add_f64 v[0:1], s[6:7], 0.51451; GFX942-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 01452; GFX942-NEXT:    s_endpgm1453  %y = fadd double %x, 0.51454  store double %y, ptr addrspace(1) %out1455  ret void1456}1457 1458define amdgpu_kernel void @add_inline_imm_neg_0.5_f64(ptr addrspace(1) %out, [8 x i32], double %x) {1459; SI-LABEL: add_inline_imm_neg_0.5_f64:1460; SI:       ; %bb.0:1461; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x131462; SI-NEXT:    s_mov_b32 s3, 0xf0001463; SI-NEXT:    s_mov_b32 s2, -11464; SI-NEXT:    s_waitcnt lgkmcnt(0)1465; SI-NEXT:    v_add_f64 v[0:1], s[0:1], -0.51466; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x91467; SI-NEXT:    s_waitcnt lgkmcnt(0)1468; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 01469; SI-NEXT:    s_endpgm1470;1471; VI-LABEL: add_inline_imm_neg_0.5_f64:1472; VI:       ; %bb.0:1473; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x4c1474; VI-NEXT:    s_mov_b32 s3, 0xf0001475; VI-NEXT:    s_mov_b32 s2, -11476; VI-NEXT:    s_waitcnt lgkmcnt(0)1477; VI-NEXT:    v_add_f64 v[0:1], s[0:1], -0.51478; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x241479; VI-NEXT:    s_waitcnt lgkmcnt(0)1480; VI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 01481; VI-NEXT:    s_endpgm1482;1483; GFX942-LABEL: add_inline_imm_neg_0.5_f64:1484; GFX942:       ; %bb.0:1485; GFX942-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x4c1486; GFX942-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x241487; GFX942-NEXT:    s_mov_b32 s3, 0xf0001488; GFX942-NEXT:    s_mov_b32 s2, -11489; GFX942-NEXT:    s_waitcnt lgkmcnt(0)1490; GFX942-NEXT:    v_add_f64 v[0:1], s[6:7], -0.51491; GFX942-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 01492; GFX942-NEXT:    s_endpgm1493  %y = fadd double %x, -0.51494  store double %y, ptr addrspace(1) %out1495  ret void1496}1497 1498define amdgpu_kernel void @add_inline_imm_1.0_f64(ptr addrspace(1) %out, [8 x i32], double %x) {1499; SI-LABEL: add_inline_imm_1.0_f64:1500; SI:       ; %bb.0:1501; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x131502; SI-NEXT:    s_mov_b32 s3, 0xf0001503; SI-NEXT:    s_mov_b32 s2, -11504; SI-NEXT:    s_waitcnt lgkmcnt(0)1505; SI-NEXT:    v_add_f64 v[0:1], s[0:1], 1.01506; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x91507; SI-NEXT:    s_waitcnt lgkmcnt(0)1508; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 01509; SI-NEXT:    s_endpgm1510;1511; VI-LABEL: add_inline_imm_1.0_f64:1512; VI:       ; %bb.0:1513; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x4c1514; VI-NEXT:    s_mov_b32 s3, 0xf0001515; VI-NEXT:    s_mov_b32 s2, -11516; VI-NEXT:    s_waitcnt lgkmcnt(0)1517; VI-NEXT:    v_add_f64 v[0:1], s[0:1], 1.01518; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x241519; VI-NEXT:    s_waitcnt lgkmcnt(0)1520; VI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 01521; VI-NEXT:    s_endpgm1522;1523; GFX942-LABEL: add_inline_imm_1.0_f64:1524; GFX942:       ; %bb.0:1525; GFX942-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x4c1526; GFX942-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x241527; GFX942-NEXT:    s_mov_b32 s3, 0xf0001528; GFX942-NEXT:    s_mov_b32 s2, -11529; GFX942-NEXT:    s_waitcnt lgkmcnt(0)1530; GFX942-NEXT:    v_add_f64 v[0:1], s[6:7], 1.01531; GFX942-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 01532; GFX942-NEXT:    s_endpgm1533  %y = fadd double %x, 1.01534  store double %y, ptr addrspace(1) %out1535  ret void1536}1537 1538define amdgpu_kernel void @add_inline_imm_neg_1.0_f64(ptr addrspace(1) %out, [8 x i32], double %x) {1539; SI-LABEL: add_inline_imm_neg_1.0_f64:1540; SI:       ; %bb.0:1541; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x131542; SI-NEXT:    s_mov_b32 s3, 0xf0001543; SI-NEXT:    s_mov_b32 s2, -11544; SI-NEXT:    s_waitcnt lgkmcnt(0)1545; SI-NEXT:    v_add_f64 v[0:1], s[0:1], -1.01546; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x91547; SI-NEXT:    s_waitcnt lgkmcnt(0)1548; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 01549; SI-NEXT:    s_endpgm1550;1551; VI-LABEL: add_inline_imm_neg_1.0_f64:1552; VI:       ; %bb.0:1553; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x4c1554; VI-NEXT:    s_mov_b32 s3, 0xf0001555; VI-NEXT:    s_mov_b32 s2, -11556; VI-NEXT:    s_waitcnt lgkmcnt(0)1557; VI-NEXT:    v_add_f64 v[0:1], s[0:1], -1.01558; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x241559; VI-NEXT:    s_waitcnt lgkmcnt(0)1560; VI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 01561; VI-NEXT:    s_endpgm1562;1563; GFX942-LABEL: add_inline_imm_neg_1.0_f64:1564; GFX942:       ; %bb.0:1565; GFX942-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x4c1566; GFX942-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x241567; GFX942-NEXT:    s_mov_b32 s3, 0xf0001568; GFX942-NEXT:    s_mov_b32 s2, -11569; GFX942-NEXT:    s_waitcnt lgkmcnt(0)1570; GFX942-NEXT:    v_add_f64 v[0:1], s[6:7], -1.01571; GFX942-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 01572; GFX942-NEXT:    s_endpgm1573  %y = fadd double %x, -1.01574  store double %y, ptr addrspace(1) %out1575  ret void1576}1577 1578define amdgpu_kernel void @add_inline_imm_2.0_f64(ptr addrspace(1) %out, [8 x i32], double %x) {1579; SI-LABEL: add_inline_imm_2.0_f64:1580; SI:       ; %bb.0:1581; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x131582; SI-NEXT:    s_mov_b32 s3, 0xf0001583; SI-NEXT:    s_mov_b32 s2, -11584; SI-NEXT:    s_waitcnt lgkmcnt(0)1585; SI-NEXT:    v_add_f64 v[0:1], s[0:1], 2.01586; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x91587; SI-NEXT:    s_waitcnt lgkmcnt(0)1588; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 01589; SI-NEXT:    s_endpgm1590;1591; VI-LABEL: add_inline_imm_2.0_f64:1592; VI:       ; %bb.0:1593; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x4c1594; VI-NEXT:    s_mov_b32 s3, 0xf0001595; VI-NEXT:    s_mov_b32 s2, -11596; VI-NEXT:    s_waitcnt lgkmcnt(0)1597; VI-NEXT:    v_add_f64 v[0:1], s[0:1], 2.01598; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x241599; VI-NEXT:    s_waitcnt lgkmcnt(0)1600; VI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 01601; VI-NEXT:    s_endpgm1602;1603; GFX942-LABEL: add_inline_imm_2.0_f64:1604; GFX942:       ; %bb.0:1605; GFX942-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x4c1606; GFX942-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x241607; GFX942-NEXT:    s_mov_b32 s3, 0xf0001608; GFX942-NEXT:    s_mov_b32 s2, -11609; GFX942-NEXT:    s_waitcnt lgkmcnt(0)1610; GFX942-NEXT:    v_add_f64 v[0:1], s[6:7], 2.01611; GFX942-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 01612; GFX942-NEXT:    s_endpgm1613  %y = fadd double %x, 2.01614  store double %y, ptr addrspace(1) %out1615  ret void1616}1617 1618define amdgpu_kernel void @add_inline_imm_neg_2.0_f64(ptr addrspace(1) %out, [8 x i32], double %x) {1619; SI-LABEL: add_inline_imm_neg_2.0_f64:1620; SI:       ; %bb.0:1621; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x131622; SI-NEXT:    s_mov_b32 s3, 0xf0001623; SI-NEXT:    s_mov_b32 s2, -11624; SI-NEXT:    s_waitcnt lgkmcnt(0)1625; SI-NEXT:    v_add_f64 v[0:1], s[0:1], -2.01626; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x91627; SI-NEXT:    s_waitcnt lgkmcnt(0)1628; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 01629; SI-NEXT:    s_endpgm1630;1631; VI-LABEL: add_inline_imm_neg_2.0_f64:1632; VI:       ; %bb.0:1633; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x4c1634; VI-NEXT:    s_mov_b32 s3, 0xf0001635; VI-NEXT:    s_mov_b32 s2, -11636; VI-NEXT:    s_waitcnt lgkmcnt(0)1637; VI-NEXT:    v_add_f64 v[0:1], s[0:1], -2.01638; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x241639; VI-NEXT:    s_waitcnt lgkmcnt(0)1640; VI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 01641; VI-NEXT:    s_endpgm1642;1643; GFX942-LABEL: add_inline_imm_neg_2.0_f64:1644; GFX942:       ; %bb.0:1645; GFX942-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x4c1646; GFX942-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x241647; GFX942-NEXT:    s_mov_b32 s3, 0xf0001648; GFX942-NEXT:    s_mov_b32 s2, -11649; GFX942-NEXT:    s_waitcnt lgkmcnt(0)1650; GFX942-NEXT:    v_add_f64 v[0:1], s[6:7], -2.01651; GFX942-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 01652; GFX942-NEXT:    s_endpgm1653  %y = fadd double %x, -2.01654  store double %y, ptr addrspace(1) %out1655  ret void1656}1657 1658define amdgpu_kernel void @add_inline_imm_4.0_f64(ptr addrspace(1) %out, [8 x i32], double %x) {1659; SI-LABEL: add_inline_imm_4.0_f64:1660; SI:       ; %bb.0:1661; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x131662; SI-NEXT:    s_mov_b32 s3, 0xf0001663; SI-NEXT:    s_mov_b32 s2, -11664; SI-NEXT:    s_waitcnt lgkmcnt(0)1665; SI-NEXT:    v_add_f64 v[0:1], s[0:1], 4.01666; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x91667; SI-NEXT:    s_waitcnt lgkmcnt(0)1668; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 01669; SI-NEXT:    s_endpgm1670;1671; VI-LABEL: add_inline_imm_4.0_f64:1672; VI:       ; %bb.0:1673; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x4c1674; VI-NEXT:    s_mov_b32 s3, 0xf0001675; VI-NEXT:    s_mov_b32 s2, -11676; VI-NEXT:    s_waitcnt lgkmcnt(0)1677; VI-NEXT:    v_add_f64 v[0:1], s[0:1], 4.01678; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x241679; VI-NEXT:    s_waitcnt lgkmcnt(0)1680; VI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 01681; VI-NEXT:    s_endpgm1682;1683; GFX942-LABEL: add_inline_imm_4.0_f64:1684; GFX942:       ; %bb.0:1685; GFX942-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x4c1686; GFX942-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x241687; GFX942-NEXT:    s_mov_b32 s3, 0xf0001688; GFX942-NEXT:    s_mov_b32 s2, -11689; GFX942-NEXT:    s_waitcnt lgkmcnt(0)1690; GFX942-NEXT:    v_add_f64 v[0:1], s[6:7], 4.01691; GFX942-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 01692; GFX942-NEXT:    s_endpgm1693  %y = fadd double %x, 4.01694  store double %y, ptr addrspace(1) %out1695  ret void1696}1697 1698define amdgpu_kernel void @add_inline_imm_neg_4.0_f64(ptr addrspace(1) %out, [8 x i32], double %x) {1699; SI-LABEL: add_inline_imm_neg_4.0_f64:1700; SI:       ; %bb.0:1701; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x131702; SI-NEXT:    s_mov_b32 s3, 0xf0001703; SI-NEXT:    s_mov_b32 s2, -11704; SI-NEXT:    s_waitcnt lgkmcnt(0)1705; SI-NEXT:    v_add_f64 v[0:1], s[0:1], -4.01706; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x91707; SI-NEXT:    s_waitcnt lgkmcnt(0)1708; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 01709; SI-NEXT:    s_endpgm1710;1711; VI-LABEL: add_inline_imm_neg_4.0_f64:1712; VI:       ; %bb.0:1713; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x4c1714; VI-NEXT:    s_mov_b32 s3, 0xf0001715; VI-NEXT:    s_mov_b32 s2, -11716; VI-NEXT:    s_waitcnt lgkmcnt(0)1717; VI-NEXT:    v_add_f64 v[0:1], s[0:1], -4.01718; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x241719; VI-NEXT:    s_waitcnt lgkmcnt(0)1720; VI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 01721; VI-NEXT:    s_endpgm1722;1723; GFX942-LABEL: add_inline_imm_neg_4.0_f64:1724; GFX942:       ; %bb.0:1725; GFX942-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x4c1726; GFX942-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x241727; GFX942-NEXT:    s_mov_b32 s3, 0xf0001728; GFX942-NEXT:    s_mov_b32 s2, -11729; GFX942-NEXT:    s_waitcnt lgkmcnt(0)1730; GFX942-NEXT:    v_add_f64 v[0:1], s[6:7], -4.01731; GFX942-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 01732; GFX942-NEXT:    s_endpgm1733  %y = fadd double %x, -4.01734  store double %y, ptr addrspace(1) %out1735  ret void1736}1737 1738define amdgpu_kernel void @add_inline_imm_inv_2pi_f64(ptr addrspace(1) %out, [8 x i32], double %x) {1739; SI-LABEL: add_inline_imm_inv_2pi_f64:1740; SI:       ; %bb.0:1741; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x131742; SI-NEXT:    v_mov_b32_e32 v0, 0x6dc9c8821743; SI-NEXT:    v_mov_b32_e32 v1, 0x3fc45f301744; SI-NEXT:    s_mov_b32 s3, 0xf0001745; SI-NEXT:    s_mov_b32 s2, -11746; SI-NEXT:    s_waitcnt lgkmcnt(0)1747; SI-NEXT:    v_add_f64 v[0:1], s[0:1], v[0:1]1748; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x91749; SI-NEXT:    s_waitcnt lgkmcnt(0)1750; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 01751; SI-NEXT:    s_endpgm1752;1753; VI-LABEL: add_inline_imm_inv_2pi_f64:1754; VI:       ; %bb.0:1755; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x4c1756; VI-NEXT:    s_mov_b32 s3, 0xf0001757; VI-NEXT:    s_mov_b32 s2, -11758; VI-NEXT:    s_waitcnt lgkmcnt(0)1759; VI-NEXT:    v_add_f64 v[0:1], s[0:1], 0.159154943091895321760; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x241761; VI-NEXT:    s_waitcnt lgkmcnt(0)1762; VI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 01763; VI-NEXT:    s_endpgm1764;1765; GFX942-LABEL: add_inline_imm_inv_2pi_f64:1766; GFX942:       ; %bb.0:1767; GFX942-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x4c1768; GFX942-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x241769; GFX942-NEXT:    s_mov_b32 s3, 0xf0001770; GFX942-NEXT:    s_mov_b32 s2, -11771; GFX942-NEXT:    s_waitcnt lgkmcnt(0)1772; GFX942-NEXT:    v_add_f64 v[0:1], s[6:7], 0.159154943091895321773; GFX942-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 01774; GFX942-NEXT:    s_endpgm1775  %y = fadd double %x, 0x3fc45f306dc9c8821776  store double %y, ptr addrspace(1) %out1777  ret void1778}1779 1780define amdgpu_kernel void @add_m_inv_2pi_f64(ptr addrspace(1) %out, [8 x i32], double %x) {1781; SI-LABEL: add_m_inv_2pi_f64:1782; SI:       ; %bb.0:1783; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x131784; SI-NEXT:    v_mov_b32_e32 v0, 0x6dc9c8821785; SI-NEXT:    v_mov_b32_e32 v1, 0xbfc45f301786; SI-NEXT:    s_mov_b32 s3, 0xf0001787; SI-NEXT:    s_mov_b32 s2, -11788; SI-NEXT:    s_waitcnt lgkmcnt(0)1789; SI-NEXT:    v_add_f64 v[0:1], s[0:1], v[0:1]1790; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x91791; SI-NEXT:    s_waitcnt lgkmcnt(0)1792; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 01793; SI-NEXT:    s_endpgm1794;1795; VI-LABEL: add_m_inv_2pi_f64:1796; VI:       ; %bb.0:1797; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x4c1798; VI-NEXT:    v_mov_b32_e32 v0, 0x6dc9c8821799; VI-NEXT:    v_mov_b32_e32 v1, 0xbfc45f301800; VI-NEXT:    s_mov_b32 s3, 0xf0001801; VI-NEXT:    s_mov_b32 s2, -11802; VI-NEXT:    s_waitcnt lgkmcnt(0)1803; VI-NEXT:    v_add_f64 v[0:1], s[0:1], v[0:1]1804; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x241805; VI-NEXT:    s_waitcnt lgkmcnt(0)1806; VI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 01807; VI-NEXT:    s_endpgm1808;1809; GFX942-LABEL: add_m_inv_2pi_f64:1810; GFX942:       ; %bb.0:1811; GFX942-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x241812; GFX942-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x4c1813; GFX942-NEXT:    v_mov_b32_e32 v0, 0x6dc9c8821814; GFX942-NEXT:    v_mov_b32_e32 v1, 0xbfc45f301815; GFX942-NEXT:    s_mov_b32 s3, 0xf0001816; GFX942-NEXT:    s_mov_b32 s2, -11817; GFX942-NEXT:    s_waitcnt lgkmcnt(0)1818; GFX942-NEXT:    v_add_f64 v[0:1], s[6:7], v[0:1]1819; GFX942-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 01820; GFX942-NEXT:    s_endpgm1821  %y = fadd double %x, 0xbfc45f306dc9c8821822  store double %y, ptr addrspace(1) %out1823  ret void1824}1825 1826define amdgpu_kernel void @add_inline_imm_1_f64(ptr addrspace(1) %out, [8 x i32], double %x) {1827; SI-LABEL: add_inline_imm_1_f64:1828; SI:       ; %bb.0:1829; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x131830; SI-NEXT:    s_mov_b32 s3, 0xf0001831; SI-NEXT:    s_mov_b32 s2, -11832; SI-NEXT:    s_waitcnt lgkmcnt(0)1833; SI-NEXT:    v_add_f64 v[0:1], s[0:1], 11834; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x91835; SI-NEXT:    s_waitcnt lgkmcnt(0)1836; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 01837; SI-NEXT:    s_endpgm1838;1839; VI-LABEL: add_inline_imm_1_f64:1840; VI:       ; %bb.0:1841; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x4c1842; VI-NEXT:    s_mov_b32 s3, 0xf0001843; VI-NEXT:    s_mov_b32 s2, -11844; VI-NEXT:    s_waitcnt lgkmcnt(0)1845; VI-NEXT:    v_add_f64 v[0:1], s[0:1], 11846; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x241847; VI-NEXT:    s_waitcnt lgkmcnt(0)1848; VI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 01849; VI-NEXT:    s_endpgm1850;1851; GFX942-LABEL: add_inline_imm_1_f64:1852; GFX942:       ; %bb.0:1853; GFX942-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x4c1854; GFX942-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x241855; GFX942-NEXT:    s_mov_b32 s3, 0xf0001856; GFX942-NEXT:    s_mov_b32 s2, -11857; GFX942-NEXT:    s_waitcnt lgkmcnt(0)1858; GFX942-NEXT:    v_add_f64 v[0:1], s[6:7], 11859; GFX942-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 01860; GFX942-NEXT:    s_endpgm1861  %y = fadd double %x, 0x00000000000000011862  store double %y, ptr addrspace(1) %out1863  ret void1864}1865 1866define amdgpu_kernel void @add_inline_imm_2_f64(ptr addrspace(1) %out, [8 x i32], double %x) {1867; SI-LABEL: add_inline_imm_2_f64:1868; SI:       ; %bb.0:1869; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x131870; SI-NEXT:    s_mov_b32 s3, 0xf0001871; SI-NEXT:    s_mov_b32 s2, -11872; SI-NEXT:    s_waitcnt lgkmcnt(0)1873; SI-NEXT:    v_add_f64 v[0:1], s[0:1], 21874; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x91875; SI-NEXT:    s_waitcnt lgkmcnt(0)1876; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 01877; SI-NEXT:    s_endpgm1878;1879; VI-LABEL: add_inline_imm_2_f64:1880; VI:       ; %bb.0:1881; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x4c1882; VI-NEXT:    s_mov_b32 s3, 0xf0001883; VI-NEXT:    s_mov_b32 s2, -11884; VI-NEXT:    s_waitcnt lgkmcnt(0)1885; VI-NEXT:    v_add_f64 v[0:1], s[0:1], 21886; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x241887; VI-NEXT:    s_waitcnt lgkmcnt(0)1888; VI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 01889; VI-NEXT:    s_endpgm1890;1891; GFX942-LABEL: add_inline_imm_2_f64:1892; GFX942:       ; %bb.0:1893; GFX942-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x4c1894; GFX942-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x241895; GFX942-NEXT:    s_mov_b32 s3, 0xf0001896; GFX942-NEXT:    s_mov_b32 s2, -11897; GFX942-NEXT:    s_waitcnt lgkmcnt(0)1898; GFX942-NEXT:    v_add_f64 v[0:1], s[6:7], 21899; GFX942-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 01900; GFX942-NEXT:    s_endpgm1901  %y = fadd double %x, 0x00000000000000021902  store double %y, ptr addrspace(1) %out1903  ret void1904}1905 1906define amdgpu_kernel void @add_inline_imm_16_f64(ptr addrspace(1) %out, [8 x i32], double %x) {1907; SI-LABEL: add_inline_imm_16_f64:1908; SI:       ; %bb.0:1909; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x131910; SI-NEXT:    s_mov_b32 s3, 0xf0001911; SI-NEXT:    s_mov_b32 s2, -11912; SI-NEXT:    s_waitcnt lgkmcnt(0)1913; SI-NEXT:    v_add_f64 v[0:1], s[0:1], 161914; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x91915; SI-NEXT:    s_waitcnt lgkmcnt(0)1916; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 01917; SI-NEXT:    s_endpgm1918;1919; VI-LABEL: add_inline_imm_16_f64:1920; VI:       ; %bb.0:1921; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x4c1922; VI-NEXT:    s_mov_b32 s3, 0xf0001923; VI-NEXT:    s_mov_b32 s2, -11924; VI-NEXT:    s_waitcnt lgkmcnt(0)1925; VI-NEXT:    v_add_f64 v[0:1], s[0:1], 161926; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x241927; VI-NEXT:    s_waitcnt lgkmcnt(0)1928; VI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 01929; VI-NEXT:    s_endpgm1930;1931; GFX942-LABEL: add_inline_imm_16_f64:1932; GFX942:       ; %bb.0:1933; GFX942-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x4c1934; GFX942-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x241935; GFX942-NEXT:    s_mov_b32 s3, 0xf0001936; GFX942-NEXT:    s_mov_b32 s2, -11937; GFX942-NEXT:    s_waitcnt lgkmcnt(0)1938; GFX942-NEXT:    v_add_f64 v[0:1], s[6:7], 161939; GFX942-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 01940; GFX942-NEXT:    s_endpgm1941  %y = fadd double %x, 0x00000000000000101942  store double %y, ptr addrspace(1) %out1943  ret void1944}1945 1946define amdgpu_kernel void @add_inline_imm_neg_1_f64(ptr addrspace(1) %out, [8 x i32], double %x) {1947; SI-LABEL: add_inline_imm_neg_1_f64:1948; SI:       ; %bb.0:1949; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x91950; SI-NEXT:    v_mov_b32_e32 v0, -11951; SI-NEXT:    s_mov_b32 s3, 0xf0001952; SI-NEXT:    s_mov_b32 s2, -11953; SI-NEXT:    v_mov_b32_e32 v1, v01954; SI-NEXT:    s_waitcnt lgkmcnt(0)1955; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 01956; SI-NEXT:    s_endpgm1957;1958; VI-LABEL: add_inline_imm_neg_1_f64:1959; VI:       ; %bb.0:1960; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x241961; VI-NEXT:    v_mov_b32_e32 v0, -11962; VI-NEXT:    s_mov_b32 s3, 0xf0001963; VI-NEXT:    s_mov_b32 s2, -11964; VI-NEXT:    v_mov_b32_e32 v1, v01965; VI-NEXT:    s_waitcnt lgkmcnt(0)1966; VI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 01967; VI-NEXT:    s_endpgm1968;1969; GFX942-LABEL: add_inline_imm_neg_1_f64:1970; GFX942:       ; %bb.0:1971; GFX942-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x241972; GFX942-NEXT:    v_mov_b32_e32 v0, -11973; GFX942-NEXT:    s_mov_b32 s3, 0xf0001974; GFX942-NEXT:    s_mov_b32 s2, -11975; GFX942-NEXT:    v_mov_b32_e32 v1, v01976; GFX942-NEXT:    s_waitcnt lgkmcnt(0)1977; GFX942-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 01978; GFX942-NEXT:    s_endpgm1979  %y = fadd double %x, 0xffffffffffffffff1980  store double %y, ptr addrspace(1) %out1981  ret void1982}1983 1984define amdgpu_kernel void @add_inline_imm_neg_2_f64(ptr addrspace(1) %out, [8 x i32], double %x) {1985; SI-LABEL: add_inline_imm_neg_2_f64:1986; SI:       ; %bb.0:1987; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x91988; SI-NEXT:    s_mov_b32 s3, 0xf0001989; SI-NEXT:    s_mov_b32 s2, -11990; SI-NEXT:    v_mov_b32_e32 v0, -21991; SI-NEXT:    v_mov_b32_e32 v1, -11992; SI-NEXT:    s_waitcnt lgkmcnt(0)1993; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 01994; SI-NEXT:    s_endpgm1995;1996; VI-LABEL: add_inline_imm_neg_2_f64:1997; VI:       ; %bb.0:1998; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x241999; VI-NEXT:    s_mov_b32 s3, 0xf0002000; VI-NEXT:    s_mov_b32 s2, -12001; VI-NEXT:    v_mov_b32_e32 v0, -22002; VI-NEXT:    v_mov_b32_e32 v1, -12003; VI-NEXT:    s_waitcnt lgkmcnt(0)2004; VI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 02005; VI-NEXT:    s_endpgm2006;2007; GFX942-LABEL: add_inline_imm_neg_2_f64:2008; GFX942:       ; %bb.0:2009; GFX942-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x242010; GFX942-NEXT:    s_mov_b32 s3, 0xf0002011; GFX942-NEXT:    s_mov_b32 s2, -12012; GFX942-NEXT:    v_mov_b32_e32 v0, -22013; GFX942-NEXT:    v_mov_b32_e32 v1, -12014; GFX942-NEXT:    s_waitcnt lgkmcnt(0)2015; GFX942-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 02016; GFX942-NEXT:    s_endpgm2017  %y = fadd double %x, 0xfffffffffffffffe2018  store double %y, ptr addrspace(1) %out2019  ret void2020}2021 2022define amdgpu_kernel void @add_inline_imm_neg_16_f64(ptr addrspace(1) %out, [8 x i32], double %x) {2023; SI-LABEL: add_inline_imm_neg_16_f64:2024; SI:       ; %bb.0:2025; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x92026; SI-NEXT:    s_mov_b32 s3, 0xf0002027; SI-NEXT:    s_mov_b32 s2, -12028; SI-NEXT:    v_mov_b32_e32 v0, -162029; SI-NEXT:    v_mov_b32_e32 v1, -12030; SI-NEXT:    s_waitcnt lgkmcnt(0)2031; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 02032; SI-NEXT:    s_endpgm2033;2034; VI-LABEL: add_inline_imm_neg_16_f64:2035; VI:       ; %bb.0:2036; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x242037; VI-NEXT:    s_mov_b32 s3, 0xf0002038; VI-NEXT:    s_mov_b32 s2, -12039; VI-NEXT:    v_mov_b32_e32 v0, -162040; VI-NEXT:    v_mov_b32_e32 v1, -12041; VI-NEXT:    s_waitcnt lgkmcnt(0)2042; VI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 02043; VI-NEXT:    s_endpgm2044;2045; GFX942-LABEL: add_inline_imm_neg_16_f64:2046; GFX942:       ; %bb.0:2047; GFX942-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x242048; GFX942-NEXT:    s_mov_b32 s3, 0xf0002049; GFX942-NEXT:    s_mov_b32 s2, -12050; GFX942-NEXT:    v_mov_b32_e32 v0, -162051; GFX942-NEXT:    v_mov_b32_e32 v1, -12052; GFX942-NEXT:    s_waitcnt lgkmcnt(0)2053; GFX942-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 02054; GFX942-NEXT:    s_endpgm2055  %y = fadd double %x, 0xfffffffffffffff02056  store double %y, ptr addrspace(1) %out2057  ret void2058}2059 2060define amdgpu_kernel void @add_inline_imm_63_f64(ptr addrspace(1) %out, [8 x i32], double %x) {2061; SI-LABEL: add_inline_imm_63_f64:2062; SI:       ; %bb.0:2063; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x132064; SI-NEXT:    s_mov_b32 s3, 0xf0002065; SI-NEXT:    s_mov_b32 s2, -12066; SI-NEXT:    s_waitcnt lgkmcnt(0)2067; SI-NEXT:    v_add_f64 v[0:1], s[0:1], 632068; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x92069; SI-NEXT:    s_waitcnt lgkmcnt(0)2070; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 02071; SI-NEXT:    s_endpgm2072;2073; VI-LABEL: add_inline_imm_63_f64:2074; VI:       ; %bb.0:2075; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x4c2076; VI-NEXT:    s_mov_b32 s3, 0xf0002077; VI-NEXT:    s_mov_b32 s2, -12078; VI-NEXT:    s_waitcnt lgkmcnt(0)2079; VI-NEXT:    v_add_f64 v[0:1], s[0:1], 632080; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x242081; VI-NEXT:    s_waitcnt lgkmcnt(0)2082; VI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 02083; VI-NEXT:    s_endpgm2084;2085; GFX942-LABEL: add_inline_imm_63_f64:2086; GFX942:       ; %bb.0:2087; GFX942-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x4c2088; GFX942-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x242089; GFX942-NEXT:    s_mov_b32 s3, 0xf0002090; GFX942-NEXT:    s_mov_b32 s2, -12091; GFX942-NEXT:    s_waitcnt lgkmcnt(0)2092; GFX942-NEXT:    v_add_f64 v[0:1], s[6:7], 632093; GFX942-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 02094; GFX942-NEXT:    s_endpgm2095  %y = fadd double %x, 0x000000000000003F2096  store double %y, ptr addrspace(1) %out2097  ret void2098}2099 2100define amdgpu_kernel void @add_inline_imm_64_f64(ptr addrspace(1) %out, [8 x i32], double %x) {2101; SI-LABEL: add_inline_imm_64_f64:2102; SI:       ; %bb.0:2103; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x132104; SI-NEXT:    s_mov_b32 s3, 0xf0002105; SI-NEXT:    s_mov_b32 s2, -12106; SI-NEXT:    s_waitcnt lgkmcnt(0)2107; SI-NEXT:    v_add_f64 v[0:1], s[0:1], 642108; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x92109; SI-NEXT:    s_waitcnt lgkmcnt(0)2110; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 02111; SI-NEXT:    s_endpgm2112;2113; VI-LABEL: add_inline_imm_64_f64:2114; VI:       ; %bb.0:2115; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x4c2116; VI-NEXT:    s_mov_b32 s3, 0xf0002117; VI-NEXT:    s_mov_b32 s2, -12118; VI-NEXT:    s_waitcnt lgkmcnt(0)2119; VI-NEXT:    v_add_f64 v[0:1], s[0:1], 642120; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x242121; VI-NEXT:    s_waitcnt lgkmcnt(0)2122; VI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 02123; VI-NEXT:    s_endpgm2124;2125; GFX942-LABEL: add_inline_imm_64_f64:2126; GFX942:       ; %bb.0:2127; GFX942-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x4c2128; GFX942-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x242129; GFX942-NEXT:    s_mov_b32 s3, 0xf0002130; GFX942-NEXT:    s_mov_b32 s2, -12131; GFX942-NEXT:    s_waitcnt lgkmcnt(0)2132; GFX942-NEXT:    v_add_f64 v[0:1], s[6:7], 642133; GFX942-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 02134; GFX942-NEXT:    s_endpgm2135  %y = fadd double %x, 0x00000000000000402136  store double %y, ptr addrspace(1) %out2137  ret void2138}2139 2140define amdgpu_kernel void @store_inline_imm_0.0_f64(ptr addrspace(1) %out) {2141; SI-LABEL: store_inline_imm_0.0_f64:2142; SI:       ; %bb.0:2143; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x92144; SI-NEXT:    v_mov_b32_e32 v0, 02145; SI-NEXT:    s_mov_b32 s3, 0xf0002146; SI-NEXT:    s_mov_b32 s2, -12147; SI-NEXT:    v_mov_b32_e32 v1, v02148; SI-NEXT:    s_waitcnt lgkmcnt(0)2149; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 02150; SI-NEXT:    s_endpgm2151;2152; VI-LABEL: store_inline_imm_0.0_f64:2153; VI:       ; %bb.0:2154; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x242155; VI-NEXT:    v_mov_b32_e32 v0, 02156; VI-NEXT:    s_mov_b32 s3, 0xf0002157; VI-NEXT:    s_mov_b32 s2, -12158; VI-NEXT:    v_mov_b32_e32 v1, v02159; VI-NEXT:    s_waitcnt lgkmcnt(0)2160; VI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 02161; VI-NEXT:    s_endpgm2162;2163; GFX942-LABEL: store_inline_imm_0.0_f64:2164; GFX942:       ; %bb.0:2165; GFX942-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x242166; GFX942-NEXT:    v_mov_b32_e32 v0, 02167; GFX942-NEXT:    s_mov_b32 s3, 0xf0002168; GFX942-NEXT:    s_mov_b32 s2, -12169; GFX942-NEXT:    v_mov_b32_e32 v1, v02170; GFX942-NEXT:    s_waitcnt lgkmcnt(0)2171; GFX942-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 02172; GFX942-NEXT:    s_endpgm2173  store double 0.0, ptr addrspace(1) %out2174  ret void2175}2176 2177define amdgpu_kernel void @store_literal_imm_neg_0.0_f64(ptr addrspace(1) %out) {2178; SI-LABEL: store_literal_imm_neg_0.0_f64:2179; SI:       ; %bb.0:2180; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x92181; SI-NEXT:    s_mov_b32 s3, 0xf0002182; SI-NEXT:    s_mov_b32 s2, -12183; SI-NEXT:    v_mov_b32_e32 v0, 02184; SI-NEXT:    v_bfrev_b32_e32 v1, 12185; SI-NEXT:    s_waitcnt lgkmcnt(0)2186; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 02187; SI-NEXT:    s_endpgm2188;2189; VI-LABEL: store_literal_imm_neg_0.0_f64:2190; VI:       ; %bb.0:2191; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x242192; VI-NEXT:    s_mov_b32 s3, 0xf0002193; VI-NEXT:    s_mov_b32 s2, -12194; VI-NEXT:    v_mov_b32_e32 v0, 02195; VI-NEXT:    v_bfrev_b32_e32 v1, 12196; VI-NEXT:    s_waitcnt lgkmcnt(0)2197; VI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 02198; VI-NEXT:    s_endpgm2199;2200; GFX942-LABEL: store_literal_imm_neg_0.0_f64:2201; GFX942:       ; %bb.0:2202; GFX942-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x242203; GFX942-NEXT:    s_mov_b32 s3, 0xf0002204; GFX942-NEXT:    s_mov_b32 s2, -12205; GFX942-NEXT:    v_mov_b32_e32 v0, 02206; GFX942-NEXT:    v_bfrev_b32_e32 v1, 12207; GFX942-NEXT:    s_waitcnt lgkmcnt(0)2208; GFX942-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 02209; GFX942-NEXT:    s_endpgm2210  store double -0.0, ptr addrspace(1) %out2211  ret void2212}2213 2214define amdgpu_kernel void @store_inline_imm_0.5_f64(ptr addrspace(1) %out) {2215; SI-LABEL: store_inline_imm_0.5_f64:2216; SI:       ; %bb.0:2217; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x92218; SI-NEXT:    s_mov_b32 s3, 0xf0002219; SI-NEXT:    s_mov_b32 s2, -12220; SI-NEXT:    v_mov_b32_e32 v0, 02221; SI-NEXT:    v_mov_b32_e32 v1, 0x3fe000002222; SI-NEXT:    s_waitcnt lgkmcnt(0)2223; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 02224; SI-NEXT:    s_endpgm2225;2226; VI-LABEL: store_inline_imm_0.5_f64:2227; VI:       ; %bb.0:2228; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x242229; VI-NEXT:    s_mov_b32 s3, 0xf0002230; VI-NEXT:    s_mov_b32 s2, -12231; VI-NEXT:    v_mov_b32_e32 v0, 02232; VI-NEXT:    v_mov_b32_e32 v1, 0x3fe000002233; VI-NEXT:    s_waitcnt lgkmcnt(0)2234; VI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 02235; VI-NEXT:    s_endpgm2236;2237; GFX942-LABEL: store_inline_imm_0.5_f64:2238; GFX942:       ; %bb.0:2239; GFX942-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x242240; GFX942-NEXT:    s_mov_b32 s3, 0xf0002241; GFX942-NEXT:    s_mov_b32 s2, -12242; GFX942-NEXT:    v_mov_b32_e32 v0, 02243; GFX942-NEXT:    v_mov_b32_e32 v1, 0x3fe000002244; GFX942-NEXT:    s_waitcnt lgkmcnt(0)2245; GFX942-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 02246; GFX942-NEXT:    s_endpgm2247  store double 0.5, ptr addrspace(1) %out2248  ret void2249}2250 2251define amdgpu_kernel void @store_inline_imm_m_0.5_f64(ptr addrspace(1) %out) {2252; SI-LABEL: store_inline_imm_m_0.5_f64:2253; SI:       ; %bb.0:2254; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x92255; SI-NEXT:    s_mov_b32 s3, 0xf0002256; SI-NEXT:    s_mov_b32 s2, -12257; SI-NEXT:    v_mov_b32_e32 v0, 02258; SI-NEXT:    v_mov_b32_e32 v1, 0xbfe000002259; SI-NEXT:    s_waitcnt lgkmcnt(0)2260; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 02261; SI-NEXT:    s_endpgm2262;2263; VI-LABEL: store_inline_imm_m_0.5_f64:2264; VI:       ; %bb.0:2265; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x242266; VI-NEXT:    s_mov_b32 s3, 0xf0002267; VI-NEXT:    s_mov_b32 s2, -12268; VI-NEXT:    v_mov_b32_e32 v0, 02269; VI-NEXT:    v_mov_b32_e32 v1, 0xbfe000002270; VI-NEXT:    s_waitcnt lgkmcnt(0)2271; VI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 02272; VI-NEXT:    s_endpgm2273;2274; GFX942-LABEL: store_inline_imm_m_0.5_f64:2275; GFX942:       ; %bb.0:2276; GFX942-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x242277; GFX942-NEXT:    s_mov_b32 s3, 0xf0002278; GFX942-NEXT:    s_mov_b32 s2, -12279; GFX942-NEXT:    v_mov_b32_e32 v0, 02280; GFX942-NEXT:    v_mov_b32_e32 v1, 0xbfe000002281; GFX942-NEXT:    s_waitcnt lgkmcnt(0)2282; GFX942-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 02283; GFX942-NEXT:    s_endpgm2284  store double -0.5, ptr addrspace(1) %out2285  ret void2286}2287 2288define amdgpu_kernel void @store_inline_imm_1.0_f64(ptr addrspace(1) %out) {2289; SI-LABEL: store_inline_imm_1.0_f64:2290; SI:       ; %bb.0:2291; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x92292; SI-NEXT:    s_mov_b32 s3, 0xf0002293; SI-NEXT:    s_mov_b32 s2, -12294; SI-NEXT:    v_mov_b32_e32 v0, 02295; SI-NEXT:    v_mov_b32_e32 v1, 0x3ff000002296; SI-NEXT:    s_waitcnt lgkmcnt(0)2297; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 02298; SI-NEXT:    s_endpgm2299;2300; VI-LABEL: store_inline_imm_1.0_f64:2301; VI:       ; %bb.0:2302; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x242303; VI-NEXT:    s_mov_b32 s3, 0xf0002304; VI-NEXT:    s_mov_b32 s2, -12305; VI-NEXT:    v_mov_b32_e32 v0, 02306; VI-NEXT:    v_mov_b32_e32 v1, 0x3ff000002307; VI-NEXT:    s_waitcnt lgkmcnt(0)2308; VI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 02309; VI-NEXT:    s_endpgm2310;2311; GFX942-LABEL: store_inline_imm_1.0_f64:2312; GFX942:       ; %bb.0:2313; GFX942-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x242314; GFX942-NEXT:    s_mov_b32 s3, 0xf0002315; GFX942-NEXT:    s_mov_b32 s2, -12316; GFX942-NEXT:    v_mov_b32_e32 v0, 02317; GFX942-NEXT:    v_mov_b32_e32 v1, 0x3ff000002318; GFX942-NEXT:    s_waitcnt lgkmcnt(0)2319; GFX942-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 02320; GFX942-NEXT:    s_endpgm2321  store double 1.0, ptr addrspace(1) %out2322  ret void2323}2324 2325define amdgpu_kernel void @store_inline_imm_m_1.0_f64(ptr addrspace(1) %out) {2326; SI-LABEL: store_inline_imm_m_1.0_f64:2327; SI:       ; %bb.0:2328; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x92329; SI-NEXT:    s_mov_b32 s3, 0xf0002330; SI-NEXT:    s_mov_b32 s2, -12331; SI-NEXT:    v_mov_b32_e32 v0, 02332; SI-NEXT:    v_mov_b32_e32 v1, 0xbff000002333; SI-NEXT:    s_waitcnt lgkmcnt(0)2334; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 02335; SI-NEXT:    s_endpgm2336;2337; VI-LABEL: store_inline_imm_m_1.0_f64:2338; VI:       ; %bb.0:2339; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x242340; VI-NEXT:    s_mov_b32 s3, 0xf0002341; VI-NEXT:    s_mov_b32 s2, -12342; VI-NEXT:    v_mov_b32_e32 v0, 02343; VI-NEXT:    v_mov_b32_e32 v1, 0xbff000002344; VI-NEXT:    s_waitcnt lgkmcnt(0)2345; VI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 02346; VI-NEXT:    s_endpgm2347;2348; GFX942-LABEL: store_inline_imm_m_1.0_f64:2349; GFX942:       ; %bb.0:2350; GFX942-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x242351; GFX942-NEXT:    s_mov_b32 s3, 0xf0002352; GFX942-NEXT:    s_mov_b32 s2, -12353; GFX942-NEXT:    v_mov_b32_e32 v0, 02354; GFX942-NEXT:    v_mov_b32_e32 v1, 0xbff000002355; GFX942-NEXT:    s_waitcnt lgkmcnt(0)2356; GFX942-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 02357; GFX942-NEXT:    s_endpgm2358  store double -1.0, ptr addrspace(1) %out2359  ret void2360}2361 2362define amdgpu_kernel void @store_inline_imm_2.0_f64(ptr addrspace(1) %out) {2363; SI-LABEL: store_inline_imm_2.0_f64:2364; SI:       ; %bb.0:2365; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x92366; SI-NEXT:    s_mov_b32 s3, 0xf0002367; SI-NEXT:    s_mov_b32 s2, -12368; SI-NEXT:    v_mov_b32_e32 v0, 02369; SI-NEXT:    v_mov_b32_e32 v1, 2.02370; SI-NEXT:    s_waitcnt lgkmcnt(0)2371; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 02372; SI-NEXT:    s_endpgm2373;2374; VI-LABEL: store_inline_imm_2.0_f64:2375; VI:       ; %bb.0:2376; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x242377; VI-NEXT:    s_mov_b32 s3, 0xf0002378; VI-NEXT:    s_mov_b32 s2, -12379; VI-NEXT:    v_mov_b32_e32 v0, 02380; VI-NEXT:    v_mov_b32_e32 v1, 2.02381; VI-NEXT:    s_waitcnt lgkmcnt(0)2382; VI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 02383; VI-NEXT:    s_endpgm2384;2385; GFX942-LABEL: store_inline_imm_2.0_f64:2386; GFX942:       ; %bb.0:2387; GFX942-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x242388; GFX942-NEXT:    s_mov_b32 s3, 0xf0002389; GFX942-NEXT:    s_mov_b32 s2, -12390; GFX942-NEXT:    v_mov_b32_e32 v0, 02391; GFX942-NEXT:    v_mov_b32_e32 v1, 2.02392; GFX942-NEXT:    s_waitcnt lgkmcnt(0)2393; GFX942-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 02394; GFX942-NEXT:    s_endpgm2395  store double 2.0, ptr addrspace(1) %out2396  ret void2397}2398 2399define amdgpu_kernel void @store_inline_imm_m_2.0_f64(ptr addrspace(1) %out) {2400; SI-LABEL: store_inline_imm_m_2.0_f64:2401; SI:       ; %bb.0:2402; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x92403; SI-NEXT:    s_mov_b32 s3, 0xf0002404; SI-NEXT:    s_mov_b32 s2, -12405; SI-NEXT:    v_mov_b32_e32 v0, 02406; SI-NEXT:    v_mov_b32_e32 v1, -2.02407; SI-NEXT:    s_waitcnt lgkmcnt(0)2408; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 02409; SI-NEXT:    s_endpgm2410;2411; VI-LABEL: store_inline_imm_m_2.0_f64:2412; VI:       ; %bb.0:2413; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x242414; VI-NEXT:    s_mov_b32 s3, 0xf0002415; VI-NEXT:    s_mov_b32 s2, -12416; VI-NEXT:    v_mov_b32_e32 v0, 02417; VI-NEXT:    v_mov_b32_e32 v1, -2.02418; VI-NEXT:    s_waitcnt lgkmcnt(0)2419; VI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 02420; VI-NEXT:    s_endpgm2421;2422; GFX942-LABEL: store_inline_imm_m_2.0_f64:2423; GFX942:       ; %bb.0:2424; GFX942-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x242425; GFX942-NEXT:    s_mov_b32 s3, 0xf0002426; GFX942-NEXT:    s_mov_b32 s2, -12427; GFX942-NEXT:    v_mov_b32_e32 v0, 02428; GFX942-NEXT:    v_mov_b32_e32 v1, -2.02429; GFX942-NEXT:    s_waitcnt lgkmcnt(0)2430; GFX942-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 02431; GFX942-NEXT:    s_endpgm2432  store double -2.0, ptr addrspace(1) %out2433  ret void2434}2435 2436define amdgpu_kernel void @store_inline_imm_4.0_f64(ptr addrspace(1) %out) {2437; SI-LABEL: store_inline_imm_4.0_f64:2438; SI:       ; %bb.0:2439; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x92440; SI-NEXT:    s_mov_b32 s3, 0xf0002441; SI-NEXT:    s_mov_b32 s2, -12442; SI-NEXT:    v_mov_b32_e32 v0, 02443; SI-NEXT:    v_mov_b32_e32 v1, 0x401000002444; SI-NEXT:    s_waitcnt lgkmcnt(0)2445; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 02446; SI-NEXT:    s_endpgm2447;2448; VI-LABEL: store_inline_imm_4.0_f64:2449; VI:       ; %bb.0:2450; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x242451; VI-NEXT:    s_mov_b32 s3, 0xf0002452; VI-NEXT:    s_mov_b32 s2, -12453; VI-NEXT:    v_mov_b32_e32 v0, 02454; VI-NEXT:    v_mov_b32_e32 v1, 0x401000002455; VI-NEXT:    s_waitcnt lgkmcnt(0)2456; VI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 02457; VI-NEXT:    s_endpgm2458;2459; GFX942-LABEL: store_inline_imm_4.0_f64:2460; GFX942:       ; %bb.0:2461; GFX942-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x242462; GFX942-NEXT:    s_mov_b32 s3, 0xf0002463; GFX942-NEXT:    s_mov_b32 s2, -12464; GFX942-NEXT:    v_mov_b32_e32 v0, 02465; GFX942-NEXT:    v_mov_b32_e32 v1, 0x401000002466; GFX942-NEXT:    s_waitcnt lgkmcnt(0)2467; GFX942-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 02468; GFX942-NEXT:    s_endpgm2469  store double 4.0, ptr addrspace(1) %out2470  ret void2471}2472 2473define amdgpu_kernel void @store_inline_imm_m_4.0_f64(ptr addrspace(1) %out) {2474; SI-LABEL: store_inline_imm_m_4.0_f64:2475; SI:       ; %bb.0:2476; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x92477; SI-NEXT:    s_mov_b32 s3, 0xf0002478; SI-NEXT:    s_mov_b32 s2, -12479; SI-NEXT:    v_mov_b32_e32 v0, 02480; SI-NEXT:    v_mov_b32_e32 v1, 0xc01000002481; SI-NEXT:    s_waitcnt lgkmcnt(0)2482; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 02483; SI-NEXT:    s_endpgm2484;2485; VI-LABEL: store_inline_imm_m_4.0_f64:2486; VI:       ; %bb.0:2487; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x242488; VI-NEXT:    s_mov_b32 s3, 0xf0002489; VI-NEXT:    s_mov_b32 s2, -12490; VI-NEXT:    v_mov_b32_e32 v0, 02491; VI-NEXT:    v_mov_b32_e32 v1, 0xc01000002492; VI-NEXT:    s_waitcnt lgkmcnt(0)2493; VI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 02494; VI-NEXT:    s_endpgm2495;2496; GFX942-LABEL: store_inline_imm_m_4.0_f64:2497; GFX942:       ; %bb.0:2498; GFX942-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x242499; GFX942-NEXT:    s_mov_b32 s3, 0xf0002500; GFX942-NEXT:    s_mov_b32 s2, -12501; GFX942-NEXT:    v_mov_b32_e32 v0, 02502; GFX942-NEXT:    v_mov_b32_e32 v1, 0xc01000002503; GFX942-NEXT:    s_waitcnt lgkmcnt(0)2504; GFX942-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 02505; GFX942-NEXT:    s_endpgm2506  store double -4.0, ptr addrspace(1) %out2507  ret void2508}2509 2510define amdgpu_kernel void @store_inv_2pi_f64(ptr addrspace(1) %out) {2511; SI-LABEL: store_inv_2pi_f64:2512; SI:       ; %bb.0:2513; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x92514; SI-NEXT:    s_mov_b32 s3, 0xf0002515; SI-NEXT:    s_mov_b32 s2, -12516; SI-NEXT:    v_mov_b32_e32 v0, 0x6dc9c8822517; SI-NEXT:    v_mov_b32_e32 v1, 0x3fc45f302518; SI-NEXT:    s_waitcnt lgkmcnt(0)2519; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 02520; SI-NEXT:    s_endpgm2521;2522; VI-LABEL: store_inv_2pi_f64:2523; VI:       ; %bb.0:2524; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x242525; VI-NEXT:    s_mov_b32 s3, 0xf0002526; VI-NEXT:    s_mov_b32 s2, -12527; VI-NEXT:    v_mov_b32_e32 v0, 0x6dc9c8822528; VI-NEXT:    v_mov_b32_e32 v1, 0x3fc45f302529; VI-NEXT:    s_waitcnt lgkmcnt(0)2530; VI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 02531; VI-NEXT:    s_endpgm2532;2533; GFX942-LABEL: store_inv_2pi_f64:2534; GFX942:       ; %bb.0:2535; GFX942-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x242536; GFX942-NEXT:    s_mov_b32 s3, 0xf0002537; GFX942-NEXT:    s_mov_b32 s2, -12538; GFX942-NEXT:    v_mov_b32_e32 v0, 0x6dc9c8822539; GFX942-NEXT:    v_mov_b32_e32 v1, 0x3fc45f302540; GFX942-NEXT:    s_waitcnt lgkmcnt(0)2541; GFX942-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 02542; GFX942-NEXT:    s_endpgm2543  store double 0x3fc45f306dc9c882, ptr addrspace(1) %out2544  ret void2545}2546 2547define amdgpu_kernel void @store_inline_imm_m_inv_2pi_f64(ptr addrspace(1) %out) {2548; SI-LABEL: store_inline_imm_m_inv_2pi_f64:2549; SI:       ; %bb.0:2550; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x92551; SI-NEXT:    s_mov_b32 s3, 0xf0002552; SI-NEXT:    s_mov_b32 s2, -12553; SI-NEXT:    v_mov_b32_e32 v0, 0x6dc9c8822554; SI-NEXT:    v_mov_b32_e32 v1, 0xbfc45f302555; SI-NEXT:    s_waitcnt lgkmcnt(0)2556; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 02557; SI-NEXT:    s_endpgm2558;2559; VI-LABEL: store_inline_imm_m_inv_2pi_f64:2560; VI:       ; %bb.0:2561; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x242562; VI-NEXT:    s_mov_b32 s3, 0xf0002563; VI-NEXT:    s_mov_b32 s2, -12564; VI-NEXT:    v_mov_b32_e32 v0, 0x6dc9c8822565; VI-NEXT:    v_mov_b32_e32 v1, 0xbfc45f302566; VI-NEXT:    s_waitcnt lgkmcnt(0)2567; VI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 02568; VI-NEXT:    s_endpgm2569;2570; GFX942-LABEL: store_inline_imm_m_inv_2pi_f64:2571; GFX942:       ; %bb.0:2572; GFX942-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x242573; GFX942-NEXT:    s_mov_b32 s3, 0xf0002574; GFX942-NEXT:    s_mov_b32 s2, -12575; GFX942-NEXT:    v_mov_b32_e32 v0, 0x6dc9c8822576; GFX942-NEXT:    v_mov_b32_e32 v1, 0xbfc45f302577; GFX942-NEXT:    s_waitcnt lgkmcnt(0)2578; GFX942-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 02579; GFX942-NEXT:    s_endpgm2580  store double 0xbfc45f306dc9c882, ptr addrspace(1) %out2581  ret void2582}2583 2584define amdgpu_kernel void @store_literal_imm_f64(ptr addrspace(1) %out) {2585; SI-LABEL: store_literal_imm_f64:2586; SI:       ; %bb.0:2587; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x92588; SI-NEXT:    s_mov_b32 s3, 0xf0002589; SI-NEXT:    s_mov_b32 s2, -12590; SI-NEXT:    v_mov_b32_e32 v0, 02591; SI-NEXT:    v_mov_b32_e32 v1, 0x40b000002592; SI-NEXT:    s_waitcnt lgkmcnt(0)2593; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 02594; SI-NEXT:    s_endpgm2595;2596; VI-LABEL: store_literal_imm_f64:2597; VI:       ; %bb.0:2598; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x242599; VI-NEXT:    s_mov_b32 s3, 0xf0002600; VI-NEXT:    s_mov_b32 s2, -12601; VI-NEXT:    v_mov_b32_e32 v0, 02602; VI-NEXT:    v_mov_b32_e32 v1, 0x40b000002603; VI-NEXT:    s_waitcnt lgkmcnt(0)2604; VI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 02605; VI-NEXT:    s_endpgm2606;2607; GFX942-LABEL: store_literal_imm_f64:2608; GFX942:       ; %bb.0:2609; GFX942-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x242610; GFX942-NEXT:    s_mov_b32 s3, 0xf0002611; GFX942-NEXT:    s_mov_b32 s2, -12612; GFX942-NEXT:    v_mov_b32_e32 v0, 02613; GFX942-NEXT:    v_mov_b32_e32 v1, 0x40b000002614; GFX942-NEXT:    s_waitcnt lgkmcnt(0)2615; GFX942-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 02616; GFX942-NEXT:    s_endpgm2617  store double 4096.0, ptr addrspace(1) %out2618  ret void2619}2620 2621define amdgpu_vs void @literal_folding(float %arg) {2622; GCN-LABEL: literal_folding:2623; GCN:       ; %bb.0: ; %main_body2624; GCN-NEXT:    v_mul_f32_e32 v1, 0x3f4353f8, v02625; GCN-NEXT:    v_mul_f32_e32 v0, 0xbf4353f8, v02626; GCN-NEXT:    exp pos0 v1, v1, v0, v0 done2627; GCN-NEXT:    s_endpgm2628;2629; GFX942-LABEL: literal_folding:2630; GFX942:       ; %bb.0: ; %main_body2631; GFX942-NEXT:    v_mul_f32_e32 v1, 0x3f4353f8, v02632; GFX942-NEXT:    v_mul_f32_e32 v0, 0xbf4353f8, v02633; GFX942-NEXT:    exp pos0 v1, v1, v0, v0 done2634; GFX942-NEXT:    s_endpgm2635main_body:2636  %tmp = fmul float %arg, 0x3FE86A7F000000002637  %tmp1 = fmul float %arg, 0xBFE86A7F000000002638  call void @llvm.amdgcn.exp.f32(i32 12, i32 15, float %tmp, float %tmp, float %tmp1, float %tmp1, i1 true, i1 false) #02639  ret void2640}2641 2642declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #02643 2644attributes #0 = { nounwind }2645