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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --check-attributes --check-globals2; RUN: sed 's/CODE_OBJECT_VERSION/400/g' %s | opt -S -mtriple=amdgcn-unknown-unknown -passes=amdgpu-attributor | FileCheck -check-prefixes=CHECK,V4 %s3; RUN: sed 's/CODE_OBJECT_VERSION/500/g' %s | opt -S -mtriple=amdgcn-unknown-unknown -passes=amdgpu-attributor | FileCheck -check-prefixes=CHECK,V5 %s4; RUN: sed 's/CODE_OBJECT_VERSION/600/g' %s | opt -S -mtriple=amdgcn-unknown-unknown -passes=amdgpu-attributor | FileCheck -check-prefixes=CHECK,V6 %s5 6declare ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr() #07 8declare i32 @llvm.amdgcn.workgroup.id.x() #09declare i32 @llvm.amdgcn.workgroup.id.y() #010declare i32 @llvm.amdgcn.workgroup.id.z() #011 12declare i32 @llvm.amdgcn.workitem.id.x() #013declare i32 @llvm.amdgcn.workitem.id.y() #014declare i32 @llvm.amdgcn.workitem.id.z() #015declare i32 @llvm.amdgcn.lds.kernel.id() #016declare i64 @llvm.amdgcn.dispatch.id() #017 18 19declare ptr addrspace(4) @llvm.amdgcn.dispatch.ptr() #020declare ptr addrspace(4) @llvm.amdgcn.queue.ptr() #021declare ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr() #022 23; Avoid adding all of these to the output attribute sets24define void @use_everything_else() {25; CHECK-LABEL: define {{[^@]+}}@use_everything_else26; CHECK-SAME: () #[[ATTR1:[0-9]+]] {27; CHECK-NEXT: [[VAL0:%.*]] = call i32 @llvm.amdgcn.workitem.id.x()28; CHECK-NEXT: [[VAL1:%.*]] = call i32 @llvm.amdgcn.workitem.id.y()29; CHECK-NEXT: [[VAL2:%.*]] = call i32 @llvm.amdgcn.workitem.id.z()30; CHECK-NEXT: [[VAL3:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x()31; CHECK-NEXT: [[VAL4:%.*]] = call i32 @llvm.amdgcn.workgroup.id.y()32; CHECK-NEXT: [[VAL5:%.*]] = call i32 @llvm.amdgcn.workgroup.id.z()33; CHECK-NEXT: store volatile i32 [[VAL0]], ptr addrspace(1) null, align 434; CHECK-NEXT: store volatile i32 [[VAL1]], ptr addrspace(1) null, align 435; CHECK-NEXT: store volatile i32 [[VAL2]], ptr addrspace(1) null, align 436; CHECK-NEXT: store volatile i32 [[VAL3]], ptr addrspace(1) null, align 437; CHECK-NEXT: store volatile i32 [[VAL4]], ptr addrspace(1) null, align 438; CHECK-NEXT: store volatile i32 [[VAL5]], ptr addrspace(1) null, align 439; CHECK-NEXT: [[DISPATCH_PTR:%.*]] = call ptr addrspace(4) @llvm.amdgcn.dispatch.ptr()40; CHECK-NEXT: [[QUEUE_PTR:%.*]] = call ptr addrspace(4) @llvm.amdgcn.queue.ptr()41; CHECK-NEXT: [[VAL6:%.*]] = load volatile ptr, ptr addrspace(4) [[DISPATCH_PTR]], align 842; CHECK-NEXT: [[VAL7:%.*]] = load volatile ptr, ptr addrspace(4) [[QUEUE_PTR]], align 843; CHECK-NEXT: [[VAL8:%.*]] = call i32 @llvm.amdgcn.lds.kernel.id()44; CHECK-NEXT: store volatile i32 [[VAL8]], ptr addrspace(1) null, align 445; CHECK-NEXT: [[VAL9:%.*]] = call i64 @llvm.amdgcn.dispatch.id()46; CHECK-NEXT: store volatile i64 [[VAL9]], ptr addrspace(1) null, align 847; CHECK-NEXT: ret void48;49 %val0 = call i32 @llvm.amdgcn.workitem.id.x()50 %val1 = call i32 @llvm.amdgcn.workitem.id.y()51 %val2 = call i32 @llvm.amdgcn.workitem.id.z()52 %val3 = call i32 @llvm.amdgcn.workgroup.id.x()53 %val4 = call i32 @llvm.amdgcn.workgroup.id.y()54 %val5 = call i32 @llvm.amdgcn.workgroup.id.z()55 store volatile i32 %val0, ptr addrspace(1) null56 store volatile i32 %val1, ptr addrspace(1) null57 store volatile i32 %val2, ptr addrspace(1) null58 store volatile i32 %val3, ptr addrspace(1) null59 store volatile i32 %val4, ptr addrspace(1) null60 store volatile i32 %val5, ptr addrspace(1) null61 %dispatch.ptr = call ptr addrspace(4) @llvm.amdgcn.dispatch.ptr()62 %queue.ptr = call ptr addrspace(4) @llvm.amdgcn.queue.ptr()63 %val6 = load volatile ptr, ptr addrspace(4) %dispatch.ptr64 %val7 = load volatile ptr, ptr addrspace(4) %queue.ptr65 %val8 = call i32 @llvm.amdgcn.lds.kernel.id()66 store volatile i32 %val8, ptr addrspace(1) null67 %val9 = call i64 @llvm.amdgcn.dispatch.id()68 store volatile i64 %val9, ptr addrspace(1) null69 ret void70}71 72define amdgpu_kernel void @test_default_queue_offset_v4_0(ptr addrspace(1) %kernarg) {73; V4-LABEL: define {{[^@]+}}@test_default_queue_offset_v4_074; V4-SAME: (ptr addrspace(1) [[KERNARG:%.*]]) #[[ATTR2:[0-9]+]] {75; V4-NEXT: call void @use_everything_else()76; V4-NEXT: [[IMPLICITARG_PTR:%.*]] = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()77; V4-NEXT: [[GEP:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[IMPLICITARG_PTR]], i64 3278; V4-NEXT: [[LOAD:%.*]] = load ptr, ptr addrspace(4) [[GEP]], align 879; V4-NEXT: store ptr [[LOAD]], ptr addrspace(1) [[KERNARG]], align 880; V4-NEXT: ret void81;82; V5-LABEL: define {{[^@]+}}@test_default_queue_offset_v4_083; V5-SAME: (ptr addrspace(1) [[KERNARG:%.*]]) #[[ATTR1]] {84; V5-NEXT: call void @use_everything_else()85; V5-NEXT: [[IMPLICITARG_PTR:%.*]] = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()86; V5-NEXT: [[GEP:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[IMPLICITARG_PTR]], i64 3287; V5-NEXT: [[LOAD:%.*]] = load ptr, ptr addrspace(4) [[GEP]], align 888; V5-NEXT: store ptr [[LOAD]], ptr addrspace(1) [[KERNARG]], align 889; V5-NEXT: ret void90;91; V6-LABEL: define {{[^@]+}}@test_default_queue_offset_v4_092; V6-SAME: (ptr addrspace(1) [[KERNARG:%.*]]) #[[ATTR1]] {93; V6-NEXT: call void @use_everything_else()94; V6-NEXT: [[IMPLICITARG_PTR:%.*]] = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()95; V6-NEXT: [[GEP:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[IMPLICITARG_PTR]], i64 3296; V6-NEXT: [[LOAD:%.*]] = load ptr, ptr addrspace(4) [[GEP]], align 897; V6-NEXT: store ptr [[LOAD]], ptr addrspace(1) [[KERNARG]], align 898; V6-NEXT: ret void99;100 call void @use_everything_else()101 %implicitarg.ptr = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()102 %gep = getelementptr inbounds i8, ptr addrspace(4) %implicitarg.ptr, i64 32103 %load = load ptr, ptr addrspace(4) %gep104 store ptr %load, ptr addrspace(1) %kernarg105 ret void106}107 108define amdgpu_kernel void @test_default_queue_offset_v5_0(ptr addrspace(1) %kernarg) {109; V4-LABEL: define {{[^@]+}}@test_default_queue_offset_v5_0110; V4-SAME: (ptr addrspace(1) [[KERNARG:%.*]]) #[[ATTR3:[0-9]+]] {111; V4-NEXT: call void @use_everything_else()112; V4-NEXT: [[IMPLICITARG_PTR:%.*]] = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()113; V4-NEXT: [[GEP:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[IMPLICITARG_PTR]], i64 104114; V4-NEXT: [[LOAD:%.*]] = load ptr, ptr addrspace(4) [[GEP]], align 8115; V4-NEXT: store ptr [[LOAD]], ptr addrspace(1) [[KERNARG]], align 8116; V4-NEXT: ret void117;118; V5-LABEL: define {{[^@]+}}@test_default_queue_offset_v5_0119; V5-SAME: (ptr addrspace(1) [[KERNARG:%.*]]) #[[ATTR2:[0-9]+]] {120; V5-NEXT: call void @use_everything_else()121; V5-NEXT: [[IMPLICITARG_PTR:%.*]] = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()122; V5-NEXT: [[GEP:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[IMPLICITARG_PTR]], i64 104123; V5-NEXT: [[LOAD:%.*]] = load ptr, ptr addrspace(4) [[GEP]], align 8124; V5-NEXT: store ptr [[LOAD]], ptr addrspace(1) [[KERNARG]], align 8125; V5-NEXT: ret void126;127; V6-LABEL: define {{[^@]+}}@test_default_queue_offset_v5_0128; V6-SAME: (ptr addrspace(1) [[KERNARG:%.*]]) #[[ATTR2:[0-9]+]] {129; V6-NEXT: call void @use_everything_else()130; V6-NEXT: [[IMPLICITARG_PTR:%.*]] = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()131; V6-NEXT: [[GEP:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[IMPLICITARG_PTR]], i64 104132; V6-NEXT: [[LOAD:%.*]] = load ptr, ptr addrspace(4) [[GEP]], align 8133; V6-NEXT: store ptr [[LOAD]], ptr addrspace(1) [[KERNARG]], align 8134; V6-NEXT: ret void135;136 call void @use_everything_else()137 %implicitarg.ptr = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()138 %gep = getelementptr inbounds i8, ptr addrspace(4) %implicitarg.ptr, i64 104139 %load = load ptr, ptr addrspace(4) %gep140 store ptr %load, ptr addrspace(1) %kernarg141 ret void142}143 144define amdgpu_kernel void @test_completion_action_offset_v4_0(ptr addrspace(1) %kernarg) {145; V4-LABEL: define {{[^@]+}}@test_completion_action_offset_v4_0146; V4-SAME: (ptr addrspace(1) [[KERNARG:%.*]]) #[[ATTR4:[0-9]+]] {147; V4-NEXT: call void @use_everything_else()148; V4-NEXT: [[IMPLICITARG_PTR:%.*]] = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()149; V4-NEXT: [[GEP:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[IMPLICITARG_PTR]], i64 40150; V4-NEXT: [[LOAD:%.*]] = load ptr, ptr addrspace(4) [[GEP]], align 8151; V4-NEXT: store ptr [[LOAD]], ptr addrspace(1) [[KERNARG]], align 8152; V4-NEXT: ret void153;154; V5-LABEL: define {{[^@]+}}@test_completion_action_offset_v4_0155; V5-SAME: (ptr addrspace(1) [[KERNARG:%.*]]) #[[ATTR1]] {156; V5-NEXT: call void @use_everything_else()157; V5-NEXT: [[IMPLICITARG_PTR:%.*]] = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()158; V5-NEXT: [[GEP:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[IMPLICITARG_PTR]], i64 40159; V5-NEXT: [[LOAD:%.*]] = load ptr, ptr addrspace(4) [[GEP]], align 8160; V5-NEXT: store ptr [[LOAD]], ptr addrspace(1) [[KERNARG]], align 8161; V5-NEXT: ret void162;163; V6-LABEL: define {{[^@]+}}@test_completion_action_offset_v4_0164; V6-SAME: (ptr addrspace(1) [[KERNARG:%.*]]) #[[ATTR1]] {165; V6-NEXT: call void @use_everything_else()166; V6-NEXT: [[IMPLICITARG_PTR:%.*]] = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()167; V6-NEXT: [[GEP:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[IMPLICITARG_PTR]], i64 40168; V6-NEXT: [[LOAD:%.*]] = load ptr, ptr addrspace(4) [[GEP]], align 8169; V6-NEXT: store ptr [[LOAD]], ptr addrspace(1) [[KERNARG]], align 8170; V6-NEXT: ret void171;172 call void @use_everything_else()173 %implicitarg.ptr = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()174 %gep = getelementptr inbounds i8, ptr addrspace(4) %implicitarg.ptr, i64 40175 %load = load ptr, ptr addrspace(4) %gep176 store ptr %load, ptr addrspace(1) %kernarg177 ret void178}179 180define amdgpu_kernel void @test_completion_action_offset_v5_0(ptr addrspace(1) %kernarg) {181; CHECK-LABEL: define {{[^@]+}}@test_completion_action_offset_v5_0182; CHECK-SAME: (ptr addrspace(1) [[KERNARG:%.*]]) #[[ATTR3:[0-9]+]] {183; CHECK-NEXT: call void @use_everything_else()184; CHECK-NEXT: [[IMPLICITARG_PTR:%.*]] = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()185; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[IMPLICITARG_PTR]], i64 112186; CHECK-NEXT: [[LOAD:%.*]] = load ptr, ptr addrspace(4) [[GEP]], align 8187; CHECK-NEXT: store ptr [[LOAD]], ptr addrspace(1) [[KERNARG]], align 8188; CHECK-NEXT: ret void189;190 call void @use_everything_else()191 %implicitarg.ptr = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()192 %gep = getelementptr inbounds i8, ptr addrspace(4) %implicitarg.ptr, i64 112193 %load = load ptr, ptr addrspace(4) %gep194 store ptr %load, ptr addrspace(1) %kernarg195 ret void196}197 198define amdgpu_kernel void @test_default_queue_completion_action_offset_v3_0(ptr addrspace(1) %kernarg) {199; V4-LABEL: define {{[^@]+}}@test_default_queue_completion_action_offset_v3_0200; V4-SAME: (ptr addrspace(1) [[KERNARG:%.*]]) #[[ATTR5:[0-9]+]] {201; V4-NEXT: call void @use_everything_else()202; V4-NEXT: [[IMPLICITARG_PTR:%.*]] = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()203; V4-NEXT: [[GEP:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[IMPLICITARG_PTR]], i64 32204; V4-NEXT: [[LOAD:%.*]] = load <2 x ptr>, ptr addrspace(4) [[GEP]], align 16205; V4-NEXT: store <2 x ptr> [[LOAD]], ptr addrspace(1) [[KERNARG]], align 16206; V4-NEXT: ret void207;208; V5-LABEL: define {{[^@]+}}@test_default_queue_completion_action_offset_v3_0209; V5-SAME: (ptr addrspace(1) [[KERNARG:%.*]]) #[[ATTR1]] {210; V5-NEXT: call void @use_everything_else()211; V5-NEXT: [[IMPLICITARG_PTR:%.*]] = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()212; V5-NEXT: [[GEP:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[IMPLICITARG_PTR]], i64 32213; V5-NEXT: [[LOAD:%.*]] = load <2 x ptr>, ptr addrspace(4) [[GEP]], align 16214; V5-NEXT: store <2 x ptr> [[LOAD]], ptr addrspace(1) [[KERNARG]], align 16215; V5-NEXT: ret void216;217; V6-LABEL: define {{[^@]+}}@test_default_queue_completion_action_offset_v3_0218; V6-SAME: (ptr addrspace(1) [[KERNARG:%.*]]) #[[ATTR1]] {219; V6-NEXT: call void @use_everything_else()220; V6-NEXT: [[IMPLICITARG_PTR:%.*]] = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()221; V6-NEXT: [[GEP:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[IMPLICITARG_PTR]], i64 32222; V6-NEXT: [[LOAD:%.*]] = load <2 x ptr>, ptr addrspace(4) [[GEP]], align 16223; V6-NEXT: store <2 x ptr> [[LOAD]], ptr addrspace(1) [[KERNARG]], align 16224; V6-NEXT: ret void225;226 call void @use_everything_else()227 %implicitarg.ptr = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()228 %gep = getelementptr inbounds i8, ptr addrspace(4) %implicitarg.ptr, i64 32229 %load = load <2 x ptr>, ptr addrspace(4) %gep230 store <2 x ptr> %load, ptr addrspace(1) %kernarg231 ret void232}233 234define amdgpu_kernel void @test_default_queue_completion_action_offset_v5_0(ptr addrspace(1) %kernarg) {235; V4-LABEL: define {{[^@]+}}@test_default_queue_completion_action_offset_v5_0236; V4-SAME: (ptr addrspace(1) [[KERNARG:%.*]]) #[[ATTR3]] {237; V4-NEXT: call void @use_everything_else()238; V4-NEXT: [[IMPLICITARG_PTR:%.*]] = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()239; V4-NEXT: [[GEP:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[IMPLICITARG_PTR]], i64 104240; V4-NEXT: [[LOAD:%.*]] = load <2 x ptr>, ptr addrspace(4) [[GEP]], align 16241; V4-NEXT: store <2 x ptr> [[LOAD]], ptr addrspace(1) [[KERNARG]], align 16242; V4-NEXT: ret void243;244; V5-LABEL: define {{[^@]+}}@test_default_queue_completion_action_offset_v5_0245; V5-SAME: (ptr addrspace(1) [[KERNARG:%.*]]) #[[ATTR4:[0-9]+]] {246; V5-NEXT: call void @use_everything_else()247; V5-NEXT: [[IMPLICITARG_PTR:%.*]] = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()248; V5-NEXT: [[GEP:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[IMPLICITARG_PTR]], i64 104249; V5-NEXT: [[LOAD:%.*]] = load <2 x ptr>, ptr addrspace(4) [[GEP]], align 16250; V5-NEXT: store <2 x ptr> [[LOAD]], ptr addrspace(1) [[KERNARG]], align 16251; V5-NEXT: ret void252;253; V6-LABEL: define {{[^@]+}}@test_default_queue_completion_action_offset_v5_0254; V6-SAME: (ptr addrspace(1) [[KERNARG:%.*]]) #[[ATTR4:[0-9]+]] {255; V6-NEXT: call void @use_everything_else()256; V6-NEXT: [[IMPLICITARG_PTR:%.*]] = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()257; V6-NEXT: [[GEP:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[IMPLICITARG_PTR]], i64 104258; V6-NEXT: [[LOAD:%.*]] = load <2 x ptr>, ptr addrspace(4) [[GEP]], align 16259; V6-NEXT: store <2 x ptr> [[LOAD]], ptr addrspace(1) [[KERNARG]], align 16260; V6-NEXT: ret void261;262 263 call void @use_everything_else()%implicitarg.ptr = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()264 %gep = getelementptr inbounds i8, ptr addrspace(4) %implicitarg.ptr, i64 104265 %load = load <2 x ptr>, ptr addrspace(4) %gep266 store <2 x ptr> %load, ptr addrspace(1) %kernarg267 ret void268}269 270 271attributes #0 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }272 273!llvm.module.flags = !{!0}274!0 = !{i32 1, !"amdhsa_code_object_version", i32 CODE_OBJECT_VERSION}275 276 277;.278; V4: attributes #[[ATTR0:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }279; V4: attributes #[[ATTR1]] = { "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-multigrid-sync-arg" "uniform-work-group-size"="false" }280; V4: attributes #[[ATTR2]] = { "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-multigrid-sync-arg" "uniform-work-group-size"="false" }281; V4: attributes #[[ATTR3]] = { "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-multigrid-sync-arg" "uniform-work-group-size"="false" }282; V4: attributes #[[ATTR4]] = { "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-default-queue" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-multigrid-sync-arg" "uniform-work-group-size"="false" }283; V4: attributes #[[ATTR5]] = { "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-multigrid-sync-arg" "uniform-work-group-size"="false" }284;.285; V5: attributes #[[ATTR0:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }286; V5: attributes #[[ATTR1]] = { "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-multigrid-sync-arg" "uniform-work-group-size"="false" }287; V5: attributes #[[ATTR2]] = { "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-multigrid-sync-arg" "uniform-work-group-size"="false" }288; V5: attributes #[[ATTR3]] = { "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-default-queue" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-multigrid-sync-arg" "uniform-work-group-size"="false" }289; V5: attributes #[[ATTR4]] = { "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-multigrid-sync-arg" "uniform-work-group-size"="false" }290;.291; V6: attributes #[[ATTR0:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }292; V6: attributes #[[ATTR1]] = { "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-multigrid-sync-arg" "uniform-work-group-size"="false" }293; V6: attributes #[[ATTR2]] = { "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-multigrid-sync-arg" "uniform-work-group-size"="false" }294; V6: attributes #[[ATTR3]] = { "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-default-queue" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-multigrid-sync-arg" "uniform-work-group-size"="false" }295; V6: attributes #[[ATTR4]] = { "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-multigrid-sync-arg" "uniform-work-group-size"="false" }296;.297; V4: [[META0:![0-9]+]] = !{i32 1, !"amdhsa_code_object_version", i32 400}298;.299; V5: [[META0:![0-9]+]] = !{i32 1, !"amdhsa_code_object_version", i32 500}300;.301; V6: [[META0:![0-9]+]] = !{i32 1, !"amdhsa_code_object_version", i32 600}302;.303