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1# RUN: not llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -simplify-mir -start-before=greedy,2 -stress-regalloc=4 -stop-before=virtregrewriter,2 -o - -verify-regalloc %s 2> %t.err | FileCheck %s2# RUN: FileCheck -check-prefix=ERR %s < %t.err3 4# To allocate the vreg_512_align2, the allocation will attempt to5# inflate the register class to av_512_align2. This will ultimately6# not work, and the allocation will fail. There is an unproductive7# live range split, and we end up with a snippet copy of an8# unspillable register. Recursive assignment of interfering ranges9# during last chance recoloring would delete the unspillable snippet10# live range. Make sure there's no use after free when rolling back11# the last chance assignment.12 13# ERR: error: <unknown>:0:0: ran out of registers during register allocation in function 'inflated_reg_class_copy_use_after_free'14# ERR: error: <unknown>:0:0: ran out of registers during register allocation in function 'inflated_reg_class_copy_use_after_free_lane_subset'15 16--- |17 define amdgpu_kernel void @inflated_reg_class_copy_use_after_free() {18 ret void19 }20 21 define amdgpu_kernel void @inflated_reg_class_copy_use_after_free_lane_subset() {22 ret void23 }24 25...26 27# CHECK-LABEL: name: inflated_reg_class_copy_use_after_free28# CHECK: S_NOP 0, implicit-def [[ORIG_REG:%[0-9]+]].sub0_sub1_sub2_sub329# CHECK-NEXT: SI_SPILL_AV512_SAVE [[ORIG_REG]], %stack.0, $sgpr32, 0, implicit $exec :: (store (s512) into %stack.0, align 4, addrspace 5)30# CHECK-NEXT: [[RESTORE0:%[0-9]+]]:vreg_512_align2 = SI_SPILL_AV512_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load (s512) from %stack.0, align 4, addrspace 5)31# CHECK-NEXT: early-clobber $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = V_MFMA_F32_16X16X1F32_vgprcd_e64 undef %3:vgpr_32, undef %3:vgpr_32, [[RESTORE0]], 0, 0, 0, implicit $mode, implicit $exec, implicit $mode, implicit $exec32# CHECK-NEXT: undef [[SPLIT0:%[0-9]+]].sub2_sub3:av_512_align2 = COPY undef $vgpr2_vgpr3 {33# CHECK-NEXT: internal [[SPLIT0]].sub0:av_512_align2 = COPY undef $vgpr034# CHECK-NEXT: }35# CHECK-NEXT: undef [[SPLIT2:%[0-9]+]].sub2_sub3:av_512_align2 = COPY [[SPLIT0]].sub2_sub3 {36# CHECK-NEXT: internal [[SPLIT2]].sub0:av_512_align2 = COPY [[SPLIT0]].sub037# CHECK-NEXT: }38# CHECK-NEXT: [[RESTORE2:%[0-9]+]]:av_512_align2 = SI_SPILL_AV512_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load (s512) from %stack.0, align 4, addrspace 5)39# CHECK-NEXT: [[MFMA_USE1:%[0-9]+]].sub0_sub1:vreg_512_align2 = COPY [[RESTORE2]].sub0_sub140# CHECK-NEXT: [[MFMA_USE1]].sub2:vreg_512_align2 = COPY [[SPLIT2]].sub3 41# CHECK-NEXT: [[MFMA_USE1]].sub3:vreg_512_align2 = COPY [[SPLIT2]].sub242# CHECK-NEXT: [[MFMA_USE1]].sub4:vreg_512_align2 = COPY [[SPLIT2]].sub043# CHECK-NEXT: [[MFMA_USE1]].sub5:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec44# CHECK-NEXT: [[MFMA_USE1]].sub6:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec45# CHECK-NEXT: [[MFMA_USE1]].sub7:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec46# CHECK-NEXT: [[MFMA_USE1]].sub8:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec47# CHECK-NEXT: [[MFMA_USE1]].sub9:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec48# CHECK-NEXT: [[MFMA_USE1]].sub10:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec49# CHECK-NEXT: [[MFMA_USE1]].sub11:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec50# CHECK-NEXT: [[MFMA_USE1]].sub12:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec51# CHECK-NEXT: [[MFMA_USE1]].sub13:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec52# CHECK-NEXT: [[MFMA_USE1]].sub14:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec53# CHECK-NEXT: [[MFMA_USE1]].sub15:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec54# CHECK-NEXT: [[MFMA_USE1]]:vreg_512_align2 = V_MFMA_F32_16X16X1F32_mac_vgprcd_e64 undef %3:vgpr_32, undef %3:vgpr_32, [[MFMA_USE1]], 0, 0, 0, implicit $mode, implicit $exec55 56---57name: inflated_reg_class_copy_use_after_free58tracksRegLiveness: true59machineFunctionInfo:60 isEntryFunction: true61 scratchRSrcReg: '$sgpr72_sgpr73_sgpr74_sgpr75'62 stackPtrOffsetReg: '$sgpr32'63 occupancy: 764 vgprForAGPRCopy: '$vgpr255'65 sgprForEXECCopy: '$sgpr74_sgpr75'66body: |67 bb.0:68 liveins: $vgpr0, $sgpr4_sgpr569 70 %0:vgpr_32 = IMPLICIT_DEF71 renamable $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed undef renamable $sgpr4_sgpr5, 0, 0 :: (load (s64), addrspace 4)72 S_NOP 0, implicit-def undef %1.sub12_sub13_sub14_sub15:vreg_512_align273 S_NOP 0, implicit-def %1.sub8_sub9_sub10_sub11:vreg_512_align274 S_NOP 0, implicit-def %1.sub4_sub5_sub6_sub7:vreg_512_align275 S_NOP 0, implicit-def %1.sub0_sub1_sub2_sub3:vreg_512_align276 early-clobber %2:vreg_512_align2 = V_MFMA_F32_16X16X1F32_vgprcd_e64 undef %3:vgpr_32, undef %3:vgpr_32, %1, 0, 0, 0, implicit $mode, implicit $exec, implicit $mode, implicit $exec77 %1.sub2:vreg_512_align2 = COPY %2.sub378 %1.sub3:vreg_512_align2 = COPY %2.sub279 %1.sub4:vreg_512_align2 = COPY %2.sub080 %1.sub5:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec81 %1.sub6:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec82 %1.sub7:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec83 %1.sub8:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec84 %1.sub9:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec85 %1.sub10:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec86 %1.sub11:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec87 %1.sub12:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec88 %1.sub13:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec89 %1.sub14:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec90 %1.sub15:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec91 %1:vreg_512_align2 = V_MFMA_F32_16X16X1F32_mac_vgprcd_e64 undef %3:vgpr_32, undef %3:vgpr_32, %1, 0, 0, 0, implicit $mode, implicit $exec92 GLOBAL_STORE_DWORDX4_SADDR undef %3:vgpr_32, %1.sub12_sub13_sub14_sub15, undef renamable $sgpr0_sgpr1, 96, 0, implicit $exec :: (store (s128), addrspace 1)93 S_ENDPGM 094 95...96 97# This test is similar to except it is still broken when the use98# instruction does not read the full set of lanes after one attempted fix.99 100# CHECK-LABEL: name: inflated_reg_class_copy_use_after_free_lane_subset101# CHECK: S_NOP 0, implicit-def [[ORIG_REG:%[0-9]+]].sub0_sub1_sub2_sub3102# CHECK-NEXT: SI_SPILL_AV512_SAVE [[ORIG_REG]], %stack.0, $sgpr32, 0, implicit $exec :: (store (s512) into %stack.0, align 4, addrspace 5)103# CHECK-NEXT: [[RESTORE_0:%[0-9]+]]:av_512_align2 = SI_SPILL_AV512_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load (s512) from %stack.0, align 4, addrspace 5)104# CHECK-NEXT: S_NOP 0, implicit-def early-clobber $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit [[RESTORE_0]].sub0_sub1_sub2_sub3, implicit [[RESTORE_0]].sub4_sub5_sub6_sub7105# CHECK-NEXT: undef [[SPLIT0:%[0-9]+]].sub2_sub3:av_512_align2 = COPY undef $vgpr2_vgpr3 {106# CHECK-NEXT: internal [[SPLIT0]].sub0:av_512_align2 = COPY undef $vgpr0107# CHECK-NEXT: }108# CHECK-NEXT: undef [[SPLIT1:%[0-9]+]].sub2_sub3:av_512_align2 = COPY [[SPLIT0]].sub2_sub3 {109# CHECK-NEXT: internal [[SPLIT1]].sub0:av_512_align2 = COPY [[SPLIT0]].sub0110# CHECK-NEXT: }111# CHECK-NEXT: undef [[SPLIT2:%[0-9]+]].sub2_sub3:av_512_align2 = COPY [[SPLIT1]].sub2_sub3 {112# CHECK-NEXT: internal [[SPLIT2]].sub0:av_512_align2 = COPY [[SPLIT1]].sub0113# CHECK-NEXT: }114# CHECK-NEXT: SI_SPILL_AV512_SAVE [[SPLIT2]], %stack.1, $sgpr32, 0, implicit $exec :: (store (s512) into %stack.1, align 4, addrspace 5)115# CHECK-NEXT: [[RESTORE_1:%[0-9]+]]:av_512_align2 = SI_SPILL_AV512_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load (s512) from %stack.0, align 4, addrspace 5)116# CHECK-NEXT: undef [[SPLIT3:%[0-9]+]].sub0_sub1:av_512_align2 = COPY [[RESTORE_1]].sub0_sub1117# CHECK-NEXT: [[RESTORE_2:%[0-9]+]]:av_512_align2 = SI_SPILL_AV512_RESTORE %stack.1, $sgpr32, 0, implicit $exec :: (load (s512) from %stack.1, align 4, addrspace 5)118# CHECK-NEXT: undef [[SPLIT4:%[0-9]+]].sub2_sub3:av_512_align2 = COPY [[RESTORE_2]].sub2_sub3 {119# CHECK-NEXT: internal [[SPLIT4]].sub0:av_512_align2 = COPY [[RESTORE_2]].sub0120# CHECK-NEXT: }121# CHECK-NEXT: undef [[SPLIT5:%[0-9]+]].sub2_sub3:av_512_align2 = COPY [[SPLIT4]].sub2_sub3 {122# CHECK-NEXT: internal [[SPLIT5]].sub0:av_512_align2 = COPY [[SPLIT4]].sub0123# CHECK-NEXT: }124# CHECK-NEXT: [[SPLIT3]].sub2:av_512_align2 = COPY [[SPLIT5]].sub3125# CHECK-NEXT: undef [[SPLIT6:%[0-9]+]].sub0_sub1_sub2:av_512_align2 = COPY [[SPLIT3]].sub0_sub1_sub2126# CHECK-NEXT: undef [[SPLIT7:%[0-9]+]].sub0_sub1_sub2:av_512_align2 = COPY [[SPLIT6]].sub0_sub1_sub2127# CHECK-NEXT: undef [[SPLIT8:%[0-9]+]].sub0:av_512_align2 = COPY [[SPLIT5]].sub0 {128# CHECK-NEXT: internal [[SPLIT8]].sub2:av_512_align2 = COPY [[SPLIT5]].sub2129# CHECK-NEXT: }130# CHECK-NEXT: [[SPLIT7]].sub3:av_512_align2 = COPY [[SPLIT8]].sub2131# CHECK-NEXT: undef [[SPLIT9:%[0-9]+]].sub0_sub1_sub2_sub3:av_512_align2 = COPY [[SPLIT7]].sub0_sub1_sub2_sub3132# CHECK-NEXT: undef [[LAST_USE:%[0-9]+]].sub0_sub1_sub2_sub3:vreg_512_align2 = COPY [[SPLIT9]].sub0_sub1_sub2_sub3133# CHECK-NEXT: [[LAST_USE]].sub4:vreg_512_align2 = COPY [[SPLIT8]].sub0134# CHECK-NEXT: [[LAST_USE]].sub5:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec135# CHECK-NEXT: [[LAST_USE]].sub6:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec136# CHECK-NEXT: [[LAST_USE]].sub7:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec137# CHECK-NEXT: [[LAST_USE]].sub8:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec138# CHECK-NEXT: [[LAST_USE]].sub9:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec139# CHECK-NEXT: [[LAST_USE]].sub10:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec140# CHECK-NEXT: [[LAST_USE]].sub11:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec141# CHECK-NEXT: [[LAST_USE]].sub12:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec142# CHECK-NEXT: [[LAST_USE]].sub13:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec143# CHECK-NEXT: [[LAST_USE]].sub14:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec144# CHECK-NEXT: [[LAST_USE]].sub15:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec145# CHECK-NEXT: S_NOP 0, implicit-def [[LAST_USE]], implicit [[LAST_USE]].sub0_sub1_sub2_sub3, implicit [[LAST_USE]].sub4_sub5_sub6_sub7, implicit [[LAST_USE]].sub8_sub9_sub10_sub11146 147---148name: inflated_reg_class_copy_use_after_free_lane_subset149tracksRegLiveness: true150machineFunctionInfo:151 isEntryFunction: true152 scratchRSrcReg: '$sgpr72_sgpr73_sgpr74_sgpr75'153 stackPtrOffsetReg: '$sgpr32'154 occupancy: 7155 vgprForAGPRCopy: '$vgpr255'156 sgprForEXECCopy: '$sgpr74_sgpr75'157body: |158 bb.0:159 liveins: $vgpr0, $sgpr4_sgpr5160 161 %0:vgpr_32 = IMPLICIT_DEF162 renamable $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed undef renamable $sgpr4_sgpr5, 0, 0 :: (load (s64), addrspace 4)163 S_NOP 0, implicit-def undef %1.sub12_sub13_sub14_sub15:vreg_512_align2164 S_NOP 0, implicit-def %1.sub8_sub9_sub10_sub11:vreg_512_align2165 S_NOP 0, implicit-def %1.sub4_sub5_sub6_sub7:vreg_512_align2166 S_NOP 0, implicit-def %1.sub0_sub1_sub2_sub3:vreg_512_align2167 S_NOP 0, implicit-def early-clobber %2:vreg_512_align2, implicit %1.sub0_sub1_sub2_sub3, implicit %1.sub4_sub5_sub6_sub7168 %1.sub2:vreg_512_align2 = COPY %2.sub3169 %1.sub3:vreg_512_align2 = COPY %2.sub2170 %1.sub4:vreg_512_align2 = COPY %2.sub0171 %1.sub5:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec172 %1.sub6:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec173 %1.sub7:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec174 %1.sub8:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec175 %1.sub9:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec176 %1.sub10:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec177 %1.sub11:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec178 %1.sub12:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec179 %1.sub13:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec180 %1.sub14:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec181 %1.sub15:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec182 S_NOP 0, implicit-def %1:vreg_512_align2, implicit %1.sub0_sub1_sub2_sub3, implicit %1.sub4_sub5_sub6_sub7, implicit %1.sub8_sub9_sub10_sub11183 GLOBAL_STORE_DWORDX4_SADDR undef %3:vgpr_32, %1.sub12_sub13_sub14_sub15, undef renamable $sgpr0_sgpr1, 96, 0, implicit $exec :: (store (s128), addrspace 1)184 S_ENDPGM 0185 186...187