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1; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx1200 < %s | FileCheck %s2 3; CHECK-LABEL: .shader_functions:4 5; Make sure that .vgpr_count doesn't include the %inactive.vgpr registers.6; CHECK-LABEL: leaf_shader:7; CHECK: .vgpr_count: 0xc{{$}}8 9; Function without calls.10define amdgpu_cs_chain void @_leaf_shader(ptr %output.ptr, i32 inreg %input.value,11 i32 %active.vgpr1, i32 %active.vgpr2,12 i32 %inactive.vgpr1, i32 %inactive.vgpr2, i32 %inactive.vgpr3,13 i32 %inactive.vgpr4, i32 %inactive.vgpr5, i32 %inactive.vgpr6)14 local_unnamed_addr {15entry:16 %dead.val = call i32 @llvm.amdgcn.dead.i32()17 %is.whole.wave = call i1 @llvm.amdgcn.init.whole.wave()18 br i1 %is.whole.wave, label %compute, label %merge19 20compute:21 ; Perform a more complex computation using active VGPRs22 %square = mul i32 %active.vgpr1, %active.vgpr123 %product = mul i32 %square, %active.vgpr224 %sum = add i32 %product, %input.value25 %result = add i32 %sum, 4226 br label %merge27 28merge:29 %final.result = phi i32 [ 0, %entry ], [ %result, %compute ]30 %final.inactive1 = phi i32 [ %inactive.vgpr1, %entry ], [ %dead.val, %compute ]31 %final.inactive2 = phi i32 [ %inactive.vgpr2, %entry ], [ %dead.val, %compute ]32 %final.inactive3 = phi i32 [ %inactive.vgpr3, %entry ], [ %dead.val, %compute ]33 %final.inactive4 = phi i32 [ %inactive.vgpr4, %entry ], [ %dead.val, %compute ]34 %final.inactive5 = phi i32 [ %inactive.vgpr5, %entry ], [ %dead.val, %compute ]35 %final.inactive6 = phi i32 [ %inactive.vgpr6, %entry ], [ %dead.val, %compute ]36 37 store i32 %final.result, ptr %output.ptr, align 438 39 ret void40}41 42declare i32 @llvm.amdgcn.dead.i32()43declare i1 @llvm.amdgcn.init.whole.wave()44declare void @llvm.amdgcn.cs.chain.p0.i32.v4i32.sl_i32i32i32i32i32i32i32i32i32i32i32i32s(ptr, i32, <4 x i32>, { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }, i32 immarg, ...)45 46declare amdgpu_cs_chain void @retry_vgpr_alloc.v4i32(<4 x i32> inreg)47