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1; RUN: llc -mtriple=amdgcn < %s | FileCheck --check-prefix=CHECK %s2; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck --check-prefix=CHECK %s3 4; CHECK-LABEL: {{^}}inline_asm:5; CHECK: s_endpgm6; CHECK: s_endpgm7define amdgpu_kernel void @inline_asm(ptr addrspace(1) %out) {8entry:9 store i32 5, ptr addrspace(1) %out10 call void asm sideeffect "s_endpgm", ""()11 ret void12}13 14; CHECK-LABEL: {{^}}inline_asm_shader:15; CHECK: s_endpgm16; CHECK: s_endpgm17define amdgpu_ps void @inline_asm_shader() {18entry:19 call void asm sideeffect "s_endpgm", ""()20 ret void21}22 23 24; CHECK-LABEL: {{^}}branch_on_asm_vgpr:25; Make sure VGPR inline assembly is treated as divergent.26; CHECK: v_mov_b32 v{{[0-9]+}}, 027; CHECK: v_cmp_eq_u3228; CHECK: s_and_saveexec_b6429define amdgpu_kernel void @branch_on_asm_vgpr(ptr addrspace(1) %out) {30 %zero = call i32 asm "v_mov_b32 $0, 0", "=v"()31 %cmp = icmp eq i32 %zero, 032 br i1 %cmp, label %if, label %endif33 34if:35 store i32 0, ptr addrspace(1) %out36 br label %endif37 38endif:39 ret void40}41 42; CHECK-LABEL: {{^}}branch_on_asm_sgpr:43; Make sure SGPR inline assembly is treated as uniform44; CHECK: s_mov_b32 s{{[0-9]+}}, 045; CHECK: s_cmp_lg_u3246; CHECK: s_cbranch_scc047define amdgpu_kernel void @branch_on_asm_sgpr(ptr addrspace(1) %out) {48 %zero = call i32 asm "s_mov_b32 $0, 0", "=s"()49 %cmp = icmp eq i32 %zero, 050 br i1 %cmp, label %if, label %endif51 52if:53 store i32 0, ptr addrspace(1) %out54 br label %endif55 56endif:57 ret void58}59 60; CHECK-LABEL: {{^}}v_cmp_asm:61; CHECK: v_mov_b32_e32 [[SRC:v[0-9]+]], s{{[0-9]+}}62; CHECK: v_cmp_ne_u32_e64 s[[[MASK_LO:[0-9]+]]:[[MASK_HI:[0-9]+]]], 0, [[SRC]]63; CHECK-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[MASK_LO]]64; CHECK-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], s[[MASK_HI]]65; CHECK: buffer_store_dwordx2 v[[[V_LO]]:[[V_HI]]]66define amdgpu_kernel void @v_cmp_asm(ptr addrspace(1) %out, i32 %in) {67 %sgpr = tail call i64 asm "v_cmp_ne_u32_e64 $0, 0, $1", "=s,v"(i32 %in)68 store i64 %sgpr, ptr addrspace(1) %out69 ret void70}71 72; CHECK-LABEL: {{^}}code_size_inline_asm:73; CHECK: codeLenInByte = 1274define amdgpu_kernel void @code_size_inline_asm(ptr addrspace(1) %out) {75entry:76 call void asm sideeffect "v_nop_e64", ""()77 ret void78}79 80; All inlineasm instructions are assumed to be the maximum size81; CHECK-LABEL: {{^}}code_size_inline_asm_small_inst:82; CHECK: codeLenInByte = 1283define amdgpu_kernel void @code_size_inline_asm_small_inst(ptr addrspace(1) %out) {84entry:85 call void asm sideeffect "v_nop_e32", ""()86 ret void87}88 89; CHECK-LABEL: {{^}}code_size_inline_asm_2_inst:90; CHECK: codeLenInByte = 2091define amdgpu_kernel void @code_size_inline_asm_2_inst(ptr addrspace(1) %out) {92entry:93 call void asm sideeffect "94 v_nop_e6495 v_nop_e6496 ", ""()97 ret void98}99 100; CHECK-LABEL: {{^}}code_size_inline_asm_2_inst_extra_newline:101; CHECK: codeLenInByte = 20102define amdgpu_kernel void @code_size_inline_asm_2_inst_extra_newline(ptr addrspace(1) %out) {103entry:104 call void asm sideeffect "105 v_nop_e64106 107 v_nop_e64108 ", ""()109 ret void110}111 112; CHECK-LABEL: {{^}}code_size_inline_asm_0_inst:113; CHECK: codeLenInByte = 4114define amdgpu_kernel void @code_size_inline_asm_0_inst(ptr addrspace(1) %out) {115entry:116 call void asm sideeffect "", ""()117 ret void118}119 120; CHECK-LABEL: {{^}}code_size_inline_asm_1_comment:121; CHECK: codeLenInByte = 4122define amdgpu_kernel void @code_size_inline_asm_1_comment(ptr addrspace(1) %out) {123entry:124 call void asm sideeffect "; comment", ""()125 ret void126}127 128; CHECK-LABEL: {{^}}code_size_inline_asm_newline_1_comment:129; CHECK: codeLenInByte = 4130define amdgpu_kernel void @code_size_inline_asm_newline_1_comment(ptr addrspace(1) %out) {131entry:132 call void asm sideeffect "133; comment", ""()134 ret void135}136 137; CHECK-LABEL: {{^}}code_size_inline_asm_1_comment_newline:138; CHECK: codeLenInByte = 4139define amdgpu_kernel void @code_size_inline_asm_1_comment_newline(ptr addrspace(1) %out) {140entry:141 call void asm sideeffect "; comment142", ""()143 ret void144}145 146; CHECK-LABEL: {{^}}code_size_inline_asm_2_comments_line:147; CHECK: codeLenInByte = 4148define amdgpu_kernel void @code_size_inline_asm_2_comments_line(ptr addrspace(1) %out) {149entry:150 call void asm sideeffect "; first comment ; second comment", ""()151 ret void152}153 154; CHECK-LABEL: {{^}}code_size_inline_asm_2_comments_line_nospace:155; CHECK: codeLenInByte = 4156define amdgpu_kernel void @code_size_inline_asm_2_comments_line_nospace(ptr addrspace(1) %out) {157entry:158 call void asm sideeffect "; first comment;second comment", ""()159 ret void160}161 162; CHECK-LABEL: {{^}}code_size_inline_asm_mixed_comments0:163; CHECK: codeLenInByte = 20164define amdgpu_kernel void @code_size_inline_asm_mixed_comments0(ptr addrspace(1) %out) {165entry:166 call void asm sideeffect "; comment167 v_nop_e64 ; inline comment168; separate comment169 v_nop_e64170 171 ; trailing comment172 ; extra comment173 ", ""()174 ret void175}176 177; CHECK-LABEL: {{^}}code_size_inline_asm_mixed_comments1:178; CHECK: codeLenInByte = 20179define amdgpu_kernel void @code_size_inline_asm_mixed_comments1(ptr addrspace(1) %out) {180entry:181 call void asm sideeffect "v_nop_e64 ; inline comment182; separate comment183 v_nop_e64184 185 ; trailing comment186 ; extra comment187 ", ""()188 ret void189}190 191; CHECK-LABEL: {{^}}code_size_inline_asm_mixed_comments_operands:192; CHECK: codeLenInByte = 20193define amdgpu_kernel void @code_size_inline_asm_mixed_comments_operands(ptr addrspace(1) %out) {194entry:195 call void asm sideeffect "; comment196 v_add_i32_e32 v0, vcc, v1, v2 ; inline comment197; separate comment198 v_bfrev_b32_e32 v0, 1199 200 ; trailing comment201 ; extra comment202 ", ""()203 ret void204}205 206; FIXME: Should not have intermediate sgprs207; CHECK-LABEL: {{^}}i64_imm_input_phys_vgpr:208; CHECK: v_mov_b32_e32 v0, 0x1e240209; CHECK: v_mov_b32_e32 v1, 0210; CHECK: use v[0:1]211define amdgpu_kernel void @i64_imm_input_phys_vgpr() {212entry:213 call void asm sideeffect "; use $0 ", "{v[0:1]}"(i64 123456)214 ret void215}216 217; CHECK-LABEL: {{^}}i1_imm_input_phys_vgpr:218; CHECK: v_mov_b32_e32 v0, 1{{$}}219; CHECK: ; use v0220define amdgpu_kernel void @i1_imm_input_phys_vgpr() {221entry:222 call void asm sideeffect "; use $0 ", "{v0}"(i1 true)223 ret void224}225 226 227; FIXME: This behavior is nonsense. We should probably disallow i1 asm228 229; CHECK-LABEL: {{^}}i1_input_phys_vgpr:230; CHECK: {{buffer|flat}}_load_ubyte [[LOAD:v[0-9]+]]231; CHECK-NOT: [[LOAD]]232; CHECK: ; use v0233; CHECK: v_and_b32_e32 [[STORE:v[0-9]+]], 1, v1234; CHECK: {{buffer|flat}}_store_byte [[STORE]],235define amdgpu_kernel void @i1_input_phys_vgpr() {236entry:237 %val = load i1, ptr addrspace(1) poison238 %cc = call i1 asm sideeffect "; use $1, def $0 ", "={v1}, {v0}"(i1 %val)239 store i1 %cc, ptr addrspace(1) poison240 ret void241}242 243; FIXME: Should prodbably be masking high bits of load.244; CHECK-LABEL: {{^}}i1_input_phys_vgpr_x2:245; CHECK: buffer_load_ubyte v0246; CHECK-NEXT: s_waitcnt247; CHECK-NEXT: buffer_load_ubyte v1248; CHECK-NEXT: s_waitcnt249; CHECK-NEXT: ASMSTART250define amdgpu_kernel void @i1_input_phys_vgpr_x2() {251entry:252 %val0 = load volatile i1, ptr addrspace(1) poison253 %val1 = load volatile i1, ptr addrspace(1) poison254 call void asm sideeffect "; use $0 $1 ", "{v0}, {v1}"(i1 %val0, i1 %val1)255 ret void256}257 258; CHECK-LABEL: {{^}}muliple_def_phys_vgpr:259; CHECK: ; def v0260; CHECK: v_mov_b32_e32 v1, v0261; CHECK: ; def v0262; CHECK: v_lshlrev_b32_e32 v{{[0-9]+}}, v0, v1263define amdgpu_kernel void @muliple_def_phys_vgpr() {264entry:265 %def0 = call i32 asm sideeffect "; def $0 ", "={v0}"()266 %def1 = call i32 asm sideeffect "; def $0 ", "={v0}"()267 %add = shl i32 %def0, %def1268 store i32 %add, ptr addrspace(1) poison269 ret void270}271 272; CHECK-LABEL: {{^}}asm_constraint_c_n:273; CHECK: s_trap 10{{$}}274define amdgpu_kernel void @asm_constraint_c_n() {275entry:276 tail call void asm sideeffect "s_trap ${0:c}", "n"(i32 10) #1277 ret void278}279 280; CHECK-LABEL: {{^}}asm_constraint_n_n:281; CHECK: s_trap -10{{$}}282define amdgpu_kernel void @asm_constraint_n_n() {283entry:284 tail call void asm sideeffect "s_trap ${0:n}", "n"(i32 10) #1285 ret void286}287 288; Make sure tuples of 3 SGPRs are printed with the [] syntax instead289; of the tablegen default.290; CHECK-LABEL: {{^}}sgpr96_name_format:291; CHECK: ; sgpr96 s[0:2]292define amdgpu_kernel void @sgpr96_name_format() {293entry:294 tail call void asm sideeffect "; sgpr96 $0", "s"(<3 x i32> <i32 10, i32 11, i32 12>) #1295 ret void296}297 298; Check aggregate types are handled properly.299; CHECK-LABEL: mad_u64300; CHECK: v_mad_u64_u32301define void @mad_u64(i32 %x, i1 %c0) {302entry:303 br i1 %c0, label %exit, label %false304 305false:306 %s0 = tail call { i64, i64 } asm sideeffect "v_mad_u64_u32 $0, $1, $2, $3, $4", "=v,=s,v,v,v"(i32 -766435501, i32 %x, i64 0)307 br label %exit308 309exit:310 %s1 = phi { i64, i64} [ poison, %entry ], [ %s0, %false]311 %v0 = extractvalue { i64, i64 } %s1, 0312 %v1 = extractvalue { i64, i64 } %s1, 1313 tail call void asm sideeffect "; use $0", "v"(i64 %v0)314 tail call void asm sideeffect "; use $0", "v"(i64 %v1)315 ret void316}317 318; CHECK-LABEL: {{^}}scc_as_i32:319; CHECK: ; def scc320; CHECK: ; use scc321define void @scc_as_i32() {322 %scc = call i32 asm sideeffect "; def $0", "={scc}"()323 call void asm sideeffect "; use $0 ", "{scc}"(i32 %scc)324 ret void325}326 327; CHECK-LABEL: {{^}}scc_as_i1:328; CHECK: ; def scc329; CHECK: ; use scc330define void @scc_as_i1() {331 %scc = call i1 asm sideeffect "; def $0", "={scc}"()332 call void asm sideeffect "; use $0 ", "{scc}"(i1 %scc)333 ret void334}335 336; Make sure the SGPR def is treated as a uniform value when the inline337; assembly also defines a divergent value. The add should be scalar338; and not introduce illegal vgpr to sgpr copies.339; CHECK-LABEL: {{^}}mixed_def_vgpr_sgpr_def_asm:340; CHECK: ; def v0 s[4:5]341; CHECK: s_add_u32342; CHECK-NEXT: s_addc_u32343; CHECK: ; use s[4:5]344define void @mixed_def_vgpr_sgpr_def_asm() {345 %vgpr_sgpr = call { i32, i64 } asm sideeffect "; def $0 $1 ", "=v,={s[4:5]}"()346 %vgpr = extractvalue { i32, i64 } %vgpr_sgpr, 0347 %sgpr = extractvalue { i32, i64 } %vgpr_sgpr, 1348 %sgpr.add = add i64 %sgpr, 2349 call void asm sideeffect "; use $0 ", "{s[4:5]}"(i64 %sgpr.add)350 ret void351}352 353; CHECK-LABEL: {{^}}mixed_def_sgpr_vgpr_def_asm:354; CHECK: ; def s[4:5] v0355; CHECK: s_add_u32356; CHECK-NEXT: s_addc_u32357; CHECK: ; use s[4:5]358define void @mixed_def_sgpr_vgpr_def_asm() {359 %sgpr_vgpr = call { i64, i32 } asm sideeffect "; def $0 $1 ", "={s[4:5]},=v"()360 %sgpr = extractvalue { i64, i32 } %sgpr_vgpr, 0361 %vgpr = extractvalue { i64, i32 } %sgpr_vgpr, 1362 %sgpr.add = add i64 %sgpr, 2363 call void asm sideeffect "; use $0 ", "{s[4:5]}"(i64 %sgpr.add)364 ret void365}366