71 lines · plain
1; RUN: opt -mtriple=amdgcn-- -passes='cgscc(inline)' -S -amdgpu-inline-max-bb=2 %s | FileCheck %s --check-prefix=NOINL2; RUN: opt -mtriple=amdgcn-- -passes='cgscc(inline)' -S -amdgpu-inline-max-bb=3 %s | FileCheck %s --check-prefix=INL3; RUN: opt -mtriple=amdgcn-- -passes=inline -S -amdgpu-inline-max-bb=2 %s | FileCheck %s --check-prefix=NOINL4; RUN: opt -mtriple=amdgcn-- -passes=inline -S -amdgpu-inline-max-bb=3 %s | FileCheck %s --check-prefix=INL5 6define i32 @callee(i32 %x) {7entry:8 %cc = icmp eq i32 %x, 19 br i1 %cc, label %ret_res, label %mulx10 11mulx:12 %mul1 = mul i32 %x, %x13 %mul2 = mul i32 %mul1, %x14 %mul3 = mul i32 %mul1, %mul215 %mul4 = mul i32 %mul3, %mul216 %mul5 = mul i32 %mul4, %mul317 br label %ret_res18 19ret_res:20 %r = phi i32 [ %mul5, %mulx ], [ %x, %entry ]21 ret i32 %r22}23 24; INL-LABEL: @caller25; NOINL-LABEL: @caller26; INL: mul i3227; INL-NOT: call i3228; NOINL-NOT: mul i3229; NOINL: call i3230 31define amdgpu_kernel void @caller(i32 %x) {32 %res = call i32 @callee(i32 %x)33 store volatile i32 %res, ptr addrspace(1) poison34 ret void35}36 37 38; inlinehint39define i32 @callee_hint(i32 %x) #0 {40entry:41 %cc = icmp eq i32 %x, 142 br i1 %cc, label %ret_res, label %mulx43 44mulx:45 %mul1 = mul i32 %x, %x46 %mul2 = mul i32 %mul1, %x47 %mul3 = mul i32 %mul1, %mul248 %mul4 = mul i32 %mul3, %mul249 %mul5 = mul i32 %mul4, %mul350 br label %ret_res51 52ret_res:53 %r = phi i32 [ %mul5, %mulx ], [ %x, %entry ]54 ret i32 %r55}56 57; INL-LABEL: @caller_hint58; NOINL-LABEL: @caller_hint59; INL: mul i3260; INL-NOT: call i3261; NOINL: mul i3262; NOINL-NOT: call i3263 64define amdgpu_kernel void @caller_hint(i32 %x) {65 %res = call i32 @callee_hint(i32 %x)66 store volatile i32 %res, ptr addrspace(1) poison67 ret void68}69 70attributes #0 = { inlinehint }71