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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefix=CHECK %s3 4; Allow single registers that are too wide for the IR type:5 6define i16 @inline_asm_i16_in_v_def() {7; CHECK-LABEL: inline_asm_i16_in_v_def:8; CHECK: ; %bb.0:9; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)10; CHECK-NEXT: ;;#ASMSTART11; CHECK-NEXT: ; def v812; CHECK-NEXT: ;;#ASMEND13; CHECK-NEXT: ;;#ASMSTART14; CHECK-NEXT: ; def v015; CHECK-NEXT: ;;#ASMEND16; CHECK-NEXT: v_and_b32_e32 v0, v8, v017; CHECK-NEXT: s_setpc_b64 s[30:31]18 %phys = call i16 asm sideeffect "; def $0", "={v8}"()19 %virt = call i16 asm sideeffect "; def $0", "=v"()20 %r = and i16 %phys, %virt21 ret i16 %r22}23 24define void @inline_asm_i16_in_v_use(i16 %val) {25; CHECK-LABEL: inline_asm_i16_in_v_use:26; CHECK: ; %bb.0:27; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)28; CHECK-NEXT: v_and_b32_e32 v8, 0xffff, v029; CHECK-NEXT: ;;#ASMSTART30; CHECK-NEXT: ; use v831; CHECK-NEXT: ;;#ASMEND32; CHECK-NEXT: ;;#ASMSTART33; CHECK-NEXT: ; use v834; CHECK-NEXT: ;;#ASMEND35; CHECK-NEXT: s_setpc_b64 s[30:31]36 call void asm sideeffect "; use $0", "{v8}"(i16 %val)37 call void asm sideeffect "; use $0", "v"(i16 %val)38 ret void39}40 41define i16 @inline_asm_i16_in_s_def() {42; CHECK-LABEL: inline_asm_i16_in_s_def:43; CHECK: ; %bb.0:44; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)45; CHECK-NEXT: ;;#ASMSTART46; CHECK-NEXT: ; def s847; CHECK-NEXT: ;;#ASMEND48; CHECK-NEXT: ;;#ASMSTART49; CHECK-NEXT: ; def s450; CHECK-NEXT: ;;#ASMEND51; CHECK-NEXT: s_and_b32 s4, s8, s452; CHECK-NEXT: v_mov_b32_e32 v0, s453; CHECK-NEXT: s_setpc_b64 s[30:31]54 %phys = call i16 asm sideeffect "; def $0", "={s8}"()55 %virt = call i16 asm sideeffect "; def $0", "=s"()56 %r = and i16 %phys, %virt57 ret i16 %r58}59 60define i8 @inline_asm_i8_in_v_def() {61; CHECK-LABEL: inline_asm_i8_in_v_def:62; CHECK: ; %bb.0:63; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)64; CHECK-NEXT: ;;#ASMSTART65; CHECK-NEXT: ; def v866; CHECK-NEXT: ;;#ASMEND67; CHECK-NEXT: v_mov_b32_e32 v0, v868; CHECK-NEXT: s_setpc_b64 s[30:31]69 %phys = call i8 asm sideeffect "; def $0", "={v8}"()70 ; %virt = call i8 asm sideeffect "; def $0", "=v"() ; currently fails71 ; %r = and i8 %phys, %virt72 ; ret i8 %r73 ret i8 %phys74}75 76; currently broken, v8 should be set to v0 & 0xFF77define void @inline_asm_i8_in_v_use(i8 %val) {78; CHECK-LABEL: inline_asm_i8_in_v_use:79; CHECK: ; %bb.0:80; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)81; CHECK-NEXT: v_mov_b32_e32 v8, v082; CHECK-NEXT: ;;#ASMSTART83; CHECK-NEXT: ; use v884; CHECK-NEXT: ;;#ASMEND85; CHECK-NEXT: s_setpc_b64 s[30:31]86 call void asm sideeffect "; use $0", "{v8}"(i8 %val)87 ; call void asm sideeffect "; use $0", "v"(i8 %val) ; currently fails88 ret void89}90 91define i8 @inline_asm_i8_in_sphys_def() {92; CHECK-LABEL: inline_asm_i8_in_sphys_def:93; CHECK: ; %bb.0:94; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)95; CHECK-NEXT: ;;#ASMSTART96; CHECK-NEXT: ; def s897; CHECK-NEXT: ;;#ASMEND98; CHECK-NEXT: v_mov_b32_e32 v0, s899; CHECK-NEXT: s_setpc_b64 s[30:31]100 %phys = call i8 asm sideeffect "; def $0", "={s8}"()101 ; %virt = call i8 asm sideeffect "; def $0", "=s"() ; currently fails102 ; %r = and i8 %phys, %virt103 ; ret i8 %r104 ret i8 %phys105}106 107 108; Single registers for vector types that fit are fine.109 110define void @inline_asm_2xi16_in_v_use(<2 x i16> %val) {111; CHECK-LABEL: inline_asm_2xi16_in_v_use:112; CHECK: ; %bb.0:113; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)114; CHECK-NEXT: v_mov_b32_e32 v8, v0115; CHECK-NEXT: ;;#ASMSTART116; CHECK-NEXT: ; use v8117; CHECK-NEXT: ;;#ASMEND118; CHECK-NEXT: ;;#ASMSTART119; CHECK-NEXT: ; use v0120; CHECK-NEXT: ;;#ASMEND121; CHECK-NEXT: s_setpc_b64 s[30:31]122 call void asm sideeffect "; use $0", "{v8}"(<2 x i16> %val)123 call void asm sideeffect "; use $0", "v"(<2 x i16> %val)124 ret void125}126 127define <2 x i16> @inline_asm_2xi16_in_v_def() {128; CHECK-LABEL: inline_asm_2xi16_in_v_def:129; CHECK: ; %bb.0:130; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)131; CHECK-NEXT: ;;#ASMSTART132; CHECK-NEXT: ; def v8133; CHECK-NEXT: ;;#ASMEND134; CHECK-NEXT: ;;#ASMSTART135; CHECK-NEXT: ; def v0136; CHECK-NEXT: ;;#ASMEND137; CHECK-NEXT: v_and_b32_e32 v0, v8, v0138; CHECK-NEXT: s_setpc_b64 s[30:31]139 %phys = call <2 x i16> asm sideeffect "; def $0", "={v8}"()140 %virt = call <2 x i16> asm sideeffect "; def $0", "=v"()141 %r = and <2 x i16> %phys, %virt142 ret <2 x i16> %r143}144 145define <2 x i16> @inline_asm_2xi16_in_s_def() {146; CHECK-LABEL: inline_asm_2xi16_in_s_def:147; CHECK: ; %bb.0:148; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)149; CHECK-NEXT: ;;#ASMSTART150; CHECK-NEXT: ; def s8151; CHECK-NEXT: ;;#ASMEND152; CHECK-NEXT: ;;#ASMSTART153; CHECK-NEXT: ; def s4154; CHECK-NEXT: ;;#ASMEND155; CHECK-NEXT: s_and_b32 s4, s8, s4156; CHECK-NEXT: v_mov_b32_e32 v0, s4157; CHECK-NEXT: s_setpc_b64 s[30:31]158 %phys = call <2 x i16> asm sideeffect "; def $0", "={s8}"()159 %virt = call <2 x i16> asm sideeffect "; def $0", "=s"()160 %r = and <2 x i16> %phys, %virt161 ret <2 x i16> %r162}163