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1# NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64 -verify-machineinstrs -start-before=amdgpu-insert-delay-alu %s -o - | FileCheck %s3 4 5--- |6 7 define void @valu_dep_1() {8 ; CHECK-LABEL: valu_dep_1:9 ; CHECK: ; %bb.0:10 ; CHECK-NEXT: v_add_nc_u32_e32 v0, v0, v011 ; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1)12 ; CHECK-NEXT: v_add_nc_u32_e32 v0, v0, v013 ret void14 }15 16 define void @valu_dep_2() {17 ; CHECK-LABEL: valu_dep_2:18 ; CHECK: ; %bb.0:19 ; CHECK-NEXT: v_add_nc_u32_e32 v0, v0, v020 ; CHECK-NEXT: v_add_nc_u32_e32 v1, v1, v121 ; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_2)22 ; CHECK-NEXT: v_add_nc_u32_e32 v0, v0, v023 ret void24 }25 26 define void @valu_dep_3() {27 ; CHECK-LABEL: valu_dep_3:28 ; CHECK: ; %bb.0:29 ; CHECK-NEXT: v_add_nc_u32_e32 v0, v0, v030 ; CHECK-NEXT: v_add_nc_u32_e32 v1, v1, v131 ; CHECK-NEXT: v_add_nc_u32_e32 v2, v2, v232 ; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_3)33 ; CHECK-NEXT: v_add_nc_u32_e32 v0, v0, v034 ret void35 }36 37 define void @valu_dep_4() {38 ; CHECK-LABEL: valu_dep_4:39 ; CHECK: ; %bb.0:40 ; CHECK-NEXT: v_add_nc_u32_e32 v0, v0, v041 ; CHECK-NEXT: v_add_nc_u32_e32 v1, v1, v142 ; CHECK-NEXT: v_add_nc_u32_e32 v2, v2, v243 ; CHECK-NEXT: v_add_nc_u32_e32 v3, v3, v344 ; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_4)45 ; CHECK-NEXT: v_add_nc_u32_e32 v0, v0, v046 ret void47 }48 49 define void @valu_dep_5() {50 ; CHECK-LABEL: valu_dep_5:51 ; CHECK: ; %bb.0:52 ; CHECK-NEXT: v_add_nc_u32_e32 v0, v0, v053 ; CHECK-NEXT: v_add_nc_u32_e32 v1, v1, v154 ; CHECK-NEXT: v_add_nc_u32_e32 v2, v2, v255 ; CHECK-NEXT: v_add_nc_u32_e32 v3, v3, v356 ; CHECK-NEXT: v_add_nc_u32_e32 v4, v4, v457 ; CHECK-NEXT: v_add_nc_u32_e32 v0, v0, v058 ret void59 }60 61 define void @trans32_dep_1() {62 ; CHECK-LABEL: trans32_dep_1:63 ; CHECK: ; %bb.0:64 ; CHECK-NEXT: v_exp_f32_e32 v0, v065 ; CHECK-NEXT: s_delay_alu instid0(TRANS32_DEP_1)66 ; CHECK-NEXT: v_add_nc_u32_e32 v0, v0, v067 ret void68 }69 70 define void @trans32_dep_2() {71 ; CHECK-LABEL: trans32_dep_2:72 ; CHECK: ; %bb.0:73 ; CHECK-NEXT: v_exp_f32_e32 v0, v074 ; CHECK-NEXT: v_exp_f32_e32 v1, v175 ; CHECK-NEXT: s_delay_alu instid0(TRANS32_DEP_2)76 ; CHECK-NEXT: v_add_nc_u32_e32 v0, v0, v077 ret void78 }79 80 define void @trans32_dep_3() {81 ; CHECK-LABEL: trans32_dep_3:82 ; CHECK: ; %bb.0:83 ; CHECK-NEXT: v_exp_f32_e32 v0, v084 ; CHECK-NEXT: v_exp_f32_e32 v1, v185 ; CHECK-NEXT: v_exp_f32_e32 v2, v286 ; CHECK-NEXT: s_delay_alu instid0(TRANS32_DEP_3)87 ; CHECK-NEXT: v_add_nc_u32_e32 v0, v0, v088 ret void89 }90 91 define void @trans32_dep_4() {92 ; CHECK-LABEL: trans32_dep_4:93 ; CHECK: ; %bb.0:94 ; CHECK-NEXT: v_exp_f32_e32 v0, v095 ; CHECK-NEXT: v_exp_f32_e32 v1, v196 ; CHECK-NEXT: v_exp_f32_e32 v2, v297 ; CHECK-NEXT: v_exp_f32_e32 v3, v398 ; CHECK-NEXT: v_add_nc_u32_e32 v0, v0, v099 ret void100 }101 102 define void @salu_cycle_1() {103 ; CHECK-LABEL: salu_cycle_1:104 ; CHECK: ; %bb.0:105 ; CHECK-NEXT: s_mov_b32 s0, 0106 ; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_1)107 ; CHECK-NEXT: v_add_nc_u32_e32 v0, s0, v0108 ret void109 }110 111 define void @salu_cycle_2() {112 ; CHECK-LABEL: salu_cycle_2:113 ; CHECK: ; %bb.0:114 ; CHECK-NEXT: s_mov_b32 s0, 0115 ; CHECK-NEXT: v_add_nc_u32_e32 v1, v1, v1116 ; CHECK-NEXT: v_add_nc_u32_e32 v0, s0, v0117 ret void118 }119 120 define void @valu_dep_1_same_trans32_dep_1() {121 ; CHECK-LABEL: valu_dep_1_same_trans32_dep_1:122 ; CHECK: ; %bb.0:123 ; CHECK-NEXT: v_exp_f32_e32 v0, v0124 ; CHECK-NEXT: v_add_nc_u32_e32 v1, v1, v1125 ; CHECK-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instid1(VALU_DEP_1)126 ; CHECK-NEXT: v_add_nc_u32_e32 v0, v0, v1127 ret void128 }129 130 define void @trans32_dep_1_only() {131 ; CHECK-LABEL: trans32_dep_1_only:132 ; CHECK: ; %bb.0:133 ; CHECK-NEXT: v_add_nc_u32_e32 v0, v0, v0134 ; CHECK-NEXT: v_exp_f32_e32 v1, v1135 ; CHECK-NEXT: s_delay_alu instid0(TRANS32_DEP_1)136 ; CHECK-NEXT: v_add_nc_u32_e32 v0, v0, v1137 ret void138 }139 140 define void @valu_dep_1_same_salu_cycle_1() {141 ; CHECK-LABEL: valu_dep_1_same_salu_cycle_1:142 ; CHECK: ; %bb.0:143 ; CHECK-NEXT: v_add_nc_u32_e32 v0, v0, v0144 ; CHECK-NEXT: s_mov_b32 s0, 0145 ; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)146 ; CHECK-NEXT: v_add_nc_u32_e32 v0, s0, v0147 ret void148 }149 150 define void @valu_dep_1_next_valu_dep_1() {151 ; CHECK-LABEL: valu_dep_1_next_valu_dep_1:152 ; CHECK: ; %bb.0:153 ; CHECK-NEXT: v_add_nc_u32_e32 v0, v0, v0154 ; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)155 ; CHECK-NEXT: v_add_nc_u32_e32 v0, v0, v0156 ; CHECK-NEXT: v_add_nc_u32_e32 v0, v0, v0157 ret void158 }159 160 define void @valu_dep_2_next_valu_dep_2() {161 ; CHECK-LABEL: valu_dep_2_next_valu_dep_2:162 ; CHECK: ; %bb.0:163 ; CHECK-NEXT: v_add_nc_u32_e32 v0, v0, v0164 ; CHECK-NEXT: v_add_nc_u32_e32 v1, v1, v1165 ; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)166 ; CHECK-NEXT: v_add_nc_u32_e32 v0, v0, v0167 ; CHECK-NEXT: v_add_nc_u32_e32 v1, v1, v1168 ret void169 }170 171 define void @valu_dep_1_no_next_1() {172 ; CHECK-LABEL: valu_dep_1_no_next_1:173 ; CHECK: ; %bb.0:174 ; CHECK-NEXT: v_add_f32_e32 v0, v0, v0175 ; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1)176 ; CHECK-NEXT: v_mul_f32_e32 v1, v0, v0177 ; CHECK-NEXT: v_mul_f32_e32 v2, v0, v0178 ret void179 }180 181 define void @valu_dep_1_no_next_2() {182 ; CHECK-LABEL: valu_dep_1_no_next_2:183 ; CHECK: ; %bb.0:184 ; CHECK-NEXT: v_add_f32_e32 v0, v0, v0185 ; CHECK-NEXT: v_mul_f32_e32 v1, v1, v1186 ; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)187 ; CHECK-NEXT: v_mul_f32_e32 v1, v1, v1188 ; CHECK-NEXT: v_add_f32_e32 v0, v0, v0189 ret void190 }191 192 define void @implicit_cmp_cndmask() {193 ; CHECK-LABEL: implicit_cmp_cndmask:194 ; CHECK: ; %bb.0:195 ; CHECK-NEXT: v_cmp_eq_i32_e32 vcc, v0, v1196 ; CHECK-NEXT: v_cndmask_b32_e64 v2, v3, v4, vcc197 ret void198 }199 200 define void @explicit_cmp_cndmask() {201 ; CHECK-LABEL: explicit_cmp_cndmask:202 ; CHECK: ; %bb.0:203 ; CHECK-NEXT: v_cmp_eq_i32_e64 s[0:1], v0, v1204 ; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1)205 ; CHECK-NEXT: v_cndmask_b32_e64 v2, v3, v4, s[0:1]206 ret void207 }208 209 define void @implicit_addc_addc() {210 ; CHECK-LABEL: implicit_addc_addc:211 ; CHECK: ; %bb.0:212 ; CHECK-NEXT: v_add_co_ci_u32_e32 v0, vcc, v0, v0, vcc213 ; CHECK-NEXT: v_add_co_ci_u32_e32 v1, vcc, v1, v1, vcc214 ret void215 }216 217 define void @explicit_addc_addc() {218 ; CHECK-LABEL: explicit_addc_addc:219 ; CHECK: ; %bb.0:220 ; CHECK-NEXT: v_add_co_u32 v0, vcc, v0, v0221 ; CHECK-NEXT: v_add_co_ci_u32_e32 v1, vcc, v1, v1, vcc222 ret void223 }224 225 define void @valu_dep_3_bundle() {226 ; CHECK-LABEL: valu_dep_3_bundle:227 ; CHECK: ; %bb.0:228 ; CHECK-NEXT: v_add_nc_u32_e32 v0, v0, v0229 ; CHECK-NEXT: v_add_nc_u32_e32 v1, v1, v1230 ; CHECK-NEXT: v_add_nc_u32_e32 v2, v2, v2231 ; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_3)232 ; CHECK-NEXT: v_add_nc_u32_e32 v0, v0, v0233 ret void234 }235 236 define void @if() {237 ; CHECK-LABEL: if:238 ; CHECK: ; %bb.0:239 ; CHECK-NEXT: s_cbranch_vccz .LBB23_2240 ; CHECK-NEXT: ; %bb.1:241 ; CHECK-NEXT: v_add_nc_u32_e32 v0, v0, v0242 ; CHECK-NEXT: .LBB23_2:243 ; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1)244 ; CHECK-NEXT: v_add_nc_u32_e32 v0, v0, v0245 ret void246 }247 248 define void @else() {249 ; CHECK-LABEL: else:250 ; CHECK: ; %bb.0:251 ; CHECK-NEXT: s_cbranch_vccz .LBB24_2252 ; CHECK-NEXT: ; %bb.1:253 ; CHECK-NEXT: s_branch .LBB24_3254 ; CHECK-NEXT: .LBB24_2:255 ; CHECK-NEXT: v_add_nc_u32_e32 v0, v0, v0256 ; CHECK-NEXT: .LBB24_3:257 ; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1)258 ; CHECK-NEXT: v_add_nc_u32_e32 v0, v0, v0259 ret void260 }261 262 define void @if_else() {263 ; CHECK-LABEL: if_else:264 ; CHECK: ; %bb.0:265 ; CHECK-NEXT: s_cbranch_vccz .LBB25_2266 ; CHECK-NEXT: ; %bb.1:267 ; CHECK-NEXT: v_add_nc_u32_e32 v0, v0, v0268 ; CHECK-NEXT: s_branch .LBB25_3269 ; CHECK-NEXT: .LBB25_2:270 ; CHECK-NEXT: v_add_nc_u32_e32 v0, v0, v0271 ; CHECK-NEXT: v_add_nc_u32_e32 v0, v1, v1272 ; CHECK-NEXT: .LBB25_3:273 ; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1)274 ; CHECK-NEXT: v_add_nc_u32_e32 v0, v0, v0275 ret void276 }277 278 define void @loop_1() {279 ; CHECK-LABEL: loop_1:280 ; CHECK: ; %bb.0:281 ; CHECK-NEXT: v_add_nc_u32_e32 v0, v0, v0282 ; CHECK-NEXT: .LBB26_1: ; =>This Inner Loop Header: Depth=1283 ; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1)284 ; CHECK-NEXT: v_add_nc_u32_e32 v1, v0, v0285 ; CHECK-NEXT: s_cbranch_vccz .LBB26_1286 ; CHECK-NEXT: ; %bb.2:287 ret void288 }289 290 define void @loop_2() {291 ; CHECK-LABEL: loop_2:292 ; CHECK: ; %bb.0:293 ; CHECK-NEXT: .LBB27_1: ; =>This Inner Loop Header: Depth=1294 ; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1)295 ; CHECK-NEXT: v_add_nc_u32_e32 v0, v0, v0296 ; CHECK-NEXT: s_cbranch_vccz .LBB27_1297 ; CHECK-NEXT: ; %bb.2:298 ret void299 }300 301 define void @sendmsg_rtn() {302 ; CHECK-LABEL: sendmsg_rtn:303 ; CHECK: ; %bb.0:304 ; CHECK-NEXT: v_mov_b32_e32 v0, 0305 ; CHECK-NEXT: s_sendmsg_rtn_b32 s0, sendmsg(MSG_RTN_GET_DOORBELL)306 ; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_1)307 ; CHECK-NEXT: s_add_u32 s0, s0, s0308 ; CHECK-NEXT: v_add_nc_u32_e32 v0, v0, v0309 ret void310 }311 312 define void @flat_load() {313 ; CHECK-LABEL: flat_load:314 ; CHECK: ; %bb.0:315 ; CHECK-NEXT: v_mov_b32_e32 v0, 0316 ; CHECK-NEXT: v_mov_b32_e32 v1, 0317 ; CHECK-NEXT: v_mov_b32_e32 v2, 0318 ; CHECK-NEXT: flat_load_b32 v0, v[0:1]319 ; CHECK-NEXT: v_add_nc_u32_e32 v0, v2, v2320 ret void321 }322 323 define void @waitcnt_depctr() {324 ; CHECK-LABEL: waitcnt_depctr:325 ; CHECK: ; %bb.0:326 ; CHECK-NEXT: v_mov_b32_e32 v0, 0327 ; CHECK-NEXT: s_waitcnt_depctr 0xfff328 ; CHECK-NEXT: v_add_nc_u32_e32 v0, v0, v0329 ret void330 }331 332 define void @writelane1() {333 ; CHECK-LABEL: writelane1:334 ; CHECK: ; %bb.0:335 ; CHECK-NEXT: v_writelane_b32 v0, s0, 0336 ; CHECK-NEXT: v_writelane_b32 v0, s0, 1337 ; CHECK-NEXT: v_writelane_b32 v0, s0, 2338 ; CHECK-NEXT: v_writelane_b32 v0, s0, 3339 ret void340 }341 342 define void @writelane2() {343 ; CHECK-LABEL: writelane2:344 ; CHECK: ; %bb.0:345 ; CHECK-NEXT: v_writelane_b32 v0, s0, 3346 ; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1)347 ; CHECK-NEXT: v_add_nc_u32_e32 v0, v0, v0348 ret void349 }350 351 define void @delay_alu() {352 ; CHECK-LABEL: delay_alu:353 ; CHECK: ; %bb.0:354 ; CHECK-NEXT: v_cmp_eq_u32_e64 s[0:1], s0, s1355 ; CHECK-NEXT: v_mul_f32_e64 v0, v0, v0356 ; CHECK-NEXT: s_or_b32 s0, s0, s1357 ; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1)358 ; CHECK-NEXT: v_mul_f32_e64 v0, v0, v0359 ret void360 }361 362 define void @redundant_delay_alu() {363 ; CHECK-LABEL: redundant_delay_alu:364 ; CHECK: ; %bb.0:365 ; CHECK-NEXT: v_cmp_eq_u32_e64 s[0:1], s4, s5366 ; CHECK-NEXT: v_mul_f32_e64 v0, v0, v0367 ; CHECK-NEXT: v_cmp_eq_u32_e64 s[6:7], s6, s7368 ; CHECK-NEXT: s_or_b32 s0, s0, s1369 ; CHECK-NEXT: v_mul_f32_e64 v0, v0, v0370 ret void371 }372 373 define void @redundant_delay_alu_2() {374 ; CHECK-LABEL: redundant_delay_alu_2:375 ; CHECK: ; %bb.0:376 ; CHECK-NEXT: v_mul_f32_e64 v0, v0, v0377 ; CHECK-NEXT: v_cmp_eq_u32_e64 s[0:1], s0, s1378 ; CHECK-NEXT: s_or_b32 s0, s0, s1379 ; CHECK-NEXT: v_mul_f32_e64 v0, v0, v0380 ret void;381 }382...383 384---385name: valu_dep_1386body: |387 bb.0:388 $vgpr0 = V_ADD_U32_e32 $vgpr0, $vgpr0, implicit $exec389 $vgpr0 = V_ADD_U32_e32 $vgpr0, $vgpr0, implicit $exec390...391 392---393name: valu_dep_2394body: |395 bb.0:396 $vgpr0 = V_ADD_U32_e32 $vgpr0, $vgpr0, implicit $exec397 $vgpr1 = V_ADD_U32_e32 $vgpr1, $vgpr1, implicit $exec398 $vgpr0 = V_ADD_U32_e32 $vgpr0, $vgpr0, implicit $exec399...400 401---402name: valu_dep_3403body: |404 bb.0:405 $vgpr0 = V_ADD_U32_e32 $vgpr0, $vgpr0, implicit $exec406 $vgpr1 = V_ADD_U32_e32 $vgpr1, $vgpr1, implicit $exec407 $vgpr2 = V_ADD_U32_e32 $vgpr2, $vgpr2, implicit $exec408 $vgpr0 = V_ADD_U32_e32 $vgpr0, $vgpr0, implicit $exec409...410 411---412name: valu_dep_4413body: |414 bb.0:415 $vgpr0 = V_ADD_U32_e32 $vgpr0, $vgpr0, implicit $exec416 $vgpr1 = V_ADD_U32_e32 $vgpr1, $vgpr1, implicit $exec417 $vgpr2 = V_ADD_U32_e32 $vgpr2, $vgpr2, implicit $exec418 $vgpr3 = V_ADD_U32_e32 $vgpr3, $vgpr3, implicit $exec419 $vgpr0 = V_ADD_U32_e32 $vgpr0, $vgpr0, implicit $exec420...421 422# There's no encoding for VALU_DEP_5. A normal VALU instruction will have423# completed already.424---425name: valu_dep_5426body: |427 bb.0:428 $vgpr0 = V_ADD_U32_e32 $vgpr0, $vgpr0, implicit $exec429 $vgpr1 = V_ADD_U32_e32 $vgpr1, $vgpr1, implicit $exec430 $vgpr2 = V_ADD_U32_e32 $vgpr2, $vgpr2, implicit $exec431 $vgpr3 = V_ADD_U32_e32 $vgpr3, $vgpr3, implicit $exec432 $vgpr4 = V_ADD_U32_e32 $vgpr4, $vgpr4, implicit $exec433 $vgpr0 = V_ADD_U32_e32 $vgpr0, $vgpr0, implicit $exec434...435 436---437name: trans32_dep_1438body: |439 bb.0:440 $vgpr0 = V_EXP_F32_e32 $vgpr0, implicit $exec, implicit $mode441 $vgpr0 = V_ADD_U32_e32 $vgpr0, $vgpr0, implicit $exec442...443 444---445name: trans32_dep_2446body: |447 bb.0:448 $vgpr0 = V_EXP_F32_e32 $vgpr0, implicit $exec, implicit $mode449 $vgpr1 = V_EXP_F32_e32 $vgpr1, implicit $exec, implicit $mode450 $vgpr0 = V_ADD_U32_e32 $vgpr0, $vgpr0, implicit $exec451...452 453---454name: trans32_dep_3455body: |456 bb.0:457 $vgpr0 = V_EXP_F32_e32 $vgpr0, implicit $exec, implicit $mode458 $vgpr1 = V_EXP_F32_e32 $vgpr1, implicit $exec, implicit $mode459 $vgpr2 = V_EXP_F32_e32 $vgpr2, implicit $exec, implicit $mode460 $vgpr0 = V_ADD_U32_e32 $vgpr0, $vgpr0, implicit $exec461...462 463# There's no encoding for TRANS32_DEP_4. A normal TRANS instruction will have464# completed already.465---466name: trans32_dep_4467body: |468 bb.0:469 $vgpr0 = V_EXP_F32_e32 $vgpr0, implicit $exec, implicit $mode470 $vgpr1 = V_EXP_F32_e32 $vgpr1, implicit $exec, implicit $mode471 $vgpr2 = V_EXP_F32_e32 $vgpr2, implicit $exec, implicit $mode472 $vgpr3 = V_EXP_F32_e32 $vgpr3, implicit $exec, implicit $mode473 $vgpr0 = V_ADD_U32_e32 $vgpr0, $vgpr0, implicit $exec474...475 476---477name: salu_cycle_1478body: |479 bb.0:480 $sgpr0 = S_MOV_B32 0481 $vgpr0 = V_ADD_U32_e32 $sgpr0, $vgpr0, implicit $exec482...483 484# There's no need for SALU_CYCLE_2 here because the s_mov will have completed485# already.486---487name: salu_cycle_2488body: |489 bb.0:490 $sgpr0 = S_MOV_B32 0491 $vgpr1 = V_ADD_U32_e32 $vgpr1, $vgpr1, implicit $exec492 $vgpr0 = V_ADD_U32_e32 $sgpr0, $vgpr0, implicit $exec493...494 495---496name: valu_dep_1_same_trans32_dep_1497body: |498 bb.0:499 $vgpr0 = V_EXP_F32_e32 $vgpr0, implicit $exec, implicit $mode500 $vgpr1 = V_ADD_U32_e32 $vgpr1, $vgpr1, implicit $exec501 $vgpr0 = V_ADD_U32_e32 $vgpr0, $vgpr1, implicit $exec502...503 504# There's no need to encode the VALU depdendency because it will complete before505# the TRANS.506---507name: trans32_dep_1_only508body: |509 bb.0:510 $vgpr0 = V_ADD_U32_e32 $vgpr0, $vgpr0, implicit $exec511 $vgpr1 = V_EXP_F32_e32 $vgpr1, implicit $exec, implicit $mode512 $vgpr0 = V_ADD_U32_e32 $vgpr0, $vgpr1, implicit $exec513...514 515---516name: valu_dep_1_same_salu_cycle_1517body: |518 bb.0:519 $vgpr0 = V_ADD_U32_e32 $vgpr0, $vgpr0, implicit $exec520 $sgpr0 = S_MOV_B32 0521 $vgpr0 = V_ADD_U32_e32 $sgpr0, $vgpr0, implicit $exec522...523 524---525name: valu_dep_1_next_valu_dep_1526body: |527 bb.0:528 $vgpr0 = V_ADD_U32_e32 $vgpr0, $vgpr0, implicit $exec529 $vgpr0 = V_ADD_U32_e32 $vgpr0, $vgpr0, implicit $exec530 $vgpr0 = V_ADD_U32_e32 $vgpr0, $vgpr0, implicit $exec531...532 533---534name: valu_dep_2_next_valu_dep_2535body: |536 bb.0:537 $vgpr0 = V_ADD_U32_e32 $vgpr0, $vgpr0, implicit $exec538 $vgpr1 = V_ADD_U32_e32 $vgpr1, $vgpr1, implicit $exec539 $vgpr0 = V_ADD_U32_e32 $vgpr0, $vgpr0, implicit $exec540 $vgpr1 = V_ADD_U32_e32 $vgpr1, $vgpr1, implicit $exec541...542 543# There's no need to encode a dependency for the second mul, because the544# dependency for the first mul has already guaranteed that the add has545# completed.546---547name: valu_dep_1_no_next_1548body: |549 bb.0:550 $vgpr0 = V_ADD_F32_e32 $vgpr0, $vgpr0, implicit $exec, implicit $mode551 $vgpr1 = V_MUL_F32_e32 $vgpr0, $vgpr0, implicit $exec, implicit $mode552 $vgpr2 = V_MUL_F32_e32 $vgpr0, $vgpr0, implicit $exec, implicit $mode553...554 555# There's no need to encode a dependency for the second add, because the556# dependency for the second mul has already guaranteed that a later VALU has557# completed.558---559name: valu_dep_1_no_next_2560body: |561 bb.0:562 $vgpr0 = V_ADD_F32_e32 $vgpr0, $vgpr0, implicit $exec, implicit $mode563 $vgpr1 = V_MUL_F32_e32 $vgpr1, $vgpr1, implicit $exec, implicit $mode564 $vgpr1 = V_MUL_F32_e32 $vgpr1, $vgpr1, implicit $exec, implicit $mode565 $vgpr0 = V_ADD_F32_e32 $vgpr0, $vgpr0, implicit $exec, implicit $mode566...567 568# There are no wait states between an add/sub/cmp generating carry and an569# add/sub/cndmask that consumes it, so no need to encode a dependency.570 571---572name: implicit_cmp_cndmask573body: |574 bb.0:575 implicit $vcc = V_CMP_EQ_I32_e32 $vgpr0, $vgpr1, implicit $exec576 $vgpr2 = V_CNDMASK_B32_e64 0, $vgpr3, 0, $vgpr4, $vcc, implicit $exec577...578 579# TODO: There should be no s_delay_alu here.580---581name: explicit_cmp_cndmask582body: |583 bb.0:584 $sgpr0_sgpr1 = V_CMP_EQ_I32_e64 $vgpr0, $vgpr1, implicit $exec585 $vgpr2 = V_CNDMASK_B32_e64 0, $vgpr3, 0, $vgpr4, $sgpr0_sgpr1, implicit $exec586...587 588---589name: implicit_addc_addc590body: |591 bb.0:592 $vgpr0 = V_ADDC_U32_e32 $vgpr0, $vgpr0, implicit-def $vcc, implicit $vcc, implicit $exec593 $vgpr1 = V_ADDC_U32_e32 $vgpr1, $vgpr1, implicit-def $vcc, implicit $vcc, implicit $exec594...595 596---597name: explicit_addc_addc598body: |599 bb.0:600 $vgpr0,$vcc = V_ADD_CO_U32_e64 $vgpr0, $vgpr0, 0, implicit $exec601 $vgpr1 = V_ADDC_U32_e32 $vgpr1, $vgpr1, implicit-def $vcc, implicit $vcc, implicit $exec602...603 604---605name: valu_dep_3_bundle606body: |607 bb.0:608 $vgpr0 = V_ADD_U32_e32 $vgpr0, $vgpr0, implicit $exec609 BUNDLE {610 $vgpr1 = V_ADD_U32_e32 $vgpr1, $vgpr1, implicit $exec611 $vgpr2 = V_ADD_U32_e32 $vgpr2, $vgpr2, implicit $exec612 }613 $vgpr0 = V_ADD_U32_e32 $vgpr0, $vgpr0, implicit $exec614...615 616---617name: if618body: |619 bb.0:620 S_CBRANCH_VCCZ %bb.2, implicit $vcc621 bb.1:622 $vgpr0 = V_ADD_U32_e32 $vgpr0, $vgpr0, implicit $exec623 bb.2:624 $vgpr0 = V_ADD_U32_e32 $vgpr0, $vgpr0, implicit $exec625...626 627---628name: else629body: |630 bb.0:631 S_CBRANCH_VCCZ %bb.2, implicit $vcc632 bb.1:633 S_BRANCH %bb.3634 bb.2:635 $vgpr0 = V_ADD_U32_e32 $vgpr0, $vgpr0, implicit $exec636 bb.3:637 $vgpr0 = V_ADD_U32_e32 $vgpr0, $vgpr0, implicit $exec638...639 640---641name: if_else642body: |643 bb.0:644 S_CBRANCH_VCCZ %bb.2, implicit $vcc645 bb.1:646 $vgpr0 = V_ADD_U32_e32 $vgpr0, $vgpr0, implicit $exec647 S_BRANCH %bb.3648 bb.2:649 $vgpr0 = V_ADD_U32_e32 $vgpr0, $vgpr0, implicit $exec650 $vgpr0 = V_ADD_U32_e32 $vgpr1, $vgpr1, implicit $exec651 bb.3:652 $vgpr0 = V_ADD_U32_e32 $vgpr0, $vgpr0, implicit $exec653...654 655# Dependency from outside the loop.656---657name: loop_1658body: |659 bb.0:660 $vgpr0 = V_ADD_U32_e32 $vgpr0, $vgpr0, implicit $exec661 bb.1:662 $vgpr1 = V_ADD_U32_e32 $vgpr0, $vgpr0, implicit $exec663 S_CBRANCH_VCCZ %bb.1, implicit $vcc664 bb.2:665...666 667# Dependency from inside the loop.668---669name: loop_2670body: |671 bb.0:672 bb.1:673 $vgpr0 = V_ADD_U32_e32 $vgpr0, $vgpr0, implicit $exec674 S_CBRANCH_VCCZ %bb.1, implicit $vcc675 bb.2:676...677 678# No VALU delay across s_sendmsg_rtn because it waits for all outstanding VALU679# to complete.680---681name: sendmsg_rtn682body: |683 bb.0:684 $vgpr0 = V_MOV_B32_e32 0, implicit $exec685 $sgpr0 = S_SENDMSG_RTN_B32 128686 $sgpr0 = S_ADD_U32 $sgpr0, $sgpr0, implicit-def $scc687 $vgpr0 = V_ADD_U32_e32 $vgpr0, $vgpr0, implicit $exec688...689 690# No VALU delay before or across FLAT because it waits for all outstanding VALU691# to complete.692---693name: flat_load694body: |695 bb.0:696 $vgpr0 = V_MOV_B32_e32 0, implicit $exec697 $vgpr1 = V_MOV_B32_e32 0, implicit $exec698 $vgpr2 = V_MOV_B32_e32 0, implicit $exec699 $vgpr0 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, implicit $exec, implicit $flat_scr700 $vgpr0 = V_ADD_U32_e32 $vgpr2, $vgpr2, implicit $exec701...702 703# No VALU delay across an s_waitcnt_depctr that waits for all outstanding VALU704# to complete.705---706name: waitcnt_depctr707body: |708 bb.0:709 $vgpr0 = V_MOV_B32_e32 0, implicit $exec710 S_WAITCNT_DEPCTR 4095711 $vgpr0 = V_ADD_U32_e32 $vgpr0, $vgpr0, implicit $exec712...713 714# Check that no delays are emitted for writelane instructions.715---716name: writelane1717body: |718 bb.0:719 $vgpr0 = V_WRITELANE_B32 $sgpr0, 0, $vgpr0720 $vgpr0 = V_WRITELANE_B32 $sgpr0, 1, $vgpr0721 $vgpr0 = V_WRITELANE_B32 $sgpr0, 2, $vgpr0722 $vgpr0 = V_WRITELANE_B32 $sgpr0, 3, $vgpr0723...724 725# Check if a VALU delay is added after writelane.726---727name: writelane2728body: |729 bb.0:730 $vgpr0 = V_WRITELANE_B32 $sgpr0, 3, $vgpr0731 $vgpr0 = V_ADD_U32_e32 $vgpr0, $vgpr0, implicit $exec732...733# Check if s_delay_alu is added734---735name: delay_alu736body: |737 bb.0:738 $sgpr0_sgpr1 = V_CMP_EQ_U32_e64 $sgpr0, $sgpr1, implicit $exec739 $vgpr0 = V_MUL_F32_e64 0, $vgpr0, 0, $vgpr0, 0, 0, implicit $mode, implicit $exec740 $sgpr0 = S_OR_B32 $sgpr0, $sgpr1, implicit-def $scc741 $vgpr0 = V_MUL_F32_e64 0, $vgpr0, 0, $vgpr0, 0, 0, implicit $mode, implicit $exec742...743# Check if redundant delay_alu is removed744---745name: redundant_delay_alu746body: |747 bb.0:748 $sgpr0_sgpr1 = V_CMP_EQ_U32_e64 $sgpr4, $sgpr5, implicit $exec749 $vgpr0 = V_MUL_F32_e64 0, $vgpr0, 0, $vgpr0, 0, 0, implicit $mode, implicit $exec750 $sgpr6_sgpr7 = V_CMP_EQ_U32_e64 $sgpr6, $sgpr7, implicit $exec751 $sgpr0 = S_OR_B32 $sgpr0, $sgpr1, implicit-def $scc752 $vgpr0 = V_MUL_F32_e64 0, $vgpr0, 0, $vgpr0, 0, 0, implicit $mode, implicit $exec753...754# Check if redundant delay_alu is removed755---756name: redundant_delay_alu_2757body: |758 bb.0:759 $vgpr0 = V_MUL_F32_e64 0, $vgpr0, 0, $vgpr0, 0, 0, implicit $mode, implicit $exec760 $sgpr0_sgpr1 = V_CMP_EQ_U32_e64 $sgpr0, $sgpr1, implicit $exec761 $sgpr0 = S_OR_B32 $sgpr0, $sgpr1, implicit-def $scc762 $vgpr0 = V_MUL_F32_e64 0, $vgpr0, 0, $vgpr0, 0, 0, implicit $mode, implicit $exec763...764 765