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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=kaveri -mattr=-flat-for-global,+max-private-element-size-16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s3; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=tonga -mattr=-flat-for-global -mattr=+max-private-element-size-16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI %s4 5; FIXME: Broken on evergreen6; FIXME: For some reason the 8 and 16 vectors are being stored as7; individual elements instead of 128-bit stores.8 9define amdgpu_kernel void @insertelement_v2f32_0(ptr addrspace(1) %out, <2 x float> %a) nounwind {10; SI-LABEL: insertelement_v2f32_0:11; SI: ; %bb.0:12; SI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x013; SI-NEXT: s_mov_b32 s7, 0x100f00014; SI-NEXT: s_mov_b32 s6, -115; SI-NEXT: v_mov_b32_e32 v0, 0x40a0000016; SI-NEXT: s_waitcnt lgkmcnt(0)17; SI-NEXT: s_mov_b32 s4, s018; SI-NEXT: s_mov_b32 s5, s119; SI-NEXT: v_mov_b32_e32 v1, s320; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 021; SI-NEXT: s_endpgm22;23; VI-LABEL: insertelement_v2f32_0:24; VI: ; %bb.0:25; VI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x026; VI-NEXT: s_mov_b32 s7, 0x1100f00027; VI-NEXT: s_mov_b32 s6, -128; VI-NEXT: v_mov_b32_e32 v0, 0x40a0000029; VI-NEXT: s_waitcnt lgkmcnt(0)30; VI-NEXT: s_mov_b32 s4, s031; VI-NEXT: s_mov_b32 s5, s132; VI-NEXT: v_mov_b32_e32 v1, s333; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 034; VI-NEXT: s_endpgm35 %vecins = insertelement <2 x float> %a, float 5.000000e+00, i32 036 store <2 x float> %vecins, ptr addrspace(1) %out, align 1637 ret void38}39 40define amdgpu_kernel void @insertelement_v2f32_1(ptr addrspace(1) %out, <2 x float> %a) nounwind {41; SI-LABEL: insertelement_v2f32_1:42; SI: ; %bb.0:43; SI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x044; SI-NEXT: s_mov_b32 s7, 0x100f00045; SI-NEXT: s_mov_b32 s6, -146; SI-NEXT: v_mov_b32_e32 v1, 0x40a0000047; SI-NEXT: s_waitcnt lgkmcnt(0)48; SI-NEXT: s_mov_b32 s4, s049; SI-NEXT: s_mov_b32 s5, s150; SI-NEXT: v_mov_b32_e32 v0, s251; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 052; SI-NEXT: s_endpgm53;54; VI-LABEL: insertelement_v2f32_1:55; VI: ; %bb.0:56; VI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x057; VI-NEXT: s_mov_b32 s7, 0x1100f00058; VI-NEXT: s_mov_b32 s6, -159; VI-NEXT: v_mov_b32_e32 v1, 0x40a0000060; VI-NEXT: s_waitcnt lgkmcnt(0)61; VI-NEXT: s_mov_b32 s4, s062; VI-NEXT: s_mov_b32 s5, s163; VI-NEXT: v_mov_b32_e32 v0, s264; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 065; VI-NEXT: s_endpgm66 %vecins = insertelement <2 x float> %a, float 5.000000e+00, i32 167 store <2 x float> %vecins, ptr addrspace(1) %out, align 1668 ret void69}70 71define amdgpu_kernel void @insertelement_v2i32_0(ptr addrspace(1) %out, <2 x i32> %a) nounwind {72; SI-LABEL: insertelement_v2i32_0:73; SI: ; %bb.0:74; SI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x075; SI-NEXT: s_mov_b32 s7, 0x100f00076; SI-NEXT: s_mov_b32 s6, -177; SI-NEXT: v_mov_b32_e32 v0, 0x3e778; SI-NEXT: s_waitcnt lgkmcnt(0)79; SI-NEXT: s_mov_b32 s4, s080; SI-NEXT: s_mov_b32 s5, s181; SI-NEXT: v_mov_b32_e32 v1, s382; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 083; SI-NEXT: s_endpgm84;85; VI-LABEL: insertelement_v2i32_0:86; VI: ; %bb.0:87; VI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x088; VI-NEXT: s_mov_b32 s7, 0x1100f00089; VI-NEXT: s_mov_b32 s6, -190; VI-NEXT: v_mov_b32_e32 v0, 0x3e791; VI-NEXT: s_waitcnt lgkmcnt(0)92; VI-NEXT: s_mov_b32 s4, s093; VI-NEXT: s_mov_b32 s5, s194; VI-NEXT: v_mov_b32_e32 v1, s395; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 096; VI-NEXT: s_endpgm97 %vecins = insertelement <2 x i32> %a, i32 999, i32 098 store <2 x i32> %vecins, ptr addrspace(1) %out, align 1699 ret void100}101 102define amdgpu_kernel void @insertelement_v2i32_1(ptr addrspace(1) %out, <2 x i32> %a) nounwind {103; SI-LABEL: insertelement_v2i32_1:104; SI: ; %bb.0:105; SI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0106; SI-NEXT: s_mov_b32 s7, 0x100f000107; SI-NEXT: s_mov_b32 s6, -1108; SI-NEXT: v_mov_b32_e32 v1, 0x3e7109; SI-NEXT: s_waitcnt lgkmcnt(0)110; SI-NEXT: s_mov_b32 s4, s0111; SI-NEXT: s_mov_b32 s5, s1112; SI-NEXT: v_mov_b32_e32 v0, s2113; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0114; SI-NEXT: s_endpgm115;116; VI-LABEL: insertelement_v2i32_1:117; VI: ; %bb.0:118; VI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0119; VI-NEXT: s_mov_b32 s7, 0x1100f000120; VI-NEXT: s_mov_b32 s6, -1121; VI-NEXT: v_mov_b32_e32 v1, 0x3e7122; VI-NEXT: s_waitcnt lgkmcnt(0)123; VI-NEXT: s_mov_b32 s4, s0124; VI-NEXT: s_mov_b32 s5, s1125; VI-NEXT: v_mov_b32_e32 v0, s2126; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0127; VI-NEXT: s_endpgm128 %vecins = insertelement <2 x i32> %a, i32 999, i32 1129 store <2 x i32> %vecins, ptr addrspace(1) %out, align 16130 ret void131}132 133; FIXME: Why is the constant moved into the intermediate register and134; not just directly into the vector component?135define amdgpu_kernel void @insertelement_v4f32_0(ptr addrspace(1) %out, <4 x float> %a) nounwind {136; SI-LABEL: insertelement_v4f32_0:137; SI: ; %bb.0:138; SI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x4139; SI-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x0140; SI-NEXT: s_waitcnt lgkmcnt(0)141; SI-NEXT: s_mov_b32 s0, 0x40a00000142; SI-NEXT: s_mov_b32 s7, 0x100f000143; SI-NEXT: s_mov_b32 s6, -1144; SI-NEXT: v_mov_b32_e32 v0, s0145; SI-NEXT: v_mov_b32_e32 v1, s1146; SI-NEXT: v_mov_b32_e32 v2, s2147; SI-NEXT: v_mov_b32_e32 v3, s3148; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0149; SI-NEXT: s_endpgm150;151; VI-LABEL: insertelement_v4f32_0:152; VI: ; %bb.0:153; VI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x10154; VI-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x0155; VI-NEXT: s_waitcnt lgkmcnt(0)156; VI-NEXT: s_mov_b32 s0, 0x40a00000157; VI-NEXT: s_mov_b32 s7, 0x1100f000158; VI-NEXT: s_mov_b32 s6, -1159; VI-NEXT: v_mov_b32_e32 v0, s0160; VI-NEXT: v_mov_b32_e32 v1, s1161; VI-NEXT: v_mov_b32_e32 v2, s2162; VI-NEXT: v_mov_b32_e32 v3, s3163; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0164; VI-NEXT: s_endpgm165 %vecins = insertelement <4 x float> %a, float 5.000000e+00, i32 0166 store <4 x float> %vecins, ptr addrspace(1) %out, align 16167 ret void168}169 170define amdgpu_kernel void @insertelement_v4f32_1(ptr addrspace(1) %out, <4 x float> %a) nounwind {171; SI-LABEL: insertelement_v4f32_1:172; SI: ; %bb.0:173; SI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x4174; SI-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x0175; SI-NEXT: s_waitcnt lgkmcnt(0)176; SI-NEXT: s_mov_b32 s1, 0x40a00000177; SI-NEXT: s_mov_b32 s7, 0x100f000178; SI-NEXT: s_mov_b32 s6, -1179; SI-NEXT: v_mov_b32_e32 v0, s0180; SI-NEXT: v_mov_b32_e32 v1, s1181; SI-NEXT: v_mov_b32_e32 v2, s2182; SI-NEXT: v_mov_b32_e32 v3, s3183; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0184; SI-NEXT: s_endpgm185;186; VI-LABEL: insertelement_v4f32_1:187; VI: ; %bb.0:188; VI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x10189; VI-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x0190; VI-NEXT: s_waitcnt lgkmcnt(0)191; VI-NEXT: s_mov_b32 s1, 0x40a00000192; VI-NEXT: s_mov_b32 s7, 0x1100f000193; VI-NEXT: s_mov_b32 s6, -1194; VI-NEXT: v_mov_b32_e32 v0, s0195; VI-NEXT: v_mov_b32_e32 v1, s1196; VI-NEXT: v_mov_b32_e32 v2, s2197; VI-NEXT: v_mov_b32_e32 v3, s3198; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0199; VI-NEXT: s_endpgm200 %vecins = insertelement <4 x float> %a, float 5.000000e+00, i32 1201 store <4 x float> %vecins, ptr addrspace(1) %out, align 16202 ret void203}204 205define amdgpu_kernel void @insertelement_v4f32_2(ptr addrspace(1) %out, <4 x float> %a) nounwind {206; SI-LABEL: insertelement_v4f32_2:207; SI: ; %bb.0:208; SI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x4209; SI-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x0210; SI-NEXT: s_waitcnt lgkmcnt(0)211; SI-NEXT: s_mov_b32 s2, 0x40a00000212; SI-NEXT: s_mov_b32 s7, 0x100f000213; SI-NEXT: s_mov_b32 s6, -1214; SI-NEXT: v_mov_b32_e32 v0, s0215; SI-NEXT: v_mov_b32_e32 v1, s1216; SI-NEXT: v_mov_b32_e32 v2, s2217; SI-NEXT: v_mov_b32_e32 v3, s3218; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0219; SI-NEXT: s_endpgm220;221; VI-LABEL: insertelement_v4f32_2:222; VI: ; %bb.0:223; VI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x10224; VI-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x0225; VI-NEXT: s_waitcnt lgkmcnt(0)226; VI-NEXT: s_mov_b32 s2, 0x40a00000227; VI-NEXT: s_mov_b32 s7, 0x1100f000228; VI-NEXT: s_mov_b32 s6, -1229; VI-NEXT: v_mov_b32_e32 v0, s0230; VI-NEXT: v_mov_b32_e32 v1, s1231; VI-NEXT: v_mov_b32_e32 v2, s2232; VI-NEXT: v_mov_b32_e32 v3, s3233; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0234; VI-NEXT: s_endpgm235 %vecins = insertelement <4 x float> %a, float 5.000000e+00, i32 2236 store <4 x float> %vecins, ptr addrspace(1) %out, align 16237 ret void238}239 240define amdgpu_kernel void @insertelement_v4f32_3(ptr addrspace(1) %out, <4 x float> %a) nounwind {241; SI-LABEL: insertelement_v4f32_3:242; SI: ; %bb.0:243; SI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x4244; SI-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x0245; SI-NEXT: s_waitcnt lgkmcnt(0)246; SI-NEXT: s_mov_b32 s3, 0x40a00000247; SI-NEXT: s_mov_b32 s7, 0x100f000248; SI-NEXT: s_mov_b32 s6, -1249; SI-NEXT: v_mov_b32_e32 v0, s0250; SI-NEXT: v_mov_b32_e32 v1, s1251; SI-NEXT: v_mov_b32_e32 v2, s2252; SI-NEXT: v_mov_b32_e32 v3, s3253; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0254; SI-NEXT: s_endpgm255;256; VI-LABEL: insertelement_v4f32_3:257; VI: ; %bb.0:258; VI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x10259; VI-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x0260; VI-NEXT: s_waitcnt lgkmcnt(0)261; VI-NEXT: s_mov_b32 s3, 0x40a00000262; VI-NEXT: s_mov_b32 s7, 0x1100f000263; VI-NEXT: s_mov_b32 s6, -1264; VI-NEXT: v_mov_b32_e32 v0, s0265; VI-NEXT: v_mov_b32_e32 v1, s1266; VI-NEXT: v_mov_b32_e32 v2, s2267; VI-NEXT: v_mov_b32_e32 v3, s3268; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0269; VI-NEXT: s_endpgm270 %vecins = insertelement <4 x float> %a, float 5.000000e+00, i32 3271 store <4 x float> %vecins, ptr addrspace(1) %out, align 16272 ret void273}274 275define amdgpu_kernel void @insertelement_v4i32_0(ptr addrspace(1) %out, <4 x i32> %a) nounwind {276; SI-LABEL: insertelement_v4i32_0:277; SI: ; %bb.0:278; SI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x4279; SI-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x0280; SI-NEXT: s_waitcnt lgkmcnt(0)281; SI-NEXT: s_movk_i32 s0, 0x3e7282; SI-NEXT: s_mov_b32 s7, 0x100f000283; SI-NEXT: s_mov_b32 s6, -1284; SI-NEXT: v_mov_b32_e32 v0, s0285; SI-NEXT: v_mov_b32_e32 v1, s1286; SI-NEXT: v_mov_b32_e32 v2, s2287; SI-NEXT: v_mov_b32_e32 v3, s3288; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0289; SI-NEXT: s_endpgm290;291; VI-LABEL: insertelement_v4i32_0:292; VI: ; %bb.0:293; VI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x10294; VI-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x0295; VI-NEXT: s_waitcnt lgkmcnt(0)296; VI-NEXT: s_movk_i32 s0, 0x3e7297; VI-NEXT: s_mov_b32 s7, 0x1100f000298; VI-NEXT: s_mov_b32 s6, -1299; VI-NEXT: v_mov_b32_e32 v0, s0300; VI-NEXT: v_mov_b32_e32 v1, s1301; VI-NEXT: v_mov_b32_e32 v2, s2302; VI-NEXT: v_mov_b32_e32 v3, s3303; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0304; VI-NEXT: s_endpgm305 %vecins = insertelement <4 x i32> %a, i32 999, i32 0306 store <4 x i32> %vecins, ptr addrspace(1) %out, align 16307 ret void308}309 310define amdgpu_kernel void @insertelement_v3f32_1(ptr addrspace(1) %out, <3 x float> %a) nounwind {311; SI-LABEL: insertelement_v3f32_1:312; SI: ; %bb.0:313; SI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x4314; SI-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x0315; SI-NEXT: s_mov_b32 s7, 0x100f000316; SI-NEXT: s_mov_b32 s6, -1317; SI-NEXT: v_mov_b32_e32 v1, 0x40a00000318; SI-NEXT: s_waitcnt lgkmcnt(0)319; SI-NEXT: v_mov_b32_e32 v0, s0320; SI-NEXT: v_mov_b32_e32 v2, s2321; SI-NEXT: buffer_store_dwordx3 v[0:2], off, s[4:7], 0322; SI-NEXT: s_endpgm323;324; VI-LABEL: insertelement_v3f32_1:325; VI: ; %bb.0:326; VI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x10327; VI-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x0328; VI-NEXT: s_mov_b32 s7, 0x1100f000329; VI-NEXT: s_mov_b32 s6, -1330; VI-NEXT: v_mov_b32_e32 v1, 0x40a00000331; VI-NEXT: s_waitcnt lgkmcnt(0)332; VI-NEXT: v_mov_b32_e32 v0, s0333; VI-NEXT: v_mov_b32_e32 v2, s2334; VI-NEXT: buffer_store_dwordx3 v[0:2], off, s[4:7], 0335; VI-NEXT: s_endpgm336 %vecins = insertelement <3 x float> %a, float 5.000000e+00, i32 1337 store <3 x float> %vecins, ptr addrspace(1) %out, align 16338 ret void339}340 341define amdgpu_kernel void @insertelement_v3f32_2(ptr addrspace(1) %out, <3 x float> %a) nounwind {342; SI-LABEL: insertelement_v3f32_2:343; SI: ; %bb.0:344; SI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x4345; SI-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x0346; SI-NEXT: s_mov_b32 s7, 0x100f000347; SI-NEXT: s_mov_b32 s6, -1348; SI-NEXT: v_mov_b32_e32 v2, 0x40a00000349; SI-NEXT: s_waitcnt lgkmcnt(0)350; SI-NEXT: v_mov_b32_e32 v0, s0351; SI-NEXT: v_mov_b32_e32 v1, s1352; SI-NEXT: buffer_store_dwordx3 v[0:2], off, s[4:7], 0353; SI-NEXT: s_endpgm354;355; VI-LABEL: insertelement_v3f32_2:356; VI: ; %bb.0:357; VI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x10358; VI-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x0359; VI-NEXT: s_mov_b32 s7, 0x1100f000360; VI-NEXT: s_mov_b32 s6, -1361; VI-NEXT: v_mov_b32_e32 v2, 0x40a00000362; VI-NEXT: s_waitcnt lgkmcnt(0)363; VI-NEXT: v_mov_b32_e32 v0, s0364; VI-NEXT: v_mov_b32_e32 v1, s1365; VI-NEXT: buffer_store_dwordx3 v[0:2], off, s[4:7], 0366; VI-NEXT: s_endpgm367 %vecins = insertelement <3 x float> %a, float 5.000000e+00, i32 2368 store <3 x float> %vecins, ptr addrspace(1) %out, align 16369 ret void370}371 372define amdgpu_kernel void @insertelement_v3f32_3(ptr addrspace(1) %out, <3 x float> %a) nounwind {373; GCN-LABEL: insertelement_v3f32_3:374; GCN: ; %bb.0:375; GCN-NEXT: s_endpgm376 %vecins = insertelement <3 x float> %a, float 5.000000e+00, i32 3377 store <3 x float> %vecins, ptr addrspace(1) %out, align 16378 ret void379}380 381define <4 x float> @insertelement_to_sgpr() nounwind {382; GCN-LABEL: insertelement_to_sgpr:383; GCN: ; %bb.0:384; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)385; GCN-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x0386; GCN-NEXT: s_waitcnt lgkmcnt(0)387; GCN-NEXT: s_mov_b32 s4, 0388; GCN-NEXT: image_gather4_lz v[0:3], v[0:1], s[4:11], s[4:7] dmask:0x1389; GCN-NEXT: s_waitcnt vmcnt(0)390; GCN-NEXT: s_setpc_b64 s[30:31]391 %tmp = load <4 x i32>, ptr addrspace(4) poison392 %tmp1 = insertelement <4 x i32> %tmp, i32 0, i32 0393 %tmp2 = call <4 x float> @llvm.amdgcn.image.gather4.lz.2d.v4f32.f32(i32 1, float poison, float poison, <8 x i32> poison, <4 x i32> %tmp1, i1 0, i32 0, i32 0)394 ret <4 x float> %tmp2395}396 397define <9 x float> @insertelement_to_v9f32_undef() nounwind {398; GCN-LABEL: insertelement_to_v9f32_undef:399; GCN: ; %bb.0:400; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)401; GCN-NEXT: s_load_dwordx8 s[4:11], s[4:5], 0x0402; GCN-NEXT: v_mov_b32_e32 v0, 0x40a00000403; GCN-NEXT: v_mov_b32_e32 v2, 0xc0a00000404; GCN-NEXT: v_mov_b32_e32 v7, 0x41880000405; GCN-NEXT: s_waitcnt lgkmcnt(0)406; GCN-NEXT: s_load_dword s4, s[4:5], 0x0407; GCN-NEXT: v_mov_b32_e32 v1, s5408; GCN-NEXT: v_mov_b32_e32 v3, s7409; GCN-NEXT: v_mov_b32_e32 v4, s8410; GCN-NEXT: v_mov_b32_e32 v5, s9411; GCN-NEXT: v_mov_b32_e32 v6, s10412; GCN-NEXT: s_waitcnt lgkmcnt(0)413; GCN-NEXT: v_mov_b32_e32 v8, s4414; GCN-NEXT: s_setpc_b64 s[30:31]415 %tmp = load <9 x float>, ptr addrspace(4) poison416 %tmp1 = insertelement <9 x float> %tmp, float 5.000, i32 0417 %tmp2 = insertelement <9 x float> %tmp1, float -5.000, i32 2418 %tmp3 = insertelement <9 x float> %tmp2, float 17.000, i32 7419 ret <9 x float> %tmp3420}421 422define <10 x float> @insertelement_to_v10f32_undef() nounwind {423; GCN-LABEL: insertelement_to_v10f32_undef:424; GCN: ; %bb.0:425; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)426; GCN-NEXT: s_load_dwordx8 s[4:11], s[4:5], 0x0427; GCN-NEXT: v_mov_b32_e32 v0, 2.0428; GCN-NEXT: s_waitcnt lgkmcnt(0)429; GCN-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x0430; GCN-NEXT: v_mov_b32_e32 v1, s5431; GCN-NEXT: v_mov_b32_e32 v2, s6432; GCN-NEXT: v_mov_b32_e32 v3, s7433; GCN-NEXT: v_mov_b32_e32 v4, s8434; GCN-NEXT: v_mov_b32_e32 v5, s9435; GCN-NEXT: v_mov_b32_e32 v6, s10436; GCN-NEXT: v_mov_b32_e32 v7, s11437; GCN-NEXT: s_waitcnt lgkmcnt(0)438; GCN-NEXT: v_mov_b32_e32 v8, s12439; GCN-NEXT: v_mov_b32_e32 v9, s13440; GCN-NEXT: s_setpc_b64 s[30:31]441 %tmp = load <10 x float>, ptr addrspace(4) poison442 %tmp1 = insertelement <10 x float> %tmp, float 2.0, i32 0443 ret <10 x float> %tmp1444}445 446define <11 x float> @insertelement_to_v11f32_undef() nounwind {447; GCN-LABEL: insertelement_to_v11f32_undef:448; GCN: ; %bb.0:449; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)450; GCN-NEXT: s_load_dwordx8 s[4:11], s[4:5], 0x0451; GCN-NEXT: v_mov_b32_e32 v0, 1.0452; GCN-NEXT: s_waitcnt lgkmcnt(0)453; GCN-NEXT: s_load_dwordx4 s[12:15], s[4:5], 0x0454; GCN-NEXT: v_mov_b32_e32 v1, s5455; GCN-NEXT: v_mov_b32_e32 v2, s6456; GCN-NEXT: v_mov_b32_e32 v3, s7457; GCN-NEXT: v_mov_b32_e32 v4, s8458; GCN-NEXT: v_mov_b32_e32 v5, s9459; GCN-NEXT: v_mov_b32_e32 v6, s10460; GCN-NEXT: v_mov_b32_e32 v7, s11461; GCN-NEXT: s_waitcnt lgkmcnt(0)462; GCN-NEXT: v_mov_b32_e32 v8, s12463; GCN-NEXT: v_mov_b32_e32 v9, s13464; GCN-NEXT: v_mov_b32_e32 v10, s14465; GCN-NEXT: s_setpc_b64 s[30:31]466 %tmp = load <11 x float>, ptr addrspace(4) poison467 %tmp1 = insertelement <11 x float> %tmp, float 1.000, i32 0468 ret <11 x float> %tmp1469}470 471define <12 x float> @insertelement_to_v12f32_undef() nounwind {472; GCN-LABEL: insertelement_to_v12f32_undef:473; GCN: ; %bb.0:474; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)475; GCN-NEXT: s_load_dwordx8 s[4:11], s[4:5], 0x0476; GCN-NEXT: v_mov_b32_e32 v0, 4.0477; GCN-NEXT: s_waitcnt lgkmcnt(0)478; GCN-NEXT: s_load_dwordx4 s[12:15], s[4:5], 0x0479; GCN-NEXT: v_mov_b32_e32 v1, s5480; GCN-NEXT: v_mov_b32_e32 v2, s6481; GCN-NEXT: v_mov_b32_e32 v3, s7482; GCN-NEXT: v_mov_b32_e32 v4, s8483; GCN-NEXT: v_mov_b32_e32 v5, s9484; GCN-NEXT: v_mov_b32_e32 v6, s10485; GCN-NEXT: v_mov_b32_e32 v7, s11486; GCN-NEXT: s_waitcnt lgkmcnt(0)487; GCN-NEXT: v_mov_b32_e32 v8, s12488; GCN-NEXT: v_mov_b32_e32 v9, s13489; GCN-NEXT: v_mov_b32_e32 v10, s14490; GCN-NEXT: v_mov_b32_e32 v11, s15491; GCN-NEXT: s_setpc_b64 s[30:31]492 %tmp = load <12 x float>, ptr addrspace(4) poison493 %tmp1 = insertelement <12 x float> %tmp, float 4.0, i32 0494 ret <12 x float> %tmp1495}496 497define amdgpu_kernel void @dynamic_insertelement_v2f32(ptr addrspace(1) %out, <2 x float> %a, i32 %b) nounwind {498; SI-LABEL: dynamic_insertelement_v2f32:499; SI: ; %bb.0:500; SI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x2501; SI-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x0502; SI-NEXT: v_mov_b32_e32 v0, 0x40a00000503; SI-NEXT: s_mov_b32 s7, 0x100f000504; SI-NEXT: s_mov_b32 s6, -1505; SI-NEXT: s_waitcnt lgkmcnt(0)506; SI-NEXT: s_cmp_lg_u32 s2, 1507; SI-NEXT: v_mov_b32_e32 v1, s1508; SI-NEXT: s_cselect_b64 vcc, -1, 0509; SI-NEXT: s_cmp_lg_u32 s2, 0510; SI-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc511; SI-NEXT: v_mov_b32_e32 v2, s0512; SI-NEXT: s_cselect_b64 vcc, -1, 0513; SI-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc514; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0515; SI-NEXT: s_endpgm516;517; VI-LABEL: dynamic_insertelement_v2f32:518; VI: ; %bb.0:519; VI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x8520; VI-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x0521; VI-NEXT: v_mov_b32_e32 v0, 0x40a00000522; VI-NEXT: s_mov_b32 s7, 0x1100f000523; VI-NEXT: s_mov_b32 s6, -1524; VI-NEXT: s_waitcnt lgkmcnt(0)525; VI-NEXT: s_cmp_lg_u32 s2, 1526; VI-NEXT: v_mov_b32_e32 v1, s1527; VI-NEXT: s_cselect_b64 vcc, -1, 0528; VI-NEXT: s_cmp_lg_u32 s2, 0529; VI-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc530; VI-NEXT: v_mov_b32_e32 v2, s0531; VI-NEXT: s_cselect_b64 vcc, -1, 0532; VI-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc533; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0534; VI-NEXT: s_endpgm535 %vecins = insertelement <2 x float> %a, float 5.000000e+00, i32 %b536 store <2 x float> %vecins, ptr addrspace(1) %out, align 8537 ret void538}539 540define amdgpu_kernel void @dynamic_insertelement_v3f32(ptr addrspace(1) %out, <3 x float> %a, i32 %b) nounwind {541; SI-LABEL: dynamic_insertelement_v3f32:542; SI: ; %bb.0:543; SI-NEXT: s_load_dword s10, s[8:9], 0x8544; SI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0545; SI-NEXT: s_load_dwordx4 s[4:7], s[8:9], 0x4546; SI-NEXT: v_mov_b32_e32 v0, 0x40a00000547; SI-NEXT: s_mov_b32 s3, 0x100f000548; SI-NEXT: s_waitcnt lgkmcnt(0)549; SI-NEXT: s_cmp_lg_u32 s10, 2550; SI-NEXT: s_cselect_b64 vcc, -1, 0551; SI-NEXT: v_mov_b32_e32 v1, s6552; SI-NEXT: s_cmp_lg_u32 s10, 1553; SI-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc554; SI-NEXT: v_mov_b32_e32 v1, s5555; SI-NEXT: s_cselect_b64 vcc, -1, 0556; SI-NEXT: s_cmp_lg_u32 s10, 0557; SI-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc558; SI-NEXT: v_mov_b32_e32 v3, s4559; SI-NEXT: s_cselect_b64 vcc, -1, 0560; SI-NEXT: s_mov_b32 s2, -1561; SI-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc562; SI-NEXT: buffer_store_dwordx3 v[0:2], off, s[0:3], 0563; SI-NEXT: s_endpgm564;565; VI-LABEL: dynamic_insertelement_v3f32:566; VI: ; %bb.0:567; VI-NEXT: s_load_dword s10, s[8:9], 0x20568; VI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0569; VI-NEXT: s_load_dwordx4 s[4:7], s[8:9], 0x10570; VI-NEXT: v_mov_b32_e32 v0, 0x40a00000571; VI-NEXT: s_mov_b32 s3, 0x1100f000572; VI-NEXT: s_waitcnt lgkmcnt(0)573; VI-NEXT: s_cmp_lg_u32 s10, 2574; VI-NEXT: s_cselect_b64 vcc, -1, 0575; VI-NEXT: v_mov_b32_e32 v1, s6576; VI-NEXT: s_cmp_lg_u32 s10, 1577; VI-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc578; VI-NEXT: v_mov_b32_e32 v1, s5579; VI-NEXT: s_cselect_b64 vcc, -1, 0580; VI-NEXT: s_cmp_lg_u32 s10, 0581; VI-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc582; VI-NEXT: v_mov_b32_e32 v3, s4583; VI-NEXT: s_cselect_b64 vcc, -1, 0584; VI-NEXT: s_mov_b32 s2, -1585; VI-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc586; VI-NEXT: buffer_store_dwordx3 v[0:2], off, s[0:3], 0587; VI-NEXT: s_endpgm588 %vecins = insertelement <3 x float> %a, float 5.000000e+00, i32 %b589 store <3 x float> %vecins, ptr addrspace(1) %out, align 16590 ret void591}592 593define amdgpu_kernel void @dynamic_insertelement_v4f32(ptr addrspace(1) %out, <4 x float> %a, i32 %b) nounwind {594; SI-LABEL: dynamic_insertelement_v4f32:595; SI: ; %bb.0:596; SI-NEXT: s_load_dword s10, s[8:9], 0x8597; SI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0598; SI-NEXT: s_load_dwordx4 s[4:7], s[8:9], 0x4599; SI-NEXT: v_mov_b32_e32 v0, 0x40a00000600; SI-NEXT: s_mov_b32 s3, 0x100f000601; SI-NEXT: s_waitcnt lgkmcnt(0)602; SI-NEXT: s_cmp_lg_u32 s10, 3603; SI-NEXT: s_cselect_b64 vcc, -1, 0604; SI-NEXT: v_mov_b32_e32 v1, s7605; SI-NEXT: s_cmp_lg_u32 s10, 2606; SI-NEXT: v_cndmask_b32_e32 v3, v0, v1, vcc607; SI-NEXT: v_mov_b32_e32 v1, s6608; SI-NEXT: s_cselect_b64 vcc, -1, 0609; SI-NEXT: s_cmp_lg_u32 s10, 1610; SI-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc611; SI-NEXT: v_mov_b32_e32 v1, s5612; SI-NEXT: s_cselect_b64 vcc, -1, 0613; SI-NEXT: s_cmp_lg_u32 s10, 0614; SI-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc615; SI-NEXT: v_mov_b32_e32 v4, s4616; SI-NEXT: s_cselect_b64 vcc, -1, 0617; SI-NEXT: s_mov_b32 s2, -1618; SI-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc619; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0620; SI-NEXT: s_endpgm621;622; VI-LABEL: dynamic_insertelement_v4f32:623; VI: ; %bb.0:624; VI-NEXT: s_load_dword s10, s[8:9], 0x20625; VI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0626; VI-NEXT: s_load_dwordx4 s[4:7], s[8:9], 0x10627; VI-NEXT: v_mov_b32_e32 v0, 0x40a00000628; VI-NEXT: s_mov_b32 s3, 0x1100f000629; VI-NEXT: s_waitcnt lgkmcnt(0)630; VI-NEXT: s_cmp_lg_u32 s10, 3631; VI-NEXT: s_cselect_b64 vcc, -1, 0632; VI-NEXT: v_mov_b32_e32 v1, s7633; VI-NEXT: s_cmp_lg_u32 s10, 2634; VI-NEXT: v_cndmask_b32_e32 v3, v0, v1, vcc635; VI-NEXT: v_mov_b32_e32 v1, s6636; VI-NEXT: s_cselect_b64 vcc, -1, 0637; VI-NEXT: s_cmp_lg_u32 s10, 1638; VI-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc639; VI-NEXT: v_mov_b32_e32 v1, s5640; VI-NEXT: s_cselect_b64 vcc, -1, 0641; VI-NEXT: s_cmp_lg_u32 s10, 0642; VI-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc643; VI-NEXT: v_mov_b32_e32 v4, s4644; VI-NEXT: s_cselect_b64 vcc, -1, 0645; VI-NEXT: s_mov_b32 s2, -1646; VI-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc647; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0648; VI-NEXT: s_endpgm649 %vecins = insertelement <4 x float> %a, float 5.000000e+00, i32 %b650 store <4 x float> %vecins, ptr addrspace(1) %out, align 16651 ret void652}653 654define amdgpu_kernel void @dynamic_insertelement_v8f32(ptr addrspace(1) %out, <8 x float> %a, i32 %b) nounwind {655; SI-LABEL: dynamic_insertelement_v8f32:656; SI: ; %bb.0:657; SI-NEXT: s_load_dwordx8 s[0:7], s[8:9], 0x8658; SI-NEXT: s_load_dwordx2 s[12:13], s[8:9], 0x0659; SI-NEXT: s_load_dword s8, s[8:9], 0x10660; SI-NEXT: v_mov_b32_e32 v8, 0x40a00000661; SI-NEXT: s_mov_b32 s15, 0x100f000662; SI-NEXT: s_mov_b32 s14, -1663; SI-NEXT: s_waitcnt lgkmcnt(0)664; SI-NEXT: v_mov_b32_e32 v0, s0665; SI-NEXT: v_mov_b32_e32 v1, s1666; SI-NEXT: v_mov_b32_e32 v2, s2667; SI-NEXT: v_mov_b32_e32 v3, s3668; SI-NEXT: v_mov_b32_e32 v4, s4669; SI-NEXT: v_mov_b32_e32 v5, s5670; SI-NEXT: v_mov_b32_e32 v6, s6671; SI-NEXT: v_mov_b32_e32 v7, s7672; SI-NEXT: s_mov_b32 m0, s8673; SI-NEXT: v_movreld_b32_e32 v0, v8674; SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[12:15], 0 offset:16675; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[12:15], 0676; SI-NEXT: s_endpgm677;678; VI-LABEL: dynamic_insertelement_v8f32:679; VI: ; %bb.0:680; VI-NEXT: s_load_dwordx8 s[0:7], s[8:9], 0x20681; VI-NEXT: s_load_dwordx2 s[12:13], s[8:9], 0x0682; VI-NEXT: s_load_dword s8, s[8:9], 0x40683; VI-NEXT: v_mov_b32_e32 v8, 0x40a00000684; VI-NEXT: s_mov_b32 s15, 0x1100f000685; VI-NEXT: s_mov_b32 s14, -1686; VI-NEXT: s_waitcnt lgkmcnt(0)687; VI-NEXT: v_mov_b32_e32 v0, s0688; VI-NEXT: v_mov_b32_e32 v1, s1689; VI-NEXT: v_mov_b32_e32 v2, s2690; VI-NEXT: v_mov_b32_e32 v3, s3691; VI-NEXT: v_mov_b32_e32 v4, s4692; VI-NEXT: v_mov_b32_e32 v5, s5693; VI-NEXT: v_mov_b32_e32 v6, s6694; VI-NEXT: v_mov_b32_e32 v7, s7695; VI-NEXT: s_mov_b32 m0, s8696; VI-NEXT: v_movreld_b32_e32 v0, v8697; VI-NEXT: buffer_store_dwordx4 v[4:7], off, s[12:15], 0 offset:16698; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[12:15], 0699; VI-NEXT: s_endpgm700 %vecins = insertelement <8 x float> %a, float 5.000000e+00, i32 %b701 store <8 x float> %vecins, ptr addrspace(1) %out, align 32702 ret void703}704 705define amdgpu_kernel void @dynamic_insertelement_v9f32(ptr addrspace(1) %out, <9 x float> %a, i32 %b) nounwind {706; SI-LABEL: dynamic_insertelement_v9f32:707; SI: ; %bb.0:708; SI-NEXT: s_load_dwordx2 s[12:13], s[8:9], 0x0709; SI-NEXT: s_load_dwordx8 s[0:7], s[8:9], 0x10710; SI-NEXT: s_load_dword s10, s[8:9], 0x18711; SI-NEXT: s_load_dword s8, s[8:9], 0x20712; SI-NEXT: v_mov_b32_e32 v9, 0x40a00000713; SI-NEXT: s_mov_b32 s15, 0x100f000714; SI-NEXT: s_waitcnt lgkmcnt(0)715; SI-NEXT: v_mov_b32_e32 v0, s0716; SI-NEXT: v_mov_b32_e32 v1, s1717; SI-NEXT: v_mov_b32_e32 v2, s2718; SI-NEXT: v_mov_b32_e32 v3, s3719; SI-NEXT: v_mov_b32_e32 v4, s4720; SI-NEXT: v_mov_b32_e32 v5, s5721; SI-NEXT: v_mov_b32_e32 v6, s6722; SI-NEXT: v_mov_b32_e32 v7, s7723; SI-NEXT: v_mov_b32_e32 v8, s10724; SI-NEXT: s_mov_b32 m0, s8725; SI-NEXT: s_mov_b32 s14, -1726; SI-NEXT: v_movreld_b32_e32 v0, v9727; SI-NEXT: buffer_store_dword v8, off, s[12:15], 0 offset:32728; SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[12:15], 0 offset:16729; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[12:15], 0730; SI-NEXT: s_endpgm731;732; VI-LABEL: dynamic_insertelement_v9f32:733; VI: ; %bb.0:734; VI-NEXT: s_load_dwordx8 s[0:7], s[8:9], 0x40735; VI-NEXT: s_load_dwordx2 s[12:13], s[8:9], 0x0736; VI-NEXT: s_load_dword s10, s[8:9], 0x60737; VI-NEXT: v_mov_b32_e32 v9, 0x40a00000738; VI-NEXT: s_mov_b32 s15, 0x1100f000739; VI-NEXT: s_mov_b32 s14, -1740; VI-NEXT: s_waitcnt lgkmcnt(0)741; VI-NEXT: v_mov_b32_e32 v0, s0742; VI-NEXT: s_load_dword s0, s[8:9], 0x80743; VI-NEXT: v_mov_b32_e32 v1, s1744; VI-NEXT: v_mov_b32_e32 v2, s2745; VI-NEXT: v_mov_b32_e32 v3, s3746; VI-NEXT: v_mov_b32_e32 v4, s4747; VI-NEXT: v_mov_b32_e32 v5, s5748; VI-NEXT: v_mov_b32_e32 v6, s6749; VI-NEXT: v_mov_b32_e32 v7, s7750; VI-NEXT: v_mov_b32_e32 v8, s10751; VI-NEXT: s_waitcnt lgkmcnt(0)752; VI-NEXT: s_mov_b32 m0, s0753; VI-NEXT: v_movreld_b32_e32 v0, v9754; VI-NEXT: buffer_store_dword v8, off, s[12:15], 0 offset:32755; VI-NEXT: buffer_store_dwordx4 v[4:7], off, s[12:15], 0 offset:16756; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[12:15], 0757; VI-NEXT: s_endpgm758 %vecins = insertelement <9 x float> %a, float 5.000000e+00, i32 %b759 store <9 x float> %vecins, ptr addrspace(1) %out, align 32760 ret void761}762 763define amdgpu_kernel void @dynamic_insertelement_v10f32(ptr addrspace(1) %out, <10 x float> %a, i32 %b) nounwind {764; SI-LABEL: dynamic_insertelement_v10f32:765; SI: ; %bb.0:766; SI-NEXT: s_load_dwordx2 s[12:13], s[8:9], 0x0767; SI-NEXT: s_load_dwordx8 s[0:7], s[8:9], 0x10768; SI-NEXT: s_load_dwordx2 s[10:11], s[8:9], 0x18769; SI-NEXT: s_load_dword s8, s[8:9], 0x20770; SI-NEXT: v_mov_b32_e32 v10, 0x40a00000771; SI-NEXT: s_mov_b32 s15, 0x100f000772; SI-NEXT: s_waitcnt lgkmcnt(0)773; SI-NEXT: v_mov_b32_e32 v0, s0774; SI-NEXT: v_mov_b32_e32 v1, s1775; SI-NEXT: v_mov_b32_e32 v2, s2776; SI-NEXT: v_mov_b32_e32 v3, s3777; SI-NEXT: v_mov_b32_e32 v4, s4778; SI-NEXT: v_mov_b32_e32 v5, s5779; SI-NEXT: v_mov_b32_e32 v6, s6780; SI-NEXT: v_mov_b32_e32 v7, s7781; SI-NEXT: v_mov_b32_e32 v8, s10782; SI-NEXT: v_mov_b32_e32 v9, s11783; SI-NEXT: s_mov_b32 m0, s8784; SI-NEXT: s_mov_b32 s14, -1785; SI-NEXT: v_movreld_b32_e32 v0, v10786; SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[12:15], 0 offset:16787; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[12:15], 0788; SI-NEXT: buffer_store_dwordx2 v[8:9], off, s[12:15], 0 offset:32789; SI-NEXT: s_endpgm790;791; VI-LABEL: dynamic_insertelement_v10f32:792; VI: ; %bb.0:793; VI-NEXT: s_load_dwordx8 s[12:19], s[8:9], 0x40794; VI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0795; VI-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x60796; VI-NEXT: s_load_dword s6, s[8:9], 0x80797; VI-NEXT: v_mov_b32_e32 v10, 0x40a00000798; VI-NEXT: s_mov_b32 s3, 0x1100f000799; VI-NEXT: s_waitcnt lgkmcnt(0)800; VI-NEXT: v_mov_b32_e32 v0, s12801; VI-NEXT: v_mov_b32_e32 v1, s13802; VI-NEXT: v_mov_b32_e32 v2, s14803; VI-NEXT: v_mov_b32_e32 v3, s15804; VI-NEXT: v_mov_b32_e32 v4, s16805; VI-NEXT: v_mov_b32_e32 v5, s17806; VI-NEXT: v_mov_b32_e32 v6, s18807; VI-NEXT: v_mov_b32_e32 v7, s19808; VI-NEXT: v_mov_b32_e32 v8, s4809; VI-NEXT: v_mov_b32_e32 v9, s5810; VI-NEXT: s_mov_b32 m0, s6811; VI-NEXT: s_mov_b32 s2, -1812; VI-NEXT: v_movreld_b32_e32 v0, v10813; VI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16814; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0815; VI-NEXT: buffer_store_dwordx2 v[8:9], off, s[0:3], 0 offset:32816; VI-NEXT: s_endpgm817 %vecins = insertelement <10 x float> %a, float 5.000000e+00, i32 %b818 store <10 x float> %vecins, ptr addrspace(1) %out, align 32819 ret void820}821 822define amdgpu_kernel void @dynamic_insertelement_v11f32(ptr addrspace(1) %out, <11 x float> %a, i32 %b) nounwind {823; SI-LABEL: dynamic_insertelement_v11f32:824; SI: ; %bb.0:825; SI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0826; SI-NEXT: s_load_dwordx8 s[12:19], s[8:9], 0x10827; SI-NEXT: s_load_dwordx4 s[4:7], s[8:9], 0x18828; SI-NEXT: s_waitcnt lgkmcnt(0)829; SI-NEXT: s_load_dword s7, s[8:9], 0x20830; SI-NEXT: v_mov_b32_e32 v11, 0x40a00000831; SI-NEXT: s_mov_b32 s3, 0x100f000832; SI-NEXT: v_mov_b32_e32 v0, s12833; SI-NEXT: v_mov_b32_e32 v1, s13834; SI-NEXT: v_mov_b32_e32 v2, s14835; SI-NEXT: v_mov_b32_e32 v3, s15836; SI-NEXT: v_mov_b32_e32 v4, s16837; SI-NEXT: v_mov_b32_e32 v5, s17838; SI-NEXT: v_mov_b32_e32 v6, s18839; SI-NEXT: v_mov_b32_e32 v7, s19840; SI-NEXT: v_mov_b32_e32 v8, s4841; SI-NEXT: v_mov_b32_e32 v9, s5842; SI-NEXT: v_mov_b32_e32 v10, s6843; SI-NEXT: s_waitcnt lgkmcnt(0)844; SI-NEXT: s_mov_b32 m0, s7845; SI-NEXT: s_mov_b32 s2, -1846; SI-NEXT: v_movreld_b32_e32 v0, v11847; SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16848; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0849; SI-NEXT: buffer_store_dwordx3 v[8:10], off, s[0:3], 0 offset:32850; SI-NEXT: s_endpgm851;852; VI-LABEL: dynamic_insertelement_v11f32:853; VI: ; %bb.0:854; VI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0855; VI-NEXT: s_load_dwordx4 s[4:7], s[8:9], 0x60856; VI-NEXT: s_load_dwordx8 s[12:19], s[8:9], 0x40857; VI-NEXT: s_waitcnt lgkmcnt(0)858; VI-NEXT: s_load_dword s7, s[8:9], 0x80859; VI-NEXT: v_mov_b32_e32 v11, 0x40a00000860; VI-NEXT: s_mov_b32 s3, 0x1100f000861; VI-NEXT: v_mov_b32_e32 v8, s4862; VI-NEXT: v_mov_b32_e32 v0, s12863; VI-NEXT: v_mov_b32_e32 v1, s13864; VI-NEXT: v_mov_b32_e32 v2, s14865; VI-NEXT: v_mov_b32_e32 v3, s15866; VI-NEXT: v_mov_b32_e32 v4, s16867; VI-NEXT: v_mov_b32_e32 v5, s17868; VI-NEXT: v_mov_b32_e32 v6, s18869; VI-NEXT: v_mov_b32_e32 v7, s19870; VI-NEXT: v_mov_b32_e32 v9, s5871; VI-NEXT: v_mov_b32_e32 v10, s6872; VI-NEXT: s_waitcnt lgkmcnt(0)873; VI-NEXT: s_mov_b32 m0, s7874; VI-NEXT: s_mov_b32 s2, -1875; VI-NEXT: v_movreld_b32_e32 v0, v11876; VI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16877; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0878; VI-NEXT: buffer_store_dwordx3 v[8:10], off, s[0:3], 0 offset:32879; VI-NEXT: s_endpgm880 %vecins = insertelement <11 x float> %a, float 5.000000e+00, i32 %b881 store <11 x float> %vecins, ptr addrspace(1) %out, align 32882 ret void883}884 885define amdgpu_kernel void @dynamic_insertelement_v12f32(ptr addrspace(1) %out, <12 x float> %a, i32 %b) nounwind {886; SI-LABEL: dynamic_insertelement_v12f32:887; SI: ; %bb.0:888; SI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0889; SI-NEXT: s_load_dwordx8 s[12:19], s[8:9], 0x10890; SI-NEXT: s_load_dwordx4 s[4:7], s[8:9], 0x18891; SI-NEXT: s_load_dword s8, s[8:9], 0x20892; SI-NEXT: v_mov_b32_e32 v12, 0x40a00000893; SI-NEXT: s_mov_b32 s3, 0x100f000894; SI-NEXT: s_waitcnt lgkmcnt(0)895; SI-NEXT: v_mov_b32_e32 v0, s12896; SI-NEXT: v_mov_b32_e32 v1, s13897; SI-NEXT: v_mov_b32_e32 v2, s14898; SI-NEXT: v_mov_b32_e32 v3, s15899; SI-NEXT: v_mov_b32_e32 v4, s16900; SI-NEXT: v_mov_b32_e32 v5, s17901; SI-NEXT: v_mov_b32_e32 v6, s18902; SI-NEXT: v_mov_b32_e32 v7, s19903; SI-NEXT: v_mov_b32_e32 v8, s4904; SI-NEXT: v_mov_b32_e32 v9, s5905; SI-NEXT: v_mov_b32_e32 v10, s6906; SI-NEXT: v_mov_b32_e32 v11, s7907; SI-NEXT: s_mov_b32 m0, s8908; SI-NEXT: s_mov_b32 s2, -1909; SI-NEXT: v_movreld_b32_e32 v0, v12910; SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16911; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0912; SI-NEXT: buffer_store_dwordx4 v[8:11], off, s[0:3], 0 offset:32913; SI-NEXT: s_endpgm914;915; VI-LABEL: dynamic_insertelement_v12f32:916; VI: ; %bb.0:917; VI-NEXT: s_load_dwordx8 s[12:19], s[8:9], 0x40918; VI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0919; VI-NEXT: s_load_dwordx4 s[4:7], s[8:9], 0x60920; VI-NEXT: s_load_dword s8, s[8:9], 0x80921; VI-NEXT: v_mov_b32_e32 v12, 0x40a00000922; VI-NEXT: s_mov_b32 s3, 0x1100f000923; VI-NEXT: s_waitcnt lgkmcnt(0)924; VI-NEXT: v_mov_b32_e32 v0, s12925; VI-NEXT: v_mov_b32_e32 v1, s13926; VI-NEXT: v_mov_b32_e32 v2, s14927; VI-NEXT: v_mov_b32_e32 v3, s15928; VI-NEXT: v_mov_b32_e32 v4, s16929; VI-NEXT: v_mov_b32_e32 v5, s17930; VI-NEXT: v_mov_b32_e32 v6, s18931; VI-NEXT: v_mov_b32_e32 v7, s19932; VI-NEXT: v_mov_b32_e32 v8, s4933; VI-NEXT: v_mov_b32_e32 v9, s5934; VI-NEXT: v_mov_b32_e32 v10, s6935; VI-NEXT: v_mov_b32_e32 v11, s7936; VI-NEXT: s_mov_b32 m0, s8937; VI-NEXT: s_mov_b32 s2, -1938; VI-NEXT: v_movreld_b32_e32 v0, v12939; VI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16940; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0941; VI-NEXT: buffer_store_dwordx4 v[8:11], off, s[0:3], 0 offset:32942; VI-NEXT: s_endpgm943 %vecins = insertelement <12 x float> %a, float 5.000000e+00, i32 %b944 store <12 x float> %vecins, ptr addrspace(1) %out, align 32945 ret void946}947 948define amdgpu_kernel void @dynamic_insertelement_v16f32(ptr addrspace(1) %out, <16 x float> %a, i32 %b) nounwind {949; SI-LABEL: dynamic_insertelement_v16f32:950; SI: ; %bb.0:951; SI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0952; SI-NEXT: s_load_dwordx16 s[12:27], s[8:9], 0x10953; SI-NEXT: s_load_dword s4, s[8:9], 0x20954; SI-NEXT: v_mov_b32_e32 v16, 0x40a00000955; SI-NEXT: s_mov_b32 s3, 0x100f000956; SI-NEXT: s_mov_b32 s2, -1957; SI-NEXT: s_waitcnt lgkmcnt(0)958; SI-NEXT: v_mov_b32_e32 v0, s12959; SI-NEXT: v_mov_b32_e32 v1, s13960; SI-NEXT: v_mov_b32_e32 v2, s14961; SI-NEXT: v_mov_b32_e32 v3, s15962; SI-NEXT: v_mov_b32_e32 v4, s16963; SI-NEXT: v_mov_b32_e32 v5, s17964; SI-NEXT: v_mov_b32_e32 v6, s18965; SI-NEXT: v_mov_b32_e32 v7, s19966; SI-NEXT: v_mov_b32_e32 v8, s20967; SI-NEXT: v_mov_b32_e32 v9, s21968; SI-NEXT: v_mov_b32_e32 v10, s22969; SI-NEXT: v_mov_b32_e32 v11, s23970; SI-NEXT: v_mov_b32_e32 v12, s24971; SI-NEXT: v_mov_b32_e32 v13, s25972; SI-NEXT: v_mov_b32_e32 v14, s26973; SI-NEXT: v_mov_b32_e32 v15, s27974; SI-NEXT: s_mov_b32 m0, s4975; SI-NEXT: v_movreld_b32_e32 v0, v16976; SI-NEXT: buffer_store_dwordx4 v[12:15], off, s[0:3], 0 offset:48977; SI-NEXT: buffer_store_dwordx4 v[8:11], off, s[0:3], 0 offset:32978; SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16979; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0980; SI-NEXT: s_endpgm981;982; VI-LABEL: dynamic_insertelement_v16f32:983; VI: ; %bb.0:984; VI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0985; VI-NEXT: s_load_dwordx16 s[12:27], s[8:9], 0x40986; VI-NEXT: s_load_dword s4, s[8:9], 0x80987; VI-NEXT: v_mov_b32_e32 v16, 0x40a00000988; VI-NEXT: s_mov_b32 s3, 0x1100f000989; VI-NEXT: s_mov_b32 s2, -1990; VI-NEXT: s_waitcnt lgkmcnt(0)991; VI-NEXT: v_mov_b32_e32 v0, s12992; VI-NEXT: v_mov_b32_e32 v1, s13993; VI-NEXT: v_mov_b32_e32 v2, s14994; VI-NEXT: v_mov_b32_e32 v3, s15995; VI-NEXT: v_mov_b32_e32 v4, s16996; VI-NEXT: v_mov_b32_e32 v5, s17997; VI-NEXT: v_mov_b32_e32 v6, s18998; VI-NEXT: v_mov_b32_e32 v7, s19999; VI-NEXT: v_mov_b32_e32 v8, s201000; VI-NEXT: v_mov_b32_e32 v9, s211001; VI-NEXT: v_mov_b32_e32 v10, s221002; VI-NEXT: v_mov_b32_e32 v11, s231003; VI-NEXT: v_mov_b32_e32 v12, s241004; VI-NEXT: v_mov_b32_e32 v13, s251005; VI-NEXT: v_mov_b32_e32 v14, s261006; VI-NEXT: v_mov_b32_e32 v15, s271007; VI-NEXT: s_mov_b32 m0, s41008; VI-NEXT: v_movreld_b32_e32 v0, v161009; VI-NEXT: buffer_store_dwordx4 v[12:15], off, s[0:3], 0 offset:481010; VI-NEXT: buffer_store_dwordx4 v[8:11], off, s[0:3], 0 offset:321011; VI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:161012; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 01013; VI-NEXT: s_endpgm1014 %vecins = insertelement <16 x float> %a, float 5.000000e+00, i32 %b1015 store <16 x float> %vecins, ptr addrspace(1) %out, align 641016 ret void1017}1018 1019define amdgpu_kernel void @dynamic_insertelement_v2i32(ptr addrspace(1) %out, <2 x i32> %a, i32 %b) nounwind {1020; SI-LABEL: dynamic_insertelement_v2i32:1021; SI: ; %bb.0:1022; SI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x21023; SI-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x01024; SI-NEXT: s_mov_b32 s7, 0x100f0001025; SI-NEXT: s_mov_b32 s6, -11026; SI-NEXT: s_waitcnt lgkmcnt(0)1027; SI-NEXT: s_cmp_lg_u32 s2, 11028; SI-NEXT: s_cselect_b32 s1, s1, 51029; SI-NEXT: s_cmp_lg_u32 s2, 01030; SI-NEXT: s_cselect_b32 s0, s0, 51031; SI-NEXT: v_mov_b32_e32 v0, s01032; SI-NEXT: v_mov_b32_e32 v1, s11033; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 01034; SI-NEXT: s_endpgm1035;1036; VI-LABEL: dynamic_insertelement_v2i32:1037; VI: ; %bb.0:1038; VI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x81039; VI-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x01040; VI-NEXT: s_mov_b32 s7, 0x1100f0001041; VI-NEXT: s_mov_b32 s6, -11042; VI-NEXT: s_waitcnt lgkmcnt(0)1043; VI-NEXT: s_cmp_lg_u32 s2, 11044; VI-NEXT: s_cselect_b32 s1, s1, 51045; VI-NEXT: s_cmp_lg_u32 s2, 01046; VI-NEXT: s_cselect_b32 s0, s0, 51047; VI-NEXT: v_mov_b32_e32 v0, s01048; VI-NEXT: v_mov_b32_e32 v1, s11049; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 01050; VI-NEXT: s_endpgm1051 %vecins = insertelement <2 x i32> %a, i32 5, i32 %b1052 store <2 x i32> %vecins, ptr addrspace(1) %out, align 81053 ret void1054}1055 1056define amdgpu_kernel void @dynamic_insertelement_v3i32(ptr addrspace(1) %out, <3 x i32> %a, i32 %b) nounwind {1057; SI-LABEL: dynamic_insertelement_v3i32:1058; SI: ; %bb.0:1059; SI-NEXT: s_load_dword s10, s[8:9], 0x81060; SI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x41061; SI-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x01062; SI-NEXT: s_mov_b32 s7, 0x100f0001063; SI-NEXT: s_mov_b32 s6, -11064; SI-NEXT: s_waitcnt lgkmcnt(0)1065; SI-NEXT: s_cmp_lg_u32 s10, 21066; SI-NEXT: s_cselect_b32 s2, s2, 51067; SI-NEXT: s_cmp_lg_u32 s10, 11068; SI-NEXT: s_cselect_b32 s1, s1, 51069; SI-NEXT: s_cmp_lg_u32 s10, 01070; SI-NEXT: s_cselect_b32 s0, s0, 51071; SI-NEXT: v_mov_b32_e32 v0, s01072; SI-NEXT: v_mov_b32_e32 v1, s11073; SI-NEXT: v_mov_b32_e32 v2, s21074; SI-NEXT: buffer_store_dwordx3 v[0:2], off, s[4:7], 01075; SI-NEXT: s_endpgm1076;1077; VI-LABEL: dynamic_insertelement_v3i32:1078; VI: ; %bb.0:1079; VI-NEXT: s_load_dword s10, s[8:9], 0x201080; VI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x101081; VI-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x01082; VI-NEXT: s_mov_b32 s7, 0x1100f0001083; VI-NEXT: s_mov_b32 s6, -11084; VI-NEXT: s_waitcnt lgkmcnt(0)1085; VI-NEXT: s_cmp_lg_u32 s10, 21086; VI-NEXT: s_cselect_b32 s2, s2, 51087; VI-NEXT: s_cmp_lg_u32 s10, 11088; VI-NEXT: s_cselect_b32 s1, s1, 51089; VI-NEXT: s_cmp_lg_u32 s10, 01090; VI-NEXT: s_cselect_b32 s0, s0, 51091; VI-NEXT: v_mov_b32_e32 v0, s01092; VI-NEXT: v_mov_b32_e32 v1, s11093; VI-NEXT: v_mov_b32_e32 v2, s21094; VI-NEXT: buffer_store_dwordx3 v[0:2], off, s[4:7], 01095; VI-NEXT: s_endpgm1096 %vecins = insertelement <3 x i32> %a, i32 5, i32 %b1097 store <3 x i32> %vecins, ptr addrspace(1) %out, align 161098 ret void1099}1100 1101define amdgpu_kernel void @dynamic_insertelement_v4i32(ptr addrspace(1) %out, <4 x i32> %a, i32 %b, [8 x i32], i32 %val) nounwind {1102; SI-LABEL: dynamic_insertelement_v4i32:1103; SI: ; %bb.0:1104; SI-NEXT: s_load_dword s10, s[8:9], 0x81105; SI-NEXT: s_load_dword s11, s[8:9], 0x111106; SI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x41107; SI-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x01108; SI-NEXT: s_mov_b32 s7, 0x100f0001109; SI-NEXT: s_waitcnt lgkmcnt(0)1110; SI-NEXT: s_cmp_eq_u32 s10, 31111; SI-NEXT: s_mov_b32 s6, -11112; SI-NEXT: s_cselect_b32 s3, s11, s31113; SI-NEXT: s_cmp_eq_u32 s10, 21114; SI-NEXT: s_cselect_b32 s2, s11, s21115; SI-NEXT: s_cmp_eq_u32 s10, 11116; SI-NEXT: s_cselect_b32 s1, s11, s11117; SI-NEXT: s_cmp_eq_u32 s10, 01118; SI-NEXT: s_cselect_b32 s0, s11, s01119; SI-NEXT: v_mov_b32_e32 v0, s01120; SI-NEXT: v_mov_b32_e32 v1, s11121; SI-NEXT: v_mov_b32_e32 v2, s21122; SI-NEXT: v_mov_b32_e32 v3, s31123; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 01124; SI-NEXT: s_endpgm1125;1126; VI-LABEL: dynamic_insertelement_v4i32:1127; VI: ; %bb.0:1128; VI-NEXT: s_load_dword s10, s[8:9], 0x201129; VI-NEXT: s_load_dword s11, s[8:9], 0x441130; VI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x101131; VI-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x01132; VI-NEXT: s_mov_b32 s7, 0x1100f0001133; VI-NEXT: s_waitcnt lgkmcnt(0)1134; VI-NEXT: s_cmp_eq_u32 s10, 31135; VI-NEXT: s_mov_b32 s6, -11136; VI-NEXT: s_cselect_b32 s3, s11, s31137; VI-NEXT: s_cmp_eq_u32 s10, 21138; VI-NEXT: s_cselect_b32 s2, s11, s21139; VI-NEXT: s_cmp_eq_u32 s10, 11140; VI-NEXT: s_cselect_b32 s1, s11, s11141; VI-NEXT: s_cmp_eq_u32 s10, 01142; VI-NEXT: s_cselect_b32 s0, s11, s01143; VI-NEXT: v_mov_b32_e32 v0, s01144; VI-NEXT: v_mov_b32_e32 v1, s11145; VI-NEXT: v_mov_b32_e32 v2, s21146; VI-NEXT: v_mov_b32_e32 v3, s31147; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 01148; VI-NEXT: s_endpgm1149 %vecins = insertelement <4 x i32> %a, i32 %val, i32 %b1150 store <4 x i32> %vecins, ptr addrspace(1) %out, align 161151 ret void1152}1153 1154define amdgpu_kernel void @dynamic_insertelement_v8i32(ptr addrspace(1) %out, <8 x i32> %a, i32 %b) nounwind {1155; SI-LABEL: dynamic_insertelement_v8i32:1156; SI: ; %bb.0:1157; SI-NEXT: s_load_dwordx8 s[0:7], s[8:9], 0x81158; SI-NEXT: s_load_dwordx2 s[12:13], s[8:9], 0x01159; SI-NEXT: s_load_dword s8, s[8:9], 0x101160; SI-NEXT: s_mov_b32 s15, 0x100f0001161; SI-NEXT: s_mov_b32 s14, -11162; SI-NEXT: s_waitcnt lgkmcnt(0)1163; SI-NEXT: v_mov_b32_e32 v0, s01164; SI-NEXT: v_mov_b32_e32 v1, s11165; SI-NEXT: v_mov_b32_e32 v2, s21166; SI-NEXT: v_mov_b32_e32 v3, s31167; SI-NEXT: v_mov_b32_e32 v4, s41168; SI-NEXT: v_mov_b32_e32 v5, s51169; SI-NEXT: v_mov_b32_e32 v6, s61170; SI-NEXT: v_mov_b32_e32 v7, s71171; SI-NEXT: s_mov_b32 m0, s81172; SI-NEXT: v_movreld_b32_e32 v0, 51173; SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[12:15], 0 offset:161174; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[12:15], 01175; SI-NEXT: s_endpgm1176;1177; VI-LABEL: dynamic_insertelement_v8i32:1178; VI: ; %bb.0:1179; VI-NEXT: s_load_dwordx8 s[0:7], s[8:9], 0x201180; VI-NEXT: s_load_dwordx2 s[12:13], s[8:9], 0x01181; VI-NEXT: s_load_dword s8, s[8:9], 0x401182; VI-NEXT: s_mov_b32 s15, 0x1100f0001183; VI-NEXT: s_mov_b32 s14, -11184; VI-NEXT: s_waitcnt lgkmcnt(0)1185; VI-NEXT: v_mov_b32_e32 v0, s01186; VI-NEXT: v_mov_b32_e32 v1, s11187; VI-NEXT: v_mov_b32_e32 v2, s21188; VI-NEXT: v_mov_b32_e32 v3, s31189; VI-NEXT: v_mov_b32_e32 v4, s41190; VI-NEXT: v_mov_b32_e32 v5, s51191; VI-NEXT: v_mov_b32_e32 v6, s61192; VI-NEXT: v_mov_b32_e32 v7, s71193; VI-NEXT: s_mov_b32 m0, s81194; VI-NEXT: v_movreld_b32_e32 v0, 51195; VI-NEXT: buffer_store_dwordx4 v[4:7], off, s[12:15], 0 offset:161196; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[12:15], 01197; VI-NEXT: s_endpgm1198 %vecins = insertelement <8 x i32> %a, i32 5, i32 %b1199 store <8 x i32> %vecins, ptr addrspace(1) %out, align 321200 ret void1201}1202 1203define amdgpu_kernel void @dynamic_insertelement_v9i32(ptr addrspace(1) %out, <9 x i32> %a, i32 %b) nounwind {1204; SI-LABEL: dynamic_insertelement_v9i32:1205; SI: ; %bb.0:1206; SI-NEXT: s_load_dwordx2 s[12:13], s[8:9], 0x01207; SI-NEXT: s_load_dwordx8 s[0:7], s[8:9], 0x101208; SI-NEXT: s_load_dword s10, s[8:9], 0x181209; SI-NEXT: s_load_dword s8, s[8:9], 0x201210; SI-NEXT: s_mov_b32 s15, 0x100f0001211; SI-NEXT: s_mov_b32 s14, -11212; SI-NEXT: s_waitcnt lgkmcnt(0)1213; SI-NEXT: v_mov_b32_e32 v0, s01214; SI-NEXT: v_mov_b32_e32 v1, s11215; SI-NEXT: v_mov_b32_e32 v2, s21216; SI-NEXT: v_mov_b32_e32 v3, s31217; SI-NEXT: v_mov_b32_e32 v4, s41218; SI-NEXT: v_mov_b32_e32 v5, s51219; SI-NEXT: v_mov_b32_e32 v6, s61220; SI-NEXT: v_mov_b32_e32 v7, s71221; SI-NEXT: v_mov_b32_e32 v8, s101222; SI-NEXT: s_mov_b32 m0, s81223; SI-NEXT: v_movreld_b32_e32 v0, 51224; SI-NEXT: buffer_store_dword v8, off, s[12:15], 0 offset:321225; SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[12:15], 0 offset:161226; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[12:15], 01227; SI-NEXT: s_endpgm1228;1229; VI-LABEL: dynamic_insertelement_v9i32:1230; VI: ; %bb.0:1231; VI-NEXT: s_load_dwordx8 s[0:7], s[8:9], 0x401232; VI-NEXT: s_load_dwordx2 s[12:13], s[8:9], 0x01233; VI-NEXT: s_mov_b32 s15, 0x1100f0001234; VI-NEXT: s_mov_b32 s14, -11235; VI-NEXT: s_waitcnt lgkmcnt(0)1236; VI-NEXT: v_mov_b32_e32 v0, s01237; VI-NEXT: v_mov_b32_e32 v1, s11238; VI-NEXT: s_load_dword s0, s[8:9], 0x601239; VI-NEXT: s_load_dword s1, s[8:9], 0x801240; VI-NEXT: v_mov_b32_e32 v2, s21241; VI-NEXT: v_mov_b32_e32 v3, s31242; VI-NEXT: v_mov_b32_e32 v4, s41243; VI-NEXT: v_mov_b32_e32 v5, s51244; VI-NEXT: v_mov_b32_e32 v6, s61245; VI-NEXT: v_mov_b32_e32 v7, s71246; VI-NEXT: s_waitcnt lgkmcnt(0)1247; VI-NEXT: v_mov_b32_e32 v8, s01248; VI-NEXT: s_mov_b32 m0, s11249; VI-NEXT: v_movreld_b32_e32 v0, 51250; VI-NEXT: buffer_store_dword v8, off, s[12:15], 0 offset:321251; VI-NEXT: buffer_store_dwordx4 v[4:7], off, s[12:15], 0 offset:161252; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[12:15], 01253; VI-NEXT: s_endpgm1254 %vecins = insertelement <9 x i32> %a, i32 5, i32 %b1255 store <9 x i32> %vecins, ptr addrspace(1) %out, align 321256 ret void1257}1258 1259define amdgpu_kernel void @dynamic_insertelement_v10i32(ptr addrspace(1) %out, <10 x i32> %a, i32 %b) nounwind {1260; SI-LABEL: dynamic_insertelement_v10i32:1261; SI: ; %bb.0:1262; SI-NEXT: s_load_dwordx2 s[12:13], s[8:9], 0x01263; SI-NEXT: s_load_dwordx8 s[0:7], s[8:9], 0x101264; SI-NEXT: s_load_dwordx2 s[10:11], s[8:9], 0x181265; SI-NEXT: s_load_dword s8, s[8:9], 0x201266; SI-NEXT: s_mov_b32 s15, 0x100f0001267; SI-NEXT: s_mov_b32 s14, -11268; SI-NEXT: s_waitcnt lgkmcnt(0)1269; SI-NEXT: v_mov_b32_e32 v0, s01270; SI-NEXT: v_mov_b32_e32 v1, s11271; SI-NEXT: v_mov_b32_e32 v2, s21272; SI-NEXT: v_mov_b32_e32 v3, s31273; SI-NEXT: v_mov_b32_e32 v4, s41274; SI-NEXT: v_mov_b32_e32 v5, s51275; SI-NEXT: v_mov_b32_e32 v6, s61276; SI-NEXT: v_mov_b32_e32 v7, s71277; SI-NEXT: v_mov_b32_e32 v8, s101278; SI-NEXT: v_mov_b32_e32 v9, s111279; SI-NEXT: s_mov_b32 m0, s81280; SI-NEXT: v_movreld_b32_e32 v0, 51281; SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[12:15], 0 offset:161282; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[12:15], 01283; SI-NEXT: buffer_store_dwordx2 v[8:9], off, s[12:15], 0 offset:321284; SI-NEXT: s_endpgm1285;1286; VI-LABEL: dynamic_insertelement_v10i32:1287; VI: ; %bb.0:1288; VI-NEXT: s_load_dwordx8 s[12:19], s[8:9], 0x401289; VI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x01290; VI-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x601291; VI-NEXT: s_load_dword s6, s[8:9], 0x801292; VI-NEXT: s_mov_b32 s3, 0x1100f0001293; VI-NEXT: s_mov_b32 s2, -11294; VI-NEXT: s_waitcnt lgkmcnt(0)1295; VI-NEXT: v_mov_b32_e32 v0, s121296; VI-NEXT: v_mov_b32_e32 v1, s131297; VI-NEXT: v_mov_b32_e32 v2, s141298; VI-NEXT: v_mov_b32_e32 v3, s151299; VI-NEXT: v_mov_b32_e32 v4, s161300; VI-NEXT: v_mov_b32_e32 v5, s171301; VI-NEXT: v_mov_b32_e32 v6, s181302; VI-NEXT: v_mov_b32_e32 v7, s191303; VI-NEXT: v_mov_b32_e32 v8, s41304; VI-NEXT: v_mov_b32_e32 v9, s51305; VI-NEXT: s_mov_b32 m0, s61306; VI-NEXT: v_movreld_b32_e32 v0, 51307; VI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:161308; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 01309; VI-NEXT: buffer_store_dwordx2 v[8:9], off, s[0:3], 0 offset:321310; VI-NEXT: s_endpgm1311 %vecins = insertelement <10 x i32> %a, i32 5, i32 %b1312 store <10 x i32> %vecins, ptr addrspace(1) %out, align 321313 ret void1314}1315 1316define amdgpu_kernel void @dynamic_insertelement_v11i32(ptr addrspace(1) %out, <11 x i32> %a, i32 %b) nounwind {1317; SI-LABEL: dynamic_insertelement_v11i32:1318; SI: ; %bb.0:1319; SI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x01320; SI-NEXT: s_load_dwordx8 s[12:19], s[8:9], 0x101321; SI-NEXT: s_load_dwordx4 s[4:7], s[8:9], 0x181322; SI-NEXT: s_waitcnt lgkmcnt(0)1323; SI-NEXT: s_load_dword s7, s[8:9], 0x201324; SI-NEXT: s_mov_b32 s3, 0x100f0001325; SI-NEXT: s_mov_b32 s2, -11326; SI-NEXT: v_mov_b32_e32 v0, s121327; SI-NEXT: v_mov_b32_e32 v1, s131328; SI-NEXT: v_mov_b32_e32 v2, s141329; SI-NEXT: v_mov_b32_e32 v3, s151330; SI-NEXT: v_mov_b32_e32 v4, s161331; SI-NEXT: v_mov_b32_e32 v5, s171332; SI-NEXT: v_mov_b32_e32 v6, s181333; SI-NEXT: v_mov_b32_e32 v7, s191334; SI-NEXT: v_mov_b32_e32 v8, s41335; SI-NEXT: v_mov_b32_e32 v9, s51336; SI-NEXT: v_mov_b32_e32 v10, s61337; SI-NEXT: s_waitcnt lgkmcnt(0)1338; SI-NEXT: s_mov_b32 m0, s71339; SI-NEXT: v_movreld_b32_e32 v0, 51340; SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:161341; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 01342; SI-NEXT: buffer_store_dwordx3 v[8:10], off, s[0:3], 0 offset:321343; SI-NEXT: s_endpgm1344;1345; VI-LABEL: dynamic_insertelement_v11i32:1346; VI: ; %bb.0:1347; VI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x01348; VI-NEXT: s_load_dwordx4 s[4:7], s[8:9], 0x601349; VI-NEXT: s_load_dwordx8 s[12:19], s[8:9], 0x401350; VI-NEXT: s_waitcnt lgkmcnt(0)1351; VI-NEXT: s_load_dword s7, s[8:9], 0x801352; VI-NEXT: s_mov_b32 s3, 0x1100f0001353; VI-NEXT: s_mov_b32 s2, -11354; VI-NEXT: v_mov_b32_e32 v8, s41355; VI-NEXT: v_mov_b32_e32 v0, s121356; VI-NEXT: v_mov_b32_e32 v1, s131357; VI-NEXT: v_mov_b32_e32 v2, s141358; VI-NEXT: v_mov_b32_e32 v3, s151359; VI-NEXT: v_mov_b32_e32 v4, s161360; VI-NEXT: v_mov_b32_e32 v5, s171361; VI-NEXT: v_mov_b32_e32 v6, s181362; VI-NEXT: v_mov_b32_e32 v7, s191363; VI-NEXT: v_mov_b32_e32 v9, s51364; VI-NEXT: v_mov_b32_e32 v10, s61365; VI-NEXT: s_waitcnt lgkmcnt(0)1366; VI-NEXT: s_mov_b32 m0, s71367; VI-NEXT: v_movreld_b32_e32 v0, 51368; VI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:161369; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 01370; VI-NEXT: buffer_store_dwordx3 v[8:10], off, s[0:3], 0 offset:321371; VI-NEXT: s_endpgm1372 %vecins = insertelement <11 x i32> %a, i32 5, i32 %b1373 store <11 x i32> %vecins, ptr addrspace(1) %out, align 321374 ret void1375}1376 1377define amdgpu_kernel void @dynamic_insertelement_v12i32(ptr addrspace(1) %out, <12 x i32> %a, i32 %b) nounwind {1378; SI-LABEL: dynamic_insertelement_v12i32:1379; SI: ; %bb.0:1380; SI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x01381; SI-NEXT: s_load_dwordx8 s[12:19], s[8:9], 0x101382; SI-NEXT: s_load_dwordx4 s[4:7], s[8:9], 0x181383; SI-NEXT: s_load_dword s8, s[8:9], 0x201384; SI-NEXT: s_mov_b32 s3, 0x100f0001385; SI-NEXT: s_mov_b32 s2, -11386; SI-NEXT: s_waitcnt lgkmcnt(0)1387; SI-NEXT: v_mov_b32_e32 v0, s121388; SI-NEXT: v_mov_b32_e32 v1, s131389; SI-NEXT: v_mov_b32_e32 v2, s141390; SI-NEXT: v_mov_b32_e32 v3, s151391; SI-NEXT: v_mov_b32_e32 v4, s161392; SI-NEXT: v_mov_b32_e32 v5, s171393; SI-NEXT: v_mov_b32_e32 v6, s181394; SI-NEXT: v_mov_b32_e32 v7, s191395; SI-NEXT: v_mov_b32_e32 v8, s41396; SI-NEXT: v_mov_b32_e32 v9, s51397; SI-NEXT: v_mov_b32_e32 v10, s61398; SI-NEXT: v_mov_b32_e32 v11, s71399; SI-NEXT: s_mov_b32 m0, s81400; SI-NEXT: v_movreld_b32_e32 v0, 51401; SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:161402; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 01403; SI-NEXT: buffer_store_dwordx4 v[8:11], off, s[0:3], 0 offset:321404; SI-NEXT: s_endpgm1405;1406; VI-LABEL: dynamic_insertelement_v12i32:1407; VI: ; %bb.0:1408; VI-NEXT: s_load_dwordx8 s[12:19], s[8:9], 0x401409; VI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x01410; VI-NEXT: s_load_dwordx4 s[4:7], s[8:9], 0x601411; VI-NEXT: s_load_dword s8, s[8:9], 0x801412; VI-NEXT: s_mov_b32 s3, 0x1100f0001413; VI-NEXT: s_mov_b32 s2, -11414; VI-NEXT: s_waitcnt lgkmcnt(0)1415; VI-NEXT: v_mov_b32_e32 v0, s121416; VI-NEXT: v_mov_b32_e32 v1, s131417; VI-NEXT: v_mov_b32_e32 v2, s141418; VI-NEXT: v_mov_b32_e32 v3, s151419; VI-NEXT: v_mov_b32_e32 v4, s161420; VI-NEXT: v_mov_b32_e32 v5, s171421; VI-NEXT: v_mov_b32_e32 v6, s181422; VI-NEXT: v_mov_b32_e32 v7, s191423; VI-NEXT: v_mov_b32_e32 v8, s41424; VI-NEXT: v_mov_b32_e32 v9, s51425; VI-NEXT: v_mov_b32_e32 v10, s61426; VI-NEXT: v_mov_b32_e32 v11, s71427; VI-NEXT: s_mov_b32 m0, s81428; VI-NEXT: v_movreld_b32_e32 v0, 51429; VI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:161430; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 01431; VI-NEXT: buffer_store_dwordx4 v[8:11], off, s[0:3], 0 offset:321432; VI-NEXT: s_endpgm1433 %vecins = insertelement <12 x i32> %a, i32 5, i32 %b1434 store <12 x i32> %vecins, ptr addrspace(1) %out, align 321435 ret void1436}1437 1438define amdgpu_kernel void @dynamic_insertelement_v16i32(ptr addrspace(1) %out, <16 x i32> %a, i32 %b) nounwind {1439; SI-LABEL: dynamic_insertelement_v16i32:1440; SI: ; %bb.0:1441; SI-NEXT: s_load_dwordx16 s[12:27], s[8:9], 0x101442; SI-NEXT: s_load_dword s4, s[8:9], 0x201443; SI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x01444; SI-NEXT: s_mov_b32 s3, 0x100f0001445; SI-NEXT: s_mov_b32 s2, -11446; SI-NEXT: s_waitcnt lgkmcnt(0)1447; SI-NEXT: v_mov_b32_e32 v0, s121448; SI-NEXT: v_mov_b32_e32 v1, s131449; SI-NEXT: v_mov_b32_e32 v2, s141450; SI-NEXT: v_mov_b32_e32 v3, s151451; SI-NEXT: v_mov_b32_e32 v4, s161452; SI-NEXT: v_mov_b32_e32 v5, s171453; SI-NEXT: v_mov_b32_e32 v6, s181454; SI-NEXT: v_mov_b32_e32 v7, s191455; SI-NEXT: v_mov_b32_e32 v8, s201456; SI-NEXT: v_mov_b32_e32 v9, s211457; SI-NEXT: v_mov_b32_e32 v10, s221458; SI-NEXT: v_mov_b32_e32 v11, s231459; SI-NEXT: v_mov_b32_e32 v12, s241460; SI-NEXT: v_mov_b32_e32 v13, s251461; SI-NEXT: v_mov_b32_e32 v14, s261462; SI-NEXT: v_mov_b32_e32 v15, s271463; SI-NEXT: s_mov_b32 m0, s41464; SI-NEXT: v_movreld_b32_e32 v0, 51465; SI-NEXT: buffer_store_dwordx4 v[12:15], off, s[0:3], 0 offset:481466; SI-NEXT: buffer_store_dwordx4 v[8:11], off, s[0:3], 0 offset:321467; SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:161468; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 01469; SI-NEXT: s_endpgm1470;1471; VI-LABEL: dynamic_insertelement_v16i32:1472; VI: ; %bb.0:1473; VI-NEXT: s_load_dwordx16 s[12:27], s[8:9], 0x401474; VI-NEXT: s_load_dword s4, s[8:9], 0x801475; VI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x01476; VI-NEXT: s_mov_b32 s3, 0x1100f0001477; VI-NEXT: s_mov_b32 s2, -11478; VI-NEXT: s_waitcnt lgkmcnt(0)1479; VI-NEXT: v_mov_b32_e32 v0, s121480; VI-NEXT: v_mov_b32_e32 v1, s131481; VI-NEXT: v_mov_b32_e32 v2, s141482; VI-NEXT: v_mov_b32_e32 v3, s151483; VI-NEXT: v_mov_b32_e32 v4, s161484; VI-NEXT: v_mov_b32_e32 v5, s171485; VI-NEXT: v_mov_b32_e32 v6, s181486; VI-NEXT: v_mov_b32_e32 v7, s191487; VI-NEXT: v_mov_b32_e32 v8, s201488; VI-NEXT: v_mov_b32_e32 v9, s211489; VI-NEXT: v_mov_b32_e32 v10, s221490; VI-NEXT: v_mov_b32_e32 v11, s231491; VI-NEXT: v_mov_b32_e32 v12, s241492; VI-NEXT: v_mov_b32_e32 v13, s251493; VI-NEXT: v_mov_b32_e32 v14, s261494; VI-NEXT: v_mov_b32_e32 v15, s271495; VI-NEXT: s_mov_b32 m0, s41496; VI-NEXT: v_movreld_b32_e32 v0, 51497; VI-NEXT: buffer_store_dwordx4 v[12:15], off, s[0:3], 0 offset:481498; VI-NEXT: buffer_store_dwordx4 v[8:11], off, s[0:3], 0 offset:321499; VI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:161500; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 01501; VI-NEXT: s_endpgm1502 %vecins = insertelement <16 x i32> %a, i32 5, i32 %b1503 store <16 x i32> %vecins, ptr addrspace(1) %out, align 641504 ret void1505}1506 1507define amdgpu_kernel void @dynamic_insertelement_v2i16(ptr addrspace(1) %out, <2 x i16> %a, i32 %b) nounwind {1508; SI-LABEL: dynamic_insertelement_v2i16:1509; SI: ; %bb.0:1510; SI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x01511; SI-NEXT: s_waitcnt lgkmcnt(0)1512; SI-NEXT: s_mov_b64 s[4:5], s[2:3]1513; SI-NEXT: s_lshl_b32 s5, s5, 41514; SI-NEXT: s_xor_b32 s6, s4, 0x500051515; SI-NEXT: s_lshl_b32 s5, 0xffff, s51516; SI-NEXT: s_and_b32 s5, s6, s51517; SI-NEXT: s_xor_b32 s4, s5, s41518; SI-NEXT: s_mov_b32 s3, 0x100f0001519; SI-NEXT: s_mov_b32 s2, -11520; SI-NEXT: v_mov_b32_e32 v0, s41521; SI-NEXT: buffer_store_dword v0, off, s[0:3], 01522; SI-NEXT: s_endpgm1523;1524; VI-LABEL: dynamic_insertelement_v2i16:1525; VI: ; %bb.0:1526; VI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x01527; VI-NEXT: s_waitcnt lgkmcnt(0)1528; VI-NEXT: s_mov_b64 s[4:5], s[2:3]1529; VI-NEXT: s_lshl_b32 s5, s5, 41530; VI-NEXT: s_xor_b32 s6, s4, 0x500051531; VI-NEXT: s_lshl_b32 s5, 0xffff, s51532; VI-NEXT: s_and_b32 s5, s6, s51533; VI-NEXT: s_xor_b32 s4, s5, s41534; VI-NEXT: s_mov_b32 s3, 0x1100f0001535; VI-NEXT: s_mov_b32 s2, -11536; VI-NEXT: v_mov_b32_e32 v0, s41537; VI-NEXT: buffer_store_dword v0, off, s[0:3], 01538; VI-NEXT: s_endpgm1539 %vecins = insertelement <2 x i16> %a, i16 5, i32 %b1540 store <2 x i16> %vecins, ptr addrspace(1) %out, align 81541 ret void1542}1543 1544define amdgpu_kernel void @dynamic_insertelement_v3i16(ptr addrspace(1) %out, <3 x i16> %a, i32 %b) nounwind {1545; SI-LABEL: dynamic_insertelement_v3i16:1546; SI: ; %bb.0:1547; SI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x01548; SI-NEXT: s_load_dword s8, s[8:9], 0x41549; SI-NEXT: s_mov_b32 s7, 0x100f0001550; SI-NEXT: s_mov_b32 s6, -11551; SI-NEXT: s_waitcnt lgkmcnt(0)1552; SI-NEXT: s_mov_b32 s4, s01553; SI-NEXT: s_lshl_b32 s8, s8, 41554; SI-NEXT: s_mov_b32 s5, s11555; SI-NEXT: s_xor_b32 s1, s3, 0x500051556; SI-NEXT: s_xor_b32 s0, s2, 0x500051557; SI-NEXT: s_lshl_b64 s[8:9], 0xffff, s81558; SI-NEXT: s_and_b64 s[0:1], s[0:1], s[8:9]1559; SI-NEXT: s_xor_b64 s[0:1], s[0:1], s[2:3]1560; SI-NEXT: v_mov_b32_e32 v0, s11561; SI-NEXT: buffer_store_short v0, off, s[4:7], 0 offset:41562; SI-NEXT: v_mov_b32_e32 v0, s01563; SI-NEXT: buffer_store_dword v0, off, s[4:7], 01564; SI-NEXT: s_endpgm1565;1566; VI-LABEL: dynamic_insertelement_v3i16:1567; VI: ; %bb.0:1568; VI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x01569; VI-NEXT: s_load_dword s8, s[8:9], 0x101570; VI-NEXT: s_mov_b32 s7, 0x1100f0001571; VI-NEXT: s_mov_b32 s6, -11572; VI-NEXT: s_waitcnt lgkmcnt(0)1573; VI-NEXT: s_mov_b32 s4, s01574; VI-NEXT: s_mov_b32 s0, 0x500051575; VI-NEXT: s_mov_b32 s5, s11576; VI-NEXT: s_mov_b32 s1, s01577; VI-NEXT: s_lshl_b32 s8, s8, 41578; VI-NEXT: s_xor_b64 s[0:1], s[2:3], s[0:1]1579; VI-NEXT: s_lshl_b64 s[8:9], 0xffff, s81580; VI-NEXT: s_and_b64 s[0:1], s[0:1], s[8:9]1581; VI-NEXT: s_xor_b64 s[0:1], s[0:1], s[2:3]1582; VI-NEXT: v_mov_b32_e32 v0, s11583; VI-NEXT: buffer_store_short v0, off, s[4:7], 0 offset:41584; VI-NEXT: v_mov_b32_e32 v0, s01585; VI-NEXT: buffer_store_dword v0, off, s[4:7], 01586; VI-NEXT: s_endpgm1587 %vecins = insertelement <3 x i16> %a, i16 5, i32 %b1588 store <3 x i16> %vecins, ptr addrspace(1) %out, align 81589 ret void1590}1591 1592define amdgpu_kernel void @dynamic_insertelement_v2i8(ptr addrspace(1) %out, [8 x i32], <2 x i8> %a, [8 x i32], i32 %b) nounwind {1593; SI-LABEL: dynamic_insertelement_v2i8:1594; SI: ; %bb.0:1595; SI-NEXT: s_load_dword s4, s[8:9], 0xa1596; SI-NEXT: s_load_dword s5, s[8:9], 0x131597; SI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x01598; SI-NEXT: s_mov_b32 s3, 0x100f0001599; SI-NEXT: s_mov_b32 s2, -11600; SI-NEXT: s_waitcnt lgkmcnt(0)1601; SI-NEXT: s_xor_b32 s6, s4, 0x5051602; SI-NEXT: s_lshl_b32 s5, s5, 31603; SI-NEXT: s_lshl_b32 s5, 0xff, s51604; SI-NEXT: s_and_b32 s5, s6, s51605; SI-NEXT: s_xor_b32 s4, s5, s41606; SI-NEXT: v_mov_b32_e32 v0, s41607; SI-NEXT: buffer_store_short v0, off, s[0:3], 01608; SI-NEXT: s_endpgm1609;1610; VI-LABEL: dynamic_insertelement_v2i8:1611; VI: ; %bb.0:1612; VI-NEXT: s_load_dword s4, s[8:9], 0x281613; VI-NEXT: s_load_dword s5, s[8:9], 0x4c1614; VI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x01615; VI-NEXT: s_mov_b32 s3, 0x1100f0001616; VI-NEXT: s_mov_b32 s2, -11617; VI-NEXT: s_waitcnt lgkmcnt(0)1618; VI-NEXT: s_xor_b32 s6, s4, 0x5051619; VI-NEXT: s_lshl_b32 s5, s5, 31620; VI-NEXT: s_lshl_b32 s5, 0xff, s51621; VI-NEXT: s_and_b32 s5, s6, s51622; VI-NEXT: s_xor_b32 s4, s5, s41623; VI-NEXT: v_mov_b32_e32 v0, s41624; VI-NEXT: buffer_store_short v0, off, s[0:3], 01625; VI-NEXT: s_endpgm1626 %vecins = insertelement <2 x i8> %a, i8 5, i32 %b1627 store <2 x i8> %vecins, ptr addrspace(1) %out, align 81628 ret void1629}1630 1631; FIXME: post legalize i16 and i32 shifts aren't merged because of1632; isTypeDesirableForOp in SimplifyDemandedBits1633define amdgpu_kernel void @dynamic_insertelement_v3i8(ptr addrspace(1) %out, [8 x i32], <3 x i8> %a, [8 x i32], i32 %b) nounwind {1634; SI-LABEL: dynamic_insertelement_v3i8:1635; SI: ; %bb.0:1636; SI-NEXT: s_load_dword s4, s[8:9], 0xa1637; SI-NEXT: s_load_dword s5, s[8:9], 0x131638; SI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x01639; SI-NEXT: s_mov_b32 s3, 0x100f0001640; SI-NEXT: s_mov_b32 s2, -11641; SI-NEXT: s_waitcnt lgkmcnt(0)1642; SI-NEXT: s_xor_b32 s6, s4, 0x50505051643; SI-NEXT: s_lshl_b32 s5, s5, 31644; SI-NEXT: s_lshl_b32 s5, 0xff, s51645; SI-NEXT: s_and_b32 s5, s6, s51646; SI-NEXT: s_xor_b32 s4, s5, s41647; SI-NEXT: s_lshr_b32 s5, s4, 161648; SI-NEXT: v_mov_b32_e32 v0, s41649; SI-NEXT: buffer_store_short v0, off, s[0:3], 01650; SI-NEXT: v_mov_b32_e32 v0, s51651; SI-NEXT: buffer_store_byte v0, off, s[0:3], 0 offset:21652; SI-NEXT: s_endpgm1653;1654; VI-LABEL: dynamic_insertelement_v3i8:1655; VI: ; %bb.0:1656; VI-NEXT: s_load_dword s4, s[8:9], 0x281657; VI-NEXT: s_load_dword s5, s[8:9], 0x4c1658; VI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x01659; VI-NEXT: s_mov_b32 s3, 0x1100f0001660; VI-NEXT: s_mov_b32 s2, -11661; VI-NEXT: s_waitcnt lgkmcnt(0)1662; VI-NEXT: s_xor_b32 s6, s4, 0x50505051663; VI-NEXT: s_lshl_b32 s5, s5, 31664; VI-NEXT: s_lshl_b32 s5, 0xff, s51665; VI-NEXT: s_and_b32 s5, s6, s51666; VI-NEXT: s_xor_b32 s4, s5, s41667; VI-NEXT: s_lshr_b32 s5, s4, 161668; VI-NEXT: v_mov_b32_e32 v0, s41669; VI-NEXT: buffer_store_short v0, off, s[0:3], 01670; VI-NEXT: v_mov_b32_e32 v0, s51671; VI-NEXT: buffer_store_byte v0, off, s[0:3], 0 offset:21672; VI-NEXT: s_endpgm1673 %vecins = insertelement <3 x i8> %a, i8 5, i32 %b1674 store <3 x i8> %vecins, ptr addrspace(1) %out, align 41675 ret void1676}1677 1678define amdgpu_kernel void @dynamic_insertelement_v4i8(ptr addrspace(1) %out, [8 x i32], <4 x i8> %a, [8 x i32], i32 %b) nounwind {1679; SI-LABEL: dynamic_insertelement_v4i8:1680; SI: ; %bb.0:1681; SI-NEXT: s_load_dword s4, s[8:9], 0xa1682; SI-NEXT: s_load_dword s5, s[8:9], 0x131683; SI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x01684; SI-NEXT: s_mov_b32 s3, 0x100f0001685; SI-NEXT: s_mov_b32 s2, -11686; SI-NEXT: s_waitcnt lgkmcnt(0)1687; SI-NEXT: s_xor_b32 s6, s4, 0x50505051688; SI-NEXT: s_lshl_b32 s5, s5, 31689; SI-NEXT: s_lshl_b32 s5, 0xff, s51690; SI-NEXT: s_and_b32 s5, s6, s51691; SI-NEXT: s_xor_b32 s4, s5, s41692; SI-NEXT: v_mov_b32_e32 v0, s41693; SI-NEXT: buffer_store_dword v0, off, s[0:3], 01694; SI-NEXT: s_endpgm1695;1696; VI-LABEL: dynamic_insertelement_v4i8:1697; VI: ; %bb.0:1698; VI-NEXT: s_load_dword s4, s[8:9], 0x281699; VI-NEXT: s_load_dword s5, s[8:9], 0x4c1700; VI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x01701; VI-NEXT: s_mov_b32 s3, 0x1100f0001702; VI-NEXT: s_mov_b32 s2, -11703; VI-NEXT: s_waitcnt lgkmcnt(0)1704; VI-NEXT: s_xor_b32 s6, s4, 0x50505051705; VI-NEXT: s_lshl_b32 s5, s5, 31706; VI-NEXT: s_lshl_b32 s5, 0xff, s51707; VI-NEXT: s_and_b32 s5, s6, s51708; VI-NEXT: s_xor_b32 s4, s5, s41709; VI-NEXT: v_mov_b32_e32 v0, s41710; VI-NEXT: buffer_store_dword v0, off, s[0:3], 01711; VI-NEXT: s_endpgm1712 %vecins = insertelement <4 x i8> %a, i8 5, i32 %b1713 store <4 x i8> %vecins, ptr addrspace(1) %out, align 41714 ret void1715}1716 1717define amdgpu_kernel void @s_dynamic_insertelement_v8i8(ptr addrspace(1) %out, ptr addrspace(4) %a.ptr, i32 %b) nounwind {1718; SI-LABEL: s_dynamic_insertelement_v8i8:1719; SI: ; %bb.0:1720; SI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x01721; SI-NEXT: s_mov_b32 s7, 0x100f0001722; SI-NEXT: s_mov_b32 s6, -11723; SI-NEXT: s_load_dword s8, s[8:9], 0x41724; SI-NEXT: s_waitcnt lgkmcnt(0)1725; SI-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x01726; SI-NEXT: s_mov_b32 s4, s01727; SI-NEXT: s_mov_b32 s5, s11728; SI-NEXT: s_lshl_b32 s8, s8, 31729; SI-NEXT: s_waitcnt lgkmcnt(0)1730; SI-NEXT: s_xor_b32 s1, s3, 0x50505051731; SI-NEXT: s_xor_b32 s0, s2, 0x50505051732; SI-NEXT: s_lshl_b64 s[8:9], 0xff, s81733; SI-NEXT: s_and_b64 s[0:1], s[0:1], s[8:9]1734; SI-NEXT: s_xor_b64 s[0:1], s[0:1], s[2:3]1735; SI-NEXT: v_mov_b32_e32 v0, s01736; SI-NEXT: v_mov_b32_e32 v1, s11737; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 01738; SI-NEXT: s_endpgm1739;1740; VI-LABEL: s_dynamic_insertelement_v8i8:1741; VI: ; %bb.0:1742; VI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x01743; VI-NEXT: s_mov_b32 s7, 0x1100f0001744; VI-NEXT: s_mov_b32 s6, -11745; VI-NEXT: s_load_dword s8, s[8:9], 0x101746; VI-NEXT: s_waitcnt lgkmcnt(0)1747; VI-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x01748; VI-NEXT: s_mov_b32 s4, s01749; VI-NEXT: s_mov_b32 s5, s11750; VI-NEXT: s_lshl_b32 s8, s8, 31751; VI-NEXT: s_waitcnt lgkmcnt(0)1752; VI-NEXT: s_xor_b32 s1, s3, 0x50505051753; VI-NEXT: s_xor_b32 s0, s2, 0x50505051754; VI-NEXT: s_lshl_b64 s[8:9], 0xff, s81755; VI-NEXT: s_and_b64 s[0:1], s[0:1], s[8:9]1756; VI-NEXT: s_xor_b64 s[0:1], s[0:1], s[2:3]1757; VI-NEXT: v_mov_b32_e32 v0, s01758; VI-NEXT: v_mov_b32_e32 v1, s11759; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 01760; VI-NEXT: s_endpgm1761 %a = load <8 x i8>, ptr addrspace(4) %a.ptr, align 41762 %vecins = insertelement <8 x i8> %a, i8 5, i32 %b1763 store <8 x i8> %vecins, ptr addrspace(1) %out, align 81764 ret void1765}1766 1767define amdgpu_kernel void @dynamic_insertelement_v16i8(ptr addrspace(1) %out, <16 x i8> %a, i32 %b) nounwind {1768; SI-LABEL: dynamic_insertelement_v16i8:1769; SI: ; %bb.0:1770; SI-NEXT: s_load_dwordx4 s[4:7], s[8:9], 0x41771; SI-NEXT: s_load_dword s10, s[8:9], 0x81772; SI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x01773; SI-NEXT: s_mov_b32 s3, 0x100f0001774; SI-NEXT: s_mov_b32 s2, -11775; SI-NEXT: s_waitcnt lgkmcnt(0)1776; SI-NEXT: s_lshr_b32 s8, s7, 241777; SI-NEXT: s_cmp_lg_u32 s10, 151778; SI-NEXT: s_cselect_b32 s8, s8, 51779; SI-NEXT: s_lshl_b32 s8, s8, 241780; SI-NEXT: s_lshr_b32 s9, s7, 161781; SI-NEXT: s_cmp_lg_u32 s10, 141782; SI-NEXT: s_cselect_b32 s9, s9, 51783; SI-NEXT: s_and_b32 s9, s9, 0xff1784; SI-NEXT: s_lshl_b32 s9, s9, 161785; SI-NEXT: s_or_b32 s8, s8, s91786; SI-NEXT: s_lshr_b32 s9, s7, 81787; SI-NEXT: s_cmp_lg_u32 s10, 131788; SI-NEXT: s_cselect_b32 s9, s9, 51789; SI-NEXT: s_lshl_b32 s9, s9, 81790; SI-NEXT: s_cmp_lg_u32 s10, 121791; SI-NEXT: s_cselect_b32 s7, s7, 51792; SI-NEXT: s_and_b32 s7, s7, 0xff1793; SI-NEXT: s_or_b32 s7, s7, s91794; SI-NEXT: s_and_b32 s7, s7, 0xffff1795; SI-NEXT: s_or_b32 s7, s7, s81796; SI-NEXT: s_lshr_b32 s8, s6, 241797; SI-NEXT: s_cmp_lg_u32 s10, 111798; SI-NEXT: s_cselect_b32 s8, s8, 51799; SI-NEXT: s_lshl_b32 s8, s8, 241800; SI-NEXT: s_lshr_b32 s9, s6, 161801; SI-NEXT: s_cmp_lg_u32 s10, 101802; SI-NEXT: s_cselect_b32 s9, s9, 51803; SI-NEXT: s_and_b32 s9, s9, 0xff1804; SI-NEXT: s_lshl_b32 s9, s9, 161805; SI-NEXT: s_or_b32 s8, s8, s91806; SI-NEXT: s_lshr_b32 s9, s6, 81807; SI-NEXT: s_cmp_lg_u32 s10, 91808; SI-NEXT: s_cselect_b32 s9, s9, 51809; SI-NEXT: s_lshl_b32 s9, s9, 81810; SI-NEXT: s_cmp_lg_u32 s10, 81811; SI-NEXT: s_cselect_b32 s6, s6, 51812; SI-NEXT: s_and_b32 s6, s6, 0xff1813; SI-NEXT: s_or_b32 s6, s6, s91814; SI-NEXT: s_and_b32 s6, s6, 0xffff1815; SI-NEXT: s_or_b32 s6, s6, s81816; SI-NEXT: s_lshr_b32 s8, s5, 241817; SI-NEXT: s_cmp_lg_u32 s10, 71818; SI-NEXT: s_cselect_b32 s8, s8, 51819; SI-NEXT: s_lshl_b32 s8, s8, 241820; SI-NEXT: s_lshr_b32 s9, s5, 161821; SI-NEXT: s_cmp_lg_u32 s10, 61822; SI-NEXT: s_cselect_b32 s9, s9, 51823; SI-NEXT: s_and_b32 s9, s9, 0xff1824; SI-NEXT: s_lshl_b32 s9, s9, 161825; SI-NEXT: s_or_b32 s8, s8, s91826; SI-NEXT: s_lshr_b32 s9, s5, 81827; SI-NEXT: s_cmp_lg_u32 s10, 51828; SI-NEXT: s_cselect_b32 s9, s9, 51829; SI-NEXT: s_lshl_b32 s9, s9, 81830; SI-NEXT: s_cmp_lg_u32 s10, 41831; SI-NEXT: s_cselect_b32 s5, s5, 51832; SI-NEXT: s_and_b32 s5, s5, 0xff1833; SI-NEXT: s_or_b32 s5, s5, s91834; SI-NEXT: s_and_b32 s5, s5, 0xffff1835; SI-NEXT: s_or_b32 s5, s5, s81836; SI-NEXT: s_lshr_b32 s8, s4, 241837; SI-NEXT: s_cmp_lg_u32 s10, 31838; SI-NEXT: s_cselect_b32 s8, s8, 51839; SI-NEXT: s_lshl_b32 s8, s8, 241840; SI-NEXT: s_lshr_b32 s9, s4, 161841; SI-NEXT: s_cmp_lg_u32 s10, 21842; SI-NEXT: s_cselect_b32 s9, s9, 51843; SI-NEXT: s_and_b32 s9, s9, 0xff1844; SI-NEXT: s_lshl_b32 s9, s9, 161845; SI-NEXT: s_or_b32 s8, s8, s91846; SI-NEXT: s_lshr_b32 s9, s4, 81847; SI-NEXT: s_cmp_lg_u32 s10, 11848; SI-NEXT: s_cselect_b32 s9, s9, 51849; SI-NEXT: s_lshl_b32 s9, s9, 81850; SI-NEXT: s_cmp_lg_u32 s10, 01851; SI-NEXT: s_cselect_b32 s4, s4, 51852; SI-NEXT: s_and_b32 s4, s4, 0xff1853; SI-NEXT: s_or_b32 s4, s4, s91854; SI-NEXT: s_and_b32 s4, s4, 0xffff1855; SI-NEXT: s_or_b32 s4, s4, s81856; SI-NEXT: v_mov_b32_e32 v0, s41857; SI-NEXT: v_mov_b32_e32 v1, s51858; SI-NEXT: v_mov_b32_e32 v2, s61859; SI-NEXT: v_mov_b32_e32 v3, s71860; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 01861; SI-NEXT: s_endpgm1862;1863; VI-LABEL: dynamic_insertelement_v16i8:1864; VI: ; %bb.0:1865; VI-NEXT: s_load_dwordx4 s[4:7], s[8:9], 0x101866; VI-NEXT: s_load_dword s10, s[8:9], 0x201867; VI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x01868; VI-NEXT: s_mov_b32 s3, 0x1100f0001869; VI-NEXT: s_mov_b32 s2, -11870; VI-NEXT: s_waitcnt lgkmcnt(0)1871; VI-NEXT: s_lshr_b32 s8, s7, 241872; VI-NEXT: s_cmp_lg_u32 s10, 151873; VI-NEXT: s_cselect_b32 s8, s8, 51874; VI-NEXT: s_lshl_b32 s8, s8, 81875; VI-NEXT: s_lshr_b32 s9, s7, 161876; VI-NEXT: s_cmp_lg_u32 s10, 141877; VI-NEXT: s_cselect_b32 s9, s9, 51878; VI-NEXT: s_and_b32 s9, s9, 0xff1879; VI-NEXT: s_or_b32 s8, s9, s81880; VI-NEXT: s_lshl_b32 s8, s8, 161881; VI-NEXT: s_lshr_b32 s9, s7, 81882; VI-NEXT: s_cmp_lg_u32 s10, 131883; VI-NEXT: s_cselect_b32 s9, s9, 51884; VI-NEXT: s_lshl_b32 s9, s9, 81885; VI-NEXT: s_cmp_lg_u32 s10, 121886; VI-NEXT: s_cselect_b32 s7, s7, 51887; VI-NEXT: s_and_b32 s7, s7, 0xff1888; VI-NEXT: s_or_b32 s7, s7, s91889; VI-NEXT: s_and_b32 s7, s7, 0xffff1890; VI-NEXT: s_or_b32 s7, s7, s81891; VI-NEXT: s_lshr_b32 s8, s6, 241892; VI-NEXT: s_cmp_lg_u32 s10, 111893; VI-NEXT: s_cselect_b32 s8, s8, 51894; VI-NEXT: s_lshl_b32 s8, s8, 81895; VI-NEXT: s_lshr_b32 s9, s6, 161896; VI-NEXT: s_cmp_lg_u32 s10, 101897; VI-NEXT: s_cselect_b32 s9, s9, 51898; VI-NEXT: s_and_b32 s9, s9, 0xff1899; VI-NEXT: s_or_b32 s8, s9, s81900; VI-NEXT: s_lshl_b32 s8, s8, 161901; VI-NEXT: s_lshr_b32 s9, s6, 81902; VI-NEXT: s_cmp_lg_u32 s10, 91903; VI-NEXT: s_cselect_b32 s9, s9, 51904; VI-NEXT: s_lshl_b32 s9, s9, 81905; VI-NEXT: s_cmp_lg_u32 s10, 81906; VI-NEXT: s_cselect_b32 s6, s6, 51907; VI-NEXT: s_and_b32 s6, s6, 0xff1908; VI-NEXT: s_or_b32 s6, s6, s91909; VI-NEXT: s_and_b32 s6, s6, 0xffff1910; VI-NEXT: s_or_b32 s6, s6, s81911; VI-NEXT: s_lshr_b32 s8, s5, 241912; VI-NEXT: s_cmp_lg_u32 s10, 71913; VI-NEXT: s_cselect_b32 s8, s8, 51914; VI-NEXT: s_lshl_b32 s8, s8, 81915; VI-NEXT: s_lshr_b32 s9, s5, 161916; VI-NEXT: s_cmp_lg_u32 s10, 61917; VI-NEXT: s_cselect_b32 s9, s9, 51918; VI-NEXT: s_and_b32 s9, s9, 0xff1919; VI-NEXT: s_or_b32 s8, s9, s81920; VI-NEXT: s_lshl_b32 s8, s8, 161921; VI-NEXT: s_lshr_b32 s9, s5, 81922; VI-NEXT: s_cmp_lg_u32 s10, 51923; VI-NEXT: s_cselect_b32 s9, s9, 51924; VI-NEXT: s_lshl_b32 s9, s9, 81925; VI-NEXT: s_cmp_lg_u32 s10, 41926; VI-NEXT: s_cselect_b32 s5, s5, 51927; VI-NEXT: s_and_b32 s5, s5, 0xff1928; VI-NEXT: s_or_b32 s5, s5, s91929; VI-NEXT: s_and_b32 s5, s5, 0xffff1930; VI-NEXT: s_or_b32 s5, s5, s81931; VI-NEXT: s_lshr_b32 s8, s4, 241932; VI-NEXT: s_cmp_lg_u32 s10, 31933; VI-NEXT: s_cselect_b32 s8, s8, 51934; VI-NEXT: s_lshl_b32 s8, s8, 81935; VI-NEXT: s_lshr_b32 s9, s4, 161936; VI-NEXT: s_cmp_lg_u32 s10, 21937; VI-NEXT: s_cselect_b32 s9, s9, 51938; VI-NEXT: s_and_b32 s9, s9, 0xff1939; VI-NEXT: s_or_b32 s8, s9, s81940; VI-NEXT: s_lshl_b32 s8, s8, 161941; VI-NEXT: s_lshr_b32 s9, s4, 81942; VI-NEXT: s_cmp_lg_u32 s10, 11943; VI-NEXT: s_cselect_b32 s9, s9, 51944; VI-NEXT: s_lshl_b32 s9, s9, 81945; VI-NEXT: s_cmp_lg_u32 s10, 01946; VI-NEXT: s_cselect_b32 s4, s4, 51947; VI-NEXT: s_and_b32 s4, s4, 0xff1948; VI-NEXT: s_or_b32 s4, s4, s91949; VI-NEXT: s_and_b32 s4, s4, 0xffff1950; VI-NEXT: s_or_b32 s4, s4, s81951; VI-NEXT: v_mov_b32_e32 v0, s41952; VI-NEXT: v_mov_b32_e32 v1, s51953; VI-NEXT: v_mov_b32_e32 v2, s61954; VI-NEXT: v_mov_b32_e32 v3, s71955; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 01956; VI-NEXT: s_endpgm1957 %vecins = insertelement <16 x i8> %a, i8 5, i32 %b1958 store <16 x i8> %vecins, ptr addrspace(1) %out, align 161959 ret void1960}1961 1962; This test requires handling INSERT_SUBREG in SIFixSGPRCopies. Check that1963; the compiler doesn't crash.1964define amdgpu_kernel void @insert_split_bb(ptr addrspace(1) %out, ptr addrspace(1) %in, i32 %a, i32 %b) {1965; SI-LABEL: insert_split_bb:1966; SI: ; %bb.0: ; %entry1967; SI-NEXT: s_load_dword s4, s[8:9], 0x41968; SI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x01969; SI-NEXT: s_waitcnt lgkmcnt(0)1970; SI-NEXT: s_cmp_lg_u32 s4, 01971; SI-NEXT: s_cbranch_scc0 .LBB42_41972; SI-NEXT: ; %bb.1: ; %else1973; SI-NEXT: s_load_dword s5, s[2:3], 0x11974; SI-NEXT: s_mov_b64 s[6:7], 01975; SI-NEXT: s_andn2_b64 vcc, exec, s[6:7]1976; SI-NEXT: s_waitcnt lgkmcnt(0)1977; SI-NEXT: s_mov_b64 vcc, vcc1978; SI-NEXT: s_cbranch_vccnz .LBB42_31979; SI-NEXT: .LBB42_2: ; %if1980; SI-NEXT: s_load_dword s5, s[2:3], 0x01981; SI-NEXT: .LBB42_3: ; %endif1982; SI-NEXT: s_waitcnt lgkmcnt(0)1983; SI-NEXT: v_mov_b32_e32 v0, s41984; SI-NEXT: s_mov_b32 s3, 0x100f0001985; SI-NEXT: s_mov_b32 s2, -11986; SI-NEXT: v_mov_b32_e32 v1, s51987; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 01988; SI-NEXT: s_endpgm1989; SI-NEXT: .LBB42_4:1990; SI-NEXT: s_branch .LBB42_21991;1992; VI-LABEL: insert_split_bb:1993; VI: ; %bb.0: ; %entry1994; VI-NEXT: s_load_dword s4, s[8:9], 0x101995; VI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x01996; VI-NEXT: s_waitcnt lgkmcnt(0)1997; VI-NEXT: s_cmp_lg_u32 s4, 01998; VI-NEXT: s_cbranch_scc0 .LBB42_41999; VI-NEXT: ; %bb.1: ; %else2000; VI-NEXT: s_load_dword s5, s[2:3], 0x42001; VI-NEXT: s_cbranch_execnz .LBB42_32002; VI-NEXT: .LBB42_2: ; %if2003; VI-NEXT: s_waitcnt lgkmcnt(0)2004; VI-NEXT: s_load_dword s5, s[2:3], 0x02005; VI-NEXT: .LBB42_3: ; %endif2006; VI-NEXT: s_waitcnt lgkmcnt(0)2007; VI-NEXT: v_mov_b32_e32 v0, s42008; VI-NEXT: s_mov_b32 s3, 0x1100f0002009; VI-NEXT: s_mov_b32 s2, -12010; VI-NEXT: v_mov_b32_e32 v1, s52011; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 02012; VI-NEXT: s_endpgm2013; VI-NEXT: .LBB42_4:2014; VI-NEXT: s_branch .LBB42_22015entry:2016 %0 = insertelement <2 x i32> poison, i32 %a, i32 02017 %1 = icmp eq i32 %a, 02018 br i1 %1, label %if, label %else2019 2020if:2021 %2 = load i32, ptr addrspace(1) %in2022 %3 = insertelement <2 x i32> %0, i32 %2, i32 12023 br label %endif2024 2025else:2026 %4 = getelementptr i32, ptr addrspace(1) %in, i32 12027 %5 = load i32, ptr addrspace(1) %42028 %6 = insertelement <2 x i32> %0, i32 %5, i32 12029 br label %endif2030 2031endif:2032 %7 = phi <2 x i32> [%3, %if], [%6, %else]2033 store <2 x i32> %7, ptr addrspace(1) %out2034 ret void2035}2036 2037define amdgpu_kernel void @dynamic_insertelement_v2f64(ptr addrspace(1) %out, [8 x i32], <2 x double> %a, [8 x i32], i32 %b) nounwind {2038; SI-LABEL: dynamic_insertelement_v2f64:2039; SI: ; %bb.0:2040; SI-NEXT: s_load_dword s10, s[8:9], 0x182041; SI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0xc2042; SI-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x02043; SI-NEXT: s_mov_b32 s7, 0x100f0002044; SI-NEXT: s_mov_b32 s6, -12045; SI-NEXT: s_waitcnt lgkmcnt(0)2046; SI-NEXT: s_cmp_eq_u32 s10, 12047; SI-NEXT: s_cselect_b32 s3, 0x40200000, s32048; SI-NEXT: s_cselect_b32 s2, 0, s22049; SI-NEXT: s_cmp_eq_u32 s10, 02050; SI-NEXT: s_cselect_b32 s1, 0x40200000, s12051; SI-NEXT: s_cselect_b32 s0, 0, s02052; SI-NEXT: v_mov_b32_e32 v0, s02053; SI-NEXT: v_mov_b32_e32 v1, s12054; SI-NEXT: v_mov_b32_e32 v2, s22055; SI-NEXT: v_mov_b32_e32 v3, s32056; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 02057; SI-NEXT: s_endpgm2058;2059; VI-LABEL: dynamic_insertelement_v2f64:2060; VI: ; %bb.0:2061; VI-NEXT: s_load_dword s10, s[8:9], 0x602062; VI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x302063; VI-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x02064; VI-NEXT: s_mov_b32 s7, 0x1100f0002065; VI-NEXT: s_mov_b32 s6, -12066; VI-NEXT: s_waitcnt lgkmcnt(0)2067; VI-NEXT: s_cmp_eq_u32 s10, 12068; VI-NEXT: s_cselect_b32 s3, 0x40200000, s32069; VI-NEXT: s_cselect_b32 s2, 0, s22070; VI-NEXT: s_cmp_eq_u32 s10, 02071; VI-NEXT: s_cselect_b32 s1, 0x40200000, s12072; VI-NEXT: s_cselect_b32 s0, 0, s02073; VI-NEXT: v_mov_b32_e32 v0, s02074; VI-NEXT: v_mov_b32_e32 v1, s12075; VI-NEXT: v_mov_b32_e32 v2, s22076; VI-NEXT: v_mov_b32_e32 v3, s32077; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 02078; VI-NEXT: s_endpgm2079 %vecins = insertelement <2 x double> %a, double 8.0, i32 %b2080 store <2 x double> %vecins, ptr addrspace(1) %out, align 162081 ret void2082}2083 2084define amdgpu_kernel void @dynamic_insertelement_v2i64(ptr addrspace(1) %out, <2 x i64> %a, i32 %b) nounwind {2085; SI-LABEL: dynamic_insertelement_v2i64:2086; SI: ; %bb.0:2087; SI-NEXT: s_load_dword s10, s[8:9], 0x82088; SI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x42089; SI-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x02090; SI-NEXT: s_mov_b32 s7, 0x100f0002091; SI-NEXT: s_mov_b32 s6, -12092; SI-NEXT: s_waitcnt lgkmcnt(0)2093; SI-NEXT: s_cmp_eq_u32 s10, 12094; SI-NEXT: s_cselect_b32 s3, 0, s32095; SI-NEXT: s_cselect_b32 s2, 5, s22096; SI-NEXT: s_cmp_eq_u32 s10, 02097; SI-NEXT: s_cselect_b32 s1, 0, s12098; SI-NEXT: s_cselect_b32 s0, 5, s02099; SI-NEXT: v_mov_b32_e32 v0, s02100; SI-NEXT: v_mov_b32_e32 v1, s12101; SI-NEXT: v_mov_b32_e32 v2, s22102; SI-NEXT: v_mov_b32_e32 v3, s32103; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 02104; SI-NEXT: s_endpgm2105;2106; VI-LABEL: dynamic_insertelement_v2i64:2107; VI: ; %bb.0:2108; VI-NEXT: s_load_dword s10, s[8:9], 0x202109; VI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x102110; VI-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x02111; VI-NEXT: s_mov_b32 s7, 0x1100f0002112; VI-NEXT: s_mov_b32 s6, -12113; VI-NEXT: s_waitcnt lgkmcnt(0)2114; VI-NEXT: s_cmp_eq_u32 s10, 12115; VI-NEXT: s_cselect_b32 s3, 0, s32116; VI-NEXT: s_cselect_b32 s2, 5, s22117; VI-NEXT: s_cmp_eq_u32 s10, 02118; VI-NEXT: s_cselect_b32 s1, 0, s12119; VI-NEXT: s_cselect_b32 s0, 5, s02120; VI-NEXT: v_mov_b32_e32 v0, s02121; VI-NEXT: v_mov_b32_e32 v1, s12122; VI-NEXT: v_mov_b32_e32 v2, s22123; VI-NEXT: v_mov_b32_e32 v3, s32124; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 02125; VI-NEXT: s_endpgm2126 %vecins = insertelement <2 x i64> %a, i64 5, i32 %b2127 store <2 x i64> %vecins, ptr addrspace(1) %out, align 82128 ret void2129}2130 2131define amdgpu_kernel void @dynamic_insertelement_v3i64(ptr addrspace(1) %out, <3 x i64> %a, i32 %b) nounwind {2132; SI-LABEL: dynamic_insertelement_v3i64:2133; SI: ; %bb.0:2134; SI-NEXT: s_load_dword s10, s[8:9], 0x102135; SI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x02136; SI-NEXT: s_load_dwordx4 s[4:7], s[8:9], 0x82137; SI-NEXT: s_load_dwordx2 s[8:9], s[8:9], 0xc2138; SI-NEXT: s_mov_b32 s3, 0x100f0002139; SI-NEXT: s_waitcnt lgkmcnt(0)2140; SI-NEXT: s_cmp_eq_u32 s10, 12141; SI-NEXT: s_mov_b32 s2, -12142; SI-NEXT: s_cselect_b32 s7, 0, s72143; SI-NEXT: s_cselect_b32 s6, 5, s62144; SI-NEXT: s_cmp_eq_u32 s10, 02145; SI-NEXT: s_cselect_b32 s5, 0, s52146; SI-NEXT: s_cselect_b32 s4, 5, s42147; SI-NEXT: s_cmp_eq_u32 s10, 22148; SI-NEXT: s_cselect_b32 s9, 0, s92149; SI-NEXT: s_cselect_b32 s8, 5, s82150; SI-NEXT: v_mov_b32_e32 v0, s82151; SI-NEXT: v_mov_b32_e32 v1, s92152; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 offset:162153; SI-NEXT: v_mov_b32_e32 v0, s42154; SI-NEXT: v_mov_b32_e32 v1, s52155; SI-NEXT: v_mov_b32_e32 v2, s62156; SI-NEXT: v_mov_b32_e32 v3, s72157; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 02158; SI-NEXT: s_endpgm2159;2160; VI-LABEL: dynamic_insertelement_v3i64:2161; VI: ; %bb.0:2162; VI-NEXT: s_load_dword s10, s[8:9], 0x402163; VI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x02164; VI-NEXT: s_load_dwordx4 s[4:7], s[8:9], 0x202165; VI-NEXT: s_load_dwordx2 s[8:9], s[8:9], 0x302166; VI-NEXT: s_mov_b32 s3, 0x1100f0002167; VI-NEXT: s_waitcnt lgkmcnt(0)2168; VI-NEXT: s_cmp_eq_u32 s10, 12169; VI-NEXT: s_mov_b32 s2, -12170; VI-NEXT: s_cselect_b32 s7, 0, s72171; VI-NEXT: s_cselect_b32 s6, 5, s62172; VI-NEXT: s_cmp_eq_u32 s10, 02173; VI-NEXT: s_cselect_b32 s5, 0, s52174; VI-NEXT: s_cselect_b32 s4, 5, s42175; VI-NEXT: s_cmp_eq_u32 s10, 22176; VI-NEXT: s_cselect_b32 s9, 0, s92177; VI-NEXT: s_cselect_b32 s8, 5, s82178; VI-NEXT: v_mov_b32_e32 v0, s82179; VI-NEXT: v_mov_b32_e32 v1, s92180; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 offset:162181; VI-NEXT: v_mov_b32_e32 v0, s42182; VI-NEXT: v_mov_b32_e32 v1, s52183; VI-NEXT: v_mov_b32_e32 v2, s62184; VI-NEXT: v_mov_b32_e32 v3, s72185; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 02186; VI-NEXT: s_endpgm2187 %vecins = insertelement <3 x i64> %a, i64 5, i32 %b2188 store <3 x i64> %vecins, ptr addrspace(1) %out, align 322189 ret void2190}2191 2192define amdgpu_kernel void @dynamic_insertelement_v4f64(ptr addrspace(1) %out, <4 x double> %a, i32 %b) nounwind {2193; SI-LABEL: dynamic_insertelement_v4f64:2194; SI: ; %bb.0:2195; SI-NEXT: s_load_dword s12, s[8:9], 0x102196; SI-NEXT: s_load_dwordx8 s[0:7], s[8:9], 0x82197; SI-NEXT: s_load_dwordx2 s[8:9], s[8:9], 0x02198; SI-NEXT: s_mov_b32 s11, 0x100f0002199; SI-NEXT: s_mov_b32 s10, -12200; SI-NEXT: s_waitcnt lgkmcnt(0)2201; SI-NEXT: s_cmp_eq_u32 s12, 12202; SI-NEXT: s_cselect_b32 s3, 0x40200000, s32203; SI-NEXT: s_cselect_b32 s2, 0, s22204; SI-NEXT: s_cmp_eq_u32 s12, 02205; SI-NEXT: s_cselect_b32 s1, 0x40200000, s12206; SI-NEXT: s_cselect_b32 s0, 0, s02207; SI-NEXT: s_cmp_eq_u32 s12, 32208; SI-NEXT: s_cselect_b32 s7, 0x40200000, s72209; SI-NEXT: s_cselect_b32 s6, 0, s62210; SI-NEXT: s_cmp_eq_u32 s12, 22211; SI-NEXT: s_cselect_b32 s5, 0x40200000, s52212; SI-NEXT: s_cselect_b32 s4, 0, s42213; SI-NEXT: v_mov_b32_e32 v0, s42214; SI-NEXT: v_mov_b32_e32 v1, s52215; SI-NEXT: v_mov_b32_e32 v2, s62216; SI-NEXT: v_mov_b32_e32 v3, s72217; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0 offset:162218; SI-NEXT: s_nop 02219; SI-NEXT: v_mov_b32_e32 v0, s02220; SI-NEXT: v_mov_b32_e32 v1, s12221; SI-NEXT: v_mov_b32_e32 v2, s22222; SI-NEXT: v_mov_b32_e32 v3, s32223; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 02224; SI-NEXT: s_endpgm2225;2226; VI-LABEL: dynamic_insertelement_v4f64:2227; VI: ; %bb.0:2228; VI-NEXT: s_load_dword s12, s[8:9], 0x402229; VI-NEXT: s_load_dwordx8 s[0:7], s[8:9], 0x202230; VI-NEXT: s_load_dwordx2 s[8:9], s[8:9], 0x02231; VI-NEXT: s_mov_b32 s11, 0x1100f0002232; VI-NEXT: s_mov_b32 s10, -12233; VI-NEXT: s_waitcnt lgkmcnt(0)2234; VI-NEXT: s_cmp_eq_u32 s12, 12235; VI-NEXT: s_cselect_b32 s3, 0x40200000, s32236; VI-NEXT: s_cselect_b32 s2, 0, s22237; VI-NEXT: s_cmp_eq_u32 s12, 02238; VI-NEXT: s_cselect_b32 s1, 0x40200000, s12239; VI-NEXT: s_cselect_b32 s0, 0, s02240; VI-NEXT: s_cmp_eq_u32 s12, 32241; VI-NEXT: s_cselect_b32 s7, 0x40200000, s72242; VI-NEXT: s_cselect_b32 s6, 0, s62243; VI-NEXT: s_cmp_eq_u32 s12, 22244; VI-NEXT: s_cselect_b32 s5, 0x40200000, s52245; VI-NEXT: s_cselect_b32 s4, 0, s42246; VI-NEXT: v_mov_b32_e32 v0, s42247; VI-NEXT: v_mov_b32_e32 v1, s52248; VI-NEXT: v_mov_b32_e32 v2, s62249; VI-NEXT: v_mov_b32_e32 v3, s72250; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0 offset:162251; VI-NEXT: s_nop 02252; VI-NEXT: v_mov_b32_e32 v0, s02253; VI-NEXT: v_mov_b32_e32 v1, s12254; VI-NEXT: v_mov_b32_e32 v2, s22255; VI-NEXT: v_mov_b32_e32 v3, s32256; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 02257; VI-NEXT: s_endpgm2258 %vecins = insertelement <4 x double> %a, double 8.0, i32 %b2259 store <4 x double> %vecins, ptr addrspace(1) %out, align 162260 ret void2261}2262 2263define amdgpu_kernel void @dynamic_insertelement_v8f64(ptr addrspace(1) %out, <8 x double> %a, i32 %b) #0 {2264; SI-LABEL: dynamic_insertelement_v8f64:2265; SI: ; %bb.0:2266; SI-NEXT: s_load_dwordx16 s[12:27], s[8:9], 0x102267; SI-NEXT: s_load_dword s4, s[8:9], 0x202268; SI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x02269; SI-NEXT: v_mov_b32_e32 v16, 0x402000002270; SI-NEXT: s_mov_b32 s3, 0x100f0002271; SI-NEXT: s_waitcnt lgkmcnt(0)2272; SI-NEXT: v_mov_b32_e32 v0, s122273; SI-NEXT: v_mov_b32_e32 v1, s132274; SI-NEXT: v_mov_b32_e32 v2, s142275; SI-NEXT: v_mov_b32_e32 v3, s152276; SI-NEXT: v_mov_b32_e32 v4, s162277; SI-NEXT: v_mov_b32_e32 v5, s172278; SI-NEXT: v_mov_b32_e32 v6, s182279; SI-NEXT: v_mov_b32_e32 v7, s192280; SI-NEXT: v_mov_b32_e32 v8, s202281; SI-NEXT: v_mov_b32_e32 v9, s212282; SI-NEXT: v_mov_b32_e32 v10, s222283; SI-NEXT: v_mov_b32_e32 v11, s232284; SI-NEXT: v_mov_b32_e32 v12, s242285; SI-NEXT: v_mov_b32_e32 v13, s252286; SI-NEXT: v_mov_b32_e32 v14, s262287; SI-NEXT: v_mov_b32_e32 v15, s272288; SI-NEXT: s_lshl_b32 m0, s4, 12289; SI-NEXT: v_movreld_b32_e32 v0, 02290; SI-NEXT: s_mov_b32 s2, -12291; SI-NEXT: v_movreld_b32_e32 v1, v162292; SI-NEXT: buffer_store_dwordx4 v[12:15], off, s[0:3], 0 offset:482293; SI-NEXT: buffer_store_dwordx4 v[8:11], off, s[0:3], 0 offset:322294; SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:162295; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 02296; SI-NEXT: s_endpgm2297;2298; VI-LABEL: dynamic_insertelement_v8f64:2299; VI: ; %bb.0:2300; VI-NEXT: s_load_dwordx16 s[12:27], s[8:9], 0x402301; VI-NEXT: s_load_dword s4, s[8:9], 0x802302; VI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x02303; VI-NEXT: v_mov_b32_e32 v16, 0x402000002304; VI-NEXT: s_mov_b32 s3, 0x1100f0002305; VI-NEXT: s_waitcnt lgkmcnt(0)2306; VI-NEXT: v_mov_b32_e32 v0, s122307; VI-NEXT: v_mov_b32_e32 v1, s132308; VI-NEXT: v_mov_b32_e32 v2, s142309; VI-NEXT: v_mov_b32_e32 v3, s152310; VI-NEXT: v_mov_b32_e32 v4, s162311; VI-NEXT: v_mov_b32_e32 v5, s172312; VI-NEXT: v_mov_b32_e32 v6, s182313; VI-NEXT: v_mov_b32_e32 v7, s192314; VI-NEXT: v_mov_b32_e32 v8, s202315; VI-NEXT: v_mov_b32_e32 v9, s212316; VI-NEXT: v_mov_b32_e32 v10, s222317; VI-NEXT: v_mov_b32_e32 v11, s232318; VI-NEXT: v_mov_b32_e32 v12, s242319; VI-NEXT: v_mov_b32_e32 v13, s252320; VI-NEXT: v_mov_b32_e32 v14, s262321; VI-NEXT: v_mov_b32_e32 v15, s272322; VI-NEXT: s_lshl_b32 m0, s4, 12323; VI-NEXT: v_movreld_b32_e32 v0, 02324; VI-NEXT: s_mov_b32 s2, -12325; VI-NEXT: v_movreld_b32_e32 v1, v162326; VI-NEXT: buffer_store_dwordx4 v[12:15], off, s[0:3], 0 offset:482327; VI-NEXT: buffer_store_dwordx4 v[8:11], off, s[0:3], 0 offset:322328; VI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:162329; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 02330; VI-NEXT: s_endpgm2331 %vecins = insertelement <8 x double> %a, double 8.0, i32 %b2332 store <8 x double> %vecins, ptr addrspace(1) %out, align 162333 ret void2334}2335 2336declare <4 x float> @llvm.amdgcn.image.gather4.lz.2d.v4f32.f32(i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #12337 2338attributes #0 = { nounwind }2339attributes #1 = { nounwind readnone }2340