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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 42; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=tahiti < %s | FileCheck -check-prefix=SI %s3; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=tonga < %s | FileCheck -check-prefix=VI %s4; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX900 %s5; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 < %s | FileCheck -check-prefix=GFX942 %s6; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 < %s | FileCheck -check-prefix=GFX1250 %s7 8define amdgpu_kernel void @s_insertelement_v2bf16_0(ptr addrspace(1) %out, ptr addrspace(4) %vec.ptr) #0 {9; SI-LABEL: s_insertelement_v2bf16_0:10; SI:       ; %bb.0:11; SI-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x012; SI-NEXT:    s_waitcnt lgkmcnt(0)13; SI-NEXT:    s_load_dword s4, s[2:3], 0x014; SI-NEXT:    s_mov_b32 s3, 0x100f00015; SI-NEXT:    s_mov_b32 s2, -116; SI-NEXT:    s_waitcnt lgkmcnt(0)17; SI-NEXT:    s_and_b32 s4, s4, 0xffff000018; SI-NEXT:    s_or_b32 s4, s4, 0x40a019; SI-NEXT:    v_mov_b32_e32 v0, s420; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 021; SI-NEXT:    s_endpgm22;23; VI-LABEL: s_insertelement_v2bf16_0:24; VI:       ; %bb.0:25; VI-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x026; VI-NEXT:    s_add_i32 s12, s12, s1727; VI-NEXT:    s_mov_b32 flat_scratch_lo, s1328; VI-NEXT:    s_lshr_b32 flat_scratch_hi, s12, 829; VI-NEXT:    s_waitcnt lgkmcnt(0)30; VI-NEXT:    s_load_dword s2, s[2:3], 0x031; VI-NEXT:    v_mov_b32_e32 v0, s032; VI-NEXT:    v_mov_b32_e32 v1, s133; VI-NEXT:    s_waitcnt lgkmcnt(0)34; VI-NEXT:    s_and_b32 s0, s2, 0xffff000035; VI-NEXT:    s_or_b32 s0, s0, 0x40a036; VI-NEXT:    v_mov_b32_e32 v2, s037; VI-NEXT:    flat_store_dword v[0:1], v238; VI-NEXT:    s_endpgm39;40; GFX900-LABEL: s_insertelement_v2bf16_0:41; GFX900:       ; %bb.0:42; GFX900-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x043; GFX900-NEXT:    v_mov_b32_e32 v0, 044; GFX900-NEXT:    s_waitcnt lgkmcnt(0)45; GFX900-NEXT:    s_load_dword s2, s[2:3], 0x046; GFX900-NEXT:    s_waitcnt lgkmcnt(0)47; GFX900-NEXT:    s_lshr_b32 s2, s2, 1648; GFX900-NEXT:    s_pack_ll_b32_b16 s2, 0x40a0, s249; GFX900-NEXT:    v_mov_b32_e32 v1, s250; GFX900-NEXT:    global_store_dword v0, v1, s[0:1]51; GFX900-NEXT:    s_endpgm52;53; GFX942-LABEL: s_insertelement_v2bf16_0:54; GFX942:       ; %bb.0:55; GFX942-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x056; GFX942-NEXT:    v_mov_b32_e32 v0, 057; GFX942-NEXT:    s_waitcnt lgkmcnt(0)58; GFX942-NEXT:    s_load_dword s2, s[2:3], 0x059; GFX942-NEXT:    s_waitcnt lgkmcnt(0)60; GFX942-NEXT:    s_lshr_b32 s2, s2, 1661; GFX942-NEXT:    s_pack_ll_b32_b16 s2, 0x40a0, s262; GFX942-NEXT:    v_mov_b32_e32 v1, s263; GFX942-NEXT:    global_store_dword v0, v1, s[0:1]64; GFX942-NEXT:    s_endpgm65;66; GFX1250-LABEL: s_insertelement_v2bf16_0:67; GFX1250:       ; %bb.0:68; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 169; GFX1250-NEXT:    s_load_b128 s[0:3], s[4:5], 0x070; GFX1250-NEXT:    s_wait_kmcnt 0x071; GFX1250-NEXT:    s_load_b32 s2, s[2:3], 0x072; GFX1250-NEXT:    s_wait_kmcnt 0x073; GFX1250-NEXT:    s_lshr_b32 s2, s2, 1674; GFX1250-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)75; GFX1250-NEXT:    s_pack_ll_b32_b16 s2, 0x40a0, s276; GFX1250-NEXT:    v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s277; GFX1250-NEXT:    global_store_b32 v0, v1, s[0:1]78; GFX1250-NEXT:    s_endpgm79  %vec = load <2 x bfloat>, ptr addrspace(4) %vec.ptr80  %vecins = insertelement <2 x bfloat> %vec, bfloat 5.000000e+00, i32 081  store <2 x bfloat> %vecins, ptr addrspace(1) %out82  ret void83}84 85define amdgpu_kernel void @s_insertelement_v2bf16_1(ptr addrspace(1) %out, ptr addrspace(4) %vec.ptr) #0 {86; SI-LABEL: s_insertelement_v2bf16_1:87; SI:       ; %bb.0:88; SI-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x089; SI-NEXT:    s_waitcnt lgkmcnt(0)90; SI-NEXT:    s_load_dword s4, s[2:3], 0x091; SI-NEXT:    s_mov_b32 s3, 0x100f00092; SI-NEXT:    s_mov_b32 s2, -193; SI-NEXT:    s_waitcnt lgkmcnt(0)94; SI-NEXT:    s_and_b32 s4, s4, 0xffff95; SI-NEXT:    s_or_b32 s4, s4, 0x40a0000096; SI-NEXT:    v_mov_b32_e32 v0, s497; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 098; SI-NEXT:    s_endpgm99;100; VI-LABEL: s_insertelement_v2bf16_1:101; VI:       ; %bb.0:102; VI-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x0103; VI-NEXT:    s_add_i32 s12, s12, s17104; VI-NEXT:    s_mov_b32 flat_scratch_lo, s13105; VI-NEXT:    s_lshr_b32 flat_scratch_hi, s12, 8106; VI-NEXT:    s_waitcnt lgkmcnt(0)107; VI-NEXT:    s_load_dword s2, s[2:3], 0x0108; VI-NEXT:    v_mov_b32_e32 v0, s0109; VI-NEXT:    v_mov_b32_e32 v1, s1110; VI-NEXT:    s_waitcnt lgkmcnt(0)111; VI-NEXT:    s_and_b32 s0, s2, 0xffff112; VI-NEXT:    s_or_b32 s0, s0, 0x40a00000113; VI-NEXT:    v_mov_b32_e32 v2, s0114; VI-NEXT:    flat_store_dword v[0:1], v2115; VI-NEXT:    s_endpgm116;117; GFX900-LABEL: s_insertelement_v2bf16_1:118; GFX900:       ; %bb.0:119; GFX900-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x0120; GFX900-NEXT:    v_mov_b32_e32 v0, 0121; GFX900-NEXT:    s_waitcnt lgkmcnt(0)122; GFX900-NEXT:    s_load_dword s2, s[2:3], 0x0123; GFX900-NEXT:    s_waitcnt lgkmcnt(0)124; GFX900-NEXT:    s_pack_ll_b32_b16 s2, s2, 0x40a0125; GFX900-NEXT:    v_mov_b32_e32 v1, s2126; GFX900-NEXT:    global_store_dword v0, v1, s[0:1]127; GFX900-NEXT:    s_endpgm128;129; GFX942-LABEL: s_insertelement_v2bf16_1:130; GFX942:       ; %bb.0:131; GFX942-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0132; GFX942-NEXT:    v_mov_b32_e32 v0, 0133; GFX942-NEXT:    s_waitcnt lgkmcnt(0)134; GFX942-NEXT:    s_load_dword s2, s[2:3], 0x0135; GFX942-NEXT:    s_waitcnt lgkmcnt(0)136; GFX942-NEXT:    s_pack_ll_b32_b16 s2, s2, 0x40a0137; GFX942-NEXT:    v_mov_b32_e32 v1, s2138; GFX942-NEXT:    global_store_dword v0, v1, s[0:1]139; GFX942-NEXT:    s_endpgm140;141; GFX1250-LABEL: s_insertelement_v2bf16_1:142; GFX1250:       ; %bb.0:143; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1144; GFX1250-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0145; GFX1250-NEXT:    s_wait_kmcnt 0x0146; GFX1250-NEXT:    s_load_b32 s2, s[2:3], 0x0147; GFX1250-NEXT:    s_wait_kmcnt 0x0148; GFX1250-NEXT:    s_pack_ll_b32_b16 s2, s2, 0x40a0149; GFX1250-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)150; GFX1250-NEXT:    v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2151; GFX1250-NEXT:    global_store_b32 v0, v1, s[0:1]152; GFX1250-NEXT:    s_endpgm153  %vec = load <2 x bfloat>, ptr addrspace(4) %vec.ptr154  %vecins = insertelement <2 x bfloat> %vec, bfloat 5.000000e+00, i32 1155  store <2 x bfloat> %vecins, ptr addrspace(1) %out156  ret void157}158 159define amdgpu_kernel void @v_insertelement_v2bf16_0(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {160; SI-LABEL: v_insertelement_v2bf16_0:161; SI:       ; %bb.0:162; SI-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x0163; SI-NEXT:    s_mov_b32 s7, 0x100f000164; SI-NEXT:    s_mov_b32 s6, 0165; SI-NEXT:    v_lshlrev_b32_e32 v0, 2, v0166; SI-NEXT:    v_mov_b32_e32 v1, 0167; SI-NEXT:    s_waitcnt lgkmcnt(0)168; SI-NEXT:    s_mov_b64 s[4:5], s[2:3]169; SI-NEXT:    buffer_load_dword v2, v[0:1], s[4:7], 0 addr64170; SI-NEXT:    s_mov_b64 s[2:3], s[6:7]171; SI-NEXT:    s_waitcnt vmcnt(0)172; SI-NEXT:    v_and_b32_e32 v2, 0xffff0000, v2173; SI-NEXT:    v_or_b32_e32 v2, 0x40a0, v2174; SI-NEXT:    buffer_store_dword v2, v[0:1], s[0:3], 0 addr64175; SI-NEXT:    s_endpgm176;177; VI-LABEL: v_insertelement_v2bf16_0:178; VI:       ; %bb.0:179; VI-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x0180; VI-NEXT:    v_lshlrev_b32_e32 v2, 2, v0181; VI-NEXT:    s_add_i32 s12, s12, s17182; VI-NEXT:    s_mov_b32 flat_scratch_lo, s13183; VI-NEXT:    s_lshr_b32 flat_scratch_hi, s12, 8184; VI-NEXT:    s_waitcnt lgkmcnt(0)185; VI-NEXT:    v_mov_b32_e32 v1, s3186; VI-NEXT:    v_add_u32_e32 v0, vcc, s2, v2187; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc188; VI-NEXT:    flat_load_dword v3, v[0:1]189; VI-NEXT:    v_mov_b32_e32 v1, s1190; VI-NEXT:    v_add_u32_e32 v0, vcc, s0, v2191; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc192; VI-NEXT:    s_waitcnt vmcnt(0)193; VI-NEXT:    v_and_b32_e32 v2, 0xffff0000, v3194; VI-NEXT:    v_or_b32_e32 v2, 0x40a0, v2195; VI-NEXT:    flat_store_dword v[0:1], v2196; VI-NEXT:    s_endpgm197;198; GFX900-LABEL: v_insertelement_v2bf16_0:199; GFX900:       ; %bb.0:200; GFX900-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x0201; GFX900-NEXT:    v_lshlrev_b32_e32 v0, 2, v0202; GFX900-NEXT:    v_mov_b32_e32 v2, 0x40a0203; GFX900-NEXT:    s_waitcnt lgkmcnt(0)204; GFX900-NEXT:    global_load_dword v1, v0, s[2:3]205; GFX900-NEXT:    s_mov_b32 s2, 0xffff206; GFX900-NEXT:    s_waitcnt vmcnt(0)207; GFX900-NEXT:    v_bfi_b32 v1, s2, v2, v1208; GFX900-NEXT:    global_store_dword v0, v1, s[0:1]209; GFX900-NEXT:    s_endpgm210;211; GFX942-LABEL: v_insertelement_v2bf16_0:212; GFX942:       ; %bb.0:213; GFX942-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0214; GFX942-NEXT:    v_and_b32_e32 v0, 0x3ff, v0215; GFX942-NEXT:    v_lshlrev_b32_e32 v0, 2, v0216; GFX942-NEXT:    v_mov_b32_e32 v2, 0x40a0217; GFX942-NEXT:    s_waitcnt lgkmcnt(0)218; GFX942-NEXT:    global_load_dword v1, v0, s[2:3]219; GFX942-NEXT:    s_mov_b32 s2, 0xffff220; GFX942-NEXT:    s_waitcnt vmcnt(0)221; GFX942-NEXT:    v_bfi_b32 v1, s2, v2, v1222; GFX942-NEXT:    global_store_dword v0, v1, s[0:1]223; GFX942-NEXT:    s_endpgm224;225; GFX1250-LABEL: v_insertelement_v2bf16_0:226; GFX1250:       ; %bb.0:227; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1228; GFX1250-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0229; GFX1250-NEXT:    v_and_b32_e32 v0, 0x3ff, v0230; GFX1250-NEXT:    s_wait_kmcnt 0x0231; GFX1250-NEXT:    global_load_b32 v1, v0, s[2:3] scale_offset232; GFX1250-NEXT:    s_wait_xcnt 0x0233; GFX1250-NEXT:    s_movk_i32 s2, 0x40a0234; GFX1250-NEXT:    s_wait_loadcnt 0x0235; GFX1250-NEXT:    v_bfi_b32 v1, 0xffff, s2, v1236; GFX1250-NEXT:    global_store_b32 v0, v1, s[0:1] scale_offset237; GFX1250-NEXT:    s_endpgm238  %tid = call i32 @llvm.amdgcn.workitem.id.x() #1239  %tid.ext = sext i32 %tid to i64240  %in.gep = getelementptr inbounds <2 x bfloat>, ptr addrspace(1) %in, i64 %tid.ext241  %out.gep = getelementptr inbounds <2 x bfloat>, ptr addrspace(1) %out, i64 %tid.ext242  %vec = load <2 x bfloat>, ptr addrspace(1) %in.gep243  %vecins = insertelement <2 x bfloat> %vec, bfloat 5.000000e+00, i32 0244  store <2 x bfloat> %vecins, ptr addrspace(1) %out.gep245  ret void246}247 248define amdgpu_kernel void @v_insertelement_v2bf16_0_inlineimm(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {249; SI-LABEL: v_insertelement_v2bf16_0_inlineimm:250; SI:       ; %bb.0:251; SI-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x0252; SI-NEXT:    s_mov_b32 s7, 0x100f000253; SI-NEXT:    s_mov_b32 s6, 0254; SI-NEXT:    v_lshlrev_b32_e32 v0, 2, v0255; SI-NEXT:    v_mov_b32_e32 v1, 0256; SI-NEXT:    s_waitcnt lgkmcnt(0)257; SI-NEXT:    s_mov_b64 s[4:5], s[2:3]258; SI-NEXT:    buffer_load_dword v2, v[0:1], s[4:7], 0 addr64259; SI-NEXT:    s_mov_b64 s[2:3], s[6:7]260; SI-NEXT:    s_waitcnt vmcnt(0)261; SI-NEXT:    v_and_b32_e32 v2, 0xffff0000, v2262; SI-NEXT:    v_or_b32_e32 v2, 53, v2263; SI-NEXT:    buffer_store_dword v2, v[0:1], s[0:3], 0 addr64264; SI-NEXT:    s_endpgm265;266; VI-LABEL: v_insertelement_v2bf16_0_inlineimm:267; VI:       ; %bb.0:268; VI-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x0269; VI-NEXT:    v_lshlrev_b32_e32 v2, 2, v0270; VI-NEXT:    s_add_i32 s12, s12, s17271; VI-NEXT:    s_mov_b32 flat_scratch_lo, s13272; VI-NEXT:    s_lshr_b32 flat_scratch_hi, s12, 8273; VI-NEXT:    s_waitcnt lgkmcnt(0)274; VI-NEXT:    v_mov_b32_e32 v1, s3275; VI-NEXT:    v_add_u32_e32 v0, vcc, s2, v2276; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc277; VI-NEXT:    flat_load_dword v3, v[0:1]278; VI-NEXT:    v_mov_b32_e32 v1, s1279; VI-NEXT:    v_add_u32_e32 v0, vcc, s0, v2280; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc281; VI-NEXT:    s_waitcnt vmcnt(0)282; VI-NEXT:    v_and_b32_e32 v2, 0xffff0000, v3283; VI-NEXT:    v_or_b32_e32 v2, 53, v2284; VI-NEXT:    flat_store_dword v[0:1], v2285; VI-NEXT:    s_endpgm286;287; GFX900-LABEL: v_insertelement_v2bf16_0_inlineimm:288; GFX900:       ; %bb.0:289; GFX900-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x0290; GFX900-NEXT:    v_lshlrev_b32_e32 v0, 2, v0291; GFX900-NEXT:    s_waitcnt lgkmcnt(0)292; GFX900-NEXT:    global_load_dword v1, v0, s[2:3]293; GFX900-NEXT:    s_mov_b32 s2, 0xffff294; GFX900-NEXT:    s_waitcnt vmcnt(0)295; GFX900-NEXT:    v_bfi_b32 v1, s2, 53, v1296; GFX900-NEXT:    global_store_dword v0, v1, s[0:1]297; GFX900-NEXT:    s_endpgm298;299; GFX942-LABEL: v_insertelement_v2bf16_0_inlineimm:300; GFX942:       ; %bb.0:301; GFX942-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0302; GFX942-NEXT:    v_and_b32_e32 v0, 0x3ff, v0303; GFX942-NEXT:    v_lshlrev_b32_e32 v0, 2, v0304; GFX942-NEXT:    s_waitcnt lgkmcnt(0)305; GFX942-NEXT:    global_load_dword v1, v0, s[2:3]306; GFX942-NEXT:    s_mov_b32 s2, 0xffff307; GFX942-NEXT:    s_waitcnt vmcnt(0)308; GFX942-NEXT:    v_bfi_b32 v1, s2, 53, v1309; GFX942-NEXT:    global_store_dword v0, v1, s[0:1]310; GFX942-NEXT:    s_endpgm311;312; GFX1250-LABEL: v_insertelement_v2bf16_0_inlineimm:313; GFX1250:       ; %bb.0:314; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1315; GFX1250-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0316; GFX1250-NEXT:    v_and_b32_e32 v0, 0x3ff, v0317; GFX1250-NEXT:    s_wait_kmcnt 0x0318; GFX1250-NEXT:    global_load_b32 v1, v0, s[2:3] scale_offset319; GFX1250-NEXT:    s_wait_loadcnt 0x0320; GFX1250-NEXT:    v_bfi_b32 v1, 0xffff, 53, v1321; GFX1250-NEXT:    global_store_b32 v0, v1, s[0:1] scale_offset322; GFX1250-NEXT:    s_endpgm323  %tid = call i32 @llvm.amdgcn.workitem.id.x() #1324  %tid.ext = sext i32 %tid to i64325  %in.gep = getelementptr inbounds <2 x bfloat>, ptr addrspace(1) %in, i64 %tid.ext326  %out.gep = getelementptr inbounds <2 x bfloat>, ptr addrspace(1) %out, i64 %tid.ext327  %vec = load <2 x bfloat>, ptr addrspace(1) %in.gep328  %vecins = insertelement <2 x bfloat> %vec, bfloat 0xR0035, i32 0329  store <2 x bfloat> %vecins, ptr addrspace(1) %out.gep330  ret void331}332 333define amdgpu_kernel void @v_insertelement_v2bf16_1(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {334; SI-LABEL: v_insertelement_v2bf16_1:335; SI:       ; %bb.0:336; SI-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x0337; SI-NEXT:    s_mov_b32 s7, 0x100f000338; SI-NEXT:    s_mov_b32 s6, 0339; SI-NEXT:    v_lshlrev_b32_e32 v0, 2, v0340; SI-NEXT:    v_mov_b32_e32 v1, 0341; SI-NEXT:    s_waitcnt lgkmcnt(0)342; SI-NEXT:    s_mov_b64 s[4:5], s[2:3]343; SI-NEXT:    buffer_load_dword v2, v[0:1], s[4:7], 0 addr64344; SI-NEXT:    s_mov_b64 s[2:3], s[6:7]345; SI-NEXT:    s_waitcnt vmcnt(0)346; SI-NEXT:    v_and_b32_e32 v2, 0xffff, v2347; SI-NEXT:    v_or_b32_e32 v2, 0x40a00000, v2348; SI-NEXT:    buffer_store_dword v2, v[0:1], s[0:3], 0 addr64349; SI-NEXT:    s_endpgm350;351; VI-LABEL: v_insertelement_v2bf16_1:352; VI:       ; %bb.0:353; VI-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x0354; VI-NEXT:    v_lshlrev_b32_e32 v2, 2, v0355; VI-NEXT:    s_add_i32 s12, s12, s17356; VI-NEXT:    s_mov_b32 flat_scratch_lo, s13357; VI-NEXT:    s_lshr_b32 flat_scratch_hi, s12, 8358; VI-NEXT:    s_waitcnt lgkmcnt(0)359; VI-NEXT:    v_mov_b32_e32 v1, s3360; VI-NEXT:    v_add_u32_e32 v0, vcc, s2, v2361; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc362; VI-NEXT:    flat_load_dword v3, v[0:1]363; VI-NEXT:    v_mov_b32_e32 v1, s1364; VI-NEXT:    v_add_u32_e32 v0, vcc, s0, v2365; VI-NEXT:    v_mov_b32_e32 v2, 0x40a00000366; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc367; VI-NEXT:    s_waitcnt vmcnt(0)368; VI-NEXT:    v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD369; VI-NEXT:    flat_store_dword v[0:1], v2370; VI-NEXT:    s_endpgm371;372; GFX900-LABEL: v_insertelement_v2bf16_1:373; GFX900:       ; %bb.0:374; GFX900-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x0375; GFX900-NEXT:    v_lshlrev_b32_e32 v0, 2, v0376; GFX900-NEXT:    v_mov_b32_e32 v2, 0x5040100377; GFX900-NEXT:    s_waitcnt lgkmcnt(0)378; GFX900-NEXT:    global_load_dword v1, v0, s[2:3]379; GFX900-NEXT:    s_movk_i32 s2, 0x40a0380; GFX900-NEXT:    s_waitcnt vmcnt(0)381; GFX900-NEXT:    v_perm_b32 v1, s2, v1, v2382; GFX900-NEXT:    global_store_dword v0, v1, s[0:1]383; GFX900-NEXT:    s_endpgm384;385; GFX942-LABEL: v_insertelement_v2bf16_1:386; GFX942:       ; %bb.0:387; GFX942-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0388; GFX942-NEXT:    v_and_b32_e32 v0, 0x3ff, v0389; GFX942-NEXT:    v_lshlrev_b32_e32 v0, 2, v0390; GFX942-NEXT:    v_mov_b32_e32 v2, 0x5040100391; GFX942-NEXT:    s_waitcnt lgkmcnt(0)392; GFX942-NEXT:    global_load_dword v1, v0, s[2:3]393; GFX942-NEXT:    s_movk_i32 s2, 0x40a0394; GFX942-NEXT:    s_waitcnt vmcnt(0)395; GFX942-NEXT:    v_perm_b32 v1, s2, v1, v2396; GFX942-NEXT:    global_store_dword v0, v1, s[0:1]397; GFX942-NEXT:    s_endpgm398;399; GFX1250-LABEL: v_insertelement_v2bf16_1:400; GFX1250:       ; %bb.0:401; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1402; GFX1250-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0403; GFX1250-NEXT:    v_and_b32_e32 v0, 0x3ff, v0404; GFX1250-NEXT:    s_wait_kmcnt 0x0405; GFX1250-NEXT:    global_load_b32 v1, v0, s[2:3] scale_offset406; GFX1250-NEXT:    s_wait_xcnt 0x0407; GFX1250-NEXT:    s_movk_i32 s2, 0x40a0408; GFX1250-NEXT:    s_wait_loadcnt 0x0409; GFX1250-NEXT:    v_perm_b32 v1, s2, v1, 0x5040100410; GFX1250-NEXT:    global_store_b32 v0, v1, s[0:1] scale_offset411; GFX1250-NEXT:    s_endpgm412  %tid = call i32 @llvm.amdgcn.workitem.id.x() #1413  %tid.ext = sext i32 %tid to i64414  %in.gep = getelementptr inbounds <2 x bfloat>, ptr addrspace(1) %in, i64 %tid.ext415  %out.gep = getelementptr inbounds <2 x bfloat>, ptr addrspace(1) %out, i64 %tid.ext416  %vec = load <2 x bfloat>, ptr addrspace(1) %in.gep417  %vecins = insertelement <2 x bfloat> %vec, bfloat 5.000000e+00, i32 1418  store <2 x bfloat> %vecins, ptr addrspace(1) %out.gep419  ret void420}421 422define amdgpu_kernel void @v_insertelement_v2bf16_1_inlineimm(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {423; SI-LABEL: v_insertelement_v2bf16_1_inlineimm:424; SI:       ; %bb.0:425; SI-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x0426; SI-NEXT:    s_mov_b32 s7, 0x100f000427; SI-NEXT:    s_mov_b32 s6, 0428; SI-NEXT:    v_lshlrev_b32_e32 v0, 2, v0429; SI-NEXT:    v_mov_b32_e32 v1, 0430; SI-NEXT:    s_waitcnt lgkmcnt(0)431; SI-NEXT:    s_mov_b64 s[4:5], s[2:3]432; SI-NEXT:    buffer_load_dword v2, v[0:1], s[4:7], 0 addr64433; SI-NEXT:    s_mov_b64 s[2:3], s[6:7]434; SI-NEXT:    s_waitcnt vmcnt(0)435; SI-NEXT:    v_and_b32_e32 v2, 0xffff, v2436; SI-NEXT:    v_or_b32_e32 v2, 0x230000, v2437; SI-NEXT:    buffer_store_dword v2, v[0:1], s[0:3], 0 addr64438; SI-NEXT:    s_endpgm439;440; VI-LABEL: v_insertelement_v2bf16_1_inlineimm:441; VI:       ; %bb.0:442; VI-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x0443; VI-NEXT:    v_lshlrev_b32_e32 v2, 2, v0444; VI-NEXT:    s_add_i32 s12, s12, s17445; VI-NEXT:    s_mov_b32 flat_scratch_lo, s13446; VI-NEXT:    s_lshr_b32 flat_scratch_hi, s12, 8447; VI-NEXT:    s_waitcnt lgkmcnt(0)448; VI-NEXT:    v_mov_b32_e32 v1, s3449; VI-NEXT:    v_add_u32_e32 v0, vcc, s2, v2450; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc451; VI-NEXT:    flat_load_dword v3, v[0:1]452; VI-NEXT:    v_mov_b32_e32 v1, s1453; VI-NEXT:    v_add_u32_e32 v0, vcc, s0, v2454; VI-NEXT:    v_mov_b32_e32 v2, 0x230000455; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc456; VI-NEXT:    s_waitcnt vmcnt(0)457; VI-NEXT:    v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD458; VI-NEXT:    flat_store_dword v[0:1], v2459; VI-NEXT:    s_endpgm460;461; GFX900-LABEL: v_insertelement_v2bf16_1_inlineimm:462; GFX900:       ; %bb.0:463; GFX900-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x0464; GFX900-NEXT:    v_lshlrev_b32_e32 v0, 2, v0465; GFX900-NEXT:    v_mov_b32_e32 v2, 0x5040100466; GFX900-NEXT:    s_waitcnt lgkmcnt(0)467; GFX900-NEXT:    global_load_dword v1, v0, s[2:3]468; GFX900-NEXT:    s_waitcnt vmcnt(0)469; GFX900-NEXT:    v_perm_b32 v1, 35, v1, v2470; GFX900-NEXT:    global_store_dword v0, v1, s[0:1]471; GFX900-NEXT:    s_endpgm472;473; GFX942-LABEL: v_insertelement_v2bf16_1_inlineimm:474; GFX942:       ; %bb.0:475; GFX942-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0476; GFX942-NEXT:    v_and_b32_e32 v0, 0x3ff, v0477; GFX942-NEXT:    v_lshlrev_b32_e32 v0, 2, v0478; GFX942-NEXT:    v_mov_b32_e32 v2, 0x5040100479; GFX942-NEXT:    s_waitcnt lgkmcnt(0)480; GFX942-NEXT:    global_load_dword v1, v0, s[2:3]481; GFX942-NEXT:    s_waitcnt vmcnt(0)482; GFX942-NEXT:    v_perm_b32 v1, 35, v1, v2483; GFX942-NEXT:    global_store_dword v0, v1, s[0:1]484; GFX942-NEXT:    s_endpgm485;486; GFX1250-LABEL: v_insertelement_v2bf16_1_inlineimm:487; GFX1250:       ; %bb.0:488; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1489; GFX1250-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0490; GFX1250-NEXT:    v_and_b32_e32 v0, 0x3ff, v0491; GFX1250-NEXT:    s_wait_kmcnt 0x0492; GFX1250-NEXT:    global_load_b32 v1, v0, s[2:3] scale_offset493; GFX1250-NEXT:    s_wait_loadcnt 0x0494; GFX1250-NEXT:    v_perm_b32 v1, 35, v1, 0x5040100495; GFX1250-NEXT:    global_store_b32 v0, v1, s[0:1] scale_offset496; GFX1250-NEXT:    s_endpgm497  %tid = call i32 @llvm.amdgcn.workitem.id.x() #1498  %tid.ext = sext i32 %tid to i64499  %in.gep = getelementptr inbounds <2 x bfloat>, ptr addrspace(1) %in, i64 %tid.ext500  %out.gep = getelementptr inbounds <2 x bfloat>, ptr addrspace(1) %out, i64 %tid.ext501  %vec = load <2 x bfloat>, ptr addrspace(1) %in.gep502  %vecins = insertelement <2 x bfloat> %vec, bfloat 0xR0023, i32 1503  store <2 x bfloat> %vecins, ptr addrspace(1) %out.gep504  ret void505}506 507define amdgpu_kernel void @v_insertelement_v2bf16_dynamic_vgpr(ptr addrspace(1) %out, ptr addrspace(1) %in, ptr addrspace(1) %idx.ptr) #0 {508; SI-LABEL: v_insertelement_v2bf16_dynamic_vgpr:509; SI:       ; %bb.0:510; SI-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x0511; SI-NEXT:    s_load_dwordx2 s[4:5], s[8:9], 0x4512; SI-NEXT:    s_mov_b32 s11, 0x100f000513; SI-NEXT:    s_mov_b32 s10, 0514; SI-NEXT:    v_lshlrev_b32_e32 v0, 2, v0515; SI-NEXT:    v_mov_b32_e32 v1, 0516; SI-NEXT:    s_mov_b64 s[6:7], s[10:11]517; SI-NEXT:    s_waitcnt lgkmcnt(0)518; SI-NEXT:    buffer_load_dword v2, v[0:1], s[4:7], 0 addr64519; SI-NEXT:    s_mov_b64 s[8:9], s[2:3]520; SI-NEXT:    buffer_load_dword v3, v[0:1], s[8:11], 0 addr64521; SI-NEXT:    s_mov_b32 s4, 0x12341234522; SI-NEXT:    s_mov_b64 s[2:3], s[10:11]523; SI-NEXT:    s_waitcnt vmcnt(1)524; SI-NEXT:    v_lshlrev_b32_e32 v2, 4, v2525; SI-NEXT:    v_lshl_b32_e32 v2, 0xffff, v2526; SI-NEXT:    s_waitcnt vmcnt(0)527; SI-NEXT:    v_bfi_b32 v2, v2, s4, v3528; SI-NEXT:    buffer_store_dword v2, v[0:1], s[0:3], 0 addr64529; SI-NEXT:    s_endpgm530;531; VI-LABEL: v_insertelement_v2bf16_dynamic_vgpr:532; VI:       ; %bb.0:533; VI-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x0534; VI-NEXT:    s_load_dwordx2 s[4:5], s[8:9], 0x10535; VI-NEXT:    v_lshlrev_b32_e32 v2, 2, v0536; VI-NEXT:    s_add_i32 s12, s12, s17537; VI-NEXT:    s_mov_b32 flat_scratch_lo, s13538; VI-NEXT:    s_lshr_b32 flat_scratch_hi, s12, 8539; VI-NEXT:    s_waitcnt lgkmcnt(0)540; VI-NEXT:    v_mov_b32_e32 v1, s5541; VI-NEXT:    v_add_u32_e32 v0, vcc, s4, v2542; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc543; VI-NEXT:    v_mov_b32_e32 v3, s3544; VI-NEXT:    flat_load_dword v4, v[0:1]545; VI-NEXT:    v_add_u32_e32 v0, vcc, s2, v2546; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v3, vcc547; VI-NEXT:    flat_load_dword v3, v[0:1]548; VI-NEXT:    s_mov_b32 s2, 0xffff549; VI-NEXT:    v_add_u32_e32 v0, vcc, s0, v2550; VI-NEXT:    v_mov_b32_e32 v1, s1551; VI-NEXT:    s_mov_b32 s0, 0x12341234552; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc553; VI-NEXT:    s_waitcnt vmcnt(1)554; VI-NEXT:    v_lshlrev_b32_e32 v2, 4, v4555; VI-NEXT:    v_lshlrev_b32_e64 v2, v2, s2556; VI-NEXT:    s_waitcnt vmcnt(0)557; VI-NEXT:    v_bfi_b32 v2, v2, s0, v3558; VI-NEXT:    flat_store_dword v[0:1], v2559; VI-NEXT:    s_endpgm560;561; GFX900-LABEL: v_insertelement_v2bf16_dynamic_vgpr:562; GFX900:       ; %bb.0:563; GFX900-NEXT:    s_load_dwordx2 s[4:5], s[8:9], 0x10564; GFX900-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x0565; GFX900-NEXT:    v_lshlrev_b32_e32 v0, 2, v0566; GFX900-NEXT:    s_waitcnt lgkmcnt(0)567; GFX900-NEXT:    global_load_dword v1, v0, s[4:5]568; GFX900-NEXT:    global_load_dword v2, v0, s[2:3]569; GFX900-NEXT:    s_mov_b32 s2, 0xffff570; GFX900-NEXT:    s_waitcnt vmcnt(1)571; GFX900-NEXT:    v_lshlrev_b32_e32 v1, 4, v1572; GFX900-NEXT:    v_lshlrev_b32_e64 v1, v1, s2573; GFX900-NEXT:    s_mov_b32 s2, 0x12341234574; GFX900-NEXT:    s_waitcnt vmcnt(0)575; GFX900-NEXT:    v_bfi_b32 v1, v1, s2, v2576; GFX900-NEXT:    global_store_dword v0, v1, s[0:1]577; GFX900-NEXT:    s_endpgm578;579; GFX942-LABEL: v_insertelement_v2bf16_dynamic_vgpr:580; GFX942:       ; %bb.0:581; GFX942-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x10582; GFX942-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0583; GFX942-NEXT:    v_and_b32_e32 v0, 0x3ff, v0584; GFX942-NEXT:    v_lshlrev_b32_e32 v0, 2, v0585; GFX942-NEXT:    s_waitcnt lgkmcnt(0)586; GFX942-NEXT:    global_load_dword v1, v0, s[6:7]587; GFX942-NEXT:    global_load_dword v2, v0, s[2:3]588; GFX942-NEXT:    s_mov_b32 s2, 0xffff589; GFX942-NEXT:    s_waitcnt vmcnt(1)590; GFX942-NEXT:    v_lshlrev_b32_e32 v1, 4, v1591; GFX942-NEXT:    v_lshlrev_b32_e64 v1, v1, s2592; GFX942-NEXT:    s_mov_b32 s2, 0x12341234593; GFX942-NEXT:    s_waitcnt vmcnt(0)594; GFX942-NEXT:    v_bfi_b32 v1, v1, s2, v2595; GFX942-NEXT:    global_store_dword v0, v1, s[0:1]596; GFX942-NEXT:    s_endpgm597;598; GFX1250-LABEL: v_insertelement_v2bf16_dynamic_vgpr:599; GFX1250:       ; %bb.0:600; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1601; GFX1250-NEXT:    s_clause 0x1602; GFX1250-NEXT:    s_load_b64 s[6:7], s[4:5], 0x10603; GFX1250-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0604; GFX1250-NEXT:    v_and_b32_e32 v0, 0x3ff, v0605; GFX1250-NEXT:    s_wait_kmcnt 0x0606; GFX1250-NEXT:    s_clause 0x1607; GFX1250-NEXT:    global_load_b32 v1, v0, s[6:7] scale_offset608; GFX1250-NEXT:    global_load_b32 v2, v0, s[2:3] scale_offset609; GFX1250-NEXT:    s_wait_loadcnt 0x1610; GFX1250-NEXT:    v_lshlrev_b32_e32 v1, 4, v1611; GFX1250-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)612; GFX1250-NEXT:    v_lshlrev_b32_e64 v1, v1, 0xffff613; GFX1250-NEXT:    s_wait_loadcnt 0x0614; GFX1250-NEXT:    v_bitop3_b32 v1, 0x12341234, v2, v1 bitop3:0xe4615; GFX1250-NEXT:    global_store_b32 v0, v1, s[0:1] scale_offset616; GFX1250-NEXT:    s_endpgm617  %tid = call i32 @llvm.amdgcn.workitem.id.x() #1618  %tid.ext = sext i32 %tid to i64619  %in.gep = getelementptr inbounds <2 x bfloat>, ptr addrspace(1) %in, i64 %tid.ext620  %idx.gep = getelementptr inbounds i32, ptr addrspace(1) %idx.ptr, i64 %tid.ext621  %out.gep = getelementptr inbounds <2 x bfloat>, ptr addrspace(1) %out, i64 %tid.ext622  %idx = load i32, ptr addrspace(1) %idx.gep623  %vec = load <2 x bfloat>, ptr addrspace(1) %in.gep624  %vecins = insertelement <2 x bfloat> %vec, bfloat 0xR1234, i32 %idx625  store <2 x bfloat> %vecins, ptr addrspace(1) %out.gep626  ret void627}628 629define amdgpu_kernel void @v_insertelement_v4bf16_0(ptr addrspace(1) %out, ptr addrspace(1) %in, [8 x i32], i32 %val) #0 {630; SI-LABEL: v_insertelement_v4bf16_0:631; SI:       ; %bb.0:632; SI-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x0633; SI-NEXT:    s_mov_b32 s7, 0x100f000634; SI-NEXT:    s_mov_b32 s6, 0635; SI-NEXT:    v_lshlrev_b32_e32 v0, 3, v0636; SI-NEXT:    v_mov_b32_e32 v1, 0637; SI-NEXT:    s_waitcnt lgkmcnt(0)638; SI-NEXT:    s_mov_b64 s[4:5], s[2:3]639; SI-NEXT:    buffer_load_dwordx2 v[2:3], v[0:1], s[4:7], 0 addr64640; SI-NEXT:    s_load_dword s8, s[8:9], 0xc641; SI-NEXT:    s_mov_b32 s4, 0xffff642; SI-NEXT:    s_mov_b64 s[2:3], s[6:7]643; SI-NEXT:    s_waitcnt lgkmcnt(0)644; SI-NEXT:    v_mov_b32_e32 v4, s8645; SI-NEXT:    s_waitcnt vmcnt(0)646; SI-NEXT:    v_bfi_b32 v2, s4, v4, v2647; SI-NEXT:    buffer_store_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64648; SI-NEXT:    s_endpgm649;650; VI-LABEL: v_insertelement_v4bf16_0:651; VI:       ; %bb.0:652; VI-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x0653; VI-NEXT:    s_load_dword s4, s[8:9], 0x30654; VI-NEXT:    v_lshlrev_b32_e32 v2, 3, v0655; VI-NEXT:    s_add_i32 s12, s12, s17656; VI-NEXT:    s_mov_b32 flat_scratch_lo, s13657; VI-NEXT:    s_waitcnt lgkmcnt(0)658; VI-NEXT:    v_mov_b32_e32 v1, s3659; VI-NEXT:    v_add_u32_e32 v0, vcc, s2, v2660; VI-NEXT:    s_lshr_b32 flat_scratch_hi, s12, 8661; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc662; VI-NEXT:    flat_load_dwordx2 v[0:1], v[0:1]663; VI-NEXT:    v_mov_b32_e32 v3, s1664; VI-NEXT:    v_add_u32_e32 v2, vcc, s0, v2665; VI-NEXT:    v_mov_b32_e32 v4, 0x3020504666; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc667; VI-NEXT:    s_waitcnt vmcnt(0)668; VI-NEXT:    v_perm_b32 v0, s4, v0, v4669; VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]670; VI-NEXT:    s_endpgm671;672; GFX900-LABEL: v_insertelement_v4bf16_0:673; GFX900:       ; %bb.0:674; GFX900-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x0675; GFX900-NEXT:    s_load_dword s4, s[8:9], 0x30676; GFX900-NEXT:    v_lshlrev_b32_e32 v2, 3, v0677; GFX900-NEXT:    s_waitcnt lgkmcnt(0)678; GFX900-NEXT:    global_load_dwordx2 v[0:1], v2, s[2:3]679; GFX900-NEXT:    s_mov_b32 s2, 0xffff680; GFX900-NEXT:    v_mov_b32_e32 v3, s4681; GFX900-NEXT:    s_waitcnt vmcnt(0)682; GFX900-NEXT:    v_bfi_b32 v0, s2, v3, v0683; GFX900-NEXT:    global_store_dwordx2 v2, v[0:1], s[0:1]684; GFX900-NEXT:    s_endpgm685;686; GFX942-LABEL: v_insertelement_v4bf16_0:687; GFX942:       ; %bb.0:688; GFX942-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0689; GFX942-NEXT:    s_load_dword s6, s[4:5], 0x30690; GFX942-NEXT:    v_and_b32_e32 v0, 0x3ff, v0691; GFX942-NEXT:    v_lshlrev_b32_e32 v2, 3, v0692; GFX942-NEXT:    s_waitcnt lgkmcnt(0)693; GFX942-NEXT:    global_load_dwordx2 v[0:1], v2, s[2:3]694; GFX942-NEXT:    s_mov_b32 s2, 0xffff695; GFX942-NEXT:    v_mov_b32_e32 v3, s6696; GFX942-NEXT:    s_waitcnt vmcnt(0)697; GFX942-NEXT:    v_bfi_b32 v0, s2, v3, v0698; GFX942-NEXT:    global_store_dwordx2 v2, v[0:1], s[0:1]699; GFX942-NEXT:    s_endpgm700;701; GFX1250-LABEL: v_insertelement_v4bf16_0:702; GFX1250:       ; %bb.0:703; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1704; GFX1250-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0705; GFX1250-NEXT:    v_and_b32_e32 v2, 0x3ff, v0706; GFX1250-NEXT:    s_wait_xcnt 0x0707; GFX1250-NEXT:    s_load_b32 s4, s[4:5], 0x30708; GFX1250-NEXT:    s_wait_kmcnt 0x0709; GFX1250-NEXT:    global_load_b64 v[0:1], v2, s[2:3] scale_offset710; GFX1250-NEXT:    s_wait_loadcnt 0x0711; GFX1250-NEXT:    v_bfi_b32 v0, 0xffff, s4, v0712; GFX1250-NEXT:    global_store_b64 v2, v[0:1], s[0:1] scale_offset713; GFX1250-NEXT:    s_endpgm714  %tid = call i32 @llvm.amdgcn.workitem.id.x() #1715  %tid.ext = sext i32 %tid to i64716  %in.gep = getelementptr inbounds <4 x bfloat>, ptr addrspace(1) %in, i64 %tid.ext717  %out.gep = getelementptr inbounds <4 x bfloat>, ptr addrspace(1) %out, i64 %tid.ext718  %vec = load <4 x bfloat>, ptr addrspace(1) %in.gep719  %val.trunc = trunc i32 %val to i16720  %val.cvt = bitcast i16 %val.trunc to bfloat721  %vecins = insertelement <4 x bfloat> %vec, bfloat %val.cvt, i32 0722  store <4 x bfloat> %vecins, ptr addrspace(1) %out.gep723  ret void724}725 726define amdgpu_kernel void @v_insertelement_v4bf16_1(ptr addrspace(1) %out, ptr addrspace(1) %in, i32 %val) #0 {727; SI-LABEL: v_insertelement_v4bf16_1:728; SI:       ; %bb.0:729; SI-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x0730; SI-NEXT:    s_mov_b32 s7, 0x100f000731; SI-NEXT:    s_mov_b32 s6, 0732; SI-NEXT:    v_lshlrev_b32_e32 v0, 3, v0733; SI-NEXT:    v_mov_b32_e32 v1, 0734; SI-NEXT:    s_waitcnt lgkmcnt(0)735; SI-NEXT:    s_mov_b64 s[4:5], s[2:3]736; SI-NEXT:    buffer_load_dwordx2 v[2:3], v[0:1], s[4:7], 0 addr64737; SI-NEXT:    s_load_dword s8, s[8:9], 0x4738; SI-NEXT:    s_mov_b64 s[2:3], s[6:7]739; SI-NEXT:    s_waitcnt lgkmcnt(0)740; SI-NEXT:    s_lshl_b32 s4, s8, 16741; SI-NEXT:    s_waitcnt vmcnt(0)742; SI-NEXT:    v_and_b32_e32 v2, 0xffff, v2743; SI-NEXT:    v_or_b32_e32 v2, s4, v2744; SI-NEXT:    buffer_store_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64745; SI-NEXT:    s_endpgm746;747; VI-LABEL: v_insertelement_v4bf16_1:748; VI:       ; %bb.0:749; VI-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x0750; VI-NEXT:    s_load_dword s4, s[8:9], 0x10751; VI-NEXT:    v_lshlrev_b32_e32 v2, 3, v0752; VI-NEXT:    s_add_i32 s12, s12, s17753; VI-NEXT:    s_mov_b32 flat_scratch_lo, s13754; VI-NEXT:    s_waitcnt lgkmcnt(0)755; VI-NEXT:    v_mov_b32_e32 v1, s3756; VI-NEXT:    v_add_u32_e32 v0, vcc, s2, v2757; VI-NEXT:    s_lshr_b32 flat_scratch_hi, s12, 8758; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc759; VI-NEXT:    flat_load_dwordx2 v[0:1], v[0:1]760; VI-NEXT:    v_mov_b32_e32 v3, s1761; VI-NEXT:    v_add_u32_e32 v2, vcc, s0, v2762; VI-NEXT:    v_mov_b32_e32 v4, 0x1000504763; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc764; VI-NEXT:    s_waitcnt vmcnt(0)765; VI-NEXT:    v_perm_b32 v0, v0, s4, v4766; VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]767; VI-NEXT:    s_endpgm768;769; GFX900-LABEL: v_insertelement_v4bf16_1:770; GFX900:       ; %bb.0:771; GFX900-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x0772; GFX900-NEXT:    s_load_dword s4, s[8:9], 0x10773; GFX900-NEXT:    v_lshlrev_b32_e32 v2, 3, v0774; GFX900-NEXT:    v_mov_b32_e32 v3, 0x5040100775; GFX900-NEXT:    s_waitcnt lgkmcnt(0)776; GFX900-NEXT:    global_load_dwordx2 v[0:1], v2, s[2:3]777; GFX900-NEXT:    s_waitcnt vmcnt(0)778; GFX900-NEXT:    v_perm_b32 v0, s4, v0, v3779; GFX900-NEXT:    global_store_dwordx2 v2, v[0:1], s[0:1]780; GFX900-NEXT:    s_endpgm781;782; GFX942-LABEL: v_insertelement_v4bf16_1:783; GFX942:       ; %bb.0:784; GFX942-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0785; GFX942-NEXT:    s_load_dword s6, s[4:5], 0x10786; GFX942-NEXT:    v_and_b32_e32 v0, 0x3ff, v0787; GFX942-NEXT:    v_lshlrev_b32_e32 v2, 3, v0788; GFX942-NEXT:    v_mov_b32_e32 v3, 0x5040100789; GFX942-NEXT:    s_waitcnt lgkmcnt(0)790; GFX942-NEXT:    global_load_dwordx2 v[0:1], v2, s[2:3]791; GFX942-NEXT:    s_waitcnt vmcnt(0)792; GFX942-NEXT:    v_perm_b32 v0, s6, v0, v3793; GFX942-NEXT:    global_store_dwordx2 v2, v[0:1], s[0:1]794; GFX942-NEXT:    s_endpgm795;796; GFX1250-LABEL: v_insertelement_v4bf16_1:797; GFX1250:       ; %bb.0:798; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1799; GFX1250-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0800; GFX1250-NEXT:    v_and_b32_e32 v2, 0x3ff, v0801; GFX1250-NEXT:    s_wait_xcnt 0x0802; GFX1250-NEXT:    s_load_b32 s4, s[4:5], 0x10803; GFX1250-NEXT:    s_wait_kmcnt 0x0804; GFX1250-NEXT:    global_load_b64 v[0:1], v2, s[2:3] scale_offset805; GFX1250-NEXT:    s_wait_loadcnt 0x0806; GFX1250-NEXT:    v_perm_b32 v0, s4, v0, 0x5040100807; GFX1250-NEXT:    global_store_b64 v2, v[0:1], s[0:1] scale_offset808; GFX1250-NEXT:    s_endpgm809  %tid = call i32 @llvm.amdgcn.workitem.id.x() #1810  %tid.ext = sext i32 %tid to i64811  %in.gep = getelementptr inbounds <4 x bfloat>, ptr addrspace(1) %in, i64 %tid.ext812  %out.gep = getelementptr inbounds <4 x bfloat>, ptr addrspace(1) %out, i64 %tid.ext813  %vec = load <4 x bfloat>, ptr addrspace(1) %in.gep814  %val.trunc = trunc i32 %val to i16815  %val.cvt = bitcast i16 %val.trunc to bfloat816  %vecins = insertelement <4 x bfloat> %vec, bfloat %val.cvt, i32 1817  store <4 x bfloat> %vecins, ptr addrspace(1) %out.gep818  ret void819}820 821define amdgpu_kernel void @v_insertelement_v4bf16_2(ptr addrspace(1) %out, ptr addrspace(1) %in, [8 x i32], i32 %val) #0 {822; SI-LABEL: v_insertelement_v4bf16_2:823; SI:       ; %bb.0:824; SI-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x0825; SI-NEXT:    s_mov_b32 s7, 0x100f000826; SI-NEXT:    s_mov_b32 s6, 0827; SI-NEXT:    v_lshlrev_b32_e32 v0, 3, v0828; SI-NEXT:    v_mov_b32_e32 v1, 0829; SI-NEXT:    s_waitcnt lgkmcnt(0)830; SI-NEXT:    s_mov_b64 s[4:5], s[2:3]831; SI-NEXT:    buffer_load_dwordx2 v[2:3], v[0:1], s[4:7], 0 addr64832; SI-NEXT:    s_load_dword s8, s[8:9], 0xc833; SI-NEXT:    s_mov_b32 s4, 0xffff834; SI-NEXT:    s_mov_b64 s[2:3], s[6:7]835; SI-NEXT:    s_waitcnt lgkmcnt(0)836; SI-NEXT:    v_mov_b32_e32 v4, s8837; SI-NEXT:    s_waitcnt vmcnt(0)838; SI-NEXT:    v_bfi_b32 v3, s4, v4, v3839; SI-NEXT:    buffer_store_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64840; SI-NEXT:    s_endpgm841;842; VI-LABEL: v_insertelement_v4bf16_2:843; VI:       ; %bb.0:844; VI-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x0845; VI-NEXT:    s_load_dword s4, s[8:9], 0x30846; VI-NEXT:    v_lshlrev_b32_e32 v2, 3, v0847; VI-NEXT:    s_add_i32 s12, s12, s17848; VI-NEXT:    s_mov_b32 flat_scratch_lo, s13849; VI-NEXT:    s_waitcnt lgkmcnt(0)850; VI-NEXT:    v_mov_b32_e32 v1, s3851; VI-NEXT:    v_add_u32_e32 v0, vcc, s2, v2852; VI-NEXT:    s_lshr_b32 flat_scratch_hi, s12, 8853; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc854; VI-NEXT:    flat_load_dwordx2 v[0:1], v[0:1]855; VI-NEXT:    v_mov_b32_e32 v3, s1856; VI-NEXT:    v_add_u32_e32 v2, vcc, s0, v2857; VI-NEXT:    v_mov_b32_e32 v4, 0x3020504858; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc859; VI-NEXT:    s_waitcnt vmcnt(0)860; VI-NEXT:    v_perm_b32 v1, s4, v1, v4861; VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]862; VI-NEXT:    s_endpgm863;864; GFX900-LABEL: v_insertelement_v4bf16_2:865; GFX900:       ; %bb.0:866; GFX900-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x0867; GFX900-NEXT:    s_load_dword s4, s[8:9], 0x30868; GFX900-NEXT:    v_lshlrev_b32_e32 v2, 3, v0869; GFX900-NEXT:    s_waitcnt lgkmcnt(0)870; GFX900-NEXT:    global_load_dwordx2 v[0:1], v2, s[2:3]871; GFX900-NEXT:    s_mov_b32 s2, 0xffff872; GFX900-NEXT:    v_mov_b32_e32 v3, s4873; GFX900-NEXT:    s_waitcnt vmcnt(0)874; GFX900-NEXT:    v_bfi_b32 v1, s2, v3, v1875; GFX900-NEXT:    global_store_dwordx2 v2, v[0:1], s[0:1]876; GFX900-NEXT:    s_endpgm877;878; GFX942-LABEL: v_insertelement_v4bf16_2:879; GFX942:       ; %bb.0:880; GFX942-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0881; GFX942-NEXT:    s_load_dword s6, s[4:5], 0x30882; GFX942-NEXT:    v_and_b32_e32 v0, 0x3ff, v0883; GFX942-NEXT:    v_lshlrev_b32_e32 v2, 3, v0884; GFX942-NEXT:    s_waitcnt lgkmcnt(0)885; GFX942-NEXT:    global_load_dwordx2 v[0:1], v2, s[2:3]886; GFX942-NEXT:    s_mov_b32 s2, 0xffff887; GFX942-NEXT:    v_mov_b32_e32 v3, s6888; GFX942-NEXT:    s_waitcnt vmcnt(0)889; GFX942-NEXT:    v_bfi_b32 v1, s2, v3, v1890; GFX942-NEXT:    global_store_dwordx2 v2, v[0:1], s[0:1]891; GFX942-NEXT:    s_endpgm892;893; GFX1250-LABEL: v_insertelement_v4bf16_2:894; GFX1250:       ; %bb.0:895; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1896; GFX1250-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0897; GFX1250-NEXT:    v_and_b32_e32 v2, 0x3ff, v0898; GFX1250-NEXT:    s_wait_xcnt 0x0899; GFX1250-NEXT:    s_load_b32 s4, s[4:5], 0x30900; GFX1250-NEXT:    s_wait_kmcnt 0x0901; GFX1250-NEXT:    global_load_b64 v[0:1], v2, s[2:3] scale_offset902; GFX1250-NEXT:    s_wait_loadcnt 0x0903; GFX1250-NEXT:    v_bfi_b32 v1, 0xffff, s4, v1904; GFX1250-NEXT:    global_store_b64 v2, v[0:1], s[0:1] scale_offset905; GFX1250-NEXT:    s_endpgm906  %tid = call i32 @llvm.amdgcn.workitem.id.x() #1907  %tid.ext = sext i32 %tid to i64908  %in.gep = getelementptr inbounds <4 x bfloat>, ptr addrspace(1) %in, i64 %tid.ext909  %out.gep = getelementptr inbounds <4 x bfloat>, ptr addrspace(1) %out, i64 %tid.ext910  %vec = load <4 x bfloat>, ptr addrspace(1) %in.gep911  %val.trunc = trunc i32 %val to i16912  %val.cvt = bitcast i16 %val.trunc to bfloat913  %vecins = insertelement <4 x bfloat> %vec, bfloat %val.cvt, i32 2914  store <4 x bfloat> %vecins, ptr addrspace(1) %out.gep915  ret void916}917 918define amdgpu_kernel void @v_insertelement_v4bf16_3(ptr addrspace(1) %out, ptr addrspace(1) %in, i32 %val) #0 {919; SI-LABEL: v_insertelement_v4bf16_3:920; SI:       ; %bb.0:921; SI-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x0922; SI-NEXT:    s_mov_b32 s7, 0x100f000923; SI-NEXT:    s_mov_b32 s6, 0924; SI-NEXT:    v_lshlrev_b32_e32 v0, 3, v0925; SI-NEXT:    v_mov_b32_e32 v1, 0926; SI-NEXT:    s_waitcnt lgkmcnt(0)927; SI-NEXT:    s_mov_b64 s[4:5], s[2:3]928; SI-NEXT:    buffer_load_dwordx2 v[2:3], v[0:1], s[4:7], 0 addr64929; SI-NEXT:    s_load_dword s8, s[8:9], 0x4930; SI-NEXT:    s_mov_b64 s[2:3], s[6:7]931; SI-NEXT:    s_waitcnt lgkmcnt(0)932; SI-NEXT:    s_lshl_b32 s4, s8, 16933; SI-NEXT:    s_waitcnt vmcnt(0)934; SI-NEXT:    v_and_b32_e32 v3, 0xffff, v3935; SI-NEXT:    v_or_b32_e32 v3, s4, v3936; SI-NEXT:    buffer_store_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64937; SI-NEXT:    s_endpgm938;939; VI-LABEL: v_insertelement_v4bf16_3:940; VI:       ; %bb.0:941; VI-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x0942; VI-NEXT:    s_load_dword s4, s[8:9], 0x10943; VI-NEXT:    v_lshlrev_b32_e32 v2, 3, v0944; VI-NEXT:    s_add_i32 s12, s12, s17945; VI-NEXT:    s_mov_b32 flat_scratch_lo, s13946; VI-NEXT:    s_waitcnt lgkmcnt(0)947; VI-NEXT:    v_mov_b32_e32 v1, s3948; VI-NEXT:    v_add_u32_e32 v0, vcc, s2, v2949; VI-NEXT:    s_lshr_b32 flat_scratch_hi, s12, 8950; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc951; VI-NEXT:    flat_load_dwordx2 v[0:1], v[0:1]952; VI-NEXT:    v_mov_b32_e32 v3, s1953; VI-NEXT:    v_add_u32_e32 v2, vcc, s0, v2954; VI-NEXT:    v_mov_b32_e32 v4, 0x1000504955; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc956; VI-NEXT:    s_waitcnt vmcnt(0)957; VI-NEXT:    v_perm_b32 v1, v1, s4, v4958; VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]959; VI-NEXT:    s_endpgm960;961; GFX900-LABEL: v_insertelement_v4bf16_3:962; GFX900:       ; %bb.0:963; GFX900-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x0964; GFX900-NEXT:    s_load_dword s4, s[8:9], 0x10965; GFX900-NEXT:    v_lshlrev_b32_e32 v2, 3, v0966; GFX900-NEXT:    v_mov_b32_e32 v3, 0x5040100967; GFX900-NEXT:    s_waitcnt lgkmcnt(0)968; GFX900-NEXT:    global_load_dwordx2 v[0:1], v2, s[2:3]969; GFX900-NEXT:    s_waitcnt vmcnt(0)970; GFX900-NEXT:    v_perm_b32 v1, s4, v1, v3971; GFX900-NEXT:    global_store_dwordx2 v2, v[0:1], s[0:1]972; GFX900-NEXT:    s_endpgm973;974; GFX942-LABEL: v_insertelement_v4bf16_3:975; GFX942:       ; %bb.0:976; GFX942-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0977; GFX942-NEXT:    s_load_dword s6, s[4:5], 0x10978; GFX942-NEXT:    v_and_b32_e32 v0, 0x3ff, v0979; GFX942-NEXT:    v_lshlrev_b32_e32 v2, 3, v0980; GFX942-NEXT:    v_mov_b32_e32 v3, 0x5040100981; GFX942-NEXT:    s_waitcnt lgkmcnt(0)982; GFX942-NEXT:    global_load_dwordx2 v[0:1], v2, s[2:3]983; GFX942-NEXT:    s_waitcnt vmcnt(0)984; GFX942-NEXT:    v_perm_b32 v1, s6, v1, v3985; GFX942-NEXT:    global_store_dwordx2 v2, v[0:1], s[0:1]986; GFX942-NEXT:    s_endpgm987;988; GFX1250-LABEL: v_insertelement_v4bf16_3:989; GFX1250:       ; %bb.0:990; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1991; GFX1250-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0992; GFX1250-NEXT:    v_and_b32_e32 v2, 0x3ff, v0993; GFX1250-NEXT:    s_wait_xcnt 0x0994; GFX1250-NEXT:    s_load_b32 s4, s[4:5], 0x10995; GFX1250-NEXT:    s_wait_kmcnt 0x0996; GFX1250-NEXT:    global_load_b64 v[0:1], v2, s[2:3] scale_offset997; GFX1250-NEXT:    s_wait_loadcnt 0x0998; GFX1250-NEXT:    v_perm_b32 v1, s4, v1, 0x5040100999; GFX1250-NEXT:    global_store_b64 v2, v[0:1], s[0:1] scale_offset1000; GFX1250-NEXT:    s_endpgm1001  %tid = call i32 @llvm.amdgcn.workitem.id.x() #11002  %tid.ext = sext i32 %tid to i641003  %in.gep = getelementptr inbounds <4 x bfloat>, ptr addrspace(1) %in, i64 %tid.ext1004  %out.gep = getelementptr inbounds <4 x bfloat>, ptr addrspace(1) %out, i64 %tid.ext1005  %vec = load <4 x bfloat>, ptr addrspace(1) %in.gep1006  %val.trunc = trunc i32 %val to i161007  %val.cvt = bitcast i16 %val.trunc to bfloat1008  %vecins = insertelement <4 x bfloat> %vec, bfloat %val.cvt, i32 31009  store <4 x bfloat> %vecins, ptr addrspace(1) %out.gep1010  ret void1011}1012 1013define amdgpu_kernel void @v_insertelement_v4bf16_dynamic_sgpr(ptr addrspace(1) %out, ptr addrspace(1) %in, i32 %val, i32 %idxval) #0 {1014; SI-LABEL: v_insertelement_v4bf16_dynamic_sgpr:1015; SI:       ; %bb.0:1016; SI-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x01017; SI-NEXT:    s_mov_b32 s7, 0x100f0001018; SI-NEXT:    s_mov_b32 s6, 01019; SI-NEXT:    v_lshlrev_b32_e32 v0, 3, v01020; SI-NEXT:    v_mov_b32_e32 v1, 01021; SI-NEXT:    s_waitcnt lgkmcnt(0)1022; SI-NEXT:    s_mov_b64 s[4:5], s[2:3]1023; SI-NEXT:    buffer_load_dwordx2 v[2:3], v[0:1], s[4:7], 0 addr641024; SI-NEXT:    s_load_dwordx2 s[8:9], s[8:9], 0x41025; SI-NEXT:    s_mov_b64 s[2:3], s[6:7]1026; SI-NEXT:    s_waitcnt lgkmcnt(0)1027; SI-NEXT:    s_lshl_b32 s4, s8, 161028; SI-NEXT:    s_and_b32 s5, s8, 0xffff1029; SI-NEXT:    s_lshl_b32 s6, s9, 41030; SI-NEXT:    s_or_b32 s7, s5, s41031; SI-NEXT:    s_lshl_b64 s[4:5], 0xffff, s61032; SI-NEXT:    v_mov_b32_e32 v4, s71033; SI-NEXT:    v_mov_b32_e32 v5, s71034; SI-NEXT:    s_waitcnt vmcnt(0)1035; SI-NEXT:    v_bfi_b32 v3, s5, v4, v31036; SI-NEXT:    v_bfi_b32 v2, s4, v5, v21037; SI-NEXT:    buffer_store_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr641038; SI-NEXT:    s_endpgm1039;1040; VI-LABEL: v_insertelement_v4bf16_dynamic_sgpr:1041; VI:       ; %bb.0:1042; VI-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x01043; VI-NEXT:    s_load_dwordx2 s[4:5], s[8:9], 0x101044; VI-NEXT:    v_lshlrev_b32_e32 v2, 3, v01045; VI-NEXT:    s_add_i32 s12, s12, s171046; VI-NEXT:    s_mov_b32 flat_scratch_lo, s131047; VI-NEXT:    s_waitcnt lgkmcnt(0)1048; VI-NEXT:    v_mov_b32_e32 v1, s31049; VI-NEXT:    v_add_u32_e32 v0, vcc, s2, v21050; VI-NEXT:    s_lshr_b32 flat_scratch_hi, s12, 81051; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc1052; VI-NEXT:    flat_load_dwordx2 v[0:1], v[0:1]1053; VI-NEXT:    v_mov_b32_e32 v3, s11054; VI-NEXT:    s_lshl_b32 s1, s4, 161055; VI-NEXT:    s_and_b32 s2, s4, 0xffff1056; VI-NEXT:    s_lshl_b32 s3, s5, 41057; VI-NEXT:    s_or_b32 s2, s2, s11058; VI-NEXT:    v_add_u32_e32 v2, vcc, s0, v21059; VI-NEXT:    s_lshl_b64 s[0:1], 0xffff, s31060; VI-NEXT:    v_mov_b32_e32 v4, s21061; VI-NEXT:    v_mov_b32_e32 v5, s21062; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc1063; VI-NEXT:    s_waitcnt vmcnt(0)1064; VI-NEXT:    v_bfi_b32 v1, s1, v4, v11065; VI-NEXT:    v_bfi_b32 v0, s0, v5, v01066; VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]1067; VI-NEXT:    s_endpgm1068;1069; GFX900-LABEL: v_insertelement_v4bf16_dynamic_sgpr:1070; GFX900:       ; %bb.0:1071; GFX900-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x01072; GFX900-NEXT:    s_load_dwordx2 s[4:5], s[8:9], 0x101073; GFX900-NEXT:    v_lshlrev_b32_e32 v2, 3, v01074; GFX900-NEXT:    s_waitcnt lgkmcnt(0)1075; GFX900-NEXT:    global_load_dwordx2 v[0:1], v2, s[2:3]1076; GFX900-NEXT:    s_lshl_b32 s2, s5, 41077; GFX900-NEXT:    s_pack_ll_b32_b16 s4, s4, s41078; GFX900-NEXT:    s_lshl_b64 s[2:3], 0xffff, s21079; GFX900-NEXT:    v_mov_b32_e32 v3, s41080; GFX900-NEXT:    v_mov_b32_e32 v4, s41081; GFX900-NEXT:    s_waitcnt vmcnt(0)1082; GFX900-NEXT:    v_bfi_b32 v1, s3, v3, v11083; GFX900-NEXT:    v_bfi_b32 v0, s2, v4, v01084; GFX900-NEXT:    global_store_dwordx2 v2, v[0:1], s[0:1]1085; GFX900-NEXT:    s_endpgm1086;1087; GFX942-LABEL: v_insertelement_v4bf16_dynamic_sgpr:1088; GFX942:       ; %bb.0:1089; GFX942-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x01090; GFX942-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x101091; GFX942-NEXT:    v_and_b32_e32 v0, 0x3ff, v01092; GFX942-NEXT:    v_lshlrev_b32_e32 v2, 3, v01093; GFX942-NEXT:    s_waitcnt lgkmcnt(0)1094; GFX942-NEXT:    global_load_dwordx2 v[0:1], v2, s[2:3]1095; GFX942-NEXT:    s_lshl_b32 s2, s7, 41096; GFX942-NEXT:    s_pack_ll_b32_b16 s4, s6, s61097; GFX942-NEXT:    s_lshl_b64 s[2:3], 0xffff, s21098; GFX942-NEXT:    v_mov_b32_e32 v3, s41099; GFX942-NEXT:    v_mov_b32_e32 v4, s41100; GFX942-NEXT:    s_waitcnt vmcnt(0)1101; GFX942-NEXT:    v_bfi_b32 v1, s3, v3, v11102; GFX942-NEXT:    v_bfi_b32 v0, s2, v4, v01103; GFX942-NEXT:    global_store_dwordx2 v2, v[0:1], s[0:1]1104; GFX942-NEXT:    s_endpgm1105;1106; GFX1250-LABEL: v_insertelement_v4bf16_dynamic_sgpr:1107; GFX1250:       ; %bb.0:1108; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11109; GFX1250-NEXT:    s_load_b128 s[0:3], s[4:5], 0x01110; GFX1250-NEXT:    v_and_b32_e32 v2, 0x3ff, v01111; GFX1250-NEXT:    s_wait_xcnt 0x01112; GFX1250-NEXT:    s_load_b64 s[4:5], s[4:5], 0x101113; GFX1250-NEXT:    s_wait_kmcnt 0x01114; GFX1250-NEXT:    global_load_b64 v[0:1], v2, s[2:3] scale_offset1115; GFX1250-NEXT:    s_wait_xcnt 0x01116; GFX1250-NEXT:    s_lshl_b32 s2, s5, 41117; GFX1250-NEXT:    s_pack_ll_b32_b16 s4, s4, s41118; GFX1250-NEXT:    s_lshl_b64 s[2:3], 0xffff, s21119; GFX1250-NEXT:    s_wait_loadcnt 0x01120; GFX1250-NEXT:    v_bfi_b32 v1, s3, s4, v11121; GFX1250-NEXT:    v_bfi_b32 v0, s2, s4, v01122; GFX1250-NEXT:    global_store_b64 v2, v[0:1], s[0:1] scale_offset1123; GFX1250-NEXT:    s_endpgm1124  %tid = call i32 @llvm.amdgcn.workitem.id.x() #11125  %tid.ext = sext i32 %tid to i641126  %in.gep = getelementptr inbounds <4 x bfloat>, ptr addrspace(1) %in, i64 %tid.ext1127  %out.gep = getelementptr inbounds <4 x bfloat>, ptr addrspace(1) %out, i64 %tid.ext1128  %vec = load <4 x bfloat>, ptr addrspace(1) %in.gep1129  %val.trunc = trunc i32 %val to i161130  %val.cvt = bitcast i16 %val.trunc to bfloat1131  %vecins = insertelement <4 x bfloat> %vec, bfloat %val.cvt, i32 %idxval1132  store <4 x bfloat> %vecins, ptr addrspace(1) %out.gep1133  ret void1134}1135 1136define amdgpu_kernel void @v_insertelement_v8bf16_3(ptr addrspace(1) %out, ptr addrspace(1) %in, i32 %val) {1137; SI-LABEL: v_insertelement_v8bf16_3:1138; SI:       ; %bb.0:1139; SI-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x01140; SI-NEXT:    s_mov_b32 s7, 0x100f0001141; SI-NEXT:    s_mov_b32 s6, 01142; SI-NEXT:    v_lshlrev_b32_e32 v4, 4, v01143; SI-NEXT:    v_mov_b32_e32 v5, 01144; SI-NEXT:    s_waitcnt lgkmcnt(0)1145; SI-NEXT:    s_mov_b64 s[4:5], s[2:3]1146; SI-NEXT:    buffer_load_dwordx4 v[0:3], v[4:5], s[4:7], 0 addr641147; SI-NEXT:    s_load_dword s8, s[8:9], 0x41148; SI-NEXT:    s_mov_b64 s[2:3], s[6:7]1149; SI-NEXT:    s_waitcnt lgkmcnt(0)1150; SI-NEXT:    s_lshl_b32 s4, s8, 161151; SI-NEXT:    s_waitcnt vmcnt(0)1152; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v11153; SI-NEXT:    v_or_b32_e32 v1, s4, v11154; SI-NEXT:    buffer_store_dwordx4 v[0:3], v[4:5], s[0:3], 0 addr641155; SI-NEXT:    s_endpgm1156;1157; VI-LABEL: v_insertelement_v8bf16_3:1158; VI:       ; %bb.0:1159; VI-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x01160; VI-NEXT:    s_load_dword s4, s[8:9], 0x101161; VI-NEXT:    v_lshlrev_b32_e32 v4, 4, v01162; VI-NEXT:    s_add_i32 s12, s12, s171163; VI-NEXT:    s_mov_b32 flat_scratch_lo, s131164; VI-NEXT:    s_waitcnt lgkmcnt(0)1165; VI-NEXT:    v_mov_b32_e32 v1, s31166; VI-NEXT:    v_add_u32_e32 v0, vcc, s2, v41167; VI-NEXT:    s_lshr_b32 flat_scratch_hi, s12, 81168; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc1169; VI-NEXT:    flat_load_dwordx4 v[0:3], v[0:1]1170; VI-NEXT:    v_add_u32_e32 v4, vcc, s0, v41171; VI-NEXT:    s_lshl_b32 s0, s4, 161172; VI-NEXT:    v_mov_b32_e32 v5, s11173; VI-NEXT:    v_mov_b32_e32 v6, s01174; VI-NEXT:    v_addc_u32_e32 v5, vcc, 0, v5, vcc1175; VI-NEXT:    s_waitcnt vmcnt(0)1176; VI-NEXT:    v_or_b32_sdwa v1, v1, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD1177; VI-NEXT:    flat_store_dwordx4 v[4:5], v[0:3]1178; VI-NEXT:    s_endpgm1179;1180; GFX900-LABEL: v_insertelement_v8bf16_3:1181; GFX900:       ; %bb.0:1182; GFX900-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x01183; GFX900-NEXT:    s_load_dword s4, s[8:9], 0x101184; GFX900-NEXT:    v_lshlrev_b32_e32 v4, 4, v01185; GFX900-NEXT:    v_mov_b32_e32 v5, 0x50401001186; GFX900-NEXT:    s_waitcnt lgkmcnt(0)1187; GFX900-NEXT:    global_load_dwordx4 v[0:3], v4, s[2:3]1188; GFX900-NEXT:    s_waitcnt vmcnt(0)1189; GFX900-NEXT:    v_perm_b32 v1, s4, v1, v51190; GFX900-NEXT:    global_store_dwordx4 v4, v[0:3], s[0:1]1191; GFX900-NEXT:    s_endpgm1192;1193; GFX942-LABEL: v_insertelement_v8bf16_3:1194; GFX942:       ; %bb.0:1195; GFX942-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x01196; GFX942-NEXT:    s_load_dword s6, s[4:5], 0x101197; GFX942-NEXT:    v_and_b32_e32 v0, 0x3ff, v01198; GFX942-NEXT:    v_lshlrev_b32_e32 v4, 4, v01199; GFX942-NEXT:    v_mov_b32_e32 v5, 0x50401001200; GFX942-NEXT:    s_waitcnt lgkmcnt(0)1201; GFX942-NEXT:    global_load_dwordx4 v[0:3], v4, s[2:3]1202; GFX942-NEXT:    s_waitcnt vmcnt(0)1203; GFX942-NEXT:    v_perm_b32 v1, s6, v1, v51204; GFX942-NEXT:    global_store_dwordx4 v4, v[0:3], s[0:1]1205; GFX942-NEXT:    s_endpgm1206;1207; GFX1250-LABEL: v_insertelement_v8bf16_3:1208; GFX1250:       ; %bb.0:1209; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11210; GFX1250-NEXT:    s_load_b128 s[0:3], s[4:5], 0x01211; GFX1250-NEXT:    v_and_b32_e32 v4, 0x3ff, v01212; GFX1250-NEXT:    s_wait_xcnt 0x01213; GFX1250-NEXT:    s_load_b32 s4, s[4:5], 0x101214; GFX1250-NEXT:    s_wait_kmcnt 0x01215; GFX1250-NEXT:    global_load_b128 v[0:3], v4, s[2:3] scale_offset1216; GFX1250-NEXT:    s_wait_loadcnt 0x01217; GFX1250-NEXT:    v_perm_b32 v1, s4, v1, 0x50401001218; GFX1250-NEXT:    global_store_b128 v4, v[0:3], s[0:1] scale_offset1219; GFX1250-NEXT:    s_endpgm1220  %tid = call i32 @llvm.amdgcn.workitem.id.x() #11221  %tid.ext = sext i32 %tid to i641222  %in.gep = getelementptr inbounds <8 x bfloat>, ptr addrspace(1) %in, i64 %tid.ext1223  %out.gep = getelementptr inbounds <8 x bfloat>, ptr addrspace(1) %out, i64 %tid.ext1224  %vec = load <8 x bfloat>, ptr addrspace(1) %in.gep1225  %val.trunc = trunc i32 %val to i161226  %val.cvt = bitcast i16 %val.trunc to bfloat1227  %vecins = insertelement <8 x bfloat> %vec, bfloat %val.cvt, i32 31228  store <8 x bfloat> %vecins, ptr addrspace(1) %out.gep1229  ret void1230}1231 1232define amdgpu_kernel void @v_insertelement_v8bf16_dynamic(ptr addrspace(1) %out, ptr addrspace(1) %in, i32 %val, i32 %n) {1233; SI-LABEL: v_insertelement_v8bf16_dynamic:1234; SI:       ; %bb.0:1235; SI-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x01236; SI-NEXT:    s_mov_b32 s7, 0x100f0001237; SI-NEXT:    s_mov_b32 s6, 01238; SI-NEXT:    v_lshlrev_b32_e32 v4, 4, v01239; SI-NEXT:    v_mov_b32_e32 v5, 01240; SI-NEXT:    s_waitcnt lgkmcnt(0)1241; SI-NEXT:    s_mov_b64 s[4:5], s[2:3]1242; SI-NEXT:    buffer_load_dwordx4 v[0:3], v[4:5], s[4:7], 0 addr641243; SI-NEXT:    s_load_dwordx2 s[8:9], s[8:9], 0x41244; SI-NEXT:    s_mov_b64 s[2:3], s[6:7]1245; SI-NEXT:    s_waitcnt lgkmcnt(0)1246; SI-NEXT:    s_cmp_eq_u32 s9, 61247; SI-NEXT:    v_mov_b32_e32 v6, s81248; SI-NEXT:    s_cselect_b64 vcc, -1, 01249; SI-NEXT:    s_cmp_eq_u32 s9, 71250; SI-NEXT:    s_waitcnt vmcnt(0)1251; SI-NEXT:    v_cndmask_b32_e32 v7, v3, v6, vcc1252; SI-NEXT:    v_lshrrev_b32_e32 v3, 16, v31253; SI-NEXT:    s_cselect_b64 vcc, -1, 01254; SI-NEXT:    s_cmp_eq_u32 s9, 41255; SI-NEXT:    v_cndmask_b32_e32 v3, v3, v6, vcc1256; SI-NEXT:    s_cselect_b64 vcc, -1, 01257; SI-NEXT:    s_cmp_eq_u32 s9, 51258; SI-NEXT:    v_lshrrev_b32_e32 v8, 16, v21259; SI-NEXT:    v_cndmask_b32_e32 v2, v2, v6, vcc1260; SI-NEXT:    s_cselect_b64 vcc, -1, 01261; SI-NEXT:    s_cmp_eq_u32 s9, 21262; SI-NEXT:    v_and_b32_e32 v7, 0xffff, v71263; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v31264; SI-NEXT:    v_cndmask_b32_e32 v8, v8, v6, vcc1265; SI-NEXT:    s_cselect_b64 vcc, -1, 01266; SI-NEXT:    s_cmp_eq_u32 s9, 31267; SI-NEXT:    v_lshrrev_b32_e32 v9, 16, v11268; SI-NEXT:    v_and_b32_e32 v2, 0xffff, v21269; SI-NEXT:    v_or_b32_e32 v3, v7, v31270; SI-NEXT:    v_lshlrev_b32_e32 v7, 16, v81271; SI-NEXT:    v_cndmask_b32_e32 v1, v1, v6, vcc1272; SI-NEXT:    s_cselect_b64 vcc, -1, 01273; SI-NEXT:    s_cmp_eq_u32 s9, 01274; SI-NEXT:    v_or_b32_e32 v2, v2, v71275; SI-NEXT:    v_cndmask_b32_e32 v7, v9, v6, vcc1276; SI-NEXT:    s_cselect_b64 vcc, -1, 01277; SI-NEXT:    s_cmp_eq_u32 s9, 11278; SI-NEXT:    v_lshrrev_b32_e32 v10, 16, v01279; SI-NEXT:    v_cndmask_b32_e32 v0, v0, v6, vcc1280; SI-NEXT:    s_cselect_b64 vcc, -1, 01281; SI-NEXT:    v_cndmask_b32_e32 v6, v10, v6, vcc1282; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v11283; SI-NEXT:    v_lshlrev_b32_e32 v7, 16, v71284; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v01285; SI-NEXT:    v_lshlrev_b32_e32 v6, 16, v61286; SI-NEXT:    v_or_b32_e32 v1, v1, v71287; SI-NEXT:    v_or_b32_e32 v0, v0, v61288; SI-NEXT:    buffer_store_dwordx4 v[0:3], v[4:5], s[0:3], 0 addr641289; SI-NEXT:    s_endpgm1290;1291; VI-LABEL: v_insertelement_v8bf16_dynamic:1292; VI:       ; %bb.0:1293; VI-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x01294; VI-NEXT:    s_load_dwordx2 s[4:5], s[8:9], 0x101295; VI-NEXT:    v_lshlrev_b32_e32 v4, 4, v01296; VI-NEXT:    s_add_i32 s12, s12, s171297; VI-NEXT:    s_mov_b32 flat_scratch_lo, s131298; VI-NEXT:    s_waitcnt lgkmcnt(0)1299; VI-NEXT:    v_mov_b32_e32 v1, s31300; VI-NEXT:    v_add_u32_e32 v0, vcc, s2, v41301; VI-NEXT:    s_lshr_b32 flat_scratch_hi, s12, 81302; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc1303; VI-NEXT:    flat_load_dwordx4 v[0:3], v[0:1]1304; VI-NEXT:    v_mov_b32_e32 v5, s11305; VI-NEXT:    v_add_u32_e32 v4, vcc, s0, v41306; VI-NEXT:    s_cmp_eq_u32 s5, 61307; VI-NEXT:    v_addc_u32_e32 v5, vcc, 0, v5, vcc1308; VI-NEXT:    v_mov_b32_e32 v6, s41309; VI-NEXT:    s_cselect_b64 vcc, -1, 01310; VI-NEXT:    s_cmp_eq_u32 s5, 71311; VI-NEXT:    s_waitcnt vmcnt(0)1312; VI-NEXT:    v_cndmask_b32_e32 v7, v3, v6, vcc1313; VI-NEXT:    v_lshrrev_b32_e32 v3, 16, v31314; VI-NEXT:    s_cselect_b64 vcc, -1, 01315; VI-NEXT:    s_cmp_eq_u32 s5, 41316; VI-NEXT:    v_cndmask_b32_e32 v3, v3, v6, vcc1317; VI-NEXT:    s_cselect_b64 vcc, -1, 01318; VI-NEXT:    s_cmp_eq_u32 s5, 51319; VI-NEXT:    v_lshrrev_b32_e32 v8, 16, v21320; VI-NEXT:    v_cndmask_b32_e32 v2, v2, v6, vcc1321; VI-NEXT:    s_cselect_b64 vcc, -1, 01322; VI-NEXT:    s_cmp_eq_u32 s5, 21323; VI-NEXT:    v_lshlrev_b32_e32 v3, 16, v31324; VI-NEXT:    v_cndmask_b32_e32 v8, v8, v6, vcc1325; VI-NEXT:    s_cselect_b64 vcc, -1, 01326; VI-NEXT:    s_cmp_eq_u32 s5, 31327; VI-NEXT:    v_lshrrev_b32_e32 v9, 16, v11328; VI-NEXT:    v_or_b32_sdwa v3, v7, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD1329; VI-NEXT:    v_lshlrev_b32_e32 v7, 16, v81330; VI-NEXT:    v_cndmask_b32_e32 v1, v1, v6, vcc1331; VI-NEXT:    s_cselect_b64 vcc, -1, 01332; VI-NEXT:    s_cmp_eq_u32 s5, 01333; VI-NEXT:    v_or_b32_sdwa v2, v2, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD1334; VI-NEXT:    v_cndmask_b32_e32 v7, v9, v6, vcc1335; VI-NEXT:    s_cselect_b64 vcc, -1, 01336; VI-NEXT:    s_cmp_eq_u32 s5, 11337; VI-NEXT:    v_cndmask_b32_e32 v8, v0, v6, vcc1338; VI-NEXT:    s_cselect_b64 vcc, -1, 01339; VI-NEXT:    v_lshlrev_b32_e32 v7, 16, v71340; VI-NEXT:    v_cndmask_b32_sdwa v0, v0, v6, vcc dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1341; VI-NEXT:    v_or_b32_sdwa v1, v1, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD1342; VI-NEXT:    v_or_b32_sdwa v0, v8, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD1343; VI-NEXT:    flat_store_dwordx4 v[4:5], v[0:3]1344; VI-NEXT:    s_endpgm1345;1346; GFX900-LABEL: v_insertelement_v8bf16_dynamic:1347; GFX900:       ; %bb.0:1348; GFX900-NEXT:    s_load_dwordx4 s[16:19], s[8:9], 0x01349; GFX900-NEXT:    s_load_dwordx2 s[12:13], s[8:9], 0x101350; GFX900-NEXT:    v_lshlrev_b32_e32 v4, 4, v01351; GFX900-NEXT:    s_mov_b32 s14, 0x50401001352; GFX900-NEXT:    s_waitcnt lgkmcnt(0)1353; GFX900-NEXT:    global_load_dwordx4 v[0:3], v4, s[18:19]1354; GFX900-NEXT:    s_cmp_eq_u32 s13, 61355; GFX900-NEXT:    s_cselect_b64 vcc, -1, 01356; GFX900-NEXT:    s_cmp_eq_u32 s13, 71357; GFX900-NEXT:    s_cselect_b64 s[0:1], -1, 01358; GFX900-NEXT:    s_cmp_eq_u32 s13, 41359; GFX900-NEXT:    s_cselect_b64 s[2:3], -1, 01360; GFX900-NEXT:    s_cmp_eq_u32 s13, 51361; GFX900-NEXT:    s_cselect_b64 s[4:5], -1, 01362; GFX900-NEXT:    s_cmp_eq_u32 s13, 21363; GFX900-NEXT:    v_mov_b32_e32 v5, s121364; GFX900-NEXT:    s_cselect_b64 s[6:7], -1, 01365; GFX900-NEXT:    s_cmp_eq_u32 s13, 31366; GFX900-NEXT:    s_cselect_b64 s[8:9], -1, 01367; GFX900-NEXT:    s_cmp_eq_u32 s13, 01368; GFX900-NEXT:    s_cselect_b64 s[10:11], -1, 01369; GFX900-NEXT:    s_cmp_eq_u32 s13, 11370; GFX900-NEXT:    s_cselect_b64 s[12:13], -1, 01371; GFX900-NEXT:    s_waitcnt vmcnt(0)1372; GFX900-NEXT:    v_cndmask_b32_e32 v6, v3, v5, vcc1373; GFX900-NEXT:    s_mov_b64 vcc, s[0:1]1374; GFX900-NEXT:    v_cndmask_b32_sdwa v3, v3, v5, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1375; GFX900-NEXT:    s_mov_b64 vcc, s[4:5]1376; GFX900-NEXT:    v_cndmask_b32_e64 v7, v2, v5, s[2:3]1377; GFX900-NEXT:    v_cndmask_b32_sdwa v2, v2, v5, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1378; GFX900-NEXT:    s_mov_b64 vcc, s[8:9]1379; GFX900-NEXT:    v_cndmask_b32_e64 v8, v1, v5, s[6:7]1380; GFX900-NEXT:    v_cndmask_b32_sdwa v1, v1, v5, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1381; GFX900-NEXT:    s_mov_b64 vcc, s[12:13]1382; GFX900-NEXT:    v_cndmask_b32_e64 v9, v0, v5, s[10:11]1383; GFX900-NEXT:    v_cndmask_b32_sdwa v0, v0, v5, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1384; GFX900-NEXT:    v_perm_b32 v3, v3, v6, s141385; GFX900-NEXT:    v_perm_b32 v2, v2, v7, s141386; GFX900-NEXT:    v_perm_b32 v1, v1, v8, s141387; GFX900-NEXT:    v_perm_b32 v0, v0, v9, s141388; GFX900-NEXT:    global_store_dwordx4 v4, v[0:3], s[16:17]1389; GFX900-NEXT:    s_endpgm1390;1391; GFX942-LABEL: v_insertelement_v8bf16_dynamic:1392; GFX942:       ; %bb.0:1393; GFX942-NEXT:    s_load_dwordx4 s[16:19], s[4:5], 0x01394; GFX942-NEXT:    s_load_dwordx2 s[12:13], s[4:5], 0x101395; GFX942-NEXT:    v_and_b32_e32 v0, 0x3ff, v01396; GFX942-NEXT:    v_lshlrev_b32_e32 v4, 4, v01397; GFX942-NEXT:    s_mov_b32 s14, 0x50401001398; GFX942-NEXT:    s_waitcnt lgkmcnt(0)1399; GFX942-NEXT:    global_load_dwordx4 v[0:3], v4, s[18:19]1400; GFX942-NEXT:    s_cmp_eq_u32 s13, 61401; GFX942-NEXT:    s_cselect_b64 vcc, -1, 01402; GFX942-NEXT:    s_cmp_eq_u32 s13, 71403; GFX942-NEXT:    s_cselect_b64 s[0:1], -1, 01404; GFX942-NEXT:    s_cmp_eq_u32 s13, 41405; GFX942-NEXT:    s_cselect_b64 s[2:3], -1, 01406; GFX942-NEXT:    s_cmp_eq_u32 s13, 51407; GFX942-NEXT:    s_cselect_b64 s[4:5], -1, 01408; GFX942-NEXT:    s_cmp_eq_u32 s13, 21409; GFX942-NEXT:    v_mov_b32_e32 v5, s121410; GFX942-NEXT:    s_cselect_b64 s[6:7], -1, 01411; GFX942-NEXT:    s_cmp_eq_u32 s13, 31412; GFX942-NEXT:    s_cselect_b64 s[8:9], -1, 01413; GFX942-NEXT:    s_cmp_eq_u32 s13, 01414; GFX942-NEXT:    s_cselect_b64 s[10:11], -1, 01415; GFX942-NEXT:    s_cmp_eq_u32 s13, 11416; GFX942-NEXT:    s_cselect_b64 s[12:13], -1, 01417; GFX942-NEXT:    s_waitcnt vmcnt(0)1418; GFX942-NEXT:    v_cndmask_b32_e32 v6, v3, v5, vcc1419; GFX942-NEXT:    s_mov_b64 vcc, s[0:1]1420; GFX942-NEXT:    v_cndmask_b32_sdwa v3, v3, v5, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1421; GFX942-NEXT:    s_mov_b64 vcc, s[4:5]1422; GFX942-NEXT:    v_cndmask_b32_e64 v7, v2, v5, s[2:3]1423; GFX942-NEXT:    v_cndmask_b32_sdwa v2, v2, v5, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1424; GFX942-NEXT:    s_mov_b64 vcc, s[8:9]1425; GFX942-NEXT:    v_cndmask_b32_e64 v8, v1, v5, s[6:7]1426; GFX942-NEXT:    v_cndmask_b32_sdwa v1, v1, v5, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1427; GFX942-NEXT:    s_mov_b64 vcc, s[12:13]1428; GFX942-NEXT:    v_cndmask_b32_e64 v9, v0, v5, s[10:11]1429; GFX942-NEXT:    v_cndmask_b32_sdwa v0, v0, v5, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1430; GFX942-NEXT:    v_perm_b32 v3, v3, v6, s141431; GFX942-NEXT:    v_perm_b32 v2, v2, v7, s141432; GFX942-NEXT:    v_perm_b32 v1, v1, v8, s141433; GFX942-NEXT:    v_perm_b32 v0, v0, v9, s141434; GFX942-NEXT:    global_store_dwordx4 v4, v[0:3], s[16:17]1435; GFX942-NEXT:    s_endpgm1436;1437; GFX1250-LABEL: v_insertelement_v8bf16_dynamic:1438; GFX1250:       ; %bb.0:1439; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11440; GFX1250-NEXT:    s_load_b128 s[0:3], s[4:5], 0x01441; GFX1250-NEXT:    v_and_b32_e32 v4, 0x3ff, v01442; GFX1250-NEXT:    s_wait_xcnt 0x01443; GFX1250-NEXT:    s_load_b64 s[4:5], s[4:5], 0x101444; GFX1250-NEXT:    s_wait_kmcnt 0x01445; GFX1250-NEXT:    global_load_b128 v[0:3], v4, s[2:3] scale_offset1446; GFX1250-NEXT:    s_cmp_eq_u32 s5, 61447; GFX1250-NEXT:    s_wait_xcnt 0x01448; GFX1250-NEXT:    s_cselect_b32 s2, -1, 01449; GFX1250-NEXT:    s_cmp_eq_u32 s5, 71450; GFX1250-NEXT:    s_wait_loadcnt 0x01451; GFX1250-NEXT:    v_cndmask_b32_e64 v5, v3, s4, s21452; GFX1250-NEXT:    s_cselect_b32 s2, -1, 01453; GFX1250-NEXT:    s_cmp_eq_u32 s5, 41454; GFX1250-NEXT:    v_dual_lshrrev_b32 v3, 16, v3 :: v_dual_lshrrev_b32 v6, 16, v21455; GFX1250-NEXT:    s_cselect_b32 s3, -1, 01456; GFX1250-NEXT:    s_cmp_eq_u32 s5, 51457; GFX1250-NEXT:    v_cndmask_b32_e64 v2, v2, s4, s31458; GFX1250-NEXT:    s_cselect_b32 s3, -1, 01459; GFX1250-NEXT:    s_cmp_eq_u32 s5, 21460; GFX1250-NEXT:    v_dual_lshrrev_b32 v7, 16, v1 :: v_dual_lshrrev_b32 v8, 16, v01461; GFX1250-NEXT:    v_cndmask_b32_e64 v3, v3, s4, s21462; GFX1250-NEXT:    s_cselect_b32 s2, -1, 01463; GFX1250-NEXT:    s_cmp_eq_u32 s5, 31464; GFX1250-NEXT:    v_cndmask_b32_e64 v1, v1, s4, s21465; GFX1250-NEXT:    s_cselect_b32 s2, -1, 01466; GFX1250-NEXT:    s_cmp_eq_u32 s5, 01467; GFX1250-NEXT:    v_cndmask_b32_e64 v7, v7, s4, s21468; GFX1250-NEXT:    s_cselect_b32 s2, -1, 01469; GFX1250-NEXT:    s_cmp_eq_u32 s5, 11470; GFX1250-NEXT:    v_cndmask_b32_e64 v0, v0, s4, s21471; GFX1250-NEXT:    s_cselect_b32 s2, -1, 01472; GFX1250-NEXT:    v_cndmask_b32_e64 v6, v6, s4, s31473; GFX1250-NEXT:    v_cndmask_b32_e64 v8, v8, s4, s21474; GFX1250-NEXT:    v_perm_b32 v3, v3, v5, 0x50401001475; GFX1250-NEXT:    v_perm_b32 v1, v7, v1, 0x50401001476; GFX1250-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)1477; GFX1250-NEXT:    v_perm_b32 v2, v6, v2, 0x50401001478; GFX1250-NEXT:    v_perm_b32 v0, v8, v0, 0x50401001479; GFX1250-NEXT:    global_store_b128 v4, v[0:3], s[0:1] scale_offset1480; GFX1250-NEXT:    s_endpgm1481  %tid = call i32 @llvm.amdgcn.workitem.id.x() #11482  %tid.ext = sext i32 %tid to i641483  %in.gep = getelementptr inbounds <8 x bfloat>, ptr addrspace(1) %in, i64 %tid.ext1484  %out.gep = getelementptr inbounds <8 x bfloat>, ptr addrspace(1) %out, i64 %tid.ext1485  %vec = load <8 x bfloat>, ptr addrspace(1) %in.gep1486  %val.trunc = trunc i32 %val to i161487  %val.cvt = bitcast i16 %val.trunc to bfloat1488  %vecins = insertelement <8 x bfloat> %vec, bfloat %val.cvt, i32 %n1489  store <8 x bfloat> %vecins, ptr addrspace(1) %out.gep1490  ret void1491}1492 1493define amdgpu_kernel void @v_insertelement_v16bf16_3(ptr addrspace(1) %out, ptr addrspace(1) %in, i32 %val) {1494; SI-LABEL: v_insertelement_v16bf16_3:1495; SI:       ; %bb.0:1496; SI-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x01497; SI-NEXT:    s_mov_b32 s7, 0x100f0001498; SI-NEXT:    s_mov_b32 s6, 01499; SI-NEXT:    v_lshlrev_b32_e32 v8, 5, v01500; SI-NEXT:    v_mov_b32_e32 v9, 01501; SI-NEXT:    s_waitcnt lgkmcnt(0)1502; SI-NEXT:    s_mov_b64 s[4:5], s[2:3]1503; SI-NEXT:    buffer_load_dwordx4 v[0:3], v[8:9], s[4:7], 0 addr641504; SI-NEXT:    buffer_load_dwordx4 v[4:7], v[8:9], s[4:7], 0 addr64 offset:161505; SI-NEXT:    s_load_dword s8, s[8:9], 0x41506; SI-NEXT:    s_mov_b64 s[2:3], s[6:7]1507; SI-NEXT:    s_waitcnt lgkmcnt(0)1508; SI-NEXT:    s_lshl_b32 s4, s8, 161509; SI-NEXT:    s_waitcnt vmcnt(1)1510; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v11511; SI-NEXT:    v_or_b32_e32 v1, s4, v11512; SI-NEXT:    s_waitcnt vmcnt(0)1513; SI-NEXT:    buffer_store_dwordx4 v[4:7], v[8:9], s[0:3], 0 addr64 offset:161514; SI-NEXT:    buffer_store_dwordx4 v[0:3], v[8:9], s[0:3], 0 addr641515; SI-NEXT:    s_endpgm1516;1517; VI-LABEL: v_insertelement_v16bf16_3:1518; VI:       ; %bb.0:1519; VI-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x01520; VI-NEXT:    s_load_dword s4, s[8:9], 0x101521; VI-NEXT:    v_lshlrev_b32_e32 v8, 5, v01522; VI-NEXT:    s_add_i32 s12, s12, s171523; VI-NEXT:    s_mov_b32 flat_scratch_lo, s131524; VI-NEXT:    s_waitcnt lgkmcnt(0)1525; VI-NEXT:    v_mov_b32_e32 v1, s31526; VI-NEXT:    v_add_u32_e32 v0, vcc, s2, v81527; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc1528; VI-NEXT:    v_add_u32_e32 v4, vcc, 16, v01529; VI-NEXT:    s_lshr_b32 flat_scratch_hi, s12, 81530; VI-NEXT:    v_addc_u32_e32 v5, vcc, 0, v1, vcc1531; VI-NEXT:    flat_load_dwordx4 v[0:3], v[0:1]1532; VI-NEXT:    flat_load_dwordx4 v[4:7], v[4:5]1533; VI-NEXT:    v_mov_b32_e32 v9, s11534; VI-NEXT:    v_add_u32_e32 v8, vcc, s0, v81535; VI-NEXT:    v_addc_u32_e32 v9, vcc, 0, v9, vcc1536; VI-NEXT:    s_lshl_b32 s1, s4, 161537; VI-NEXT:    v_add_u32_e32 v10, vcc, 16, v81538; VI-NEXT:    v_mov_b32_e32 v12, s11539; VI-NEXT:    v_addc_u32_e32 v11, vcc, 0, v9, vcc1540; VI-NEXT:    s_waitcnt vmcnt(1)1541; VI-NEXT:    v_or_b32_sdwa v1, v1, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD1542; VI-NEXT:    s_waitcnt vmcnt(0)1543; VI-NEXT:    flat_store_dwordx4 v[10:11], v[4:7]1544; VI-NEXT:    flat_store_dwordx4 v[8:9], v[0:3]1545; VI-NEXT:    s_endpgm1546;1547; GFX900-LABEL: v_insertelement_v16bf16_3:1548; GFX900:       ; %bb.0:1549; GFX900-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x01550; GFX900-NEXT:    s_load_dword s4, s[8:9], 0x101551; GFX900-NEXT:    v_lshlrev_b32_e32 v8, 5, v01552; GFX900-NEXT:    v_mov_b32_e32 v9, 0x50401001553; GFX900-NEXT:    s_waitcnt lgkmcnt(0)1554; GFX900-NEXT:    global_load_dwordx4 v[0:3], v8, s[2:3]1555; GFX900-NEXT:    global_load_dwordx4 v[4:7], v8, s[2:3] offset:161556; GFX900-NEXT:    s_waitcnt vmcnt(1)1557; GFX900-NEXT:    v_perm_b32 v1, s4, v1, v91558; GFX900-NEXT:    s_waitcnt vmcnt(0)1559; GFX900-NEXT:    global_store_dwordx4 v8, v[4:7], s[0:1] offset:161560; GFX900-NEXT:    global_store_dwordx4 v8, v[0:3], s[0:1]1561; GFX900-NEXT:    s_endpgm1562;1563; GFX942-LABEL: v_insertelement_v16bf16_3:1564; GFX942:       ; %bb.0:1565; GFX942-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x01566; GFX942-NEXT:    s_load_dword s6, s[4:5], 0x101567; GFX942-NEXT:    v_and_b32_e32 v0, 0x3ff, v01568; GFX942-NEXT:    v_lshlrev_b32_e32 v4, 5, v01569; GFX942-NEXT:    v_mov_b32_e32 v5, 0x50401001570; GFX942-NEXT:    s_waitcnt lgkmcnt(0)1571; GFX942-NEXT:    global_load_dwordx4 v[0:3], v4, s[2:3]1572; GFX942-NEXT:    global_load_dwordx4 v[6:9], v4, s[2:3] offset:161573; GFX942-NEXT:    s_waitcnt vmcnt(1)1574; GFX942-NEXT:    v_perm_b32 v1, s6, v1, v51575; GFX942-NEXT:    s_waitcnt vmcnt(0)1576; GFX942-NEXT:    global_store_dwordx4 v4, v[6:9], s[0:1] offset:161577; GFX942-NEXT:    global_store_dwordx4 v4, v[0:3], s[0:1]1578; GFX942-NEXT:    s_endpgm1579;1580; GFX1250-LABEL: v_insertelement_v16bf16_3:1581; GFX1250:       ; %bb.0:1582; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11583; GFX1250-NEXT:    s_load_b128 s[0:3], s[4:5], 0x01584; GFX1250-NEXT:    v_and_b32_e32 v0, 0x3ff, v01585; GFX1250-NEXT:    s_wait_xcnt 0x01586; GFX1250-NEXT:    s_load_b32 s4, s[4:5], 0x101587; GFX1250-NEXT:    s_delay_alu instid0(VALU_DEP_1)1588; GFX1250-NEXT:    v_lshlrev_b32_e32 v8, 5, v01589; GFX1250-NEXT:    s_wait_kmcnt 0x01590; GFX1250-NEXT:    s_clause 0x11591; GFX1250-NEXT:    global_load_b128 v[0:3], v8, s[2:3]1592; GFX1250-NEXT:    global_load_b128 v[4:7], v8, s[2:3] offset:161593; GFX1250-NEXT:    s_wait_loadcnt 0x11594; GFX1250-NEXT:    v_perm_b32 v1, s4, v1, 0x50401001595; GFX1250-NEXT:    s_wait_loadcnt 0x01596; GFX1250-NEXT:    s_clause 0x11597; GFX1250-NEXT:    global_store_b128 v8, v[4:7], s[0:1] offset:161598; GFX1250-NEXT:    global_store_b128 v8, v[0:3], s[0:1]1599; GFX1250-NEXT:    s_endpgm1600  %tid = call i32 @llvm.amdgcn.workitem.id.x() #11601  %tid.ext = sext i32 %tid to i641602  %in.gep = getelementptr inbounds <16 x bfloat>, ptr addrspace(1) %in, i64 %tid.ext1603  %out.gep = getelementptr inbounds <16 x bfloat>, ptr addrspace(1) %out, i64 %tid.ext1604  %vec = load <16 x bfloat>, ptr addrspace(1) %in.gep1605  %val.trunc = trunc i32 %val to i161606  %val.cvt = bitcast i16 %val.trunc to bfloat1607  %vecins = insertelement <16 x bfloat> %vec, bfloat %val.cvt, i32 31608  store <16 x bfloat> %vecins, ptr addrspace(1) %out.gep1609  ret void1610}1611 1612define amdgpu_kernel void @v_insertelement_v16bf16_dynamic(ptr addrspace(1) %out, ptr addrspace(1) %in, i32 %val, i32 %n) {1613; SI-LABEL: v_insertelement_v16bf16_dynamic:1614; SI:       ; %bb.0:1615; SI-NEXT:    s_load_dwordx4 s[12:15], s[8:9], 0x01616; SI-NEXT:    s_load_dwordx2 s[6:7], s[8:9], 0x41617; SI-NEXT:    s_mov_b32 s3, 0x100f0001618; SI-NEXT:    s_mov_b32 s2, 01619; SI-NEXT:    v_lshlrev_b32_e32 v4, 5, v01620; SI-NEXT:    s_waitcnt lgkmcnt(0)1621; SI-NEXT:    s_mov_b64 s[0:1], s[14:15]1622; SI-NEXT:    v_mov_b32_e32 v5, 01623; SI-NEXT:    buffer_load_dwordx4 v[7:10], v[4:5], s[0:3], 0 addr641624; SI-NEXT:    buffer_load_dwordx4 v[0:3], v[4:5], s[0:3], 0 addr64 offset:161625; SI-NEXT:    s_cmp_eq_u32 s7, 61626; SI-NEXT:    v_mov_b32_e32 v6, s61627; SI-NEXT:    s_cselect_b64 vcc, -1, 01628; SI-NEXT:    s_cmp_eq_u32 s7, 71629; SI-NEXT:    s_mov_b64 s[14:15], s[2:3]1630; SI-NEXT:    s_waitcnt vmcnt(1)1631; SI-NEXT:    v_cndmask_b32_e32 v11, v10, v6, vcc1632; SI-NEXT:    s_cselect_b64 vcc, -1, 01633; SI-NEXT:    s_cmp_eq_u32 s7, 41634; SI-NEXT:    s_cselect_b64 s[0:1], -1, 01635; SI-NEXT:    s_cmp_eq_u32 s7, 51636; SI-NEXT:    v_lshrrev_b32_e32 v10, 16, v101637; SI-NEXT:    v_lshrrev_b32_e32 v12, 16, v91638; SI-NEXT:    v_cndmask_b32_e64 v9, v9, v6, s[0:1]1639; SI-NEXT:    s_cselect_b64 s[0:1], -1, 01640; SI-NEXT:    s_cmp_eq_u32 s7, 21641; SI-NEXT:    s_cselect_b64 s[2:3], -1, 01642; SI-NEXT:    s_cmp_eq_u32 s7, 31643; SI-NEXT:    v_cndmask_b32_e32 v10, v10, v6, vcc1644; SI-NEXT:    v_lshrrev_b32_e32 v13, 16, v81645; SI-NEXT:    v_cndmask_b32_e64 v8, v8, v6, s[2:3]1646; SI-NEXT:    s_cselect_b64 s[2:3], -1, 01647; SI-NEXT:    s_cmp_eq_u32 s7, 01648; SI-NEXT:    v_and_b32_e32 v11, 0xffff, v111649; SI-NEXT:    v_lshlrev_b32_e32 v10, 16, v101650; SI-NEXT:    v_cndmask_b32_e64 v12, v12, v6, s[0:1]1651; SI-NEXT:    s_cselect_b64 s[4:5], -1, 01652; SI-NEXT:    v_or_b32_e32 v10, v11, v101653; SI-NEXT:    v_lshlrev_b32_e32 v11, 16, v121654; SI-NEXT:    v_cndmask_b32_e64 v12, v13, v6, s[2:3]1655; SI-NEXT:    s_cmp_eq_u32 s7, 11656; SI-NEXT:    v_lshrrev_b32_e32 v14, 16, v71657; SI-NEXT:    v_and_b32_e32 v8, 0xffff, v81658; SI-NEXT:    v_lshlrev_b32_e32 v12, 16, v121659; SI-NEXT:    s_cselect_b64 vcc, -1, 01660; SI-NEXT:    s_cmp_eq_u32 s7, 141661; SI-NEXT:    v_cndmask_b32_e64 v7, v7, v6, s[4:5]1662; SI-NEXT:    v_or_b32_e32 v8, v8, v121663; SI-NEXT:    v_cndmask_b32_e32 v12, v14, v6, vcc1664; SI-NEXT:    s_cselect_b64 vcc, -1, 01665; SI-NEXT:    s_cmp_eq_u32 s7, 151666; SI-NEXT:    s_waitcnt vmcnt(0)1667; SI-NEXT:    v_lshrrev_b32_e32 v15, 16, v31668; SI-NEXT:    v_and_b32_e32 v7, 0xffff, v71669; SI-NEXT:    v_lshlrev_b32_e32 v12, 16, v121670; SI-NEXT:    v_cndmask_b32_e32 v3, v3, v6, vcc1671; SI-NEXT:    s_cselect_b64 vcc, -1, 01672; SI-NEXT:    s_cmp_eq_u32 s7, 121673; SI-NEXT:    v_or_b32_e32 v7, v7, v121674; SI-NEXT:    v_cndmask_b32_e32 v12, v15, v6, vcc1675; SI-NEXT:    s_cselect_b64 vcc, -1, 01676; SI-NEXT:    s_cmp_eq_u32 s7, 131677; SI-NEXT:    v_lshrrev_b32_e32 v16, 16, v21678; SI-NEXT:    v_and_b32_e32 v3, 0xffff, v31679; SI-NEXT:    v_lshlrev_b32_e32 v12, 16, v121680; SI-NEXT:    v_cndmask_b32_e32 v2, v2, v6, vcc1681; SI-NEXT:    s_cselect_b64 vcc, -1, 01682; SI-NEXT:    s_cmp_eq_u32 s7, 101683; SI-NEXT:    v_or_b32_e32 v3, v3, v121684; SI-NEXT:    v_cndmask_b32_e32 v12, v16, v6, vcc1685; SI-NEXT:    s_cselect_b64 vcc, -1, 01686; SI-NEXT:    s_cmp_eq_u32 s7, 111687; SI-NEXT:    v_lshrrev_b32_e32 v17, 16, v11688; SI-NEXT:    v_and_b32_e32 v2, 0xffff, v21689; SI-NEXT:    v_lshlrev_b32_e32 v12, 16, v121690; SI-NEXT:    v_cndmask_b32_e32 v1, v1, v6, vcc1691; SI-NEXT:    s_cselect_b64 vcc, -1, 01692; SI-NEXT:    s_cmp_eq_u32 s7, 81693; SI-NEXT:    v_and_b32_e32 v9, 0xffff, v91694; SI-NEXT:    v_or_b32_e32 v2, v2, v121695; SI-NEXT:    v_cndmask_b32_e32 v12, v17, v6, vcc1696; SI-NEXT:    s_cselect_b64 vcc, -1, 01697; SI-NEXT:    s_cmp_eq_u32 s7, 91698; SI-NEXT:    v_or_b32_e32 v9, v9, v111699; SI-NEXT:    v_lshrrev_b32_e32 v11, 16, v01700; SI-NEXT:    v_cndmask_b32_e32 v0, v0, v6, vcc1701; SI-NEXT:    s_cselect_b64 vcc, -1, 01702; SI-NEXT:    v_cndmask_b32_e32 v6, v11, v6, vcc1703; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v11704; SI-NEXT:    v_lshlrev_b32_e32 v12, 16, v121705; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v01706; SI-NEXT:    v_lshlrev_b32_e32 v6, 16, v61707; SI-NEXT:    v_or_b32_e32 v1, v1, v121708; SI-NEXT:    v_or_b32_e32 v0, v0, v61709; SI-NEXT:    buffer_store_dwordx4 v[0:3], v[4:5], s[12:15], 0 addr64 offset:161710; SI-NEXT:    buffer_store_dwordx4 v[7:10], v[4:5], s[12:15], 0 addr641711; SI-NEXT:    s_endpgm1712;1713; VI-LABEL: v_insertelement_v16bf16_dynamic:1714; VI:       ; %bb.0:1715; VI-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x01716; VI-NEXT:    s_load_dwordx2 s[6:7], s[8:9], 0x101717; VI-NEXT:    v_lshlrev_b32_e32 v8, 5, v01718; VI-NEXT:    s_add_i32 s12, s12, s171719; VI-NEXT:    s_mov_b32 flat_scratch_lo, s131720; VI-NEXT:    s_waitcnt lgkmcnt(0)1721; VI-NEXT:    v_mov_b32_e32 v0, s31722; VI-NEXT:    v_add_u32_e32 v4, vcc, s2, v81723; VI-NEXT:    v_addc_u32_e32 v5, vcc, 0, v0, vcc1724; VI-NEXT:    v_add_u32_e32 v0, vcc, 16, v41725; VI-NEXT:    s_lshr_b32 flat_scratch_hi, s12, 81726; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v5, vcc1727; VI-NEXT:    flat_load_dwordx4 v[0:3], v[0:1]1728; VI-NEXT:    flat_load_dwordx4 v[4:7], v[4:5]1729; VI-NEXT:    v_mov_b32_e32 v9, s11730; VI-NEXT:    v_add_u32_e32 v8, vcc, s0, v81731; VI-NEXT:    v_addc_u32_e32 v9, vcc, 0, v9, vcc1732; VI-NEXT:    v_add_u32_e32 v10, vcc, 16, v81733; VI-NEXT:    s_cmp_eq_u32 s7, 141734; VI-NEXT:    v_addc_u32_e32 v11, vcc, 0, v9, vcc1735; VI-NEXT:    v_mov_b32_e32 v12, s61736; VI-NEXT:    s_cselect_b64 vcc, -1, 01737; VI-NEXT:    s_cmp_eq_u32 s7, 151738; VI-NEXT:    s_waitcnt vmcnt(1)1739; VI-NEXT:    v_cndmask_b32_e32 v13, v3, v12, vcc1740; VI-NEXT:    s_cselect_b64 vcc, -1, 01741; VI-NEXT:    s_cmp_eq_u32 s7, 121742; VI-NEXT:    s_cselect_b64 s[0:1], -1, 01743; VI-NEXT:    s_cmp_eq_u32 s7, 131744; VI-NEXT:    v_lshrrev_b32_e32 v14, 16, v21745; VI-NEXT:    v_cndmask_b32_e64 v2, v2, v12, s[0:1]1746; VI-NEXT:    s_cselect_b64 s[0:1], -1, 01747; VI-NEXT:    s_cmp_eq_u32 s7, 101748; VI-NEXT:    s_cselect_b64 s[2:3], -1, 01749; VI-NEXT:    s_cmp_eq_u32 s7, 111750; VI-NEXT:    v_lshrrev_b32_e32 v15, 16, v11751; VI-NEXT:    v_cndmask_b32_e64 v1, v1, v12, s[2:3]1752; VI-NEXT:    s_cselect_b64 s[2:3], -1, 01753; VI-NEXT:    s_cmp_eq_u32 s7, 81754; VI-NEXT:    v_lshrrev_b32_e32 v3, 16, v31755; VI-NEXT:    s_cselect_b64 s[4:5], -1, 01756; VI-NEXT:    v_cndmask_b32_e64 v15, v15, v12, s[2:3]1757; VI-NEXT:    s_cmp_eq_u32 s7, 91758; VI-NEXT:    v_lshrrev_b32_e32 v16, 16, v01759; VI-NEXT:    v_cndmask_b32_e32 v3, v3, v12, vcc1760; VI-NEXT:    v_lshlrev_b32_e32 v15, 16, v151761; VI-NEXT:    s_cselect_b64 vcc, -1, 01762; VI-NEXT:    s_cmp_eq_u32 s7, 61763; VI-NEXT:    v_or_b32_sdwa v1, v1, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD1764; VI-NEXT:    v_cndmask_b32_e32 v15, v16, v12, vcc1765; VI-NEXT:    s_cselect_b64 vcc, -1, 01766; VI-NEXT:    s_cmp_eq_u32 s7, 71767; VI-NEXT:    v_cndmask_b32_e64 v0, v0, v12, s[4:5]1768; VI-NEXT:    s_waitcnt vmcnt(0)1769; VI-NEXT:    v_lshrrev_b32_e32 v17, 16, v71770; VI-NEXT:    v_lshlrev_b32_e32 v3, 16, v31771; VI-NEXT:    v_cndmask_b32_e64 v14, v14, v12, s[0:1]1772; VI-NEXT:    v_lshlrev_b32_e32 v15, 16, v151773; VI-NEXT:    v_cndmask_b32_e32 v7, v7, v12, vcc1774; VI-NEXT:    s_cselect_b64 vcc, -1, 01775; VI-NEXT:    s_cmp_eq_u32 s7, 41776; VI-NEXT:    v_or_b32_sdwa v3, v13, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD1777; VI-NEXT:    v_lshlrev_b32_e32 v13, 16, v141778; VI-NEXT:    v_or_b32_sdwa v0, v0, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD1779; VI-NEXT:    v_cndmask_b32_e32 v15, v17, v12, vcc1780; VI-NEXT:    s_cselect_b64 vcc, -1, 01781; VI-NEXT:    s_cmp_eq_u32 s7, 51782; VI-NEXT:    v_or_b32_sdwa v2, v2, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD1783; VI-NEXT:    v_lshrrev_b32_e32 v13, 16, v61784; VI-NEXT:    v_cndmask_b32_e32 v6, v6, v12, vcc1785; VI-NEXT:    s_cselect_b64 vcc, -1, 01786; VI-NEXT:    s_cmp_eq_u32 s7, 21787; VI-NEXT:    v_cndmask_b32_e32 v13, v13, v12, vcc1788; VI-NEXT:    s_cselect_b64 vcc, -1, 01789; VI-NEXT:    s_cmp_eq_u32 s7, 31790; VI-NEXT:    v_lshrrev_b32_e32 v14, 16, v51791; VI-NEXT:    v_cndmask_b32_e32 v5, v5, v12, vcc1792; VI-NEXT:    s_cselect_b64 vcc, -1, 01793; VI-NEXT:    s_cmp_eq_u32 s7, 01794; VI-NEXT:    v_lshlrev_b32_e32 v13, 16, v131795; VI-NEXT:    v_cndmask_b32_e32 v14, v14, v12, vcc1796; VI-NEXT:    s_cselect_b64 vcc, -1, 01797; VI-NEXT:    s_cmp_eq_u32 s7, 11798; VI-NEXT:    v_or_b32_sdwa v6, v6, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD1799; VI-NEXT:    v_lshrrev_b32_e32 v13, 16, v41800; VI-NEXT:    v_cndmask_b32_e32 v4, v4, v12, vcc1801; VI-NEXT:    s_cselect_b64 vcc, -1, 01802; VI-NEXT:    v_cndmask_b32_e32 v12, v13, v12, vcc1803; VI-NEXT:    v_lshlrev_b32_e32 v15, 16, v151804; VI-NEXT:    v_lshlrev_b32_e32 v14, 16, v141805; VI-NEXT:    v_lshlrev_b32_e32 v12, 16, v121806; VI-NEXT:    v_or_b32_sdwa v7, v7, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD1807; VI-NEXT:    v_or_b32_sdwa v5, v5, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD1808; VI-NEXT:    v_or_b32_sdwa v4, v4, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD1809; VI-NEXT:    flat_store_dwordx4 v[8:9], v[4:7]1810; VI-NEXT:    flat_store_dwordx4 v[10:11], v[0:3]1811; VI-NEXT:    s_endpgm1812;1813; GFX900-LABEL: v_insertelement_v16bf16_dynamic:1814; GFX900:       ; %bb.0:1815; GFX900-NEXT:    s_load_dwordx4 s[36:39], s[8:9], 0x01816; GFX900-NEXT:    s_load_dwordx2 s[28:29], s[8:9], 0x101817; GFX900-NEXT:    v_lshlrev_b32_e32 v8, 5, v01818; GFX900-NEXT:    s_mov_b32 s30, 0x50401001819; GFX900-NEXT:    s_waitcnt lgkmcnt(0)1820; GFX900-NEXT:    global_load_dwordx4 v[0:3], v8, s[38:39]1821; GFX900-NEXT:    global_load_dwordx4 v[4:7], v8, s[38:39] offset:161822; GFX900-NEXT:    s_cmp_eq_u32 s29, 61823; GFX900-NEXT:    s_cselect_b64 vcc, -1, 01824; GFX900-NEXT:    s_cmp_eq_u32 s29, 71825; GFX900-NEXT:    s_cselect_b64 s[0:1], -1, 01826; GFX900-NEXT:    s_cmp_eq_u32 s29, 41827; GFX900-NEXT:    s_cselect_b64 s[2:3], -1, 01828; GFX900-NEXT:    s_cmp_eq_u32 s29, 51829; GFX900-NEXT:    s_cselect_b64 s[4:5], -1, 01830; GFX900-NEXT:    s_cmp_eq_u32 s29, 21831; GFX900-NEXT:    s_cselect_b64 s[6:7], -1, 01832; GFX900-NEXT:    s_cmp_eq_u32 s29, 31833; GFX900-NEXT:    s_cselect_b64 s[8:9], -1, 01834; GFX900-NEXT:    s_cmp_eq_u32 s29, 01835; GFX900-NEXT:    s_cselect_b64 s[10:11], -1, 01836; GFX900-NEXT:    s_cmp_eq_u32 s29, 11837; GFX900-NEXT:    s_cselect_b64 s[12:13], -1, 01838; GFX900-NEXT:    s_cmp_eq_u32 s29, 141839; GFX900-NEXT:    v_mov_b32_e32 v9, s281840; GFX900-NEXT:    s_cselect_b64 s[14:15], -1, 01841; GFX900-NEXT:    s_cmp_eq_u32 s29, 151842; GFX900-NEXT:    s_cselect_b64 s[16:17], -1, 01843; GFX900-NEXT:    s_cmp_eq_u32 s29, 121844; GFX900-NEXT:    s_cselect_b64 s[18:19], -1, 01845; GFX900-NEXT:    s_cmp_eq_u32 s29, 131846; GFX900-NEXT:    s_cselect_b64 s[20:21], -1, 01847; GFX900-NEXT:    s_cmp_eq_u32 s29, 101848; GFX900-NEXT:    s_cselect_b64 s[22:23], -1, 01849; GFX900-NEXT:    s_cmp_eq_u32 s29, 111850; GFX900-NEXT:    s_cselect_b64 s[24:25], -1, 01851; GFX900-NEXT:    s_cmp_eq_u32 s29, 81852; GFX900-NEXT:    s_cselect_b64 s[26:27], -1, 01853; GFX900-NEXT:    s_cmp_eq_u32 s29, 91854; GFX900-NEXT:    s_cselect_b64 s[28:29], -1, 01855; GFX900-NEXT:    s_waitcnt vmcnt(1)1856; GFX900-NEXT:    v_cndmask_b32_e32 v10, v3, v9, vcc1857; GFX900-NEXT:    s_mov_b64 vcc, s[0:1]1858; GFX900-NEXT:    v_cndmask_b32_sdwa v3, v3, v9, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1859; GFX900-NEXT:    s_mov_b64 vcc, s[4:5]1860; GFX900-NEXT:    v_cndmask_b32_e64 v11, v2, v9, s[2:3]1861; GFX900-NEXT:    v_cndmask_b32_sdwa v2, v2, v9, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1862; GFX900-NEXT:    s_mov_b64 vcc, s[8:9]1863; GFX900-NEXT:    v_cndmask_b32_e64 v12, v1, v9, s[6:7]1864; GFX900-NEXT:    v_cndmask_b32_sdwa v1, v1, v9, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1865; GFX900-NEXT:    s_mov_b64 vcc, s[12:13]1866; GFX900-NEXT:    v_cndmask_b32_e64 v13, v0, v9, s[10:11]1867; GFX900-NEXT:    v_cndmask_b32_sdwa v0, v0, v9, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1868; GFX900-NEXT:    s_mov_b64 vcc, s[16:17]1869; GFX900-NEXT:    s_waitcnt vmcnt(0)1870; GFX900-NEXT:    v_cndmask_b32_e64 v14, v7, v9, s[14:15]1871; GFX900-NEXT:    v_cndmask_b32_sdwa v7, v7, v9, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1872; GFX900-NEXT:    s_mov_b64 vcc, s[20:21]1873; GFX900-NEXT:    v_cndmask_b32_e64 v15, v6, v9, s[18:19]1874; GFX900-NEXT:    v_cndmask_b32_sdwa v6, v6, v9, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1875; GFX900-NEXT:    s_mov_b64 vcc, s[24:25]1876; GFX900-NEXT:    v_perm_b32 v3, v3, v10, s301877; GFX900-NEXT:    v_cndmask_b32_e64 v10, v5, v9, s[22:23]1878; GFX900-NEXT:    v_cndmask_b32_sdwa v5, v5, v9, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1879; GFX900-NEXT:    s_mov_b64 vcc, s[28:29]1880; GFX900-NEXT:    v_perm_b32 v2, v2, v11, s301881; GFX900-NEXT:    v_cndmask_b32_e64 v11, v4, v9, s[26:27]1882; GFX900-NEXT:    v_cndmask_b32_sdwa v4, v4, v9, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1883; GFX900-NEXT:    v_perm_b32 v7, v7, v14, s301884; GFX900-NEXT:    v_perm_b32 v6, v6, v15, s301885; GFX900-NEXT:    v_perm_b32 v5, v5, v10, s301886; GFX900-NEXT:    v_perm_b32 v4, v4, v11, s301887; GFX900-NEXT:    v_perm_b32 v1, v1, v12, s301888; GFX900-NEXT:    v_perm_b32 v0, v0, v13, s301889; GFX900-NEXT:    global_store_dwordx4 v8, v[4:7], s[36:37] offset:161890; GFX900-NEXT:    global_store_dwordx4 v8, v[0:3], s[36:37]1891; GFX900-NEXT:    s_endpgm1892;1893; GFX942-LABEL: v_insertelement_v16bf16_dynamic:1894; GFX942:       ; %bb.0:1895; GFX942-NEXT:    s_load_dwordx4 s[36:39], s[4:5], 0x01896; GFX942-NEXT:    s_load_dwordx2 s[28:29], s[4:5], 0x101897; GFX942-NEXT:    v_and_b32_e32 v0, 0x3ff, v01898; GFX942-NEXT:    v_lshlrev_b32_e32 v8, 5, v01899; GFX942-NEXT:    s_mov_b32 s30, 0x50401001900; GFX942-NEXT:    s_waitcnt lgkmcnt(0)1901; GFX942-NEXT:    global_load_dwordx4 v[0:3], v8, s[38:39]1902; GFX942-NEXT:    global_load_dwordx4 v[4:7], v8, s[38:39] offset:161903; GFX942-NEXT:    s_cmp_eq_u32 s29, 61904; GFX942-NEXT:    s_cselect_b64 vcc, -1, 01905; GFX942-NEXT:    s_cmp_eq_u32 s29, 71906; GFX942-NEXT:    s_cselect_b64 s[0:1], -1, 01907; GFX942-NEXT:    s_cmp_eq_u32 s29, 41908; GFX942-NEXT:    s_cselect_b64 s[2:3], -1, 01909; GFX942-NEXT:    s_cmp_eq_u32 s29, 51910; GFX942-NEXT:    s_cselect_b64 s[4:5], -1, 01911; GFX942-NEXT:    s_cmp_eq_u32 s29, 21912; GFX942-NEXT:    s_cselect_b64 s[6:7], -1, 01913; GFX942-NEXT:    s_cmp_eq_u32 s29, 31914; GFX942-NEXT:    s_cselect_b64 s[8:9], -1, 01915; GFX942-NEXT:    s_cmp_eq_u32 s29, 01916; GFX942-NEXT:    s_cselect_b64 s[10:11], -1, 01917; GFX942-NEXT:    s_cmp_eq_u32 s29, 11918; GFX942-NEXT:    s_cselect_b64 s[12:13], -1, 01919; GFX942-NEXT:    s_cmp_eq_u32 s29, 141920; GFX942-NEXT:    v_mov_b32_e32 v9, s281921; GFX942-NEXT:    s_cselect_b64 s[14:15], -1, 01922; GFX942-NEXT:    s_cmp_eq_u32 s29, 151923; GFX942-NEXT:    s_cselect_b64 s[16:17], -1, 01924; GFX942-NEXT:    s_cmp_eq_u32 s29, 121925; GFX942-NEXT:    s_cselect_b64 s[18:19], -1, 01926; GFX942-NEXT:    s_cmp_eq_u32 s29, 131927; GFX942-NEXT:    s_cselect_b64 s[20:21], -1, 01928; GFX942-NEXT:    s_cmp_eq_u32 s29, 101929; GFX942-NEXT:    s_cselect_b64 s[22:23], -1, 01930; GFX942-NEXT:    s_cmp_eq_u32 s29, 111931; GFX942-NEXT:    s_cselect_b64 s[24:25], -1, 01932; GFX942-NEXT:    s_cmp_eq_u32 s29, 81933; GFX942-NEXT:    s_cselect_b64 s[26:27], -1, 01934; GFX942-NEXT:    s_cmp_eq_u32 s29, 91935; GFX942-NEXT:    s_cselect_b64 s[28:29], -1, 01936; GFX942-NEXT:    s_waitcnt vmcnt(1)1937; GFX942-NEXT:    v_cndmask_b32_e32 v10, v3, v9, vcc1938; GFX942-NEXT:    s_mov_b64 vcc, s[0:1]1939; GFX942-NEXT:    v_cndmask_b32_sdwa v3, v3, v9, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1940; GFX942-NEXT:    s_mov_b64 vcc, s[4:5]1941; GFX942-NEXT:    v_cndmask_b32_e64 v11, v2, v9, s[2:3]1942; GFX942-NEXT:    v_cndmask_b32_sdwa v2, v2, v9, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1943; GFX942-NEXT:    s_mov_b64 vcc, s[8:9]1944; GFX942-NEXT:    v_cndmask_b32_e64 v12, v1, v9, s[6:7]1945; GFX942-NEXT:    v_cndmask_b32_sdwa v1, v1, v9, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1946; GFX942-NEXT:    s_mov_b64 vcc, s[12:13]1947; GFX942-NEXT:    v_cndmask_b32_e64 v13, v0, v9, s[10:11]1948; GFX942-NEXT:    v_cndmask_b32_sdwa v0, v0, v9, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1949; GFX942-NEXT:    s_mov_b64 vcc, s[16:17]1950; GFX942-NEXT:    s_waitcnt vmcnt(0)1951; GFX942-NEXT:    v_cndmask_b32_e64 v14, v7, v9, s[14:15]1952; GFX942-NEXT:    v_cndmask_b32_sdwa v7, v7, v9, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1953; GFX942-NEXT:    s_mov_b64 vcc, s[20:21]1954; GFX942-NEXT:    v_cndmask_b32_e64 v15, v6, v9, s[18:19]1955; GFX942-NEXT:    v_cndmask_b32_sdwa v6, v6, v9, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1956; GFX942-NEXT:    s_mov_b64 vcc, s[24:25]1957; GFX942-NEXT:    v_cndmask_b32_e64 v16, v5, v9, s[22:23]1958; GFX942-NEXT:    v_cndmask_b32_sdwa v5, v5, v9, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1959; GFX942-NEXT:    s_mov_b64 vcc, s[28:29]1960; GFX942-NEXT:    v_cndmask_b32_e64 v17, v4, v9, s[26:27]1961; GFX942-NEXT:    v_cndmask_b32_sdwa v4, v4, v9, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1962; GFX942-NEXT:    v_perm_b32 v7, v7, v14, s301963; GFX942-NEXT:    v_perm_b32 v6, v6, v15, s301964; GFX942-NEXT:    v_perm_b32 v5, v5, v16, s301965; GFX942-NEXT:    v_perm_b32 v4, v4, v17, s301966; GFX942-NEXT:    v_perm_b32 v3, v3, v10, s301967; GFX942-NEXT:    v_perm_b32 v2, v2, v11, s301968; GFX942-NEXT:    v_perm_b32 v1, v1, v12, s301969; GFX942-NEXT:    v_perm_b32 v0, v0, v13, s301970; GFX942-NEXT:    global_store_dwordx4 v8, v[4:7], s[36:37] offset:161971; GFX942-NEXT:    global_store_dwordx4 v8, v[0:3], s[36:37]1972; GFX942-NEXT:    s_endpgm1973;1974; GFX1250-LABEL: v_insertelement_v16bf16_dynamic:1975; GFX1250:       ; %bb.0:1976; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11977; GFX1250-NEXT:    s_load_b128 s[0:3], s[4:5], 0x01978; GFX1250-NEXT:    v_and_b32_e32 v0, 0x3ff, v01979; GFX1250-NEXT:    s_wait_xcnt 0x01980; GFX1250-NEXT:    s_load_b64 s[4:5], s[4:5], 0x101981; GFX1250-NEXT:    s_delay_alu instid0(VALU_DEP_1)1982; GFX1250-NEXT:    v_lshlrev_b32_e32 v8, 5, v01983; GFX1250-NEXT:    s_wait_kmcnt 0x01984; GFX1250-NEXT:    s_clause 0x11985; GFX1250-NEXT:    global_load_b128 v[0:3], v8, s[2:3]1986; GFX1250-NEXT:    global_load_b128 v[4:7], v8, s[2:3] offset:161987; GFX1250-NEXT:    s_cmp_eq_u32 s5, 61988; GFX1250-NEXT:    s_wait_xcnt 0x01989; GFX1250-NEXT:    s_cselect_b32 s2, -1, 01990; GFX1250-NEXT:    s_cmp_eq_u32 s5, 71991; GFX1250-NEXT:    s_wait_loadcnt 0x11992; GFX1250-NEXT:    v_cndmask_b32_e64 v9, v3, s4, s21993; GFX1250-NEXT:    s_cselect_b32 s2, -1, 01994; GFX1250-NEXT:    s_cmp_eq_u32 s5, 41995; GFX1250-NEXT:    v_lshrrev_b32_e32 v3, 16, v31996; GFX1250-NEXT:    s_cselect_b32 s3, -1, 01997; GFX1250-NEXT:    s_cmp_eq_u32 s5, 51998; GFX1250-NEXT:    v_dual_lshrrev_b32 v10, 16, v2 :: v_dual_lshrrev_b32 v11, 16, v11999; GFX1250-NEXT:    v_cndmask_b32_e64 v2, v2, s4, s32000; GFX1250-NEXT:    s_cselect_b32 s3, -1, 02001; GFX1250-NEXT:    s_cmp_eq_u32 s5, 22002; GFX1250-NEXT:    v_cndmask_b32_e64 v3, v3, s4, s22003; GFX1250-NEXT:    s_cselect_b32 s2, -1, 02004; GFX1250-NEXT:    s_cmp_eq_u32 s5, 32005; GFX1250-NEXT:    v_cndmask_b32_e64 v1, v1, s4, s22006; GFX1250-NEXT:    s_cselect_b32 s2, -1, 02007; GFX1250-NEXT:    s_cmp_eq_u32 s5, 02008; GFX1250-NEXT:    s_wait_loadcnt 0x02009; GFX1250-NEXT:    v_dual_lshrrev_b32 v12, 16, v0 :: v_dual_lshrrev_b32 v13, 16, v72010; GFX1250-NEXT:    v_cndmask_b32_e64 v11, v11, s4, s22011; GFX1250-NEXT:    s_cselect_b32 s2, -1, 02012; GFX1250-NEXT:    s_cmp_eq_u32 s5, 12013; GFX1250-NEXT:    v_cndmask_b32_e64 v0, v0, s4, s22014; GFX1250-NEXT:    s_cselect_b32 s2, -1, 02015; GFX1250-NEXT:    s_cmp_eq_u32 s5, 142016; GFX1250-NEXT:    v_cndmask_b32_e64 v10, v10, s4, s32017; GFX1250-NEXT:    v_perm_b32 v3, v3, v9, 0x50401002018; GFX1250-NEXT:    v_cndmask_b32_e64 v9, v12, s4, s22019; GFX1250-NEXT:    s_cselect_b32 s2, -1, 02020; GFX1250-NEXT:    s_cmp_eq_u32 s5, 152021; GFX1250-NEXT:    v_cndmask_b32_e64 v7, v7, s4, s22022; GFX1250-NEXT:    s_cselect_b32 s2, -1, 02023; GFX1250-NEXT:    s_cmp_eq_u32 s5, 122024; GFX1250-NEXT:    v_dual_lshrrev_b32 v14, 16, v6 :: v_dual_lshrrev_b32 v15, 16, v52025; GFX1250-NEXT:    v_perm_b32 v2, v10, v2, 0x50401002026; GFX1250-NEXT:    v_cndmask_b32_e64 v10, v13, s4, s22027; GFX1250-NEXT:    s_cselect_b32 s2, -1, 02028; GFX1250-NEXT:    s_cmp_eq_u32 s5, 132029; GFX1250-NEXT:    v_cndmask_b32_e64 v6, v6, s4, s22030; GFX1250-NEXT:    s_cselect_b32 s2, -1, 02031; GFX1250-NEXT:    s_cmp_eq_u32 s5, 102032; GFX1250-NEXT:    v_cndmask_b32_e64 v12, v14, s4, s22033; GFX1250-NEXT:    s_cselect_b32 s2, -1, 02034; GFX1250-NEXT:    s_cmp_eq_u32 s5, 112035; GFX1250-NEXT:    v_cndmask_b32_e64 v5, v5, s4, s22036; GFX1250-NEXT:    s_cselect_b32 s2, -1, 02037; GFX1250-NEXT:    s_cmp_eq_u32 s5, 82038; GFX1250-NEXT:    v_lshrrev_b32_e32 v16, 16, v42039; GFX1250-NEXT:    v_cndmask_b32_e64 v13, v15, s4, s22040; GFX1250-NEXT:    s_cselect_b32 s2, -1, 02041; GFX1250-NEXT:    s_cmp_eq_u32 s5, 92042; GFX1250-NEXT:    v_cndmask_b32_e64 v4, v4, s4, s22043; GFX1250-NEXT:    s_cselect_b32 s2, -1, 02044; GFX1250-NEXT:    v_perm_b32 v7, v10, v7, 0x50401002045; GFX1250-NEXT:    v_cndmask_b32_e64 v14, v16, s4, s22046; GFX1250-NEXT:    v_perm_b32 v6, v12, v6, 0x50401002047; GFX1250-NEXT:    v_perm_b32 v5, v13, v5, 0x50401002048; GFX1250-NEXT:    v_perm_b32 v1, v11, v1, 0x50401002049; GFX1250-NEXT:    v_perm_b32 v0, v9, v0, 0x50401002050; GFX1250-NEXT:    v_perm_b32 v4, v14, v4, 0x50401002051; GFX1250-NEXT:    s_clause 0x12052; GFX1250-NEXT:    global_store_b128 v8, v[4:7], s[0:1] offset:162053; GFX1250-NEXT:    global_store_b128 v8, v[0:3], s[0:1]2054; GFX1250-NEXT:    s_endpgm2055  %tid = call i32 @llvm.amdgcn.workitem.id.x() #12056  %tid.ext = sext i32 %tid to i642057  %in.gep = getelementptr inbounds <16 x bfloat>, ptr addrspace(1) %in, i64 %tid.ext2058  %out.gep = getelementptr inbounds <16 x bfloat>, ptr addrspace(1) %out, i64 %tid.ext2059  %vec = load <16 x bfloat>, ptr addrspace(1) %in.gep2060  %val.trunc = trunc i32 %val to i162061  %val.cvt = bitcast i16 %val.trunc to bfloat2062  %vecins = insertelement <16 x bfloat> %vec, bfloat %val.cvt, i32 %n2063  store <16 x bfloat> %vecins, ptr addrspace(1) %out.gep2064  ret void2065}2066 2067declare i32 @llvm.amdgcn.workitem.id.x() #12068 2069attributes #0 = { nounwind }2070attributes #1 = { nounwind readnone }2071