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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 < %s | FileCheck -check-prefixes=GCN,GFX7 %s3; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9 %s4; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s5; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s6 7; Demonstrate that the conversion of bitmasks affecting the sign bit on integers to srcmods8; does not apply to canonicalizing instructions.9 10define double @v_uitofp_i32_to_f64_abs(i32 %arg0) nounwind {11; GCN-LABEL: v_uitofp_i32_to_f64_abs:12; GCN: ; %bb.0:13; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)14; GCN-NEXT: v_and_b32_e32 v0, 0x7fffffff, v015; GCN-NEXT: v_cvt_f64_u32_e32 v[0:1], v016; GCN-NEXT: s_setpc_b64 s[30:31]17;18; GFX11-LABEL: v_uitofp_i32_to_f64_abs:19; GFX11: ; %bb.0:20; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)21; GFX11-NEXT: v_and_b32_e32 v0, 0x7fffffff, v022; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)23; GFX11-NEXT: v_cvt_f64_u32_e32 v[0:1], v024; GFX11-NEXT: s_setpc_b64 s[30:31]25 %arg0.abs = and i32 %arg0, u0x7fffffff26 %cvt = uitofp i32 %arg0.abs to double27 ret double %cvt28}29 30define double @v_uitofp_i32_to_f64_neg(i32 %arg0) nounwind {31; GCN-LABEL: v_uitofp_i32_to_f64_neg:32; GCN: ; %bb.0:33; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)34; GCN-NEXT: v_and_b32_e32 v0, 0x80000000, v035; GCN-NEXT: v_cvt_f64_u32_e32 v[0:1], v036; GCN-NEXT: s_setpc_b64 s[30:31]37;38; GFX11-LABEL: v_uitofp_i32_to_f64_neg:39; GFX11: ; %bb.0:40; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)41; GFX11-NEXT: v_and_b32_e32 v0, 0x80000000, v042; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)43; GFX11-NEXT: v_cvt_f64_u32_e32 v[0:1], v044; GFX11-NEXT: s_setpc_b64 s[30:31]45 %arg0.neg = and i32 %arg0, u0x8000000046 %cvt = uitofp i32 %arg0.neg to double47 ret double %cvt48}49 50define double @s_uitofp_i32_to_f64_abs(i32 inreg %arg0) nounwind {51; GCN-LABEL: s_uitofp_i32_to_f64_abs:52; GCN: ; %bb.0:53; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)54; GCN-NEXT: s_bitset0_b32 s16, 3155; GCN-NEXT: v_cvt_f64_u32_e32 v[0:1], s1656; GCN-NEXT: s_setpc_b64 s[30:31]57;58; GFX11-LABEL: s_uitofp_i32_to_f64_abs:59; GFX11: ; %bb.0:60; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)61; GFX11-NEXT: s_bitset0_b32 s0, 3162; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)63; GFX11-NEXT: v_cvt_f64_u32_e32 v[0:1], s064; GFX11-NEXT: s_setpc_b64 s[30:31]65 %arg0.abs = and i32 %arg0, u0x7fffffff66 %cvt = uitofp i32 %arg0.abs to double67 ret double %cvt68}69 70define double @s_uitofp_i32_to_f64_neg(i32 inreg %arg0) nounwind {71; GCN-LABEL: s_uitofp_i32_to_f64_neg:72; GCN: ; %bb.0:73; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)74; GCN-NEXT: s_and_b32 s4, s16, 0x8000000075; GCN-NEXT: v_cvt_f64_u32_e32 v[0:1], s476; GCN-NEXT: s_setpc_b64 s[30:31]77;78; GFX11-LABEL: s_uitofp_i32_to_f64_neg:79; GFX11: ; %bb.0:80; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)81; GFX11-NEXT: s_and_b32 s0, s0, 0x8000000082; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)83; GFX11-NEXT: v_cvt_f64_u32_e32 v[0:1], s084; GFX11-NEXT: s_setpc_b64 s[30:31]85 %arg0.neg = and i32 %arg0, u0x8000000086 %cvt = uitofp i32 %arg0.neg to double87 ret double %cvt88}89 90define half @v_uitofp_i16_to_f16_abs(i16 %arg0) nounwind {91; GFX7-LABEL: v_uitofp_i16_to_f16_abs:92; GFX7: ; %bb.0:93; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)94; GFX7-NEXT: v_and_b32_e32 v0, 0x7fff, v095; GFX7-NEXT: v_cvt_f32_u32_e32 v0, v096; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v097; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v098; GFX7-NEXT: s_setpc_b64 s[30:31]99;100; GFX9-LABEL: v_uitofp_i16_to_f16_abs:101; GFX9: ; %bb.0:102; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)103; GFX9-NEXT: v_and_b32_e32 v0, 0x7fff, v0104; GFX9-NEXT: v_cvt_f16_u16_e32 v0, v0105; GFX9-NEXT: s_setpc_b64 s[30:31]106;107; GFX11-TRUE16-LABEL: v_uitofp_i16_to_f16_abs:108; GFX11-TRUE16: ; %bb.0:109; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)110; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0x7fff, v0.l111; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)112; GFX11-TRUE16-NEXT: v_cvt_f16_u16_e32 v0.l, v0.l113; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]114;115; GFX11-FAKE16-LABEL: v_uitofp_i16_to_f16_abs:116; GFX11-FAKE16: ; %bb.0:117; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)118; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0x7fff, v0119; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)120; GFX11-FAKE16-NEXT: v_cvt_f16_u16_e32 v0, v0121; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]122 %arg0.abs = and i16 %arg0, u0x7fff123 %cvt = uitofp i16 %arg0.abs to half124 ret half %cvt125}126 127define half @v_uitofp_i16_to_f16_neg(i16 %arg0) nounwind {128; GFX7-LABEL: v_uitofp_i16_to_f16_neg:129; GFX7: ; %bb.0:130; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)131; GFX7-NEXT: v_and_b32_e32 v0, 0x8000, v0132; GFX7-NEXT: v_cvt_f32_u32_e32 v0, v0133; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0134; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0135; GFX7-NEXT: s_setpc_b64 s[30:31]136;137; GFX9-LABEL: v_uitofp_i16_to_f16_neg:138; GFX9: ; %bb.0:139; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)140; GFX9-NEXT: v_and_b32_e32 v0, 0xffff8000, v0141; GFX9-NEXT: v_cvt_f16_u16_e32 v0, v0142; GFX9-NEXT: s_setpc_b64 s[30:31]143;144; GFX11-TRUE16-LABEL: v_uitofp_i16_to_f16_neg:145; GFX11-TRUE16: ; %bb.0:146; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)147; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0x8000, v0.l148; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)149; GFX11-TRUE16-NEXT: v_cvt_f16_u16_e32 v0.l, v0.l150; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]151;152; GFX11-FAKE16-LABEL: v_uitofp_i16_to_f16_neg:153; GFX11-FAKE16: ; %bb.0:154; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)155; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff8000, v0156; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)157; GFX11-FAKE16-NEXT: v_cvt_f16_u16_e32 v0, v0158; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]159 %arg0.neg = and i16 %arg0, u0x8000160 %cvt = uitofp i16 %arg0.neg to half161 ret half %cvt162}163 164define half @s_uitofp_i16_to_f16_abs(i16 inreg %arg0) nounwind {165; GFX7-LABEL: s_uitofp_i16_to_f16_abs:166; GFX7: ; %bb.0:167; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)168; GFX7-NEXT: s_and_b32 s4, s16, 0x7fff169; GFX7-NEXT: v_cvt_f32_u32_e32 v0, s4170; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0171; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0172; GFX7-NEXT: s_setpc_b64 s[30:31]173;174; GFX9-LABEL: s_uitofp_i16_to_f16_abs:175; GFX9: ; %bb.0:176; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)177; GFX9-NEXT: s_and_b32 s4, s16, 0x7fff178; GFX9-NEXT: v_cvt_f16_u16_e32 v0, s4179; GFX9-NEXT: s_setpc_b64 s[30:31]180;181; GFX11-TRUE16-LABEL: s_uitofp_i16_to_f16_abs:182; GFX11-TRUE16: ; %bb.0:183; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)184; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, 0x7fff185; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)186; GFX11-TRUE16-NEXT: v_cvt_f16_u16_e32 v0.l, s0187; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]188;189; GFX11-FAKE16-LABEL: s_uitofp_i16_to_f16_abs:190; GFX11-FAKE16: ; %bb.0:191; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)192; GFX11-FAKE16-NEXT: s_and_b32 s0, s0, 0x7fff193; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)194; GFX11-FAKE16-NEXT: v_cvt_f16_u16_e32 v0, s0195; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]196 %arg0.abs = and i16 %arg0, u0x7fff197 %cvt = uitofp i16 %arg0.abs to half198 ret half %cvt199}200 201define half @s_uitofp_i16_to_f16_neg(i16 inreg %arg0) nounwind {202; GFX7-LABEL: s_uitofp_i16_to_f16_neg:203; GFX7: ; %bb.0:204; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)205; GFX7-NEXT: s_and_b32 s4, s16, 0x8000206; GFX7-NEXT: v_cvt_f32_u32_e32 v0, s4207; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0208; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0209; GFX7-NEXT: s_setpc_b64 s[30:31]210;211; GFX9-LABEL: s_uitofp_i16_to_f16_neg:212; GFX9: ; %bb.0:213; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)214; GFX9-NEXT: s_and_b32 s4, s16, 0x8000215; GFX9-NEXT: v_cvt_f16_u16_e32 v0, s4216; GFX9-NEXT: s_setpc_b64 s[30:31]217;218; GFX11-TRUE16-LABEL: s_uitofp_i16_to_f16_neg:219; GFX11-TRUE16: ; %bb.0:220; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)221; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, 0x8000222; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)223; GFX11-TRUE16-NEXT: v_cvt_f16_u16_e32 v0.l, s0224; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]225;226; GFX11-FAKE16-LABEL: s_uitofp_i16_to_f16_neg:227; GFX11-FAKE16: ; %bb.0:228; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)229; GFX11-FAKE16-NEXT: s_and_b32 s0, s0, 0x8000230; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)231; GFX11-FAKE16-NEXT: v_cvt_f16_u16_e32 v0, s0232; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]233 %arg0.neg = and i16 %arg0, u0x8000234 %cvt = uitofp i16 %arg0.neg to half235 ret half %cvt236}237 238