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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 < %s | FileCheck -check-prefixes=GCN,GFX7 %s3; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9 %s4; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s5; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s6 7define i32 @fneg_select_i32_1(i32 %cond, i32 %a, i32 %b) {8; GCN-LABEL: fneg_select_i32_1:9; GCN: ; %bb.0:10; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)11; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v012; GCN-NEXT: v_cndmask_b32_e64 v0, v2, -v1, vcc13; GCN-NEXT: s_setpc_b64 s[30:31]14;15; GFX11-LABEL: fneg_select_i32_1:16; GFX11: ; %bb.0:17; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)18; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v019; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, -v1, vcc_lo20; GFX11-NEXT: s_setpc_b64 s[30:31]21 %neg.a = xor i32 %a, u0x8000000022 %cmp = icmp eq i32 %cond, zeroinitializer23 %select = select i1 %cmp, i32 %neg.a, i32 %b24 ret i32 %select25}26 27define i32 @fneg_select_i32_2(i32 %cond, i32 %a, i32 %b) {28; GCN-LABEL: fneg_select_i32_2:29; GCN: ; %bb.0:30; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)31; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v032; GCN-NEXT: v_cndmask_b32_e64 v0, -v1, v2, vcc33; GCN-NEXT: s_setpc_b64 s[30:31]34;35; GFX11-LABEL: fneg_select_i32_2:36; GFX11: ; %bb.0:37; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)38; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v039; GFX11-NEXT: v_cndmask_b32_e64 v0, -v1, v2, vcc_lo40; GFX11-NEXT: s_setpc_b64 s[30:31]41 %neg.a = xor i32 %a, u0x8000000042 %cmp = icmp eq i32 %cond, zeroinitializer43 %select = select i1 %cmp, i32 %b, i32 %neg.a44 ret i32 %select45}46 47define i32 @fneg_select_i32_both(i32 %cond, i32 %a, i32 %b) {48; GCN-LABEL: fneg_select_i32_both:49; GCN: ; %bb.0:50; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)51; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v052; GCN-NEXT: v_cndmask_b32_e64 v0, -v2, -v1, vcc53; GCN-NEXT: s_setpc_b64 s[30:31]54;55; GFX11-LABEL: fneg_select_i32_both:56; GFX11: ; %bb.0:57; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)58; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v059; GFX11-NEXT: v_cndmask_b32_e64 v0, -v2, -v1, vcc_lo60; GFX11-NEXT: s_setpc_b64 s[30:31]61 %neg.a = xor i32 %a, u0x8000000062 %neg.b = xor i32 %b, u0x8000000063 %cmp = icmp eq i32 %cond, zeroinitializer64 %select = select i1 %cmp, i32 %neg.a, i32 %neg.b65 ret i32 %select66}67 68define i32 @fneg_1_fabs_2_select_i32(i32 %cond, i32 %a, i32 %b) {69; GCN-LABEL: fneg_1_fabs_2_select_i32:70; GCN: ; %bb.0:71; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)72; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v073; GCN-NEXT: v_cndmask_b32_e64 v0, |v1|, -v1, vcc74; GCN-NEXT: s_setpc_b64 s[30:31]75;76; GFX11-LABEL: fneg_1_fabs_2_select_i32:77; GFX11: ; %bb.0:78; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)79; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v080; GFX11-NEXT: v_cndmask_b32_e64 v0, |v1|, -v1, vcc_lo81; GFX11-NEXT: s_setpc_b64 s[30:31]82 %neg.a = xor i32 %a, u0x8000000083 %abs.b = and i32 %a, u0x7fffffff84 %cmp = icmp eq i32 %cond, zeroinitializer85 %select = select i1 %cmp, i32 %neg.a, i32 %abs.b86 ret i32 %select87}88 89define i32 @s_fneg_select_i32_1(i32 inreg %cond, i32 inreg %a, i32 inreg %b) {90; GCN-LABEL: s_fneg_select_i32_1:91; GCN: ; %bb.0:92; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)93; GCN-NEXT: s_xor_b32 s4, s17, 0x8000000094; GCN-NEXT: s_cmp_eq_u32 s16, 095; GCN-NEXT: s_cselect_b32 s4, s4, s1896; GCN-NEXT: v_mov_b32_e32 v0, s497; GCN-NEXT: s_setpc_b64 s[30:31]98;99; GFX11-LABEL: s_fneg_select_i32_1:100; GFX11: ; %bb.0:101; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)102; GFX11-NEXT: s_xor_b32 s1, s1, 0x80000000103; GFX11-NEXT: s_cmp_eq_u32 s0, 0104; GFX11-NEXT: s_cselect_b32 s0, s1, s2105; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)106; GFX11-NEXT: v_mov_b32_e32 v0, s0107; GFX11-NEXT: s_setpc_b64 s[30:31]108 %neg.a = xor i32 %a, u0x80000000109 %cmp = icmp eq i32 %cond, zeroinitializer110 %select = select i1 %cmp, i32 %neg.a, i32 %b111 ret i32 %select112}113 114define i32 @s_fneg_1_fabs_2_select_i32(i32 inreg %cond, i32 %a, i32 %b) {115; GCN-LABEL: s_fneg_1_fabs_2_select_i32:116; GCN: ; %bb.0:117; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)118; GCN-NEXT: s_cmp_eq_u32 s16, 0119; GCN-NEXT: s_cselect_b64 s[4:5], -1, 0120; GCN-NEXT: v_cndmask_b32_e64 v0, |v0|, -v0, s[4:5]121; GCN-NEXT: s_setpc_b64 s[30:31]122;123; GFX11-LABEL: s_fneg_1_fabs_2_select_i32:124; GFX11: ; %bb.0:125; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)126; GFX11-NEXT: s_cmp_eq_u32 s0, 0127; GFX11-NEXT: s_cselect_b32 s0, -1, 0128; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)129; GFX11-NEXT: v_cndmask_b32_e64 v0, |v0|, -v0, s0130; GFX11-NEXT: s_setpc_b64 s[30:31]131 %neg.a = xor i32 %a, u0x80000000132 %abs.b = and i32 %a, u0x7fffffff133 %cmp = icmp eq i32 %cond, zeroinitializer134 %select = select i1 %cmp, i32 %neg.a, i32 %abs.b135 ret i32 %select136}137 138define <2 x i32> @fneg_select_v2i32_1(<2 x i32> %cond, <2 x i32> %a, <2 x i32> %b) {139; GCN-LABEL: fneg_select_v2i32_1:140; GCN: ; %bb.0:141; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)142; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0143; GCN-NEXT: v_cndmask_b32_e64 v0, v4, -v2, vcc144; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1145; GCN-NEXT: v_cndmask_b32_e64 v1, v5, -v3, vcc146; GCN-NEXT: s_setpc_b64 s[30:31]147;148; GFX11-LABEL: fneg_select_v2i32_1:149; GFX11: ; %bb.0:150; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)151; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0152; GFX11-NEXT: v_cndmask_b32_e64 v0, v4, -v2, vcc_lo153; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1154; GFX11-NEXT: v_cndmask_b32_e64 v1, v5, -v3, vcc_lo155; GFX11-NEXT: s_setpc_b64 s[30:31]156 %neg.a = xor <2 x i32> %a, splat (i32 u0x80000000)157 %cmp = icmp eq <2 x i32> %cond, zeroinitializer158 %select = select <2 x i1> %cmp, <2 x i32> %neg.a, <2 x i32> %b159 ret <2 x i32> %select160}161 162define <2 x i32> @fneg_select_v2i32_2(<2 x i32> %cond, <2 x i32> %a, <2 x i32> %b) {163; GCN-LABEL: fneg_select_v2i32_2:164; GCN: ; %bb.0:165; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)166; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0167; GCN-NEXT: v_cndmask_b32_e64 v0, -v2, v4, vcc168; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1169; GCN-NEXT: v_cndmask_b32_e64 v1, -v3, v5, vcc170; GCN-NEXT: s_setpc_b64 s[30:31]171;172; GFX11-LABEL: fneg_select_v2i32_2:173; GFX11: ; %bb.0:174; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)175; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0176; GFX11-NEXT: v_cndmask_b32_e64 v0, -v2, v4, vcc_lo177; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1178; GFX11-NEXT: v_cndmask_b32_e64 v1, -v3, v5, vcc_lo179; GFX11-NEXT: s_setpc_b64 s[30:31]180 %neg.a = xor <2 x i32> %a, splat (i32 u0x80000000)181 %cmp = icmp eq <2 x i32> %cond, zeroinitializer182 %select = select <2 x i1> %cmp, <2 x i32> %b, <2 x i32> %neg.a183 ret <2 x i32> %select184}185 186define i32 @fabs_select_i32_1(i32 %cond, i32 %a, i32 %b) {187; GCN-LABEL: fabs_select_i32_1:188; GCN: ; %bb.0:189; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)190; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0191; GCN-NEXT: v_cndmask_b32_e64 v0, v2, |v1|, vcc192; GCN-NEXT: s_setpc_b64 s[30:31]193;194; GFX11-LABEL: fabs_select_i32_1:195; GFX11: ; %bb.0:196; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)197; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0198; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, |v1|, vcc_lo199; GFX11-NEXT: s_setpc_b64 s[30:31]200 %neg.a = and i32 %a, u0x7fffffff201 %cmp = icmp eq i32 %cond, zeroinitializer202 %select = select i1 %cmp, i32 %neg.a, i32 %b203 ret i32 %select204}205 206define i32 @fabs_select_i32_2(i32 %cond, i32 %a, i32 %b) {207; GCN-LABEL: fabs_select_i32_2:208; GCN: ; %bb.0:209; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)210; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0211; GCN-NEXT: v_cndmask_b32_e64 v0, |v1|, v2, vcc212; GCN-NEXT: s_setpc_b64 s[30:31]213;214; GFX11-LABEL: fabs_select_i32_2:215; GFX11: ; %bb.0:216; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)217; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0218; GFX11-NEXT: v_cndmask_b32_e64 v0, |v1|, v2, vcc_lo219; GFX11-NEXT: s_setpc_b64 s[30:31]220 %neg.a = and i32 %a, u0x7fffffff221 %cmp = icmp eq i32 %cond, zeroinitializer222 %select = select i1 %cmp, i32 %b, i32 %neg.a223 ret i32 %select224}225 226define <2 x i32> @fneg_1_fabs_2_select_v2i32(<2 x i32> %cond, <2 x i32> %a, <2 x i32> %b) {227; GCN-LABEL: fneg_1_fabs_2_select_v2i32:228; GCN: ; %bb.0:229; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)230; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0231; GCN-NEXT: v_cndmask_b32_e64 v0, -v2, |v2|, vcc232; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1233; GCN-NEXT: v_cndmask_b32_e64 v1, -v3, |v3|, vcc234; GCN-NEXT: s_setpc_b64 s[30:31]235;236; GFX11-LABEL: fneg_1_fabs_2_select_v2i32:237; GFX11: ; %bb.0:238; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)239; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0240; GFX11-NEXT: v_cndmask_b32_e64 v0, -v2, |v2|, vcc_lo241; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1242; GFX11-NEXT: v_cndmask_b32_e64 v1, -v3, |v3|, vcc_lo243; GFX11-NEXT: s_setpc_b64 s[30:31]244 %neg.a = xor <2 x i32> %a, splat (i32 u0x80000000)245 %abs.b = and <2 x i32> %a, splat (i32 u0x7fffffff)246 %cmp = icmp eq <2 x i32> %cond, zeroinitializer247 %select = select <2 x i1> %cmp, <2 x i32> %abs.b, <2 x i32> %neg.a248 ret <2 x i32> %select249}250 251define i32 @fneg_fabs_select_i32_1(i32 %cond, i32 %a, i32 %b) {252; GCN-LABEL: fneg_fabs_select_i32_1:253; GCN: ; %bb.0:254; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)255; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0256; GCN-NEXT: v_cndmask_b32_e64 v0, v2, -|v1|, vcc257; GCN-NEXT: s_setpc_b64 s[30:31]258;259; GFX11-LABEL: fneg_fabs_select_i32_1:260; GFX11: ; %bb.0:261; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)262; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0263; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, -|v1|, vcc_lo264; GFX11-NEXT: s_setpc_b64 s[30:31]265 %neg.a = or i32 %a, u0x80000000266 %cmp = icmp eq i32 %cond, zeroinitializer267 %select = select i1 %cmp, i32 %neg.a, i32 %b268 ret i32 %select269}270 271define i32 @fneg_fabs_select_i32_2(i32 %cond, i32 %a, i32 %b) {272; GCN-LABEL: fneg_fabs_select_i32_2:273; GCN: ; %bb.0:274; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)275; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0276; GCN-NEXT: v_cndmask_b32_e64 v0, -|v1|, v2, vcc277; GCN-NEXT: s_setpc_b64 s[30:31]278;279; GFX11-LABEL: fneg_fabs_select_i32_2:280; GFX11: ; %bb.0:281; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)282; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0283; GFX11-NEXT: v_cndmask_b32_e64 v0, -|v1|, v2, vcc_lo284; GFX11-NEXT: s_setpc_b64 s[30:31]285 %neg.a = or i32 %a, u0x80000000286 %cmp = icmp eq i32 %cond, zeroinitializer287 %select = select i1 %cmp, i32 %b, i32 %neg.a288 ret i32 %select289}290 291define <2 x i32> @fneg_fabs_select_v2i32_1(<2 x i32> %cond, <2 x i32> %a, <2 x i32> %b) {292; GCN-LABEL: fneg_fabs_select_v2i32_1:293; GCN: ; %bb.0:294; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)295; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0296; GCN-NEXT: v_cndmask_b32_e64 v0, v4, -|v2|, vcc297; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1298; GCN-NEXT: v_cndmask_b32_e64 v1, v5, -|v3|, vcc299; GCN-NEXT: s_setpc_b64 s[30:31]300;301; GFX11-LABEL: fneg_fabs_select_v2i32_1:302; GFX11: ; %bb.0:303; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)304; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0305; GFX11-NEXT: v_cndmask_b32_e64 v0, v4, -|v2|, vcc_lo306; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1307; GFX11-NEXT: v_cndmask_b32_e64 v1, v5, -|v3|, vcc_lo308; GFX11-NEXT: s_setpc_b64 s[30:31]309 %neg.a = or <2 x i32> %a, splat (i32 u0x80000000)310 %cmp = icmp eq <2 x i32> %cond, zeroinitializer311 %select = select <2 x i1> %cmp, <2 x i32> %neg.a, <2 x i32> %b312 ret <2 x i32> %select313}314 315define <2 x i32> @fneg_fabs_select_v2i32_2(<2 x i32> %cond, <2 x i32> %a, <2 x i32> %b) {316; GCN-LABEL: fneg_fabs_select_v2i32_2:317; GCN: ; %bb.0:318; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)319; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0320; GCN-NEXT: v_cndmask_b32_e64 v0, -|v2|, v4, vcc321; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1322; GCN-NEXT: v_cndmask_b32_e64 v1, -|v3|, v5, vcc323; GCN-NEXT: s_setpc_b64 s[30:31]324;325; GFX11-LABEL: fneg_fabs_select_v2i32_2:326; GFX11: ; %bb.0:327; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)328; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0329; GFX11-NEXT: v_cndmask_b32_e64 v0, -|v2|, v4, vcc_lo330; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1331; GFX11-NEXT: v_cndmask_b32_e64 v1, -|v3|, v5, vcc_lo332; GFX11-NEXT: s_setpc_b64 s[30:31]333 %neg.a = or <2 x i32> %a, splat (i32 u0x80000000)334 %cmp = icmp eq <2 x i32> %cond, zeroinitializer335 %select = select <2 x i1> %cmp, <2 x i32> %b, <2 x i32> %neg.a336 ret <2 x i32> %select337}338 339 340define <2 x i32> @s_fneg_select_v2i32_1(<2 x i32> inreg %cond, <2 x i32> inreg %a, <2 x i32> inreg %b) {341; GCN-LABEL: s_fneg_select_v2i32_1:342; GCN: ; %bb.0:343; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)344; GCN-NEXT: s_brev_b32 s4, 1345; GCN-NEXT: s_mov_b32 s5, s4346; GCN-NEXT: s_xor_b64 s[4:5], s[18:19], s[4:5]347; GCN-NEXT: s_cmp_eq_u32 s16, 0348; GCN-NEXT: s_cselect_b32 s4, s4, s20349; GCN-NEXT: s_cmp_eq_u32 s17, 0350; GCN-NEXT: s_cselect_b32 s5, s5, s21351; GCN-NEXT: v_mov_b32_e32 v0, s4352; GCN-NEXT: v_mov_b32_e32 v1, s5353; GCN-NEXT: s_setpc_b64 s[30:31]354;355; GFX11-LABEL: s_fneg_select_v2i32_1:356; GFX11: ; %bb.0:357; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)358; GFX11-NEXT: s_brev_b32 s4, 1359; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)360; GFX11-NEXT: s_mov_b32 s5, s4361; GFX11-NEXT: s_xor_b64 s[2:3], s[2:3], s[4:5]362; GFX11-NEXT: s_cmp_eq_u32 s0, 0363; GFX11-NEXT: s_cselect_b32 s0, s2, s16364; GFX11-NEXT: s_cmp_eq_u32 s1, 0365; GFX11-NEXT: s_cselect_b32 s1, s3, s17366; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)367; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1368; GFX11-NEXT: s_setpc_b64 s[30:31]369 %neg.a = xor <2 x i32> %a, splat (i32 u0x80000000)370 %cmp = icmp eq <2 x i32> %cond, zeroinitializer371 %select = select <2 x i1> %cmp, <2 x i32> %neg.a, <2 x i32> %b372 ret <2 x i32> %select373}374 375define <2 x i32> @s_fneg_fabs_select_v2i32_2(<2 x i32> inreg %cond, <2 x i32> inreg %a, <2 x i32> inreg %b) {376; GCN-LABEL: s_fneg_fabs_select_v2i32_2:377; GCN: ; %bb.0:378; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)379; GCN-NEXT: s_brev_b32 s4, 1380; GCN-NEXT: s_mov_b32 s5, s4381; GCN-NEXT: s_or_b64 s[4:5], s[18:19], s[4:5]382; GCN-NEXT: s_cmp_eq_u32 s16, 0383; GCN-NEXT: s_cselect_b32 s4, s20, s4384; GCN-NEXT: s_cmp_eq_u32 s17, 0385; GCN-NEXT: s_cselect_b32 s5, s21, s5386; GCN-NEXT: v_mov_b32_e32 v0, s4387; GCN-NEXT: v_mov_b32_e32 v1, s5388; GCN-NEXT: s_setpc_b64 s[30:31]389;390; GFX11-LABEL: s_fneg_fabs_select_v2i32_2:391; GFX11: ; %bb.0:392; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)393; GFX11-NEXT: s_brev_b32 s4, 1394; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)395; GFX11-NEXT: s_mov_b32 s5, s4396; GFX11-NEXT: s_or_b64 s[2:3], s[2:3], s[4:5]397; GFX11-NEXT: s_cmp_eq_u32 s0, 0398; GFX11-NEXT: s_cselect_b32 s0, s16, s2399; GFX11-NEXT: s_cmp_eq_u32 s1, 0400; GFX11-NEXT: s_cselect_b32 s1, s17, s3401; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)402; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1403; GFX11-NEXT: s_setpc_b64 s[30:31]404 %neg.a = or <2 x i32> %a, splat (i32 u0x80000000)405 %cmp = icmp eq <2 x i32> %cond, zeroinitializer406 %select = select <2 x i1> %cmp, <2 x i32> %b, <2 x i32> %neg.a407 ret <2 x i32> %select408}409 410define i64 @fneg_select_i64_1(i64 %cond, i64 %a, i64 %b) {411; GCN-LABEL: fneg_select_i64_1:412; GCN: ; %bb.0:413; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)414; GCN-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1]415; GCN-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc416; GCN-NEXT: v_cndmask_b32_e64 v1, v5, -v3, vcc417; GCN-NEXT: s_setpc_b64 s[30:31]418;419; GFX11-LABEL: fneg_select_i64_1:420; GFX11: ; %bb.0:421; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)422; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]423; GFX11-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc_lo424; GFX11-NEXT: v_cndmask_b32_e64 v1, v5, -v3, vcc_lo425; GFX11-NEXT: s_setpc_b64 s[30:31]426 %neg.a = xor i64 %a, u0x8000000000000000427 %cmp = icmp eq i64 %cond, zeroinitializer428 %select = select i1 %cmp, i64 %neg.a, i64 %b429 ret i64 %select430}431 432define i64 @fneg_select_i64_2(i64 %cond, i64 %a, i64 %b) {433; GCN-LABEL: fneg_select_i64_2:434; GCN: ; %bb.0:435; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)436; GCN-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1]437; GCN-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc438; GCN-NEXT: v_cndmask_b32_e64 v1, -v3, v5, vcc439; GCN-NEXT: s_setpc_b64 s[30:31]440;441; GFX11-LABEL: fneg_select_i64_2:442; GFX11: ; %bb.0:443; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)444; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]445; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc_lo446; GFX11-NEXT: v_cndmask_b32_e64 v1, -v3, v5, vcc_lo447; GFX11-NEXT: s_setpc_b64 s[30:31]448 %neg.a = xor i64 %a, u0x8000000000000000449 %cmp = icmp eq i64 %cond, zeroinitializer450 %select = select i1 %cmp, i64 %b, i64 %neg.a451 ret i64 %select452}453 454define i64 @fneg_1_fabs_2_select_i64(i64 %cond, i64 %a, i64 %b) {455; GCN-LABEL: fneg_1_fabs_2_select_i64:456; GCN: ; %bb.0:457; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)458; GCN-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1]459; GCN-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc460; GCN-NEXT: v_cndmask_b32_e64 v1, |v5|, -v3, vcc461; GCN-NEXT: s_setpc_b64 s[30:31]462;463; GFX11-LABEL: fneg_1_fabs_2_select_i64:464; GFX11: ; %bb.0:465; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)466; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]467; GFX11-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc_lo468; GFX11-NEXT: v_cndmask_b32_e64 v1, |v5|, -v3, vcc_lo469; GFX11-NEXT: s_setpc_b64 s[30:31]470 %neg.a = xor i64 %a, u0x8000000000000000471 %abs.b = and i64 %b, u0x7fffffffffffffff472 %cmp = icmp eq i64 %cond, zeroinitializer473 %select = select i1 %cmp, i64 %neg.a, i64 %abs.b474 ret i64 %select475}476 477define i64 @fabs_select_i64_1(i64 %cond, i64 %a, i64 %b) {478; GCN-LABEL: fabs_select_i64_1:479; GCN: ; %bb.0:480; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)481; GCN-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1]482; GCN-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc483; GCN-NEXT: v_cndmask_b32_e64 v1, v5, |v3|, vcc484; GCN-NEXT: s_setpc_b64 s[30:31]485;486; GFX11-LABEL: fabs_select_i64_1:487; GFX11: ; %bb.0:488; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)489; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]490; GFX11-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc_lo491; GFX11-NEXT: v_cndmask_b32_e64 v1, v5, |v3|, vcc_lo492; GFX11-NEXT: s_setpc_b64 s[30:31]493 %neg.a = and i64 %a, u0x7fffffffffffffff494 %cmp = icmp eq i64 %cond, zeroinitializer495 %select = select i1 %cmp, i64 %neg.a, i64 %b496 ret i64 %select497}498 499define i64 @fabs_select_i64_2(i64 %cond, i64 %a, i64 %b) {500; GCN-LABEL: fabs_select_i64_2:501; GCN: ; %bb.0:502; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)503; GCN-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1]504; GCN-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc505; GCN-NEXT: v_cndmask_b32_e64 v1, |v3|, v5, vcc506; GCN-NEXT: s_setpc_b64 s[30:31]507;508; GFX11-LABEL: fabs_select_i64_2:509; GFX11: ; %bb.0:510; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)511; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]512; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc_lo513; GFX11-NEXT: v_cndmask_b32_e64 v1, |v3|, v5, vcc_lo514; GFX11-NEXT: s_setpc_b64 s[30:31]515 %neg.a = and i64 %a, u0x7fffffffffffffff516 %cmp = icmp eq i64 %cond, zeroinitializer517 %select = select i1 %cmp, i64 %b, i64 %neg.a518 ret i64 %select519}520 521define i64 @fneg_fabs_select_i64_1(i64 %cond, i64 %a, i64 %b) {522; GCN-LABEL: fneg_fabs_select_i64_1:523; GCN: ; %bb.0:524; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)525; GCN-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1]526; GCN-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc527; GCN-NEXT: v_cndmask_b32_e64 v1, v5, -|v3|, vcc528; GCN-NEXT: s_setpc_b64 s[30:31]529;530; GFX11-LABEL: fneg_fabs_select_i64_1:531; GFX11: ; %bb.0:532; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)533; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]534; GFX11-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc_lo535; GFX11-NEXT: v_cndmask_b32_e64 v1, v5, -|v3|, vcc_lo536; GFX11-NEXT: s_setpc_b64 s[30:31]537 %neg.a = or i64 %a, u0x8000000000000000538 %cmp = icmp eq i64 %cond, zeroinitializer539 %select = select i1 %cmp, i64 %neg.a, i64 %b540 ret i64 %select541}542 543define i64 @fneg_fabs_select_i64_2(i64 %cond, i64 %a, i64 %b) {544; GCN-LABEL: fneg_fabs_select_i64_2:545; GCN: ; %bb.0:546; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)547; GCN-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1]548; GCN-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc549; GCN-NEXT: v_cndmask_b32_e64 v1, -|v3|, v5, vcc550; GCN-NEXT: s_setpc_b64 s[30:31]551;552; GFX11-LABEL: fneg_fabs_select_i64_2:553; GFX11: ; %bb.0:554; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)555; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]556; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc_lo557; GFX11-NEXT: v_cndmask_b32_e64 v1, -|v3|, v5, vcc_lo558; GFX11-NEXT: s_setpc_b64 s[30:31]559 %neg.a = or i64 %a, u0x8000000000000000560 %cmp = icmp eq i64 %cond, zeroinitializer561 %select = select i1 %cmp, i64 %b, i64 %neg.a562 ret i64 %select563}564 565define i64 @s_fneg_select_i64_1(i64 inreg %cond, i64 inreg %a, i64 inreg %b) {566; GFX7-LABEL: s_fneg_select_i64_1:567; GFX7: ; %bb.0:568; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)569; GFX7-NEXT: v_cmp_eq_u64_e64 s[4:5], s[16:17], 0570; GFX7-NEXT: s_xor_b32 s6, s19, 0x80000000571; GFX7-NEXT: s_and_b64 s[4:5], s[4:5], exec572; GFX7-NEXT: s_cselect_b32 s4, s18, s20573; GFX7-NEXT: s_cselect_b32 s5, s6, s21574; GFX7-NEXT: v_mov_b32_e32 v0, s4575; GFX7-NEXT: v_mov_b32_e32 v1, s5576; GFX7-NEXT: s_setpc_b64 s[30:31]577;578; GFX9-LABEL: s_fneg_select_i64_1:579; GFX9: ; %bb.0:580; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)581; GFX9-NEXT: s_xor_b32 s4, s19, 0x80000000582; GFX9-NEXT: s_cmp_eq_u64 s[16:17], 0583; GFX9-NEXT: s_cselect_b32 s5, s18, s20584; GFX9-NEXT: s_cselect_b32 s4, s4, s21585; GFX9-NEXT: v_mov_b32_e32 v0, s5586; GFX9-NEXT: v_mov_b32_e32 v1, s4587; GFX9-NEXT: s_setpc_b64 s[30:31]588;589; GFX11-LABEL: s_fneg_select_i64_1:590; GFX11: ; %bb.0:591; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)592; GFX11-NEXT: s_xor_b32 s3, s3, 0x80000000593; GFX11-NEXT: s_cmp_eq_u64 s[0:1], 0594; GFX11-NEXT: s_cselect_b32 s0, s2, s16595; GFX11-NEXT: s_cselect_b32 s1, s3, s17596; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)597; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1598; GFX11-NEXT: s_setpc_b64 s[30:31]599 %neg.a = xor i64 %a, u0x8000000000000000600 %cmp = icmp eq i64 %cond, zeroinitializer601 %select = select i1 %cmp, i64 %neg.a, i64 %b602 ret i64 %select603}604 605define i64 @s_fneg_select_i64_2(i64 inreg %cond, i64 inreg %a, i64 inreg %b) {606; GFX7-LABEL: s_fneg_select_i64_2:607; GFX7: ; %bb.0:608; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)609; GFX7-NEXT: v_cmp_eq_u64_e64 s[4:5], s[16:17], 0610; GFX7-NEXT: s_xor_b32 s6, s19, 0x80000000611; GFX7-NEXT: s_and_b64 s[4:5], s[4:5], exec612; GFX7-NEXT: s_cselect_b32 s4, s20, s18613; GFX7-NEXT: s_cselect_b32 s5, s21, s6614; GFX7-NEXT: v_mov_b32_e32 v0, s4615; GFX7-NEXT: v_mov_b32_e32 v1, s5616; GFX7-NEXT: s_setpc_b64 s[30:31]617;618; GFX9-LABEL: s_fneg_select_i64_2:619; GFX9: ; %bb.0:620; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)621; GFX9-NEXT: s_xor_b32 s4, s19, 0x80000000622; GFX9-NEXT: s_cmp_eq_u64 s[16:17], 0623; GFX9-NEXT: s_cselect_b32 s5, s20, s18624; GFX9-NEXT: s_cselect_b32 s4, s21, s4625; GFX9-NEXT: v_mov_b32_e32 v0, s5626; GFX9-NEXT: v_mov_b32_e32 v1, s4627; GFX9-NEXT: s_setpc_b64 s[30:31]628;629; GFX11-LABEL: s_fneg_select_i64_2:630; GFX11: ; %bb.0:631; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)632; GFX11-NEXT: s_xor_b32 s3, s3, 0x80000000633; GFX11-NEXT: s_cmp_eq_u64 s[0:1], 0634; GFX11-NEXT: s_cselect_b32 s0, s16, s2635; GFX11-NEXT: s_cselect_b32 s1, s17, s3636; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)637; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1638; GFX11-NEXT: s_setpc_b64 s[30:31]639 %neg.a = xor i64 %a, u0x8000000000000000640 %cmp = icmp eq i64 %cond, zeroinitializer641 %select = select i1 %cmp, i64 %b, i64 %neg.a642 ret i64 %select643}644 645define i64 @s_fneg_1_fabs_2_select_i64(i64 inreg %cond, i64 inreg %a, i64 inreg %b) {646; GFX7-LABEL: s_fneg_1_fabs_2_select_i64:647; GFX7: ; %bb.0:648; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)649; GFX7-NEXT: v_cmp_eq_u64_e64 s[4:5], s[16:17], 0650; GFX7-NEXT: s_xor_b32 s6, s19, 0x80000000651; GFX7-NEXT: s_bitset0_b32 s21, 31652; GFX7-NEXT: s_and_b64 s[4:5], s[4:5], exec653; GFX7-NEXT: s_cselect_b32 s4, s18, s20654; GFX7-NEXT: s_cselect_b32 s5, s6, s21655; GFX7-NEXT: v_mov_b32_e32 v0, s4656; GFX7-NEXT: v_mov_b32_e32 v1, s5657; GFX7-NEXT: s_setpc_b64 s[30:31]658;659; GFX9-LABEL: s_fneg_1_fabs_2_select_i64:660; GFX9: ; %bb.0:661; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)662; GFX9-NEXT: s_xor_b32 s4, s19, 0x80000000663; GFX9-NEXT: s_bitset0_b32 s21, 31664; GFX9-NEXT: s_cmp_eq_u64 s[16:17], 0665; GFX9-NEXT: s_cselect_b32 s5, s18, s20666; GFX9-NEXT: s_cselect_b32 s4, s4, s21667; GFX9-NEXT: v_mov_b32_e32 v0, s5668; GFX9-NEXT: v_mov_b32_e32 v1, s4669; GFX9-NEXT: s_setpc_b64 s[30:31]670;671; GFX11-LABEL: s_fneg_1_fabs_2_select_i64:672; GFX11: ; %bb.0:673; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)674; GFX11-NEXT: s_xor_b32 s3, s3, 0x80000000675; GFX11-NEXT: s_bitset0_b32 s17, 31676; GFX11-NEXT: s_cmp_eq_u64 s[0:1], 0677; GFX11-NEXT: s_cselect_b32 s0, s2, s16678; GFX11-NEXT: s_cselect_b32 s1, s3, s17679; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)680; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1681; GFX11-NEXT: s_setpc_b64 s[30:31]682 %neg.a = xor i64 %a, u0x8000000000000000683 %abs.b = and i64 %b, u0x7fffffffffffffff684 %cmp = icmp eq i64 %cond, zeroinitializer685 %select = select i1 %cmp, i64 %neg.a, i64 %abs.b686 ret i64 %select687}688 689define i64 @s_fabs_select_i64_1(i64 inreg %cond, i64 inreg %a, i64 inreg %b) {690; GFX7-LABEL: s_fabs_select_i64_1:691; GFX7: ; %bb.0:692; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)693; GFX7-NEXT: v_cmp_eq_u64_e64 s[4:5], s[16:17], 0694; GFX7-NEXT: s_bitset0_b32 s19, 31695; GFX7-NEXT: s_and_b64 s[4:5], s[4:5], exec696; GFX7-NEXT: s_cselect_b32 s4, s18, s20697; GFX7-NEXT: s_cselect_b32 s5, s19, s21698; GFX7-NEXT: v_mov_b32_e32 v0, s4699; GFX7-NEXT: v_mov_b32_e32 v1, s5700; GFX7-NEXT: s_setpc_b64 s[30:31]701;702; GFX9-LABEL: s_fabs_select_i64_1:703; GFX9: ; %bb.0:704; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)705; GFX9-NEXT: s_bitset0_b32 s19, 31706; GFX9-NEXT: s_cmp_eq_u64 s[16:17], 0707; GFX9-NEXT: s_cselect_b32 s4, s18, s20708; GFX9-NEXT: s_cselect_b32 s5, s19, s21709; GFX9-NEXT: v_mov_b32_e32 v0, s4710; GFX9-NEXT: v_mov_b32_e32 v1, s5711; GFX9-NEXT: s_setpc_b64 s[30:31]712;713; GFX11-LABEL: s_fabs_select_i64_1:714; GFX11: ; %bb.0:715; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)716; GFX11-NEXT: s_bitset0_b32 s3, 31717; GFX11-NEXT: s_cmp_eq_u64 s[0:1], 0718; GFX11-NEXT: s_cselect_b32 s0, s2, s16719; GFX11-NEXT: s_cselect_b32 s1, s3, s17720; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)721; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1722; GFX11-NEXT: s_setpc_b64 s[30:31]723 %neg.a = and i64 %a, u0x7fffffffffffffff724 %cmp = icmp eq i64 %cond, zeroinitializer725 %select = select i1 %cmp, i64 %neg.a, i64 %b726 ret i64 %select727}728 729define i64 @s_fabs_select_i64_2(i64 inreg %cond, i64 inreg %a, i64 inreg %b) {730; GFX7-LABEL: s_fabs_select_i64_2:731; GFX7: ; %bb.0:732; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)733; GFX7-NEXT: v_cmp_eq_u64_e64 s[4:5], s[16:17], 0734; GFX7-NEXT: s_bitset0_b32 s19, 31735; GFX7-NEXT: s_and_b64 s[4:5], s[4:5], exec736; GFX7-NEXT: s_cselect_b32 s4, s20, s18737; GFX7-NEXT: s_cselect_b32 s5, s21, s19738; GFX7-NEXT: v_mov_b32_e32 v0, s4739; GFX7-NEXT: v_mov_b32_e32 v1, s5740; GFX7-NEXT: s_setpc_b64 s[30:31]741;742; GFX9-LABEL: s_fabs_select_i64_2:743; GFX9: ; %bb.0:744; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)745; GFX9-NEXT: s_bitset0_b32 s19, 31746; GFX9-NEXT: s_cmp_eq_u64 s[16:17], 0747; GFX9-NEXT: s_cselect_b32 s4, s20, s18748; GFX9-NEXT: s_cselect_b32 s5, s21, s19749; GFX9-NEXT: v_mov_b32_e32 v0, s4750; GFX9-NEXT: v_mov_b32_e32 v1, s5751; GFX9-NEXT: s_setpc_b64 s[30:31]752;753; GFX11-LABEL: s_fabs_select_i64_2:754; GFX11: ; %bb.0:755; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)756; GFX11-NEXT: s_bitset0_b32 s3, 31757; GFX11-NEXT: s_cmp_eq_u64 s[0:1], 0758; GFX11-NEXT: s_cselect_b32 s0, s16, s2759; GFX11-NEXT: s_cselect_b32 s1, s17, s3760; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)761; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1762; GFX11-NEXT: s_setpc_b64 s[30:31]763 %neg.a = and i64 %a, u0x7fffffffffffffff764 %cmp = icmp eq i64 %cond, zeroinitializer765 %select = select i1 %cmp, i64 %b, i64 %neg.a766 ret i64 %select767}768 769define i64 @s_fneg_fabs_select_i64_1(i64 inreg %cond, i64 inreg %a, i64 inreg %b) {770; GFX7-LABEL: s_fneg_fabs_select_i64_1:771; GFX7: ; %bb.0:772; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)773; GFX7-NEXT: v_cmp_eq_u64_e64 s[4:5], s[16:17], 0774; GFX7-NEXT: s_bitset1_b32 s19, 31775; GFX7-NEXT: s_and_b64 s[4:5], s[4:5], exec776; GFX7-NEXT: s_cselect_b32 s4, s18, s20777; GFX7-NEXT: s_cselect_b32 s5, s19, s21778; GFX7-NEXT: v_mov_b32_e32 v0, s4779; GFX7-NEXT: v_mov_b32_e32 v1, s5780; GFX7-NEXT: s_setpc_b64 s[30:31]781;782; GFX9-LABEL: s_fneg_fabs_select_i64_1:783; GFX9: ; %bb.0:784; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)785; GFX9-NEXT: s_bitset1_b32 s19, 31786; GFX9-NEXT: s_cmp_eq_u64 s[16:17], 0787; GFX9-NEXT: s_cselect_b32 s4, s18, s20788; GFX9-NEXT: s_cselect_b32 s5, s19, s21789; GFX9-NEXT: v_mov_b32_e32 v0, s4790; GFX9-NEXT: v_mov_b32_e32 v1, s5791; GFX9-NEXT: s_setpc_b64 s[30:31]792;793; GFX11-LABEL: s_fneg_fabs_select_i64_1:794; GFX11: ; %bb.0:795; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)796; GFX11-NEXT: s_bitset1_b32 s3, 31797; GFX11-NEXT: s_cmp_eq_u64 s[0:1], 0798; GFX11-NEXT: s_cselect_b32 s0, s2, s16799; GFX11-NEXT: s_cselect_b32 s1, s3, s17800; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)801; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1802; GFX11-NEXT: s_setpc_b64 s[30:31]803 %neg.a = or i64 %a, u0x8000000000000000804 %cmp = icmp eq i64 %cond, zeroinitializer805 %select = select i1 %cmp, i64 %neg.a, i64 %b806 ret i64 %select807}808 809define i64 @s_fneg_fabs_select_i64_2(i64 inreg %cond, i64 inreg %a, i64 inreg %b) {810; GFX7-LABEL: s_fneg_fabs_select_i64_2:811; GFX7: ; %bb.0:812; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)813; GFX7-NEXT: v_cmp_eq_u64_e64 s[4:5], s[16:17], 0814; GFX7-NEXT: s_bitset1_b32 s19, 31815; GFX7-NEXT: s_and_b64 s[4:5], s[4:5], exec816; GFX7-NEXT: s_cselect_b32 s4, s20, s18817; GFX7-NEXT: s_cselect_b32 s5, s21, s19818; GFX7-NEXT: v_mov_b32_e32 v0, s4819; GFX7-NEXT: v_mov_b32_e32 v1, s5820; GFX7-NEXT: s_setpc_b64 s[30:31]821;822; GFX9-LABEL: s_fneg_fabs_select_i64_2:823; GFX9: ; %bb.0:824; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)825; GFX9-NEXT: s_bitset1_b32 s19, 31826; GFX9-NEXT: s_cmp_eq_u64 s[16:17], 0827; GFX9-NEXT: s_cselect_b32 s4, s20, s18828; GFX9-NEXT: s_cselect_b32 s5, s21, s19829; GFX9-NEXT: v_mov_b32_e32 v0, s4830; GFX9-NEXT: v_mov_b32_e32 v1, s5831; GFX9-NEXT: s_setpc_b64 s[30:31]832;833; GFX11-LABEL: s_fneg_fabs_select_i64_2:834; GFX11: ; %bb.0:835; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)836; GFX11-NEXT: s_bitset1_b32 s3, 31837; GFX11-NEXT: s_cmp_eq_u64 s[0:1], 0838; GFX11-NEXT: s_cselect_b32 s0, s16, s2839; GFX11-NEXT: s_cselect_b32 s1, s17, s3840; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)841; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1842; GFX11-NEXT: s_setpc_b64 s[30:31]843 %neg.a = or i64 %a, u0x8000000000000000844 %cmp = icmp eq i64 %cond, zeroinitializer845 %select = select i1 %cmp, i64 %b, i64 %neg.a846 ret i64 %select847}848 849define i16 @fneg_select_i16_1(i16 %cond, i16 %a, i16 %b) {850; GFX7-LABEL: fneg_select_i16_1:851; GFX7: ; %bb.0:852; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)853; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0854; GFX7-NEXT: v_xor_b32_e32 v1, 0xffff8000, v1855; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0856; GFX7-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc857; GFX7-NEXT: s_setpc_b64 s[30:31]858;859; GFX9-LABEL: fneg_select_i16_1:860; GFX9: ; %bb.0:861; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)862; GFX9-NEXT: v_xor_b32_e32 v1, 0xffff8000, v1863; GFX9-NEXT: v_cmp_eq_u16_e32 vcc, 0, v0864; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc865; GFX9-NEXT: s_setpc_b64 s[30:31]866;867; GFX11-TRUE16-LABEL: fneg_select_i16_1:868; GFX11-TRUE16: ; %bb.0:869; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)870; GFX11-TRUE16-NEXT: v_xor_b16 v0.h, 0x8000, v1.l871; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0.l872; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)873; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.h, vcc_lo874; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]875;876; GFX11-FAKE16-LABEL: fneg_select_i16_1:877; GFX11-FAKE16: ; %bb.0:878; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)879; GFX11-FAKE16-NEXT: v_xor_b32_e32 v1, 0xffff8000, v1880; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0881; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)882; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc_lo883; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]884 %neg.a = xor i16 %a, u0x8000885 %cmp = icmp eq i16 %cond, zeroinitializer886 %select = select i1 %cmp, i16 %neg.a, i16 %b887 ret i16 %select888}889 890define i16 @fneg_select_i16_2(i16 %cond, i16 %a, i16 %b) {891; GFX7-LABEL: fneg_select_i16_2:892; GFX7: ; %bb.0:893; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)894; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0895; GFX7-NEXT: v_xor_b32_e32 v1, 0xffff8000, v1896; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0897; GFX7-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc898; GFX7-NEXT: s_setpc_b64 s[30:31]899;900; GFX9-LABEL: fneg_select_i16_2:901; GFX9: ; %bb.0:902; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)903; GFX9-NEXT: v_xor_b32_e32 v1, 0xffff8000, v1904; GFX9-NEXT: v_cmp_eq_u16_e32 vcc, 0, v0905; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc906; GFX9-NEXT: s_setpc_b64 s[30:31]907;908; GFX11-TRUE16-LABEL: fneg_select_i16_2:909; GFX11-TRUE16: ; %bb.0:910; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)911; GFX11-TRUE16-NEXT: v_xor_b16 v0.h, 0x8000, v1.l912; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0.l913; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)914; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.h, v2.l, vcc_lo915; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]916;917; GFX11-FAKE16-LABEL: fneg_select_i16_2:918; GFX11-FAKE16: ; %bb.0:919; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)920; GFX11-FAKE16-NEXT: v_xor_b32_e32 v1, 0xffff8000, v1921; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0922; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)923; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo924; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]925 %neg.a = xor i16 %a, u0x8000926 %cmp = icmp eq i16 %cond, zeroinitializer927 %select = select i1 %cmp, i16 %b, i16 %neg.a928 ret i16 %select929}930 931define i16 @fneg_select_i16_both(i16 %cond, i16 %a, i16 %b) {932; GFX7-LABEL: fneg_select_i16_both:933; GFX7: ; %bb.0:934; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)935; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0936; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0937; GFX7-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc938; GFX7-NEXT: v_xor_b32_e32 v0, 0xffff8000, v0939; GFX7-NEXT: s_setpc_b64 s[30:31]940;941; GFX9-LABEL: fneg_select_i16_both:942; GFX9: ; %bb.0:943; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)944; GFX9-NEXT: v_cmp_eq_u16_e32 vcc, 0, v0945; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc946; GFX9-NEXT: v_xor_b32_e32 v0, 0xffff8000, v0947; GFX9-NEXT: s_setpc_b64 s[30:31]948;949; GFX11-TRUE16-LABEL: fneg_select_i16_both:950; GFX11-TRUE16: ; %bb.0:951; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)952; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0.l953; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v1.l, vcc_lo954; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)955; GFX11-TRUE16-NEXT: v_xor_b16 v0.l, 0x8000, v0.l956; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]957;958; GFX11-FAKE16-LABEL: fneg_select_i16_both:959; GFX11-FAKE16: ; %bb.0:960; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)961; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0962; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc_lo963; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)964; GFX11-FAKE16-NEXT: v_xor_b32_e32 v0, 0xffff8000, v0965; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]966 %neg.a = xor i16 %a, u0x8000967 %neg.b = xor i16 %b, u0x8000968 %cmp = icmp eq i16 %cond, zeroinitializer969 %select = select i1 %cmp, i16 %neg.a, i16 %neg.b970 ret i16 %select971}972 973define i16 @fneg_1_fabs_2_select_i16(i16 %cond, i16 %a, i16 %b) {974; GFX7-LABEL: fneg_1_fabs_2_select_i16:975; GFX7: ; %bb.0:976; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)977; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0978; GFX7-NEXT: v_xor_b32_e32 v2, 0xffff8000, v1979; GFX7-NEXT: v_and_b32_e32 v1, 0x7fff, v1980; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0981; GFX7-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc982; GFX7-NEXT: s_setpc_b64 s[30:31]983;984; GFX9-LABEL: fneg_1_fabs_2_select_i16:985; GFX9: ; %bb.0:986; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)987; GFX9-NEXT: v_xor_b32_e32 v2, 0xffff8000, v1988; GFX9-NEXT: v_and_b32_e32 v1, 0x7fff, v1989; GFX9-NEXT: v_cmp_eq_u16_e32 vcc, 0, v0990; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc991; GFX9-NEXT: s_setpc_b64 s[30:31]992;993; GFX11-TRUE16-LABEL: fneg_1_fabs_2_select_i16:994; GFX11-TRUE16: ; %bb.0:995; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)996; GFX11-TRUE16-NEXT: v_xor_b16 v0.h, 0x8000, v1.l997; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0x7fff, v1.l998; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0.l999; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)1000; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v0.h, vcc_lo1001; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]1002;1003; GFX11-FAKE16-LABEL: fneg_1_fabs_2_select_i16:1004; GFX11-FAKE16: ; %bb.0:1005; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1006; GFX11-FAKE16-NEXT: v_xor_b32_e32 v2, 0xffff8000, v11007; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0x7fff, v11008; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v01009; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)1010; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo1011; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]1012 %neg.a = xor i16 %a, u0x80001013 %abs.b = and i16 %a, u0x7fff1014 %cmp = icmp eq i16 %cond, zeroinitializer1015 %select = select i1 %cmp, i16 %neg.a, i16 %abs.b1016 ret i16 %select1017}1018