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1; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 52; RUN: llc -global-isel=1 -mtriple=amdgcn--amdpal -mcpu=gfx1200 -stop-after=irtranslator < %s | FileCheck %s3 4define amdgpu_gfx_whole_wave i32 @basic_test(i1 %active, i32 %a, i32 %b) {5 ; CHECK-LABEL: name: basic_test6 ; CHECK: bb.1 (%ir-block.0):7 ; CHECK-NEXT: liveins: $vgpr0, $vgpr18 ; CHECK-NEXT: {{ $}}9 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr010 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr111 ; CHECK-NEXT: [[AMDGPU_WHOLE_WAVE_FUNC_SETUP:%[0-9]+]]:_(s1) = G_AMDGPU_WHOLE_WAVE_FUNC_SETUP12 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 513 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 314 ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AMDGPU_WHOLE_WAVE_FUNC_SETUP]](s1), [[COPY]], [[C]]15 ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[AMDGPU_WHOLE_WAVE_FUNC_SETUP]](s1), [[COPY1]], [[C1]]16 ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.update.dpp), [[SELECT]](s32), [[SELECT1]](s32), 1, 1, 1, 017 ; CHECK-NEXT: $vgpr0 = COPY [[INTRINSIC_CONVERGENT]](s32)18 ; CHECK-NEXT: G_AMDGPU_WHOLE_WAVE_FUNC_RETURN [[AMDGPU_WHOLE_WAVE_FUNC_SETUP]](s1), implicit $vgpr019 %x = select i1 %active, i32 %a, i32 520 %y = select i1 %active, i32 %b, i32 321 %ret = call i32 @llvm.amdgcn.update.dpp.i32(i32 %x, i32 %y, i32 1, i32 1, i32 1, i1 false)22 ret i32 %ret23}24 25; Make sure we don't crash if %active is not used at all.26define amdgpu_gfx_whole_wave i32 @unused_active(i1 %active, i32 %a, i32 %b) {27 ; CHECK-LABEL: name: unused_active28 ; CHECK: bb.1 (%ir-block.0):29 ; CHECK-NEXT: liveins: $vgpr0, $vgpr130 ; CHECK-NEXT: {{ $}}31 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr032 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr133 ; CHECK-NEXT: [[AMDGPU_WHOLE_WAVE_FUNC_SETUP:%[0-9]+]]:_(s1) = G_AMDGPU_WHOLE_WAVE_FUNC_SETUP34 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1435 ; CHECK-NEXT: $vgpr0 = COPY [[C]](s32)36 ; CHECK-NEXT: G_AMDGPU_WHOLE_WAVE_FUNC_RETURN [[AMDGPU_WHOLE_WAVE_FUNC_SETUP]](s1), implicit $vgpr037 ret i32 1438}39 40define amdgpu_gfx_whole_wave i32 @multiple_blocks(i1 %active, i32 %a, i32 %b) {41 ; CHECK-LABEL: name: multiple_blocks42 ; CHECK: bb.1 (%ir-block.0):43 ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000)44 ; CHECK-NEXT: liveins: $vgpr0, $vgpr145 ; CHECK-NEXT: {{ $}}46 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr047 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr148 ; CHECK-NEXT: [[AMDGPU_WHOLE_WAVE_FUNC_SETUP:%[0-9]+]]:_(s1) = G_AMDGPU_WHOLE_WAVE_FUNC_SETUP49 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]50 ; CHECK-NEXT: [[INT:%[0-9]+]]:_(s1), [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), [[ICMP]](s1)51 ; CHECK-NEXT: G_BRCOND [[INT]](s1), %bb.252 ; CHECK-NEXT: G_BR %bb.353 ; CHECK-NEXT: {{ $}}54 ; CHECK-NEXT: bb.2.if.then:55 ; CHECK-NEXT: successors: %bb.3(0x80000000)56 ; CHECK-NEXT: {{ $}}57 ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY1]]58 ; CHECK-NEXT: {{ $}}59 ; CHECK-NEXT: bb.3.if.end:60 ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(s32) = G_PHI [[COPY1]](s32), %bb.1, [[ADD]](s32), %bb.261 ; CHECK-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[INT1]](s32)62 ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AMDGPU_WHOLE_WAVE_FUNC_SETUP]](s1), [[COPY]], [[PHI]]63 ; CHECK-NEXT: $vgpr0 = COPY [[SELECT]](s32)64 ; CHECK-NEXT: G_AMDGPU_WHOLE_WAVE_FUNC_RETURN [[AMDGPU_WHOLE_WAVE_FUNC_SETUP]](s1), implicit $vgpr065 %c = icmp eq i32 %a, %b66 br i1 %c, label %if.then, label %if.end67 68if.then: ; preds = %069 %d = add i32 %a, %b70 br label %if.end71 72if.end:73 %f = phi i32 [ %d, %if.then ], [ %b, %0 ]74 %e = select i1 %active, i32 %a, i32 %f75 ret i32 %e76}77 78define amdgpu_gfx_whole_wave i64 @ret_64(i1 %active, i64 %a, i64 %b) {79 ; CHECK-LABEL: name: ret_6480 ; CHECK: bb.1 (%ir-block.0):81 ; CHECK-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr382 ; CHECK-NEXT: {{ $}}83 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr084 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr185 ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)86 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr287 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr388 ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)89 ; CHECK-NEXT: [[AMDGPU_WHOLE_WAVE_FUNC_SETUP:%[0-9]+]]:_(s1) = G_AMDGPU_WHOLE_WAVE_FUNC_SETUP90 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 591 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 392 ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AMDGPU_WHOLE_WAVE_FUNC_SETUP]](s1), [[MV]], [[C]]93 ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[AMDGPU_WHOLE_WAVE_FUNC_SETUP]](s1), [[MV1]], [[C1]]94 ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(s64) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.update.dpp), [[SELECT]](s64), [[SELECT1]](s64), 1, 1, 1, 095 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[INTRINSIC_CONVERGENT]](s64)96 ; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32)97 ; CHECK-NEXT: $vgpr1 = COPY [[UV1]](s32)98 ; CHECK-NEXT: G_AMDGPU_WHOLE_WAVE_FUNC_RETURN [[AMDGPU_WHOLE_WAVE_FUNC_SETUP]](s1), implicit $vgpr0, implicit $vgpr199 %x = select i1 %active, i64 %a, i64 5100 %y = select i1 %active, i64 %b, i64 3101 %ret = call i64 @llvm.amdgcn.update.dpp.i64(i64 %x, i64 %y, i32 1, i32 1, i32 1, i1 false)102 ret i64 %ret103}104 105declare amdgpu_gfx_whole_wave i32 @callee(i1 %active, i32 %x)106 107; Make sure we don't pass the first argument (i1).108define amdgpu_cs void @call(i32 %x, ptr %p) {109 ; CHECK-LABEL: name: call110 ; CHECK: bb.1 (%ir-block.0):111 ; CHECK-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2112 ; CHECK-NEXT: {{ $}}113 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0114 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1115 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2116 ; CHECK-NEXT: [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32)117 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @callee118 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc119 ; CHECK-NEXT: [[GV1:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @callee120 ; CHECK-NEXT: $vgpr0 = COPY [[COPY]](s32)121 ; CHECK-NEXT: $sgpr30_sgpr31 = G_SI_CALL [[GV1]](p0), @callee, csr_amdgpu_si_gfx, implicit $vgpr0, implicit-def $vgpr0122 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr0123 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc124 ; CHECK-NEXT: G_STORE [[COPY3]](s32), [[MV]](p0) :: (store (s32) into %ir.p)125 ; CHECK-NEXT: S_ENDPGM 0126 %ret = call i32(ptr, ...) @llvm.amdgcn.call.whole.wave(ptr @callee, i32 %x) convergent127 store i32 %ret, ptr %p128 ret void129}130