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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -o - %s | FileCheck %s3 4; Check for verifier error after tail duplication. An implicit_def of5; a subregsiter is needed to maintain liveness after assignment.6 7define amdgpu_vs void @test(i32 inreg %cmp, i32 %e0) {8; CHECK-LABEL: test:9; CHECK: ; %bb.0: ; %entry10; CHECK-NEXT: s_cmp_eq_u32 s0, 011; CHECK-NEXT: s_mov_b32 s0, 012; CHECK-NEXT: s_cbranch_scc1 .LBB0_213; CHECK-NEXT: ; %bb.1: ; %load14; CHECK-NEXT: s_mov_b32 s1, s015; CHECK-NEXT: s_mov_b32 s2, s016; CHECK-NEXT: s_mov_b32 s3, s017; CHECK-NEXT: v_mov_b32_e32 v1, 018; CHECK-NEXT: buffer_load_format_xy v[1:2], v1, s[0:3], 0 idxen19; CHECK-NEXT: s_waitcnt vmcnt(0)20; CHECK-NEXT: exp mrt0 v0, v1, v2, v021; CHECK-NEXT: s_endpgm22; CHECK-NEXT: .LBB0_2:23; CHECK-NEXT: v_mov_b32_e32 v1, 024; CHECK-NEXT: exp mrt0 v0, v1, v2, v025; CHECK-NEXT: s_endpgm26entry:27 %cond = icmp eq i32 %cmp, 028 br i1 %cond, label %end, label %load29 30load:31 %data1 = call <2 x i32> @llvm.amdgcn.struct.buffer.load.format.v2i32(<4 x i32> zeroinitializer, i32 0, i32 0, i32 0, i32 0)32 %e1 = extractelement <2 x i32> %data1, i32 033 %e2 = extractelement <2 x i32> %data1, i32 134 br label %end35 36end:37 %out1 = phi i32 [ 0, %entry ], [ %e1, %load ]38 %out2 = phi i32 [ poison, %entry ], [ %e2, %load ]39 call void @llvm.amdgcn.exp.i32(i32 0, i32 15, i32 %e0, i32 %out1, i32 %out2, i32 %e0, i1 false, i1 false)40 ret void41}42 43