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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=amdgcn | FileCheck -check-prefixes=SI %s3; RUN: llc < %s -mtriple=amdgcn -mcpu=tonga | FileCheck -check-prefixes=VI %s4; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx900 | FileCheck -check-prefixes=GFX9 %s5; RUN: llc < %s -mtriple=r600 -mcpu=redwood | FileCheck -check-prefixes=EGCM,EG %s6; RUN: llc < %s -mtriple=r600 -mcpu=cayman | FileCheck -check-prefixes=EGCM,CM %s7 8define amdgpu_kernel void @i8_arg(ptr addrspace(1) nocapture %out, i8 %in) nounwind {9; SI-LABEL: i8_arg:10; SI: ; %bb.0:11; SI-NEXT: s_load_dword s2, s[4:5], 0xb12; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x913; SI-NEXT: s_mov_b32 s3, 0xf00014; SI-NEXT: s_waitcnt lgkmcnt(0)15; SI-NEXT: s_and_b32 s4, s2, 0xff16; SI-NEXT: s_mov_b32 s2, -117; SI-NEXT: v_mov_b32_e32 v0, s418; SI-NEXT: buffer_store_dword v0, off, s[0:3], 019; SI-NEXT: s_endpgm20;21; VI-LABEL: i8_arg:22; VI: ; %bb.0:23; VI-NEXT: s_load_dword s2, s[4:5], 0x2c24; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2425; VI-NEXT: s_waitcnt lgkmcnt(0)26; VI-NEXT: s_and_b32 s2, s2, 0xff27; VI-NEXT: v_mov_b32_e32 v0, s028; VI-NEXT: v_mov_b32_e32 v1, s129; VI-NEXT: v_mov_b32_e32 v2, s230; VI-NEXT: flat_store_dword v[0:1], v231; VI-NEXT: s_endpgm32;33; GFX9-LABEL: i8_arg:34; GFX9: ; %bb.0:35; GFX9-NEXT: s_load_dword s2, s[8:9], 0x836; GFX9-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x037; GFX9-NEXT: v_mov_b32_e32 v0, 038; GFX9-NEXT: s_waitcnt lgkmcnt(0)39; GFX9-NEXT: s_and_b32 s2, s2, 0xff40; GFX9-NEXT: v_mov_b32_e32 v1, s241; GFX9-NEXT: global_store_dword v0, v1, s[0:1]42; GFX9-NEXT: s_endpgm43;44; EG-LABEL: i8_arg:45; EG: ; %bb.0:46; EG-NEXT: ALU 0, @8, KC0[], KC1[]47; EG-NEXT: TEX 0 @648; EG-NEXT: ALU 1, @9, KC0[CB0:0-32], KC1[]49; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 150; EG-NEXT: CF_END51; EG-NEXT: PAD52; EG-NEXT: Fetch clause starting at 6:53; EG-NEXT: VTX_READ_8 T0.X, T0.X, 40, #354; EG-NEXT: ALU clause starting at 8:55; EG-NEXT: MOV * T0.X, 0.0,56; EG-NEXT: ALU clause starting at 9:57; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,58; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)59;60; CM-LABEL: i8_arg:61; CM: ; %bb.0:62; CM-NEXT: ALU 0, @8, KC0[], KC1[]63; CM-NEXT: TEX 0 @664; CM-NEXT: ALU 1, @9, KC0[CB0:0-32], KC1[]65; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X66; CM-NEXT: CF_END67; CM-NEXT: PAD68; CM-NEXT: Fetch clause starting at 6:69; CM-NEXT: VTX_READ_8 T0.X, T0.X, 40, #370; CM-NEXT: ALU clause starting at 8:71; CM-NEXT: MOV * T0.X, 0.0,72; CM-NEXT: ALU clause starting at 9:73; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,74; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)75 %ext = zext i8 %in to i3276 store i32 %ext, ptr addrspace(1) %out, align 477 ret void78}79 80define amdgpu_kernel void @i8_zext_arg(ptr addrspace(1) nocapture %out, i8 zeroext %in) nounwind {81; SI-LABEL: i8_zext_arg:82; SI: ; %bb.0:83; SI-NEXT: s_load_dword s2, s[4:5], 0xb84; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x985; SI-NEXT: s_mov_b32 s3, 0xf00086; SI-NEXT: s_waitcnt lgkmcnt(0)87; SI-NEXT: s_and_b32 s4, s2, 0xff88; SI-NEXT: s_mov_b32 s2, -189; SI-NEXT: v_mov_b32_e32 v0, s490; SI-NEXT: buffer_store_dword v0, off, s[0:3], 091; SI-NEXT: s_endpgm92;93; VI-LABEL: i8_zext_arg:94; VI: ; %bb.0:95; VI-NEXT: s_load_dword s2, s[4:5], 0x2c96; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2497; VI-NEXT: s_waitcnt lgkmcnt(0)98; VI-NEXT: s_and_b32 s2, s2, 0xff99; VI-NEXT: v_mov_b32_e32 v0, s0100; VI-NEXT: v_mov_b32_e32 v1, s1101; VI-NEXT: v_mov_b32_e32 v2, s2102; VI-NEXT: flat_store_dword v[0:1], v2103; VI-NEXT: s_endpgm104;105; GFX9-LABEL: i8_zext_arg:106; GFX9: ; %bb.0:107; GFX9-NEXT: s_load_dword s2, s[8:9], 0x8108; GFX9-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0109; GFX9-NEXT: v_mov_b32_e32 v0, 0110; GFX9-NEXT: s_waitcnt lgkmcnt(0)111; GFX9-NEXT: s_and_b32 s2, s2, 0xff112; GFX9-NEXT: v_mov_b32_e32 v1, s2113; GFX9-NEXT: global_store_dword v0, v1, s[0:1]114; GFX9-NEXT: s_endpgm115;116; EG-LABEL: i8_zext_arg:117; EG: ; %bb.0:118; EG-NEXT: ALU 0, @8, KC0[], KC1[]119; EG-NEXT: TEX 0 @6120; EG-NEXT: ALU 2, @9, KC0[CB0:0-32], KC1[]121; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1122; EG-NEXT: CF_END123; EG-NEXT: PAD124; EG-NEXT: Fetch clause starting at 6:125; EG-NEXT: VTX_READ_8 T0.X, T0.X, 40, #3126; EG-NEXT: ALU clause starting at 8:127; EG-NEXT: MOV * T0.X, 0.0,128; EG-NEXT: ALU clause starting at 9:129; EG-NEXT: BFE_INT T0.X, T0.X, 0.0, literal.x,130; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,131; EG-NEXT: 8(1.121039e-44), 2(2.802597e-45)132;133; CM-LABEL: i8_zext_arg:134; CM: ; %bb.0:135; CM-NEXT: ALU 0, @8, KC0[], KC1[]136; CM-NEXT: TEX 0 @6137; CM-NEXT: ALU 3, @9, KC0[CB0:0-32], KC1[]138; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X139; CM-NEXT: CF_END140; CM-NEXT: PAD141; CM-NEXT: Fetch clause starting at 6:142; CM-NEXT: VTX_READ_8 T0.X, T0.X, 40, #3143; CM-NEXT: ALU clause starting at 8:144; CM-NEXT: MOV * T0.X, 0.0,145; CM-NEXT: ALU clause starting at 9:146; CM-NEXT: BFE_INT * T0.X, T0.X, 0.0, literal.x,147; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00)148; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,149; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)150 %ext = zext i8 %in to i32151 store i32 %ext, ptr addrspace(1) %out, align 4152 ret void153}154 155define amdgpu_kernel void @i8_sext_arg(ptr addrspace(1) nocapture %out, i8 signext %in) nounwind {156; SI-LABEL: i8_sext_arg:157; SI: ; %bb.0:158; SI-NEXT: s_load_dword s2, s[4:5], 0xb159; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9160; SI-NEXT: s_mov_b32 s3, 0xf000161; SI-NEXT: s_waitcnt lgkmcnt(0)162; SI-NEXT: s_sext_i32_i8 s4, s2163; SI-NEXT: s_mov_b32 s2, -1164; SI-NEXT: v_mov_b32_e32 v0, s4165; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0166; SI-NEXT: s_endpgm167;168; VI-LABEL: i8_sext_arg:169; VI: ; %bb.0:170; VI-NEXT: s_load_dword s2, s[4:5], 0x2c171; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24172; VI-NEXT: s_waitcnt lgkmcnt(0)173; VI-NEXT: s_sext_i32_i8 s2, s2174; VI-NEXT: v_mov_b32_e32 v0, s0175; VI-NEXT: v_mov_b32_e32 v1, s1176; VI-NEXT: v_mov_b32_e32 v2, s2177; VI-NEXT: flat_store_dword v[0:1], v2178; VI-NEXT: s_endpgm179;180; GFX9-LABEL: i8_sext_arg:181; GFX9: ; %bb.0:182; GFX9-NEXT: s_load_dword s2, s[8:9], 0x8183; GFX9-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0184; GFX9-NEXT: v_mov_b32_e32 v0, 0185; GFX9-NEXT: s_waitcnt lgkmcnt(0)186; GFX9-NEXT: s_sext_i32_i8 s2, s2187; GFX9-NEXT: v_mov_b32_e32 v1, s2188; GFX9-NEXT: global_store_dword v0, v1, s[0:1]189; GFX9-NEXT: s_endpgm190;191; EG-LABEL: i8_sext_arg:192; EG: ; %bb.0:193; EG-NEXT: ALU 0, @8, KC0[], KC1[]194; EG-NEXT: TEX 0 @6195; EG-NEXT: ALU 2, @9, KC0[CB0:0-32], KC1[]196; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1197; EG-NEXT: CF_END198; EG-NEXT: PAD199; EG-NEXT: Fetch clause starting at 6:200; EG-NEXT: VTX_READ_8 T0.X, T0.X, 40, #3201; EG-NEXT: ALU clause starting at 8:202; EG-NEXT: MOV * T0.X, 0.0,203; EG-NEXT: ALU clause starting at 9:204; EG-NEXT: BFE_INT T0.X, T0.X, 0.0, literal.x,205; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,206; EG-NEXT: 8(1.121039e-44), 2(2.802597e-45)207;208; CM-LABEL: i8_sext_arg:209; CM: ; %bb.0:210; CM-NEXT: ALU 0, @8, KC0[], KC1[]211; CM-NEXT: TEX 0 @6212; CM-NEXT: ALU 3, @9, KC0[CB0:0-32], KC1[]213; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X214; CM-NEXT: CF_END215; CM-NEXT: PAD216; CM-NEXT: Fetch clause starting at 6:217; CM-NEXT: VTX_READ_8 T0.X, T0.X, 40, #3218; CM-NEXT: ALU clause starting at 8:219; CM-NEXT: MOV * T0.X, 0.0,220; CM-NEXT: ALU clause starting at 9:221; CM-NEXT: BFE_INT * T0.X, T0.X, 0.0, literal.x,222; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00)223; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,224; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)225 %ext = sext i8 %in to i32226 store i32 %ext, ptr addrspace(1) %out, align 4227 ret void228}229 230define amdgpu_kernel void @i16_arg(ptr addrspace(1) nocapture %out, i16 %in) nounwind {231; SI-LABEL: i16_arg:232; SI: ; %bb.0:233; SI-NEXT: s_load_dword s2, s[4:5], 0xb234; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9235; SI-NEXT: s_mov_b32 s3, 0xf000236; SI-NEXT: s_waitcnt lgkmcnt(0)237; SI-NEXT: s_and_b32 s4, s2, 0xffff238; SI-NEXT: s_mov_b32 s2, -1239; SI-NEXT: v_mov_b32_e32 v0, s4240; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0241; SI-NEXT: s_endpgm242;243; VI-LABEL: i16_arg:244; VI: ; %bb.0:245; VI-NEXT: s_load_dword s2, s[4:5], 0x2c246; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24247; VI-NEXT: s_waitcnt lgkmcnt(0)248; VI-NEXT: s_and_b32 s2, s2, 0xffff249; VI-NEXT: v_mov_b32_e32 v0, s0250; VI-NEXT: v_mov_b32_e32 v1, s1251; VI-NEXT: v_mov_b32_e32 v2, s2252; VI-NEXT: flat_store_dword v[0:1], v2253; VI-NEXT: s_endpgm254;255; GFX9-LABEL: i16_arg:256; GFX9: ; %bb.0:257; GFX9-NEXT: s_load_dword s2, s[8:9], 0x8258; GFX9-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0259; GFX9-NEXT: v_mov_b32_e32 v0, 0260; GFX9-NEXT: s_waitcnt lgkmcnt(0)261; GFX9-NEXT: s_and_b32 s2, s2, 0xffff262; GFX9-NEXT: v_mov_b32_e32 v1, s2263; GFX9-NEXT: global_store_dword v0, v1, s[0:1]264; GFX9-NEXT: s_endpgm265;266; EG-LABEL: i16_arg:267; EG: ; %bb.0:268; EG-NEXT: ALU 0, @8, KC0[], KC1[]269; EG-NEXT: TEX 0 @6270; EG-NEXT: ALU 1, @9, KC0[CB0:0-32], KC1[]271; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1272; EG-NEXT: CF_END273; EG-NEXT: PAD274; EG-NEXT: Fetch clause starting at 6:275; EG-NEXT: VTX_READ_16 T0.X, T0.X, 40, #3276; EG-NEXT: ALU clause starting at 8:277; EG-NEXT: MOV * T0.X, 0.0,278; EG-NEXT: ALU clause starting at 9:279; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,280; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)281;282; CM-LABEL: i16_arg:283; CM: ; %bb.0:284; CM-NEXT: ALU 0, @8, KC0[], KC1[]285; CM-NEXT: TEX 0 @6286; CM-NEXT: ALU 1, @9, KC0[CB0:0-32], KC1[]287; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X288; CM-NEXT: CF_END289; CM-NEXT: PAD290; CM-NEXT: Fetch clause starting at 6:291; CM-NEXT: VTX_READ_16 T0.X, T0.X, 40, #3292; CM-NEXT: ALU clause starting at 8:293; CM-NEXT: MOV * T0.X, 0.0,294; CM-NEXT: ALU clause starting at 9:295; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,296; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)297 %ext = zext i16 %in to i32298 store i32 %ext, ptr addrspace(1) %out, align 4299 ret void300}301 302define amdgpu_kernel void @i16_zext_arg(ptr addrspace(1) nocapture %out, i16 zeroext %in) nounwind {303; SI-LABEL: i16_zext_arg:304; SI: ; %bb.0:305; SI-NEXT: s_load_dword s2, s[4:5], 0xb306; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9307; SI-NEXT: s_mov_b32 s3, 0xf000308; SI-NEXT: s_waitcnt lgkmcnt(0)309; SI-NEXT: s_and_b32 s4, s2, 0xffff310; SI-NEXT: s_mov_b32 s2, -1311; SI-NEXT: v_mov_b32_e32 v0, s4312; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0313; SI-NEXT: s_endpgm314;315; VI-LABEL: i16_zext_arg:316; VI: ; %bb.0:317; VI-NEXT: s_load_dword s2, s[4:5], 0x2c318; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24319; VI-NEXT: s_waitcnt lgkmcnt(0)320; VI-NEXT: s_and_b32 s2, s2, 0xffff321; VI-NEXT: v_mov_b32_e32 v0, s0322; VI-NEXT: v_mov_b32_e32 v1, s1323; VI-NEXT: v_mov_b32_e32 v2, s2324; VI-NEXT: flat_store_dword v[0:1], v2325; VI-NEXT: s_endpgm326;327; GFX9-LABEL: i16_zext_arg:328; GFX9: ; %bb.0:329; GFX9-NEXT: s_load_dword s2, s[8:9], 0x8330; GFX9-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0331; GFX9-NEXT: v_mov_b32_e32 v0, 0332; GFX9-NEXT: s_waitcnt lgkmcnt(0)333; GFX9-NEXT: s_and_b32 s2, s2, 0xffff334; GFX9-NEXT: v_mov_b32_e32 v1, s2335; GFX9-NEXT: global_store_dword v0, v1, s[0:1]336; GFX9-NEXT: s_endpgm337;338; EG-LABEL: i16_zext_arg:339; EG: ; %bb.0:340; EG-NEXT: ALU 0, @8, KC0[], KC1[]341; EG-NEXT: TEX 0 @6342; EG-NEXT: ALU 2, @9, KC0[CB0:0-32], KC1[]343; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1344; EG-NEXT: CF_END345; EG-NEXT: PAD346; EG-NEXT: Fetch clause starting at 6:347; EG-NEXT: VTX_READ_16 T0.X, T0.X, 40, #3348; EG-NEXT: ALU clause starting at 8:349; EG-NEXT: MOV * T0.X, 0.0,350; EG-NEXT: ALU clause starting at 9:351; EG-NEXT: BFE_INT T0.X, T0.X, 0.0, literal.x,352; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,353; EG-NEXT: 16(2.242078e-44), 2(2.802597e-45)354;355; CM-LABEL: i16_zext_arg:356; CM: ; %bb.0:357; CM-NEXT: ALU 0, @8, KC0[], KC1[]358; CM-NEXT: TEX 0 @6359; CM-NEXT: ALU 3, @9, KC0[CB0:0-32], KC1[]360; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X361; CM-NEXT: CF_END362; CM-NEXT: PAD363; CM-NEXT: Fetch clause starting at 6:364; CM-NEXT: VTX_READ_16 T0.X, T0.X, 40, #3365; CM-NEXT: ALU clause starting at 8:366; CM-NEXT: MOV * T0.X, 0.0,367; CM-NEXT: ALU clause starting at 9:368; CM-NEXT: BFE_INT * T0.X, T0.X, 0.0, literal.x,369; CM-NEXT: 16(2.242078e-44), 0(0.000000e+00)370; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,371; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)372 %ext = zext i16 %in to i32373 store i32 %ext, ptr addrspace(1) %out, align 4374 ret void375}376 377define amdgpu_kernel void @i16_sext_arg(ptr addrspace(1) nocapture %out, i16 signext %in) nounwind {378; SI-LABEL: i16_sext_arg:379; SI: ; %bb.0:380; SI-NEXT: s_load_dword s2, s[4:5], 0xb381; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9382; SI-NEXT: s_mov_b32 s3, 0xf000383; SI-NEXT: s_waitcnt lgkmcnt(0)384; SI-NEXT: s_sext_i32_i16 s4, s2385; SI-NEXT: s_mov_b32 s2, -1386; SI-NEXT: v_mov_b32_e32 v0, s4387; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0388; SI-NEXT: s_endpgm389;390; VI-LABEL: i16_sext_arg:391; VI: ; %bb.0:392; VI-NEXT: s_load_dword s2, s[4:5], 0x2c393; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24394; VI-NEXT: s_waitcnt lgkmcnt(0)395; VI-NEXT: s_sext_i32_i16 s2, s2396; VI-NEXT: v_mov_b32_e32 v0, s0397; VI-NEXT: v_mov_b32_e32 v1, s1398; VI-NEXT: v_mov_b32_e32 v2, s2399; VI-NEXT: flat_store_dword v[0:1], v2400; VI-NEXT: s_endpgm401;402; GFX9-LABEL: i16_sext_arg:403; GFX9: ; %bb.0:404; GFX9-NEXT: s_load_dword s2, s[8:9], 0x8405; GFX9-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0406; GFX9-NEXT: v_mov_b32_e32 v0, 0407; GFX9-NEXT: s_waitcnt lgkmcnt(0)408; GFX9-NEXT: s_sext_i32_i16 s2, s2409; GFX9-NEXT: v_mov_b32_e32 v1, s2410; GFX9-NEXT: global_store_dword v0, v1, s[0:1]411; GFX9-NEXT: s_endpgm412;413; EG-LABEL: i16_sext_arg:414; EG: ; %bb.0:415; EG-NEXT: ALU 0, @8, KC0[], KC1[]416; EG-NEXT: TEX 0 @6417; EG-NEXT: ALU 2, @9, KC0[CB0:0-32], KC1[]418; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1419; EG-NEXT: CF_END420; EG-NEXT: PAD421; EG-NEXT: Fetch clause starting at 6:422; EG-NEXT: VTX_READ_16 T0.X, T0.X, 40, #3423; EG-NEXT: ALU clause starting at 8:424; EG-NEXT: MOV * T0.X, 0.0,425; EG-NEXT: ALU clause starting at 9:426; EG-NEXT: BFE_INT T0.X, T0.X, 0.0, literal.x,427; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,428; EG-NEXT: 16(2.242078e-44), 2(2.802597e-45)429;430; CM-LABEL: i16_sext_arg:431; CM: ; %bb.0:432; CM-NEXT: ALU 0, @8, KC0[], KC1[]433; CM-NEXT: TEX 0 @6434; CM-NEXT: ALU 3, @9, KC0[CB0:0-32], KC1[]435; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X436; CM-NEXT: CF_END437; CM-NEXT: PAD438; CM-NEXT: Fetch clause starting at 6:439; CM-NEXT: VTX_READ_16 T0.X, T0.X, 40, #3440; CM-NEXT: ALU clause starting at 8:441; CM-NEXT: MOV * T0.X, 0.0,442; CM-NEXT: ALU clause starting at 9:443; CM-NEXT: BFE_INT * T0.X, T0.X, 0.0, literal.x,444; CM-NEXT: 16(2.242078e-44), 0(0.000000e+00)445; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,446; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)447 %ext = sext i16 %in to i32448 store i32 %ext, ptr addrspace(1) %out, align 4449 ret void450}451 452define amdgpu_kernel void @i32_arg(ptr addrspace(1) nocapture %out, i32 %in) nounwind {453; SI-LABEL: i32_arg:454; SI: ; %bb.0: ; %entry455; SI-NEXT: s_load_dword s6, s[4:5], 0xb456; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9457; SI-NEXT: s_mov_b32 s3, 0xf000458; SI-NEXT: s_mov_b32 s2, -1459; SI-NEXT: s_waitcnt lgkmcnt(0)460; SI-NEXT: v_mov_b32_e32 v0, s6461; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0462; SI-NEXT: s_endpgm463;464; VI-LABEL: i32_arg:465; VI: ; %bb.0: ; %entry466; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24467; VI-NEXT: s_load_dword s2, s[4:5], 0x2c468; VI-NEXT: s_waitcnt lgkmcnt(0)469; VI-NEXT: v_mov_b32_e32 v0, s0470; VI-NEXT: v_mov_b32_e32 v1, s1471; VI-NEXT: v_mov_b32_e32 v2, s2472; VI-NEXT: flat_store_dword v[0:1], v2473; VI-NEXT: s_endpgm474;475; GFX9-LABEL: i32_arg:476; GFX9: ; %bb.0: ; %entry477; GFX9-NEXT: s_load_dword s2, s[8:9], 0x8478; GFX9-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0479; GFX9-NEXT: v_mov_b32_e32 v0, 0480; GFX9-NEXT: s_waitcnt lgkmcnt(0)481; GFX9-NEXT: v_mov_b32_e32 v1, s2482; GFX9-NEXT: global_store_dword v0, v1, s[0:1]483; GFX9-NEXT: s_endpgm484;485; EG-LABEL: i32_arg:486; EG: ; %bb.0: ; %entry487; EG-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]488; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1489; EG-NEXT: CF_END490; EG-NEXT: PAD491; EG-NEXT: ALU clause starting at 4:492; EG-NEXT: LSHR T0.X, KC0[2].Y, literal.x,493; EG-NEXT: MOV * T1.X, KC0[2].Z,494; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)495;496; CM-LABEL: i32_arg:497; CM: ; %bb.0: ; %entry498; CM-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]499; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1.X, T0.X500; CM-NEXT: CF_END501; CM-NEXT: PAD502; CM-NEXT: ALU clause starting at 4:503; CM-NEXT: LSHR * T0.X, KC0[2].Y, literal.x,504; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)505; CM-NEXT: MOV * T1.X, KC0[2].Z,506entry:507 store i32 %in, ptr addrspace(1) %out, align 4508 ret void509}510 511define amdgpu_kernel void @f32_arg(ptr addrspace(1) nocapture %out, float %in) nounwind {512; SI-LABEL: f32_arg:513; SI: ; %bb.0: ; %entry514; SI-NEXT: s_load_dword s6, s[4:5], 0xb515; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9516; SI-NEXT: s_mov_b32 s3, 0xf000517; SI-NEXT: s_mov_b32 s2, -1518; SI-NEXT: s_waitcnt lgkmcnt(0)519; SI-NEXT: v_mov_b32_e32 v0, s6520; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0521; SI-NEXT: s_endpgm522;523; VI-LABEL: f32_arg:524; VI: ; %bb.0: ; %entry525; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24526; VI-NEXT: s_load_dword s2, s[4:5], 0x2c527; VI-NEXT: s_waitcnt lgkmcnt(0)528; VI-NEXT: v_mov_b32_e32 v0, s0529; VI-NEXT: v_mov_b32_e32 v1, s1530; VI-NEXT: v_mov_b32_e32 v2, s2531; VI-NEXT: flat_store_dword v[0:1], v2532; VI-NEXT: s_endpgm533;534; GFX9-LABEL: f32_arg:535; GFX9: ; %bb.0: ; %entry536; GFX9-NEXT: s_load_dword s2, s[8:9], 0x8537; GFX9-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0538; GFX9-NEXT: v_mov_b32_e32 v0, 0539; GFX9-NEXT: s_waitcnt lgkmcnt(0)540; GFX9-NEXT: v_mov_b32_e32 v1, s2541; GFX9-NEXT: global_store_dword v0, v1, s[0:1]542; GFX9-NEXT: s_endpgm543;544; EG-LABEL: f32_arg:545; EG: ; %bb.0: ; %entry546; EG-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]547; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1548; EG-NEXT: CF_END549; EG-NEXT: PAD550; EG-NEXT: ALU clause starting at 4:551; EG-NEXT: LSHR T0.X, KC0[2].Y, literal.x,552; EG-NEXT: MOV * T1.X, KC0[2].Z,553; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)554;555; CM-LABEL: f32_arg:556; CM: ; %bb.0: ; %entry557; CM-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]558; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1.X, T0.X559; CM-NEXT: CF_END560; CM-NEXT: PAD561; CM-NEXT: ALU clause starting at 4:562; CM-NEXT: LSHR * T0.X, KC0[2].Y, literal.x,563; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)564; CM-NEXT: MOV * T1.X, KC0[2].Z,565entry:566 store float %in, ptr addrspace(1) %out, align 4567 ret void568}569 570define amdgpu_kernel void @v2i8_arg(ptr addrspace(1) %out, <2 x i8> %in) {571; SI-LABEL: v2i8_arg:572; SI: ; %bb.0: ; %entry573; SI-NEXT: s_load_dword s6, s[4:5], 0xb574; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9575; SI-NEXT: s_mov_b32 s3, 0xf000576; SI-NEXT: s_mov_b32 s2, -1577; SI-NEXT: s_waitcnt lgkmcnt(0)578; SI-NEXT: v_mov_b32_e32 v0, s6579; SI-NEXT: buffer_store_short v0, off, s[0:3], 0580; SI-NEXT: s_endpgm581;582; VI-LABEL: v2i8_arg:583; VI: ; %bb.0: ; %entry584; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24585; VI-NEXT: s_load_dword s2, s[4:5], 0x2c586; VI-NEXT: s_waitcnt lgkmcnt(0)587; VI-NEXT: v_mov_b32_e32 v0, s0588; VI-NEXT: v_mov_b32_e32 v1, s1589; VI-NEXT: v_mov_b32_e32 v2, s2590; VI-NEXT: flat_store_short v[0:1], v2591; VI-NEXT: s_endpgm592;593; GFX9-LABEL: v2i8_arg:594; GFX9: ; %bb.0: ; %entry595; GFX9-NEXT: s_load_dword s2, s[8:9], 0x8596; GFX9-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0597; GFX9-NEXT: v_mov_b32_e32 v0, 0598; GFX9-NEXT: s_waitcnt lgkmcnt(0)599; GFX9-NEXT: v_mov_b32_e32 v1, s2600; GFX9-NEXT: global_store_short v0, v1, s[0:1]601; GFX9-NEXT: s_endpgm602;603; EG-LABEL: v2i8_arg:604; EG: ; %bb.0: ; %entry605; EG-NEXT: ALU 0, @8, KC0[], KC1[]606; EG-NEXT: TEX 0 @6607; EG-NEXT: ALU 11, @9, KC0[CB0:0-32], KC1[]608; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X609; EG-NEXT: CF_END610; EG-NEXT: PAD611; EG-NEXT: Fetch clause starting at 6:612; EG-NEXT: VTX_READ_16 T0.X, T0.X, 40, #3613; EG-NEXT: ALU clause starting at 8:614; EG-NEXT: MOV * T0.X, 0.0,615; EG-NEXT: ALU clause starting at 9:616; EG-NEXT: AND_INT T0.W, KC0[2].Y, literal.x,617; EG-NEXT: AND_INT * T1.W, T0.X, literal.y,618; EG-NEXT: 3(4.203895e-45), 65535(9.183409e-41)619; EG-NEXT: LSHL * T0.W, PV.W, literal.x,620; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)621; EG-NEXT: LSHL T0.X, T1.W, PV.W,622; EG-NEXT: LSHL * T0.W, literal.x, PV.W,623; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)624; EG-NEXT: MOV T0.Y, 0.0,625; EG-NEXT: MOV * T0.Z, 0.0,626; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,627; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)628;629; CM-LABEL: v2i8_arg:630; CM: ; %bb.0: ; %entry631; CM-NEXT: ALU 0, @8, KC0[], KC1[]632; CM-NEXT: TEX 0 @6633; CM-NEXT: ALU 11, @9, KC0[CB0:0-32], KC1[]634; CM-NEXT: MEM_RAT MSKOR T0.XW, T1.X635; CM-NEXT: CF_END636; CM-NEXT: PAD637; CM-NEXT: Fetch clause starting at 6:638; CM-NEXT: VTX_READ_16 T0.X, T0.X, 40, #3639; CM-NEXT: ALU clause starting at 8:640; CM-NEXT: MOV * T0.X, 0.0,641; CM-NEXT: ALU clause starting at 9:642; CM-NEXT: AND_INT * T0.W, KC0[2].Y, literal.x,643; CM-NEXT: 3(4.203895e-45), 0(0.000000e+00)644; CM-NEXT: AND_INT T0.Z, T0.X, literal.x,645; CM-NEXT: LSHL * T0.W, PV.W, literal.y,646; CM-NEXT: 65535(9.183409e-41), 3(4.203895e-45)647; CM-NEXT: LSHL T0.X, PV.Z, PV.W,648; CM-NEXT: LSHL * T0.W, literal.x, PV.W,649; CM-NEXT: 65535(9.183409e-41), 0(0.000000e+00)650; CM-NEXT: MOV T0.Y, 0.0,651; CM-NEXT: MOV * T0.Z, 0.0,652; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,653; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)654entry:655 store <2 x i8> %in, ptr addrspace(1) %out656 ret void657}658 659define amdgpu_kernel void @v2i16_arg(ptr addrspace(1) %out, <2 x i16> %in) {660; SI-LABEL: v2i16_arg:661; SI: ; %bb.0: ; %entry662; SI-NEXT: s_load_dword s6, s[4:5], 0xb663; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9664; SI-NEXT: s_mov_b32 s3, 0xf000665; SI-NEXT: s_mov_b32 s2, -1666; SI-NEXT: s_waitcnt lgkmcnt(0)667; SI-NEXT: v_mov_b32_e32 v0, s6668; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0669; SI-NEXT: s_endpgm670;671; VI-LABEL: v2i16_arg:672; VI: ; %bb.0: ; %entry673; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24674; VI-NEXT: s_load_dword s2, s[4:5], 0x2c675; VI-NEXT: s_waitcnt lgkmcnt(0)676; VI-NEXT: v_mov_b32_e32 v0, s0677; VI-NEXT: v_mov_b32_e32 v1, s1678; VI-NEXT: v_mov_b32_e32 v2, s2679; VI-NEXT: flat_store_dword v[0:1], v2680; VI-NEXT: s_endpgm681;682; GFX9-LABEL: v2i16_arg:683; GFX9: ; %bb.0: ; %entry684; GFX9-NEXT: s_load_dword s2, s[8:9], 0x8685; GFX9-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0686; GFX9-NEXT: v_mov_b32_e32 v0, 0687; GFX9-NEXT: s_waitcnt lgkmcnt(0)688; GFX9-NEXT: v_mov_b32_e32 v1, s2689; GFX9-NEXT: global_store_dword v0, v1, s[0:1]690; GFX9-NEXT: s_endpgm691;692; EG-LABEL: v2i16_arg:693; EG: ; %bb.0: ; %entry694; EG-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]695; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1696; EG-NEXT: CF_END697; EG-NEXT: PAD698; EG-NEXT: ALU clause starting at 4:699; EG-NEXT: MOV T0.X, KC0[2].Z,700; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,701; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)702;703; CM-LABEL: v2i16_arg:704; CM: ; %bb.0: ; %entry705; CM-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]706; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X707; CM-NEXT: CF_END708; CM-NEXT: PAD709; CM-NEXT: ALU clause starting at 4:710; CM-NEXT: MOV * T0.X, KC0[2].Z,711; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,712; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)713entry:714 store <2 x i16> %in, ptr addrspace(1) %out715 ret void716}717 718define amdgpu_kernel void @v2i32_arg(ptr addrspace(1) nocapture %out, <2 x i32> %in) nounwind {719; SI-LABEL: v2i32_arg:720; SI: ; %bb.0: ; %entry721; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9722; SI-NEXT: s_mov_b32 s7, 0xf000723; SI-NEXT: s_mov_b32 s6, -1724; SI-NEXT: s_waitcnt lgkmcnt(0)725; SI-NEXT: s_mov_b32 s4, s0726; SI-NEXT: s_mov_b32 s5, s1727; SI-NEXT: v_mov_b32_e32 v0, s2728; SI-NEXT: v_mov_b32_e32 v1, s3729; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0730; SI-NEXT: s_endpgm731;732; VI-LABEL: v2i32_arg:733; VI: ; %bb.0: ; %entry734; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24735; VI-NEXT: s_waitcnt lgkmcnt(0)736; VI-NEXT: v_mov_b32_e32 v0, s0737; VI-NEXT: v_mov_b32_e32 v2, s2738; VI-NEXT: v_mov_b32_e32 v1, s1739; VI-NEXT: v_mov_b32_e32 v3, s3740; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]741; VI-NEXT: s_endpgm742;743; GFX9-LABEL: v2i32_arg:744; GFX9: ; %bb.0: ; %entry745; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0746; GFX9-NEXT: v_mov_b32_e32 v2, 0747; GFX9-NEXT: s_waitcnt lgkmcnt(0)748; GFX9-NEXT: v_mov_b32_e32 v0, s2749; GFX9-NEXT: v_mov_b32_e32 v1, s3750; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]751; GFX9-NEXT: s_endpgm752;753; EG-LABEL: v2i32_arg:754; EG: ; %bb.0: ; %entry755; EG-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[]756; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1757; EG-NEXT: CF_END758; EG-NEXT: PAD759; EG-NEXT: ALU clause starting at 4:760; EG-NEXT: MOV * T0.Y, KC0[3].X,761; EG-NEXT: MOV T0.X, KC0[2].W,762; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,763; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)764;765; CM-LABEL: v2i32_arg:766; CM: ; %bb.0: ; %entry767; CM-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[]768; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0, T1.X769; CM-NEXT: CF_END770; CM-NEXT: PAD771; CM-NEXT: ALU clause starting at 4:772; CM-NEXT: MOV * T0.Y, KC0[3].X,773; CM-NEXT: MOV * T0.X, KC0[2].W,774; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,775; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)776entry:777 store <2 x i32> %in, ptr addrspace(1) %out, align 4778 ret void779}780 781define amdgpu_kernel void @v2f32_arg(ptr addrspace(1) nocapture %out, <2 x float> %in) nounwind {782; SI-LABEL: v2f32_arg:783; SI: ; %bb.0: ; %entry784; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9785; SI-NEXT: s_mov_b32 s7, 0xf000786; SI-NEXT: s_mov_b32 s6, -1787; SI-NEXT: s_waitcnt lgkmcnt(0)788; SI-NEXT: s_mov_b32 s4, s0789; SI-NEXT: s_mov_b32 s5, s1790; SI-NEXT: v_mov_b32_e32 v0, s2791; SI-NEXT: v_mov_b32_e32 v1, s3792; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0793; SI-NEXT: s_endpgm794;795; VI-LABEL: v2f32_arg:796; VI: ; %bb.0: ; %entry797; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24798; VI-NEXT: s_waitcnt lgkmcnt(0)799; VI-NEXT: v_mov_b32_e32 v0, s0800; VI-NEXT: v_mov_b32_e32 v2, s2801; VI-NEXT: v_mov_b32_e32 v1, s1802; VI-NEXT: v_mov_b32_e32 v3, s3803; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]804; VI-NEXT: s_endpgm805;806; GFX9-LABEL: v2f32_arg:807; GFX9: ; %bb.0: ; %entry808; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0809; GFX9-NEXT: v_mov_b32_e32 v2, 0810; GFX9-NEXT: s_waitcnt lgkmcnt(0)811; GFX9-NEXT: v_mov_b32_e32 v0, s2812; GFX9-NEXT: v_mov_b32_e32 v1, s3813; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]814; GFX9-NEXT: s_endpgm815;816; EG-LABEL: v2f32_arg:817; EG: ; %bb.0: ; %entry818; EG-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[]819; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1820; EG-NEXT: CF_END821; EG-NEXT: PAD822; EG-NEXT: ALU clause starting at 4:823; EG-NEXT: MOV * T0.Y, KC0[3].X,824; EG-NEXT: MOV T0.X, KC0[2].W,825; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,826; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)827;828; CM-LABEL: v2f32_arg:829; CM: ; %bb.0: ; %entry830; CM-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[]831; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0, T1.X832; CM-NEXT: CF_END833; CM-NEXT: PAD834; CM-NEXT: ALU clause starting at 4:835; CM-NEXT: MOV * T0.Y, KC0[3].X,836; CM-NEXT: MOV * T0.X, KC0[2].W,837; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,838; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)839entry:840 store <2 x float> %in, ptr addrspace(1) %out, align 4841 ret void842}843 844define amdgpu_kernel void @v3i8_arg(ptr addrspace(1) nocapture %out, <3 x i8> %in) nounwind {845; SI-LABEL: v3i8_arg:846; SI: ; %bb.0: ; %entry847; SI-NEXT: s_load_dword s6, s[4:5], 0xb848; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9849; SI-NEXT: s_mov_b32 s3, 0xf000850; SI-NEXT: s_waitcnt lgkmcnt(0)851; SI-NEXT: s_lshr_b32 s4, s6, 16852; SI-NEXT: s_mov_b32 s2, -1853; SI-NEXT: v_mov_b32_e32 v0, s6854; SI-NEXT: v_mov_b32_e32 v1, s4855; SI-NEXT: buffer_store_byte v1, off, s[0:3], 0 offset:2856; SI-NEXT: buffer_store_short v0, off, s[0:3], 0857; SI-NEXT: s_endpgm858;859; VI-LABEL: v3i8_arg:860; VI: ; %bb.0: ; %entry861; VI-NEXT: s_load_dword s2, s[4:5], 0x2c862; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24863; VI-NEXT: s_waitcnt lgkmcnt(0)864; VI-NEXT: s_lshr_b32 s3, s2, 16865; VI-NEXT: v_mov_b32_e32 v0, s0866; VI-NEXT: v_mov_b32_e32 v1, s1867; VI-NEXT: s_add_u32 s0, s0, 2868; VI-NEXT: s_addc_u32 s1, s1, 0869; VI-NEXT: v_mov_b32_e32 v3, s1870; VI-NEXT: v_mov_b32_e32 v5, s3871; VI-NEXT: v_mov_b32_e32 v2, s0872; VI-NEXT: v_mov_b32_e32 v4, s2873; VI-NEXT: flat_store_byte v[2:3], v5874; VI-NEXT: flat_store_short v[0:1], v4875; VI-NEXT: s_endpgm876;877; GFX9-LABEL: v3i8_arg:878; GFX9: ; %bb.0: ; %entry879; GFX9-NEXT: s_load_dword s2, s[8:9], 0x8880; GFX9-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0881; GFX9-NEXT: v_mov_b32_e32 v0, 0882; GFX9-NEXT: s_waitcnt lgkmcnt(0)883; GFX9-NEXT: v_mov_b32_e32 v1, s2884; GFX9-NEXT: global_store_byte_d16_hi v0, v1, s[0:1] offset:2885; GFX9-NEXT: global_store_short v0, v1, s[0:1]886; GFX9-NEXT: s_endpgm887;888; EG-LABEL: v3i8_arg:889; EG: ; %bb.0: ; %entry890; EG-NEXT: ALU 0, @12, KC0[], KC1[]891; EG-NEXT: TEX 2 @6892; EG-NEXT: ALU 28, @13, KC0[CB0:0-32], KC1[]893; EG-NEXT: MEM_RAT MSKOR T4.XW, T7.X894; EG-NEXT: MEM_RAT MSKOR T5.XW, T6.X895; EG-NEXT: CF_END896; EG-NEXT: Fetch clause starting at 6:897; EG-NEXT: VTX_READ_8 T5.X, T4.X, 41, #3898; EG-NEXT: VTX_READ_8 T6.X, T4.X, 42, #3899; EG-NEXT: VTX_READ_8 T4.X, T4.X, 40, #3900; EG-NEXT: ALU clause starting at 12:901; EG-NEXT: MOV * T4.X, 0.0,902; EG-NEXT: ALU clause starting at 13:903; EG-NEXT: LSHL T0.W, T5.X, literal.x,904; EG-NEXT: AND_INT * T1.W, T4.X, literal.y,905; EG-NEXT: 8(1.121039e-44), 255(3.573311e-43)906; EG-NEXT: AND_INT T2.W, KC0[2].Y, literal.x,907; EG-NEXT: OR_INT * T0.W, PV.W, PS,908; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)909; EG-NEXT: AND_INT T0.W, PS, literal.x,910; EG-NEXT: LSHL * T1.W, PV.W, literal.y,911; EG-NEXT: 65535(9.183409e-41), 3(4.203895e-45)912; EG-NEXT: LSHL T4.X, PV.W, PS,913; EG-NEXT: LSHL * T4.W, literal.x, PS,914; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)915; EG-NEXT: MOV T4.Y, 0.0,916; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x,917; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)918; EG-NEXT: AND_INT T1.W, PV.W, literal.x,919; EG-NEXT: AND_INT * T2.W, T6.X, literal.y,920; EG-NEXT: 3(4.203895e-45), 255(3.573311e-43)921; EG-NEXT: LSHL * T1.W, PV.W, literal.x,922; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)923; EG-NEXT: LSHL T5.X, T2.W, PV.W,924; EG-NEXT: LSHL * T5.W, literal.x, PV.W,925; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00)926; EG-NEXT: MOV T5.Y, 0.0,927; EG-NEXT: MOV T4.Z, 0.0,928; EG-NEXT: MOV * T5.Z, 0.0,929; EG-NEXT: LSHR T6.X, T0.W, literal.x,930; EG-NEXT: LSHR * T7.X, KC0[2].Y, literal.x,931; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)932;933; CM-LABEL: v3i8_arg:934; CM: ; %bb.0: ; %entry935; CM-NEXT: ALU 0, @12, KC0[], KC1[]936; CM-NEXT: TEX 2 @6937; CM-NEXT: ALU 29, @13, KC0[CB0:0-32], KC1[]938; CM-NEXT: MEM_RAT MSKOR T4.XW, T7.X939; CM-NEXT: MEM_RAT MSKOR T5.XW, T6.X940; CM-NEXT: CF_END941; CM-NEXT: Fetch clause starting at 6:942; CM-NEXT: VTX_READ_8 T5.X, T4.X, 41, #3943; CM-NEXT: VTX_READ_8 T6.X, T4.X, 42, #3944; CM-NEXT: VTX_READ_8 T4.X, T4.X, 40, #3945; CM-NEXT: ALU clause starting at 12:946; CM-NEXT: MOV * T4.X, 0.0,947; CM-NEXT: ALU clause starting at 13:948; CM-NEXT: LSHL T0.Z, T5.X, literal.x,949; CM-NEXT: AND_INT * T0.W, T4.X, literal.y, BS:VEC_120/SCL_212950; CM-NEXT: 8(1.121039e-44), 255(3.573311e-43)951; CM-NEXT: AND_INT T1.Z, KC0[2].Y, literal.x,952; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W,953; CM-NEXT: 3(4.203895e-45), 0(0.000000e+00)954; CM-NEXT: AND_INT T0.Z, PV.W, literal.x,955; CM-NEXT: LSHL * T0.W, PV.Z, literal.y,956; CM-NEXT: 65535(9.183409e-41), 3(4.203895e-45)957; CM-NEXT: LSHL T4.X, PV.Z, PV.W,958; CM-NEXT: LSHL * T4.W, literal.x, PV.W,959; CM-NEXT: 65535(9.183409e-41), 0(0.000000e+00)960; CM-NEXT: MOV T4.Y, 0.0,961; CM-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x,962; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)963; CM-NEXT: AND_INT * T1.W, PV.W, literal.x,964; CM-NEXT: 3(4.203895e-45), 0(0.000000e+00)965; CM-NEXT: AND_INT T0.Z, T6.X, literal.x,966; CM-NEXT: LSHL * T1.W, PV.W, literal.y,967; CM-NEXT: 255(3.573311e-43), 3(4.203895e-45)968; CM-NEXT: LSHL T5.X, PV.Z, PV.W,969; CM-NEXT: LSHL * T5.W, literal.x, PV.W,970; CM-NEXT: 255(3.573311e-43), 0(0.000000e+00)971; CM-NEXT: MOV T5.Y, 0.0,972; CM-NEXT: MOV * T4.Z, 0.0,973; CM-NEXT: MOV * T5.Z, 0.0,974; CM-NEXT: LSHR * T6.X, T0.W, literal.x,975; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)976; CM-NEXT: LSHR * T7.X, KC0[2].Y, literal.x,977; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)978entry:979 store <3 x i8> %in, ptr addrspace(1) %out, align 4980 ret void981}982 983define amdgpu_kernel void @v3i16_arg(ptr addrspace(1) nocapture %out, <3 x i16> %in) nounwind {984; SI-LABEL: v3i16_arg:985; SI: ; %bb.0: ; %entry986; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9987; SI-NEXT: s_mov_b32 s7, 0xf000988; SI-NEXT: s_mov_b32 s6, -1989; SI-NEXT: s_waitcnt lgkmcnt(0)990; SI-NEXT: s_mov_b32 s4, s0991; SI-NEXT: s_mov_b32 s5, s1992; SI-NEXT: v_mov_b32_e32 v0, s3993; SI-NEXT: buffer_store_short v0, off, s[4:7], 0 offset:4994; SI-NEXT: s_waitcnt expcnt(0)995; SI-NEXT: v_mov_b32_e32 v0, s2996; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0997; SI-NEXT: s_endpgm998;999; VI-LABEL: v3i16_arg:1000; VI: ; %bb.0: ; %entry1001; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241002; VI-NEXT: s_waitcnt lgkmcnt(0)1003; VI-NEXT: s_add_u32 s4, s0, 41004; VI-NEXT: s_addc_u32 s5, s1, 01005; VI-NEXT: v_mov_b32_e32 v2, s41006; VI-NEXT: v_mov_b32_e32 v4, s31007; VI-NEXT: v_mov_b32_e32 v0, s01008; VI-NEXT: v_mov_b32_e32 v3, s51009; VI-NEXT: v_mov_b32_e32 v1, s11010; VI-NEXT: v_mov_b32_e32 v5, s21011; VI-NEXT: flat_store_short v[2:3], v41012; VI-NEXT: flat_store_dword v[0:1], v51013; VI-NEXT: s_endpgm1014;1015; GFX9-LABEL: v3i16_arg:1016; GFX9: ; %bb.0: ; %entry1017; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x01018; GFX9-NEXT: v_mov_b32_e32 v0, 01019; GFX9-NEXT: s_waitcnt lgkmcnt(0)1020; GFX9-NEXT: v_mov_b32_e32 v1, s31021; GFX9-NEXT: v_mov_b32_e32 v2, s21022; GFX9-NEXT: global_store_short v0, v1, s[0:1] offset:41023; GFX9-NEXT: global_store_dword v0, v2, s[0:1]1024; GFX9-NEXT: s_endpgm1025;1026; EG-LABEL: v3i16_arg:1027; EG: ; %bb.0: ; %entry1028; EG-NEXT: ALU 0, @12, KC0[], KC1[]1029; EG-NEXT: TEX 2 @61030; EG-NEXT: ALU 19, @13, KC0[CB0:0-32], KC1[]1031; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T6.X, T7.X, 01032; EG-NEXT: MEM_RAT MSKOR T5.XW, T8.X1033; EG-NEXT: CF_END1034; EG-NEXT: Fetch clause starting at 6:1035; EG-NEXT: VTX_READ_16 T6.X, T5.X, 44, #31036; EG-NEXT: VTX_READ_16 T7.X, T5.X, 46, #31037; EG-NEXT: VTX_READ_16 T5.X, T5.X, 48, #31038; EG-NEXT: ALU clause starting at 12:1039; EG-NEXT: MOV * T5.X, 0.0,1040; EG-NEXT: ALU clause starting at 13:1041; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x,1042; EG-NEXT: 4(5.605194e-45), 0(0.000000e+00)1043; EG-NEXT: AND_INT T1.W, PV.W, literal.x,1044; EG-NEXT: AND_INT * T2.W, T5.X, literal.y,1045; EG-NEXT: 3(4.203895e-45), 65535(9.183409e-41)1046; EG-NEXT: LSHL * T1.W, PV.W, literal.x,1047; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)1048; EG-NEXT: LSHL T5.X, T2.W, PV.W,1049; EG-NEXT: LSHL * T5.W, literal.x, PV.W,1050; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)1051; EG-NEXT: MOV T5.Y, 0.0,1052; EG-NEXT: MOV * T5.Z, 0.0,1053; EG-NEXT: LSHR T8.X, T0.W, literal.x,1054; EG-NEXT: LSHL T0.W, T7.X, literal.y,1055; EG-NEXT: AND_INT * T1.W, T6.X, literal.z,1056; EG-NEXT: 2(2.802597e-45), 16(2.242078e-44)1057; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)1058; EG-NEXT: OR_INT T6.X, PV.W, PS,1059; EG-NEXT: LSHR * T7.X, KC0[2].Y, literal.x,1060; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1061;1062; CM-LABEL: v3i16_arg:1063; CM: ; %bb.0: ; %entry1064; CM-NEXT: ALU 0, @12, KC0[], KC1[]1065; CM-NEXT: TEX 2 @61066; CM-NEXT: ALU 19, @13, KC0[CB0:0-32], KC1[]1067; CM-NEXT: MEM_RAT MSKOR T5.XW, T8.X1068; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T6.X, T7.X1069; CM-NEXT: CF_END1070; CM-NEXT: Fetch clause starting at 6:1071; CM-NEXT: VTX_READ_16 T6.X, T5.X, 44, #31072; CM-NEXT: VTX_READ_16 T7.X, T5.X, 46, #31073; CM-NEXT: VTX_READ_16 T5.X, T5.X, 48, #31074; CM-NEXT: ALU clause starting at 12:1075; CM-NEXT: MOV * T5.X, 0.0,1076; CM-NEXT: ALU clause starting at 13:1077; CM-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x,1078; CM-NEXT: 4(5.605194e-45), 0(0.000000e+00)1079; CM-NEXT: AND_INT * T1.W, PV.W, literal.x,1080; CM-NEXT: 3(4.203895e-45), 0(0.000000e+00)1081; CM-NEXT: AND_INT T0.Z, T5.X, literal.x,1082; CM-NEXT: LSHL * T1.W, PV.W, literal.y,1083; CM-NEXT: 65535(9.183409e-41), 3(4.203895e-45)1084; CM-NEXT: LSHL T5.X, PV.Z, PV.W,1085; CM-NEXT: LSHL * T5.W, literal.x, PV.W,1086; CM-NEXT: 65535(9.183409e-41), 0(0.000000e+00)1087; CM-NEXT: MOV T5.Y, 0.0,1088; CM-NEXT: MOV * T5.Z, 0.0,1089; CM-NEXT: LSHL T0.Z, T7.X, literal.x,1090; CM-NEXT: AND_INT * T1.W, T6.X, literal.y, BS:VEC_120/SCL_2121091; CM-NEXT: 16(2.242078e-44), 65535(9.183409e-41)1092; CM-NEXT: OR_INT * T6.X, PV.Z, PV.W,1093; CM-NEXT: LSHR * T7.X, KC0[2].Y, literal.x,1094; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)1095; CM-NEXT: LSHR * T8.X, T0.W, literal.x,1096; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)1097entry:1098 store <3 x i16> %in, ptr addrspace(1) %out, align 41099 ret void1100}1101 1102define amdgpu_kernel void @v3i32_arg(ptr addrspace(1) nocapture %out, <3 x i32> %in) nounwind {1103; SI-LABEL: v3i32_arg:1104; SI: ; %bb.0: ; %entry1105; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xd1106; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x91107; SI-NEXT: s_mov_b32 s7, 0xf0001108; SI-NEXT: s_mov_b32 s6, -11109; SI-NEXT: s_waitcnt lgkmcnt(0)1110; SI-NEXT: v_mov_b32_e32 v0, s21111; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0 offset:81112; SI-NEXT: s_waitcnt expcnt(0)1113; SI-NEXT: v_mov_b32_e32 v0, s01114; SI-NEXT: v_mov_b32_e32 v1, s11115; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 01116; SI-NEXT: s_endpgm1117;1118; VI-LABEL: v3i32_arg:1119; VI: ; %bb.0: ; %entry1120; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x341121; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x241122; VI-NEXT: s_waitcnt lgkmcnt(0)1123; VI-NEXT: v_mov_b32_e32 v0, s01124; VI-NEXT: v_mov_b32_e32 v3, s41125; VI-NEXT: v_mov_b32_e32 v1, s11126; VI-NEXT: v_mov_b32_e32 v2, s21127; VI-NEXT: v_mov_b32_e32 v4, s51128; VI-NEXT: flat_store_dwordx3 v[3:4], v[0:2]1129; VI-NEXT: s_endpgm1130;1131; GFX9-LABEL: v3i32_arg:1132; GFX9: ; %bb.0: ; %entry1133; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x101134; GFX9-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x01135; GFX9-NEXT: v_mov_b32_e32 v3, 01136; GFX9-NEXT: s_waitcnt lgkmcnt(0)1137; GFX9-NEXT: v_mov_b32_e32 v0, s01138; GFX9-NEXT: v_mov_b32_e32 v1, s11139; GFX9-NEXT: v_mov_b32_e32 v2, s21140; GFX9-NEXT: global_store_dwordx3 v3, v[0:2], s[4:5]1141; GFX9-NEXT: s_endpgm1142;1143; EG-LABEL: v3i32_arg:1144; EG: ; %bb.0: ; %entry1145; EG-NEXT: ALU 8, @4, KC0[CB0:0-32], KC1[]1146; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T3.X, T2.X, 01147; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 11148; EG-NEXT: CF_END1149; EG-NEXT: ALU clause starting at 4:1150; EG-NEXT: MOV * T0.Y, KC0[3].Z,1151; EG-NEXT: MOV T0.X, KC0[3].Y,1152; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,1153; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1154; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x,1155; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)1156; EG-NEXT: LSHR T2.X, PV.W, literal.x,1157; EG-NEXT: MOV * T3.X, KC0[3].W,1158; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1159;1160; CM-LABEL: v3i32_arg:1161; CM: ; %bb.0: ; %entry1162; CM-NEXT: ALU 8, @4, KC0[CB0:0-32], KC1[]1163; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T2, T3.X1164; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1.X, T0.X1165; CM-NEXT: CF_END1166; CM-NEXT: ALU clause starting at 4:1167; CM-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x,1168; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00)1169; CM-NEXT: LSHR * T0.X, PV.W, literal.x,1170; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)1171; CM-NEXT: MOV T1.X, KC0[3].W,1172; CM-NEXT: MOV * T2.Y, KC0[3].Z,1173; CM-NEXT: MOV * T2.X, KC0[3].Y,1174; CM-NEXT: LSHR * T3.X, KC0[2].Y, literal.x,1175; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)1176entry:1177 store <3 x i32> %in, ptr addrspace(1) %out, align 41178 ret void1179}1180 1181define amdgpu_kernel void @v3f32_arg(ptr addrspace(1) nocapture %out, <3 x float> %in) nounwind {1182; SI-LABEL: v3f32_arg:1183; SI: ; %bb.0: ; %entry1184; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xd1185; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x91186; SI-NEXT: s_mov_b32 s7, 0xf0001187; SI-NEXT: s_mov_b32 s6, -11188; SI-NEXT: s_waitcnt lgkmcnt(0)1189; SI-NEXT: v_mov_b32_e32 v0, s21190; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0 offset:81191; SI-NEXT: s_waitcnt expcnt(0)1192; SI-NEXT: v_mov_b32_e32 v0, s01193; SI-NEXT: v_mov_b32_e32 v1, s11194; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 01195; SI-NEXT: s_endpgm1196;1197; VI-LABEL: v3f32_arg:1198; VI: ; %bb.0: ; %entry1199; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x341200; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x241201; VI-NEXT: s_waitcnt lgkmcnt(0)1202; VI-NEXT: v_mov_b32_e32 v0, s01203; VI-NEXT: v_mov_b32_e32 v3, s41204; VI-NEXT: v_mov_b32_e32 v1, s11205; VI-NEXT: v_mov_b32_e32 v2, s21206; VI-NEXT: v_mov_b32_e32 v4, s51207; VI-NEXT: flat_store_dwordx3 v[3:4], v[0:2]1208; VI-NEXT: s_endpgm1209;1210; GFX9-LABEL: v3f32_arg:1211; GFX9: ; %bb.0: ; %entry1212; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x101213; GFX9-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x01214; GFX9-NEXT: v_mov_b32_e32 v3, 01215; GFX9-NEXT: s_waitcnt lgkmcnt(0)1216; GFX9-NEXT: v_mov_b32_e32 v0, s01217; GFX9-NEXT: v_mov_b32_e32 v1, s11218; GFX9-NEXT: v_mov_b32_e32 v2, s21219; GFX9-NEXT: global_store_dwordx3 v3, v[0:2], s[4:5]1220; GFX9-NEXT: s_endpgm1221;1222; EG-LABEL: v3f32_arg:1223; EG: ; %bb.0: ; %entry1224; EG-NEXT: ALU 8, @4, KC0[CB0:0-32], KC1[]1225; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T3.X, T2.X, 01226; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 11227; EG-NEXT: CF_END1228; EG-NEXT: ALU clause starting at 4:1229; EG-NEXT: MOV * T0.Y, KC0[3].Z,1230; EG-NEXT: MOV T0.X, KC0[3].Y,1231; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,1232; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1233; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x,1234; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)1235; EG-NEXT: LSHR T2.X, PV.W, literal.x,1236; EG-NEXT: MOV * T3.X, KC0[3].W,1237; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1238;1239; CM-LABEL: v3f32_arg:1240; CM: ; %bb.0: ; %entry1241; CM-NEXT: ALU 8, @4, KC0[CB0:0-32], KC1[]1242; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T2, T3.X1243; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1.X, T0.X1244; CM-NEXT: CF_END1245; CM-NEXT: ALU clause starting at 4:1246; CM-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x,1247; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00)1248; CM-NEXT: LSHR * T0.X, PV.W, literal.x,1249; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)1250; CM-NEXT: MOV T1.X, KC0[3].W,1251; CM-NEXT: MOV * T2.Y, KC0[3].Z,1252; CM-NEXT: MOV * T2.X, KC0[3].Y,1253; CM-NEXT: LSHR * T3.X, KC0[2].Y, literal.x,1254; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)1255entry:1256 store <3 x float> %in, ptr addrspace(1) %out, align 41257 ret void1258}1259 1260define amdgpu_kernel void @v4i8_arg(ptr addrspace(1) %out, <4 x i8> %in) {1261; SI-LABEL: v4i8_arg:1262; SI: ; %bb.0: ; %entry1263; SI-NEXT: s_load_dword s6, s[4:5], 0xb1264; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x91265; SI-NEXT: s_mov_b32 s3, 0xf0001266; SI-NEXT: s_mov_b32 s2, -11267; SI-NEXT: s_waitcnt lgkmcnt(0)1268; SI-NEXT: v_mov_b32_e32 v0, s61269; SI-NEXT: buffer_store_dword v0, off, s[0:3], 01270; SI-NEXT: s_endpgm1271;1272; VI-LABEL: v4i8_arg:1273; VI: ; %bb.0: ; %entry1274; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x241275; VI-NEXT: s_load_dword s2, s[4:5], 0x2c1276; VI-NEXT: s_waitcnt lgkmcnt(0)1277; VI-NEXT: v_mov_b32_e32 v0, s01278; VI-NEXT: v_mov_b32_e32 v1, s11279; VI-NEXT: v_mov_b32_e32 v2, s21280; VI-NEXT: flat_store_dword v[0:1], v21281; VI-NEXT: s_endpgm1282;1283; GFX9-LABEL: v4i8_arg:1284; GFX9: ; %bb.0: ; %entry1285; GFX9-NEXT: s_load_dword s2, s[8:9], 0x81286; GFX9-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x01287; GFX9-NEXT: v_mov_b32_e32 v0, 01288; GFX9-NEXT: s_waitcnt lgkmcnt(0)1289; GFX9-NEXT: v_mov_b32_e32 v1, s21290; GFX9-NEXT: global_store_dword v0, v1, s[0:1]1291; GFX9-NEXT: s_endpgm1292;1293; EG-LABEL: v4i8_arg:1294; EG: ; %bb.0: ; %entry1295; EG-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]1296; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 11297; EG-NEXT: CF_END1298; EG-NEXT: PAD1299; EG-NEXT: ALU clause starting at 4:1300; EG-NEXT: MOV T0.X, KC0[2].Z,1301; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,1302; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1303;1304; CM-LABEL: v4i8_arg:1305; CM: ; %bb.0: ; %entry1306; CM-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]1307; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X1308; CM-NEXT: CF_END1309; CM-NEXT: PAD1310; CM-NEXT: ALU clause starting at 4:1311; CM-NEXT: MOV * T0.X, KC0[2].Z,1312; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,1313; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)1314entry:1315 store <4 x i8> %in, ptr addrspace(1) %out1316 ret void1317}1318 1319define amdgpu_kernel void @v4i16_arg(ptr addrspace(1) %out, <4 x i16> %in) {1320; SI-LABEL: v4i16_arg:1321; SI: ; %bb.0: ; %entry1322; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91323; SI-NEXT: s_mov_b32 s7, 0xf0001324; SI-NEXT: s_mov_b32 s6, -11325; SI-NEXT: s_waitcnt lgkmcnt(0)1326; SI-NEXT: s_mov_b32 s4, s01327; SI-NEXT: s_mov_b32 s5, s11328; SI-NEXT: v_mov_b32_e32 v0, s21329; SI-NEXT: v_mov_b32_e32 v1, s31330; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 01331; SI-NEXT: s_endpgm1332;1333; VI-LABEL: v4i16_arg:1334; VI: ; %bb.0: ; %entry1335; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241336; VI-NEXT: s_waitcnt lgkmcnt(0)1337; VI-NEXT: v_mov_b32_e32 v0, s01338; VI-NEXT: v_mov_b32_e32 v2, s21339; VI-NEXT: v_mov_b32_e32 v1, s11340; VI-NEXT: v_mov_b32_e32 v3, s31341; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]1342; VI-NEXT: s_endpgm1343;1344; GFX9-LABEL: v4i16_arg:1345; GFX9: ; %bb.0: ; %entry1346; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x01347; GFX9-NEXT: v_mov_b32_e32 v2, 01348; GFX9-NEXT: s_waitcnt lgkmcnt(0)1349; GFX9-NEXT: v_mov_b32_e32 v0, s21350; GFX9-NEXT: v_mov_b32_e32 v1, s31351; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]1352; GFX9-NEXT: s_endpgm1353;1354; EG-LABEL: v4i16_arg:1355; EG: ; %bb.0: ; %entry1356; EG-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[]1357; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 11358; EG-NEXT: CF_END1359; EG-NEXT: PAD1360; EG-NEXT: ALU clause starting at 4:1361; EG-NEXT: MOV * T0.Y, KC0[3].X,1362; EG-NEXT: MOV T0.X, KC0[2].W,1363; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,1364; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1365;1366; CM-LABEL: v4i16_arg:1367; CM: ; %bb.0: ; %entry1368; CM-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[]1369; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0, T1.X1370; CM-NEXT: CF_END1371; CM-NEXT: PAD1372; CM-NEXT: ALU clause starting at 4:1373; CM-NEXT: MOV * T0.Y, KC0[3].X,1374; CM-NEXT: MOV * T0.X, KC0[2].W,1375; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,1376; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)1377entry:1378 store <4 x i16> %in, ptr addrspace(1) %out1379 ret void1380}1381 1382define amdgpu_kernel void @v4i32_arg(ptr addrspace(1) nocapture %out, <4 x i32> %in) nounwind {1383; SI-LABEL: v4i32_arg:1384; SI: ; %bb.0: ; %entry1385; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xd1386; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x91387; SI-NEXT: s_mov_b32 s7, 0xf0001388; SI-NEXT: s_mov_b32 s6, -11389; SI-NEXT: s_waitcnt lgkmcnt(0)1390; SI-NEXT: v_mov_b32_e32 v0, s01391; SI-NEXT: v_mov_b32_e32 v1, s11392; SI-NEXT: v_mov_b32_e32 v2, s21393; SI-NEXT: v_mov_b32_e32 v3, s31394; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 01395; SI-NEXT: s_endpgm1396;1397; VI-LABEL: v4i32_arg:1398; VI: ; %bb.0: ; %entry1399; VI-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x241400; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x341401; VI-NEXT: s_waitcnt lgkmcnt(0)1402; VI-NEXT: v_mov_b32_e32 v4, s61403; VI-NEXT: v_mov_b32_e32 v0, s01404; VI-NEXT: v_mov_b32_e32 v5, s71405; VI-NEXT: v_mov_b32_e32 v1, s11406; VI-NEXT: v_mov_b32_e32 v2, s21407; VI-NEXT: v_mov_b32_e32 v3, s31408; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]1409; VI-NEXT: s_endpgm1410;1411; GFX9-LABEL: v4i32_arg:1412; GFX9: ; %bb.0: ; %entry1413; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x101414; GFX9-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x01415; GFX9-NEXT: v_mov_b32_e32 v4, 01416; GFX9-NEXT: s_waitcnt lgkmcnt(0)1417; GFX9-NEXT: v_mov_b32_e32 v0, s01418; GFX9-NEXT: v_mov_b32_e32 v1, s11419; GFX9-NEXT: v_mov_b32_e32 v2, s21420; GFX9-NEXT: v_mov_b32_e32 v3, s31421; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[4:5]1422; GFX9-NEXT: s_endpgm1423;1424; EG-LABEL: v4i32_arg:1425; EG: ; %bb.0: ; %entry1426; EG-NEXT: ALU 5, @4, KC0[CB0:0-32], KC1[]1427; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 11428; EG-NEXT: CF_END1429; EG-NEXT: PAD1430; EG-NEXT: ALU clause starting at 4:1431; EG-NEXT: MOV * T0.W, KC0[4].X,1432; EG-NEXT: MOV * T0.Z, KC0[3].W,1433; EG-NEXT: MOV * T0.Y, KC0[3].Z,1434; EG-NEXT: MOV T0.X, KC0[3].Y,1435; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,1436; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1437;1438; CM-LABEL: v4i32_arg:1439; CM: ; %bb.0: ; %entry1440; CM-NEXT: ALU 5, @4, KC0[CB0:0-32], KC1[]1441; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0, T1.X1442; CM-NEXT: CF_END1443; CM-NEXT: PAD1444; CM-NEXT: ALU clause starting at 4:1445; CM-NEXT: MOV * T0.W, KC0[4].X,1446; CM-NEXT: MOV * T0.Z, KC0[3].W,1447; CM-NEXT: MOV * T0.Y, KC0[3].Z,1448; CM-NEXT: MOV * T0.X, KC0[3].Y,1449; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,1450; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)1451entry:1452 store <4 x i32> %in, ptr addrspace(1) %out, align 41453 ret void1454}1455 1456define amdgpu_kernel void @v4f32_arg(ptr addrspace(1) nocapture %out, <4 x float> %in) nounwind {1457; SI-LABEL: v4f32_arg:1458; SI: ; %bb.0: ; %entry1459; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xd1460; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x91461; SI-NEXT: s_mov_b32 s7, 0xf0001462; SI-NEXT: s_mov_b32 s6, -11463; SI-NEXT: s_waitcnt lgkmcnt(0)1464; SI-NEXT: v_mov_b32_e32 v0, s01465; SI-NEXT: v_mov_b32_e32 v1, s11466; SI-NEXT: v_mov_b32_e32 v2, s21467; SI-NEXT: v_mov_b32_e32 v3, s31468; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 01469; SI-NEXT: s_endpgm1470;1471; VI-LABEL: v4f32_arg:1472; VI: ; %bb.0: ; %entry1473; VI-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x241474; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x341475; VI-NEXT: s_waitcnt lgkmcnt(0)1476; VI-NEXT: v_mov_b32_e32 v4, s61477; VI-NEXT: v_mov_b32_e32 v0, s01478; VI-NEXT: v_mov_b32_e32 v5, s71479; VI-NEXT: v_mov_b32_e32 v1, s11480; VI-NEXT: v_mov_b32_e32 v2, s21481; VI-NEXT: v_mov_b32_e32 v3, s31482; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]1483; VI-NEXT: s_endpgm1484;1485; GFX9-LABEL: v4f32_arg:1486; GFX9: ; %bb.0: ; %entry1487; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x101488; GFX9-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x01489; GFX9-NEXT: v_mov_b32_e32 v4, 01490; GFX9-NEXT: s_waitcnt lgkmcnt(0)1491; GFX9-NEXT: v_mov_b32_e32 v0, s01492; GFX9-NEXT: v_mov_b32_e32 v1, s11493; GFX9-NEXT: v_mov_b32_e32 v2, s21494; GFX9-NEXT: v_mov_b32_e32 v3, s31495; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[4:5]1496; GFX9-NEXT: s_endpgm1497;1498; EG-LABEL: v4f32_arg:1499; EG: ; %bb.0: ; %entry1500; EG-NEXT: ALU 5, @4, KC0[CB0:0-32], KC1[]1501; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 11502; EG-NEXT: CF_END1503; EG-NEXT: PAD1504; EG-NEXT: ALU clause starting at 4:1505; EG-NEXT: MOV * T0.W, KC0[4].X,1506; EG-NEXT: MOV * T0.Z, KC0[3].W,1507; EG-NEXT: MOV * T0.Y, KC0[3].Z,1508; EG-NEXT: MOV T0.X, KC0[3].Y,1509; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,1510; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1511;1512; CM-LABEL: v4f32_arg:1513; CM: ; %bb.0: ; %entry1514; CM-NEXT: ALU 5, @4, KC0[CB0:0-32], KC1[]1515; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0, T1.X1516; CM-NEXT: CF_END1517; CM-NEXT: PAD1518; CM-NEXT: ALU clause starting at 4:1519; CM-NEXT: MOV * T0.W, KC0[4].X,1520; CM-NEXT: MOV * T0.Z, KC0[3].W,1521; CM-NEXT: MOV * T0.Y, KC0[3].Z,1522; CM-NEXT: MOV * T0.X, KC0[3].Y,1523; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,1524; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)1525entry:1526 store <4 x float> %in, ptr addrspace(1) %out, align 41527 ret void1528}1529 1530define amdgpu_kernel void @v5i8_arg(ptr addrspace(1) nocapture %out, <5 x i8> %in) nounwind {1531; SI-LABEL: v5i8_arg:1532; SI: ; %bb.0: ; %entry1533; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91534; SI-NEXT: s_mov_b32 s7, 0xf0001535; SI-NEXT: s_mov_b32 s6, -11536; SI-NEXT: s_waitcnt lgkmcnt(0)1537; SI-NEXT: s_mov_b32 s4, s01538; SI-NEXT: s_mov_b32 s5, s11539; SI-NEXT: v_mov_b32_e32 v0, s31540; SI-NEXT: buffer_store_byte v0, off, s[4:7], 0 offset:41541; SI-NEXT: s_waitcnt expcnt(0)1542; SI-NEXT: v_mov_b32_e32 v0, s21543; SI-NEXT: buffer_store_dword v0, off, s[4:7], 01544; SI-NEXT: s_endpgm1545;1546; VI-LABEL: v5i8_arg:1547; VI: ; %bb.0: ; %entry1548; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241549; VI-NEXT: s_waitcnt lgkmcnt(0)1550; VI-NEXT: s_add_u32 s4, s0, 41551; VI-NEXT: s_addc_u32 s5, s1, 01552; VI-NEXT: v_mov_b32_e32 v2, s41553; VI-NEXT: v_mov_b32_e32 v4, s31554; VI-NEXT: v_mov_b32_e32 v0, s01555; VI-NEXT: v_mov_b32_e32 v3, s51556; VI-NEXT: v_mov_b32_e32 v1, s11557; VI-NEXT: v_mov_b32_e32 v5, s21558; VI-NEXT: flat_store_byte v[2:3], v41559; VI-NEXT: flat_store_dword v[0:1], v51560; VI-NEXT: s_endpgm1561;1562; GFX9-LABEL: v5i8_arg:1563; GFX9: ; %bb.0: ; %entry1564; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x01565; GFX9-NEXT: v_mov_b32_e32 v0, 01566; GFX9-NEXT: s_waitcnt lgkmcnt(0)1567; GFX9-NEXT: v_mov_b32_e32 v1, s31568; GFX9-NEXT: v_mov_b32_e32 v2, s21569; GFX9-NEXT: global_store_byte v0, v1, s[0:1] offset:41570; GFX9-NEXT: global_store_dword v0, v2, s[0:1]1571; GFX9-NEXT: s_endpgm1572;1573; EG-LABEL: v5i8_arg:1574; EG: ; %bb.0: ; %entry1575; EG-NEXT: ALU 0, @16, KC0[], KC1[]1576; EG-NEXT: TEX 4 @61577; EG-NEXT: ALU 28, @17, KC0[CB0:0-32], KC1[]1578; EG-NEXT: MEM_RAT MSKOR T5.XW, T8.X1579; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T6.X, T7.X, 11580; EG-NEXT: CF_END1581; EG-NEXT: Fetch clause starting at 6:1582; EG-NEXT: VTX_READ_8 T6.X, T5.X, 44, #31583; EG-NEXT: VTX_READ_8 T7.X, T5.X, 47, #31584; EG-NEXT: VTX_READ_8 T8.X, T5.X, 45, #31585; EG-NEXT: VTX_READ_8 T9.X, T5.X, 46, #31586; EG-NEXT: VTX_READ_8 T5.X, T5.X, 48, #31587; EG-NEXT: ALU clause starting at 16:1588; EG-NEXT: MOV * T5.X, 0.0,1589; EG-NEXT: ALU clause starting at 17:1590; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x,1591; EG-NEXT: 4(5.605194e-45), 0(0.000000e+00)1592; EG-NEXT: AND_INT T1.W, PV.W, literal.x,1593; EG-NEXT: AND_INT * T2.W, T5.X, literal.y,1594; EG-NEXT: 3(4.203895e-45), 255(3.573311e-43)1595; EG-NEXT: LSHL * T1.W, PV.W, literal.x,1596; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)1597; EG-NEXT: LSHL T5.X, T2.W, PV.W,1598; EG-NEXT: LSHL * T5.W, literal.x, PV.W,1599; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00)1600; EG-NEXT: MOV T5.Y, 0.0,1601; EG-NEXT: MOV T5.Z, 0.0,1602; EG-NEXT: AND_INT T1.W, T9.X, literal.x,1603; EG-NEXT: AND_INT * T0.Z, T8.X, literal.x,1604; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00)1605; EG-NEXT: LSHL T1.W, PV.W, literal.x,1606; EG-NEXT: LSHL * T2.W, T7.X, literal.y,1607; EG-NEXT: 16(2.242078e-44), 24(3.363116e-44)1608; EG-NEXT: OR_INT T1.W, PS, PV.W,1609; EG-NEXT: LSHL * T2.W, T0.Z, literal.x,1610; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)1611; EG-NEXT: OR_INT T1.W, PV.W, PS,1612; EG-NEXT: AND_INT * T2.W, T6.X, literal.x,1613; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00)1614; EG-NEXT: OR_INT T6.X, PV.W, PS,1615; EG-NEXT: LSHR * T7.X, KC0[2].Y, literal.x,1616; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1617; EG-NEXT: LSHR * T8.X, T0.W, literal.x,1618; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1619;1620; CM-LABEL: v5i8_arg:1621; CM: ; %bb.0: ; %entry1622; CM-NEXT: ALU 0, @16, KC0[], KC1[]1623; CM-NEXT: TEX 4 @61624; CM-NEXT: ALU 28, @17, KC0[CB0:0-32], KC1[]1625; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T6.X, T8.X1626; CM-NEXT: MEM_RAT MSKOR T5.XW, T7.X1627; CM-NEXT: CF_END1628; CM-NEXT: Fetch clause starting at 6:1629; CM-NEXT: VTX_READ_8 T6.X, T5.X, 44, #31630; CM-NEXT: VTX_READ_8 T7.X, T5.X, 47, #31631; CM-NEXT: VTX_READ_8 T8.X, T5.X, 45, #31632; CM-NEXT: VTX_READ_8 T9.X, T5.X, 46, #31633; CM-NEXT: VTX_READ_8 T5.X, T5.X, 48, #31634; CM-NEXT: ALU clause starting at 16:1635; CM-NEXT: MOV * T5.X, 0.0,1636; CM-NEXT: ALU clause starting at 17:1637; CM-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x,1638; CM-NEXT: 4(5.605194e-45), 0(0.000000e+00)1639; CM-NEXT: AND_INT * T1.W, PV.W, literal.x,1640; CM-NEXT: 3(4.203895e-45), 0(0.000000e+00)1641; CM-NEXT: AND_INT T0.Z, T5.X, literal.x,1642; CM-NEXT: LSHL * T1.W, PV.W, literal.y,1643; CM-NEXT: 255(3.573311e-43), 3(4.203895e-45)1644; CM-NEXT: LSHL T5.X, PV.Z, PV.W,1645; CM-NEXT: LSHL * T5.W, literal.x, PV.W,1646; CM-NEXT: 255(3.573311e-43), 0(0.000000e+00)1647; CM-NEXT: MOV T5.Y, 0.0,1648; CM-NEXT: MOV T5.Z, 0.0,1649; CM-NEXT: AND_INT * T1.W, T9.X, literal.x,1650; CM-NEXT: 255(3.573311e-43), 0(0.000000e+00)1651; CM-NEXT: AND_INT T0.Y, T8.X, literal.x,1652; CM-NEXT: LSHL T0.Z, PV.W, literal.y,1653; CM-NEXT: LSHL * T1.W, T7.X, literal.z, BS:VEC_120/SCL_2121654; CM-NEXT: 255(3.573311e-43), 16(2.242078e-44)1655; CM-NEXT: 24(3.363116e-44), 0(0.000000e+00)1656; CM-NEXT: OR_INT T0.Z, PV.W, PV.Z,1657; CM-NEXT: LSHL * T1.W, PV.Y, literal.x,1658; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00)1659; CM-NEXT: LSHR T7.X, T0.W, literal.x,1660; CM-NEXT: OR_INT T0.Z, PV.Z, PV.W,1661; CM-NEXT: AND_INT * T0.W, T6.X, literal.y,1662; CM-NEXT: 2(2.802597e-45), 255(3.573311e-43)1663; CM-NEXT: OR_INT * T6.X, PV.Z, PV.W,1664; CM-NEXT: LSHR * T8.X, KC0[2].Y, literal.x,1665; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)1666entry:1667 store <5 x i8> %in, ptr addrspace(1) %out, align 41668 ret void1669}1670 1671define amdgpu_kernel void @v5i16_arg(ptr addrspace(1) nocapture %out, <5 x i16> %in) nounwind {1672; SI-LABEL: v5i16_arg:1673; SI: ; %bb.0: ; %entry1674; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x91675; SI-NEXT: s_load_dword s6, s[4:5], 0xf1676; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd1677; SI-NEXT: s_mov_b32 s3, 0xf0001678; SI-NEXT: s_mov_b32 s2, -11679; SI-NEXT: s_waitcnt lgkmcnt(0)1680; SI-NEXT: v_mov_b32_e32 v0, s61681; SI-NEXT: buffer_store_short v0, off, s[0:3], 0 offset:81682; SI-NEXT: s_waitcnt expcnt(0)1683; SI-NEXT: v_mov_b32_e32 v0, s41684; SI-NEXT: v_mov_b32_e32 v1, s51685; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 01686; SI-NEXT: s_endpgm1687;1688; VI-LABEL: v5i16_arg:1689; VI: ; %bb.0: ; %entry1690; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x241691; VI-NEXT: s_load_dword s6, s[4:5], 0x3c1692; VI-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x341693; VI-NEXT: s_waitcnt lgkmcnt(0)1694; VI-NEXT: s_add_u32 s4, s0, 81695; VI-NEXT: s_addc_u32 s5, s1, 01696; VI-NEXT: v_mov_b32_e32 v2, s41697; VI-NEXT: v_mov_b32_e32 v4, s61698; VI-NEXT: v_mov_b32_e32 v3, s51699; VI-NEXT: v_mov_b32_e32 v0, s01700; VI-NEXT: flat_store_short v[2:3], v41701; VI-NEXT: v_mov_b32_e32 v2, s21702; VI-NEXT: v_mov_b32_e32 v1, s11703; VI-NEXT: v_mov_b32_e32 v3, s31704; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]1705; VI-NEXT: s_endpgm1706;1707; GFX9-LABEL: v5i16_arg:1708; GFX9: ; %bb.0: ; %entry1709; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x101710; GFX9-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x01711; GFX9-NEXT: v_mov_b32_e32 v2, 01712; GFX9-NEXT: s_waitcnt lgkmcnt(0)1713; GFX9-NEXT: v_mov_b32_e32 v3, s21714; GFX9-NEXT: v_mov_b32_e32 v0, s01715; GFX9-NEXT: v_mov_b32_e32 v1, s11716; GFX9-NEXT: global_store_short v2, v3, s[4:5] offset:81717; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[4:5]1718; GFX9-NEXT: s_endpgm1719;1720; EG-LABEL: v5i16_arg:1721; EG: ; %bb.0: ; %entry1722; EG-NEXT: ALU 0, @20, KC0[], KC1[]1723; EG-NEXT: TEX 4 @101724; EG-NEXT: ALU 65, @21, KC0[CB0:0-32], KC1[]1725; EG-NEXT: MEM_RAT MSKOR T5.XW, T9.X1726; EG-NEXT: MEM_RAT MSKOR T4.XW, T7.X1727; EG-NEXT: MEM_RAT MSKOR T3.XW, T2.X1728; EG-NEXT: MEM_RAT MSKOR T6.XW, T1.X1729; EG-NEXT: MEM_RAT MSKOR T8.XW, T0.X1730; EG-NEXT: CF_END1731; EG-NEXT: PAD1732; EG-NEXT: Fetch clause starting at 10:1733; EG-NEXT: VTX_READ_16 T1.X, T0.X, 58, #31734; EG-NEXT: VTX_READ_16 T2.X, T0.X, 56, #31735; EG-NEXT: VTX_READ_16 T3.X, T0.X, 54, #31736; EG-NEXT: VTX_READ_16 T4.X, T0.X, 52, #31737; EG-NEXT: VTX_READ_16 T0.X, T0.X, 60, #31738; EG-NEXT: ALU clause starting at 20:1739; EG-NEXT: MOV * T0.X, 0.0,1740; EG-NEXT: ALU clause starting at 21:1741; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x,1742; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)1743; EG-NEXT: AND_INT T1.W, PV.W, literal.x,1744; EG-NEXT: AND_INT * T2.W, T0.X, literal.y,1745; EG-NEXT: 3(4.203895e-45), 65535(9.183409e-41)1746; EG-NEXT: LSHL * T1.W, PV.W, literal.x,1747; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)1748; EG-NEXT: LSHL T5.X, T2.W, PV.W,1749; EG-NEXT: LSHL * T5.W, literal.x, PV.W,1750; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)1751; EG-NEXT: MOV T5.Y, 0.0,1752; EG-NEXT: AND_INT T1.W, KC0[2].Y, literal.x,1753; EG-NEXT: AND_INT * T2.W, T4.X, literal.y,1754; EG-NEXT: 3(4.203895e-45), 65535(9.183409e-41)1755; EG-NEXT: LSHL * T1.W, PV.W, literal.x,1756; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)1757; EG-NEXT: LSHL T4.X, T2.W, PV.W,1758; EG-NEXT: LSHL * T4.W, literal.x, PV.W,1759; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)1760; EG-NEXT: MOV T4.Y, 0.0,1761; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.x,1762; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1763; EG-NEXT: AND_INT T2.W, PV.W, literal.x,1764; EG-NEXT: AND_INT * T3.W, T3.X, literal.y,1765; EG-NEXT: 3(4.203895e-45), 65535(9.183409e-41)1766; EG-NEXT: LSHL * T2.W, PV.W, literal.x,1767; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)1768; EG-NEXT: LSHL T3.X, T3.W, PV.W,1769; EG-NEXT: LSHL * T3.W, literal.x, PV.W,1770; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)1771; EG-NEXT: MOV T3.Y, 0.0,1772; EG-NEXT: ADD_INT * T2.W, KC0[2].Y, literal.x,1773; EG-NEXT: 4(5.605194e-45), 0(0.000000e+00)1774; EG-NEXT: AND_INT T6.W, PV.W, literal.x,1775; EG-NEXT: AND_INT * T7.W, T2.X, literal.y,1776; EG-NEXT: 3(4.203895e-45), 65535(9.183409e-41)1777; EG-NEXT: LSHL * T6.W, PV.W, literal.x,1778; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)1779; EG-NEXT: LSHL T6.X, T7.W, PV.W,1780; EG-NEXT: LSHL * T6.W, literal.x, PV.W,1781; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)1782; EG-NEXT: MOV T6.Y, 0.0,1783; EG-NEXT: ADD_INT * T7.W, KC0[2].Y, literal.x,1784; EG-NEXT: 6(8.407791e-45), 0(0.000000e+00)1785; EG-NEXT: AND_INT T8.W, PV.W, literal.x,1786; EG-NEXT: AND_INT * T9.W, T1.X, literal.y,1787; EG-NEXT: 3(4.203895e-45), 65535(9.183409e-41)1788; EG-NEXT: LSHL * T8.W, PV.W, literal.x,1789; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)1790; EG-NEXT: LSHL T8.X, T9.W, PV.W,1791; EG-NEXT: LSHL * T8.W, literal.x, PV.W,1792; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)1793; EG-NEXT: MOV T8.Y, 0.0,1794; EG-NEXT: MOV T5.Z, 0.0,1795; EG-NEXT: MOV * T4.Z, 0.0,1796; EG-NEXT: MOV T3.Z, 0.0,1797; EG-NEXT: MOV * T6.Z, 0.0,1798; EG-NEXT: MOV * T8.Z, 0.0,1799; EG-NEXT: LSHR T0.X, T7.W, literal.x,1800; EG-NEXT: LSHR * T1.X, T2.W, literal.x,1801; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1802; EG-NEXT: LSHR T2.X, T1.W, literal.x,1803; EG-NEXT: LSHR * T7.X, KC0[2].Y, literal.x,1804; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1805; EG-NEXT: LSHR * T9.X, T0.W, literal.x,1806; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1807;1808; CM-LABEL: v5i16_arg:1809; CM: ; %bb.0: ; %entry1810; CM-NEXT: ALU 0, @20, KC0[], KC1[]1811; CM-NEXT: TEX 4 @101812; CM-NEXT: ALU 67, @21, KC0[CB0:0-32], KC1[]1813; CM-NEXT: MEM_RAT MSKOR T5.XW, T9.X1814; CM-NEXT: MEM_RAT MSKOR T4.XW, T7.X1815; CM-NEXT: MEM_RAT MSKOR T3.XW, T2.X1816; CM-NEXT: MEM_RAT MSKOR T6.XW, T1.X1817; CM-NEXT: MEM_RAT MSKOR T8.XW, T0.X1818; CM-NEXT: CF_END1819; CM-NEXT: PAD1820; CM-NEXT: Fetch clause starting at 10:1821; CM-NEXT: VTX_READ_16 T1.X, T0.X, 58, #31822; CM-NEXT: VTX_READ_16 T2.X, T0.X, 56, #31823; CM-NEXT: VTX_READ_16 T3.X, T0.X, 54, #31824; CM-NEXT: VTX_READ_16 T4.X, T0.X, 52, #31825; CM-NEXT: VTX_READ_16 T0.X, T0.X, 60, #31826; CM-NEXT: ALU clause starting at 20:1827; CM-NEXT: MOV * T0.X, 0.0,1828; CM-NEXT: ALU clause starting at 21:1829; CM-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x,1830; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00)1831; CM-NEXT: AND_INT * T1.W, PV.W, literal.x,1832; CM-NEXT: 3(4.203895e-45), 0(0.000000e+00)1833; CM-NEXT: AND_INT T0.Z, T0.X, literal.x,1834; CM-NEXT: LSHL * T1.W, PV.W, literal.y,1835; CM-NEXT: 65535(9.183409e-41), 3(4.203895e-45)1836; CM-NEXT: LSHL T5.X, PV.Z, PV.W,1837; CM-NEXT: LSHL * T5.W, literal.x, PV.W,1838; CM-NEXT: 65535(9.183409e-41), 0(0.000000e+00)1839; CM-NEXT: MOV T5.Y, 0.0,1840; CM-NEXT: AND_INT * T1.W, KC0[2].Y, literal.x,1841; CM-NEXT: 3(4.203895e-45), 0(0.000000e+00)1842; CM-NEXT: AND_INT T0.Z, T4.X, literal.x,1843; CM-NEXT: LSHL * T1.W, PV.W, literal.y,1844; CM-NEXT: 65535(9.183409e-41), 3(4.203895e-45)1845; CM-NEXT: LSHL T4.X, PV.Z, PV.W,1846; CM-NEXT: LSHL * T4.W, literal.x, PV.W,1847; CM-NEXT: 65535(9.183409e-41), 0(0.000000e+00)1848; CM-NEXT: MOV T4.Y, 0.0,1849; CM-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.x,1850; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)1851; CM-NEXT: AND_INT * T2.W, PV.W, literal.x,1852; CM-NEXT: 3(4.203895e-45), 0(0.000000e+00)1853; CM-NEXT: AND_INT T0.Z, T3.X, literal.x,1854; CM-NEXT: LSHL * T2.W, PV.W, literal.y,1855; CM-NEXT: 65535(9.183409e-41), 3(4.203895e-45)1856; CM-NEXT: LSHL T3.X, PV.Z, PV.W,1857; CM-NEXT: LSHL * T3.W, literal.x, PV.W,1858; CM-NEXT: 65535(9.183409e-41), 0(0.000000e+00)1859; CM-NEXT: MOV T3.Y, 0.0,1860; CM-NEXT: ADD_INT * T2.W, KC0[2].Y, literal.x,1861; CM-NEXT: 4(5.605194e-45), 0(0.000000e+00)1862; CM-NEXT: AND_INT * T6.W, PV.W, literal.x,1863; CM-NEXT: 3(4.203895e-45), 0(0.000000e+00)1864; CM-NEXT: AND_INT T0.Z, T2.X, literal.x,1865; CM-NEXT: LSHL * T6.W, PV.W, literal.y,1866; CM-NEXT: 65535(9.183409e-41), 3(4.203895e-45)1867; CM-NEXT: LSHL T6.X, PV.Z, PV.W,1868; CM-NEXT: LSHL * T6.W, literal.x, PV.W,1869; CM-NEXT: 65535(9.183409e-41), 0(0.000000e+00)1870; CM-NEXT: MOV T6.Y, 0.0,1871; CM-NEXT: ADD_INT * T7.W, KC0[2].Y, literal.x,1872; CM-NEXT: 6(8.407791e-45), 0(0.000000e+00)1873; CM-NEXT: AND_INT * T8.W, PV.W, literal.x,1874; CM-NEXT: 3(4.203895e-45), 0(0.000000e+00)1875; CM-NEXT: AND_INT T0.Z, T1.X, literal.x,1876; CM-NEXT: LSHL * T8.W, PV.W, literal.y,1877; CM-NEXT: 65535(9.183409e-41), 3(4.203895e-45)1878; CM-NEXT: LSHL T8.X, PV.Z, PV.W,1879; CM-NEXT: LSHL * T8.W, literal.x, PV.W,1880; CM-NEXT: 65535(9.183409e-41), 0(0.000000e+00)1881; CM-NEXT: MOV T8.Y, 0.0,1882; CM-NEXT: MOV * T5.Z, 0.0,1883; CM-NEXT: MOV * T4.Z, 0.0,1884; CM-NEXT: MOV * T3.Z, 0.0,1885; CM-NEXT: MOV * T6.Z, 0.0,1886; CM-NEXT: MOV * T8.Z, 0.0,1887; CM-NEXT: LSHR * T0.X, T7.W, literal.x,1888; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)1889; CM-NEXT: LSHR * T1.X, T2.W, literal.x,1890; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)1891; CM-NEXT: LSHR * T2.X, T1.W, literal.x,1892; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)1893; CM-NEXT: LSHR * T7.X, KC0[2].Y, literal.x,1894; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)1895; CM-NEXT: LSHR * T9.X, T0.W, literal.x,1896; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)1897entry:1898 store <5 x i16> %in, ptr addrspace(1) %out, align 41899 ret void1900}1901 1902define amdgpu_kernel void @v5i32_arg(ptr addrspace(1) nocapture %out, <5 x i32> %in) nounwind {1903; SI-LABEL: v5i32_arg:1904; SI: ; %bb.0: ; %entry1905; SI-NEXT: s_load_dword s8, s[4:5], 0x151906; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x91907; SI-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x111908; SI-NEXT: s_mov_b32 s3, 0xf0001909; SI-NEXT: s_mov_b32 s2, -11910; SI-NEXT: s_waitcnt lgkmcnt(0)1911; SI-NEXT: v_mov_b32_e32 v0, s81912; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:161913; SI-NEXT: s_waitcnt expcnt(0)1914; SI-NEXT: v_mov_b32_e32 v0, s41915; SI-NEXT: v_mov_b32_e32 v1, s51916; SI-NEXT: v_mov_b32_e32 v2, s61917; SI-NEXT: v_mov_b32_e32 v3, s71918; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 01919; SI-NEXT: s_endpgm1920;1921; VI-LABEL: v5i32_arg:1922; VI: ; %bb.0: ; %entry1923; VI-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x241924; VI-NEXT: s_load_dword s8, s[4:5], 0x541925; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x441926; VI-NEXT: s_waitcnt lgkmcnt(0)1927; VI-NEXT: s_add_u32 s4, s6, 161928; VI-NEXT: s_addc_u32 s5, s7, 01929; VI-NEXT: v_mov_b32_e32 v0, s41930; VI-NEXT: v_mov_b32_e32 v2, s81931; VI-NEXT: v_mov_b32_e32 v1, s51932; VI-NEXT: v_mov_b32_e32 v4, s61933; VI-NEXT: flat_store_dword v[0:1], v21934; VI-NEXT: v_mov_b32_e32 v0, s01935; VI-NEXT: v_mov_b32_e32 v5, s71936; VI-NEXT: v_mov_b32_e32 v1, s11937; VI-NEXT: v_mov_b32_e32 v2, s21938; VI-NEXT: v_mov_b32_e32 v3, s31939; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]1940; VI-NEXT: s_endpgm1941;1942; GFX9-LABEL: v5i32_arg:1943; GFX9: ; %bb.0: ; %entry1944; GFX9-NEXT: s_load_dword s6, s[8:9], 0x301945; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x201946; GFX9-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x01947; GFX9-NEXT: v_mov_b32_e32 v4, 01948; GFX9-NEXT: s_waitcnt lgkmcnt(0)1949; GFX9-NEXT: v_mov_b32_e32 v5, s61950; GFX9-NEXT: v_mov_b32_e32 v0, s01951; GFX9-NEXT: v_mov_b32_e32 v1, s11952; GFX9-NEXT: v_mov_b32_e32 v2, s21953; GFX9-NEXT: v_mov_b32_e32 v3, s31954; GFX9-NEXT: global_store_dword v4, v5, s[4:5] offset:161955; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[4:5]1956; GFX9-NEXT: s_endpgm1957;1958; EG-LABEL: v5i32_arg:1959; EG: ; %bb.0: ; %entry1960; EG-NEXT: ALU 10, @4, KC0[CB0:0-32], KC1[]1961; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T3.X, T2.X, 01962; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 11963; EG-NEXT: CF_END1964; EG-NEXT: ALU clause starting at 4:1965; EG-NEXT: MOV * T0.W, KC0[5].X,1966; EG-NEXT: MOV * T0.Z, KC0[4].W,1967; EG-NEXT: MOV * T0.Y, KC0[4].Z,1968; EG-NEXT: MOV T0.X, KC0[4].Y,1969; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,1970; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1971; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.x,1972; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)1973; EG-NEXT: LSHR T2.X, PV.W, literal.x,1974; EG-NEXT: MOV * T3.X, KC0[5].Y,1975; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1976;1977; CM-LABEL: v5i32_arg:1978; CM: ; %bb.0: ; %entry1979; CM-NEXT: ALU 10, @4, KC0[CB0:0-32], KC1[]1980; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0, T3.X1981; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T2.X, T1.X1982; CM-NEXT: CF_END1983; CM-NEXT: ALU clause starting at 4:1984; CM-NEXT: ADD_INT T0.Z, KC0[2].Y, literal.x,1985; CM-NEXT: MOV * T0.W, KC0[5].X,1986; CM-NEXT: 16(2.242078e-44), 0(0.000000e+00)1987; CM-NEXT: LSHR T1.X, PV.Z, literal.x,1988; CM-NEXT: MOV * T0.Z, KC0[4].W,1989; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)1990; CM-NEXT: MOV T2.X, KC0[5].Y,1991; CM-NEXT: MOV * T0.Y, KC0[4].Z,1992; CM-NEXT: MOV * T0.X, KC0[4].Y,1993; CM-NEXT: LSHR * T3.X, KC0[2].Y, literal.x,1994; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)1995entry:1996 store <5 x i32> %in, ptr addrspace(1) %out, align 41997 ret void1998}1999 2000define amdgpu_kernel void @v5f32_arg(ptr addrspace(1) nocapture %out, <5 x float> %in) nounwind {2001; SI-LABEL: v5f32_arg:2002; SI: ; %bb.0: ; %entry2003; SI-NEXT: s_load_dword s8, s[4:5], 0x152004; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x92005; SI-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x112006; SI-NEXT: s_mov_b32 s3, 0xf0002007; SI-NEXT: s_mov_b32 s2, -12008; SI-NEXT: s_waitcnt lgkmcnt(0)2009; SI-NEXT: v_mov_b32_e32 v0, s82010; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:162011; SI-NEXT: s_waitcnt expcnt(0)2012; SI-NEXT: v_mov_b32_e32 v0, s42013; SI-NEXT: v_mov_b32_e32 v1, s52014; SI-NEXT: v_mov_b32_e32 v2, s62015; SI-NEXT: v_mov_b32_e32 v3, s72016; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 02017; SI-NEXT: s_endpgm2018;2019; VI-LABEL: v5f32_arg:2020; VI: ; %bb.0: ; %entry2021; VI-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x242022; VI-NEXT: s_load_dword s8, s[4:5], 0x542023; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x442024; VI-NEXT: s_waitcnt lgkmcnt(0)2025; VI-NEXT: s_add_u32 s4, s6, 162026; VI-NEXT: s_addc_u32 s5, s7, 02027; VI-NEXT: v_mov_b32_e32 v1, s42028; VI-NEXT: v_mov_b32_e32 v3, s82029; VI-NEXT: v_mov_b32_e32 v2, s52030; VI-NEXT: v_mov_b32_e32 v4, s62031; VI-NEXT: v_mov_b32_e32 v0, s02032; VI-NEXT: flat_store_dword v[1:2], v32033; VI-NEXT: v_mov_b32_e32 v1, s12034; VI-NEXT: v_mov_b32_e32 v2, s22035; VI-NEXT: v_mov_b32_e32 v3, s32036; VI-NEXT: v_mov_b32_e32 v5, s72037; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]2038; VI-NEXT: s_endpgm2039;2040; GFX9-LABEL: v5f32_arg:2041; GFX9: ; %bb.0: ; %entry2042; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x202043; GFX9-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x02044; GFX9-NEXT: s_load_dword s6, s[8:9], 0x302045; GFX9-NEXT: v_mov_b32_e32 v4, 02046; GFX9-NEXT: s_waitcnt lgkmcnt(0)2047; GFX9-NEXT: v_mov_b32_e32 v0, s02048; GFX9-NEXT: v_mov_b32_e32 v1, s12049; GFX9-NEXT: v_mov_b32_e32 v2, s22050; GFX9-NEXT: v_mov_b32_e32 v3, s32051; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[4:5]2052; GFX9-NEXT: s_nop 02053; GFX9-NEXT: v_mov_b32_e32 v0, s62054; GFX9-NEXT: global_store_dword v4, v0, s[4:5] offset:162055; GFX9-NEXT: s_endpgm2056;2057; EG-LABEL: v5f32_arg:2058; EG: ; %bb.0: ; %entry2059; EG-NEXT: ALU 10, @4, KC0[CB0:0-32], KC1[]2060; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T3.X, T2.X, 02061; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 12062; EG-NEXT: CF_END2063; EG-NEXT: ALU clause starting at 4:2064; EG-NEXT: MOV * T0.W, KC0[5].X,2065; EG-NEXT: MOV * T0.Z, KC0[4].W,2066; EG-NEXT: MOV * T0.Y, KC0[4].Z,2067; EG-NEXT: MOV T0.X, KC0[4].Y,2068; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,2069; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)2070; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.x,2071; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)2072; EG-NEXT: LSHR T2.X, PV.W, literal.x,2073; EG-NEXT: MOV * T3.X, KC0[5].Y,2074; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)2075;2076; CM-LABEL: v5f32_arg:2077; CM: ; %bb.0: ; %entry2078; CM-NEXT: ALU 10, @4, KC0[CB0:0-32], KC1[]2079; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0, T3.X2080; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T2.X, T1.X2081; CM-NEXT: CF_END2082; CM-NEXT: ALU clause starting at 4:2083; CM-NEXT: ADD_INT T0.Z, KC0[2].Y, literal.x,2084; CM-NEXT: MOV * T0.W, KC0[5].X,2085; CM-NEXT: 16(2.242078e-44), 0(0.000000e+00)2086; CM-NEXT: LSHR T1.X, PV.Z, literal.x,2087; CM-NEXT: MOV * T0.Z, KC0[4].W,2088; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)2089; CM-NEXT: MOV T2.X, KC0[5].Y,2090; CM-NEXT: MOV * T0.Y, KC0[4].Z,2091; CM-NEXT: MOV * T0.X, KC0[4].Y,2092; CM-NEXT: LSHR * T3.X, KC0[2].Y, literal.x,2093; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)2094entry:2095 store <5 x float> %in, ptr addrspace(1) %out, align 42096 ret void2097}2098 2099define amdgpu_kernel void @v5i64_arg(ptr addrspace(1) nocapture %out, <5 x i64> %in) nounwind {2100; SI-LABEL: v5i64_arg:2101; SI: ; %bb.0: ; %entry2102; SI-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x192103; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x92104; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x212105; SI-NEXT: s_mov_b32 s3, 0xf0002106; SI-NEXT: s_mov_b32 s2, -12107; SI-NEXT: s_waitcnt lgkmcnt(0)2108; SI-NEXT: v_mov_b32_e32 v0, s122109; SI-NEXT: v_mov_b32_e32 v1, s132110; SI-NEXT: v_mov_b32_e32 v2, s142111; SI-NEXT: v_mov_b32_e32 v3, s152112; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:162113; SI-NEXT: s_waitcnt expcnt(0)2114; SI-NEXT: v_mov_b32_e32 v0, s82115; SI-NEXT: v_mov_b32_e32 v1, s92116; SI-NEXT: v_mov_b32_e32 v2, s102117; SI-NEXT: v_mov_b32_e32 v3, s112118; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 02119; SI-NEXT: s_waitcnt expcnt(0)2120; SI-NEXT: v_mov_b32_e32 v0, s42121; SI-NEXT: v_mov_b32_e32 v1, s52122; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 offset:322123; SI-NEXT: s_endpgm2124;2125; VI-LABEL: v5i64_arg:2126; VI: ; %bb.0: ; %entry2127; VI-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x242128; VI-NEXT: s_load_dwordx2 s[10:11], s[4:5], 0x842129; VI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x642130; VI-NEXT: s_waitcnt lgkmcnt(0)2131; VI-NEXT: s_add_u32 s12, s8, 322132; VI-NEXT: v_mov_b32_e32 v1, s102133; VI-NEXT: s_addc_u32 s13, s9, 02134; VI-NEXT: v_mov_b32_e32 v3, s122135; VI-NEXT: v_mov_b32_e32 v2, s112136; VI-NEXT: v_mov_b32_e32 v0, s42137; VI-NEXT: v_mov_b32_e32 v4, s132138; VI-NEXT: s_add_u32 s4, s8, 162139; VI-NEXT: flat_store_dwordx2 v[3:4], v[1:2]2140; VI-NEXT: v_mov_b32_e32 v1, s52141; VI-NEXT: s_addc_u32 s5, s9, 02142; VI-NEXT: v_mov_b32_e32 v4, s42143; VI-NEXT: v_mov_b32_e32 v2, s62144; VI-NEXT: v_mov_b32_e32 v3, s72145; VI-NEXT: v_mov_b32_e32 v5, s52146; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]2147; VI-NEXT: v_mov_b32_e32 v4, s82148; VI-NEXT: v_mov_b32_e32 v0, s02149; VI-NEXT: v_mov_b32_e32 v1, s12150; VI-NEXT: v_mov_b32_e32 v2, s22151; VI-NEXT: v_mov_b32_e32 v3, s32152; VI-NEXT: v_mov_b32_e32 v5, s92153; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]2154; VI-NEXT: s_endpgm2155;2156; GFX9-LABEL: v5i64_arg:2157; GFX9: ; %bb.0: ; %entry2158; GFX9-NEXT: s_load_dwordx2 s[10:11], s[8:9], 0x602159; GFX9-NEXT: s_load_dwordx8 s[0:7], s[8:9], 0x402160; GFX9-NEXT: s_load_dwordx2 s[12:13], s[8:9], 0x02161; GFX9-NEXT: v_mov_b32_e32 v4, 02162; GFX9-NEXT: s_waitcnt lgkmcnt(0)2163; GFX9-NEXT: v_mov_b32_e32 v1, s102164; GFX9-NEXT: v_mov_b32_e32 v2, s112165; GFX9-NEXT: v_mov_b32_e32 v0, s42166; GFX9-NEXT: global_store_dwordx2 v4, v[1:2], s[12:13] offset:322167; GFX9-NEXT: v_mov_b32_e32 v1, s52168; GFX9-NEXT: v_mov_b32_e32 v2, s62169; GFX9-NEXT: v_mov_b32_e32 v3, s72170; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[12:13] offset:162171; GFX9-NEXT: s_nop 02172; GFX9-NEXT: v_mov_b32_e32 v0, s02173; GFX9-NEXT: v_mov_b32_e32 v1, s12174; GFX9-NEXT: v_mov_b32_e32 v2, s22175; GFX9-NEXT: v_mov_b32_e32 v3, s32176; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[12:13]2177; GFX9-NEXT: s_endpgm2178;2179; EG-LABEL: v5i64_arg:2180; EG: ; %bb.0: ; %entry2181; EG-NEXT: ALU 18, @6, KC0[CB0:0-32], KC1[]2182; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T5.XY, T4.X, 02183; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XYZW, T3.X, 02184; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T2.X, 12185; EG-NEXT: CF_END2186; EG-NEXT: PAD2187; EG-NEXT: ALU clause starting at 6:2188; EG-NEXT: MOV * T0.W, KC0[7].X,2189; EG-NEXT: MOV * T0.Z, KC0[6].W,2190; EG-NEXT: MOV T0.Y, KC0[6].Z,2191; EG-NEXT: MOV * T1.W, KC0[8].X,2192; EG-NEXT: MOV T0.X, KC0[6].Y,2193; EG-NEXT: MOV * T1.Z, KC0[7].W,2194; EG-NEXT: LSHR T2.X, KC0[2].Y, literal.x,2195; EG-NEXT: MOV * T1.Y, KC0[7].Z,2196; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)2197; EG-NEXT: MOV T1.X, KC0[7].Y,2198; EG-NEXT: ADD_INT * T2.W, KC0[2].Y, literal.x,2199; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)2200; EG-NEXT: LSHR T3.X, PV.W, literal.x,2201; EG-NEXT: ADD_INT * T2.W, KC0[2].Y, literal.y,2202; EG-NEXT: 2(2.802597e-45), 32(4.484155e-44)2203; EG-NEXT: LSHR T4.X, PV.W, literal.x,2204; EG-NEXT: MOV T5.Y, KC0[8].Z,2205; EG-NEXT: MOV * T5.X, KC0[8].Y,2206; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)2207;2208; CM-LABEL: v5i64_arg:2209; CM: ; %bb.0: ; %entry2210; CM-NEXT: ALU 18, @6, KC0[CB0:0-32], KC1[]2211; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T2, T5.X2212; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0, T4.X2213; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1, T3.X2214; CM-NEXT: CF_END2215; CM-NEXT: PAD2216; CM-NEXT: ALU clause starting at 6:2217; CM-NEXT: MOV * T0.W, KC0[8].X,2218; CM-NEXT: MOV T1.Y, KC0[8].Z,2219; CM-NEXT: MOV * T0.Z, KC0[7].W,2220; CM-NEXT: MOV T1.X, KC0[8].Y,2221; CM-NEXT: MOV * T0.Y, KC0[7].Z,2222; CM-NEXT: MOV T0.X, KC0[7].Y,2223; CM-NEXT: ADD_INT T1.Z, KC0[2].Y, literal.x,2224; CM-NEXT: MOV * T2.W, KC0[7].X,2225; CM-NEXT: 32(4.484155e-44), 0(0.000000e+00)2226; CM-NEXT: LSHR T3.X, PV.Z, literal.x,2227; CM-NEXT: MOV T2.Z, KC0[6].W,2228; CM-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.y,2229; CM-NEXT: 2(2.802597e-45), 16(2.242078e-44)2230; CM-NEXT: LSHR T4.X, PV.W, literal.x,2231; CM-NEXT: MOV * T2.Y, KC0[6].Z,2232; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)2233; CM-NEXT: MOV * T2.X, KC0[6].Y,2234; CM-NEXT: LSHR * T5.X, KC0[2].Y, literal.x,2235; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)2236entry:2237 store <5 x i64> %in, ptr addrspace(1) %out, align 82238 ret void2239}2240 2241define amdgpu_kernel void @v5f64_arg(ptr addrspace(1) nocapture %out, <5 x double> %in) nounwind {2242; SI-LABEL: v5f64_arg:2243; SI: ; %bb.0: ; %entry2244; SI-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x192245; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x92246; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x212247; SI-NEXT: s_mov_b32 s3, 0xf0002248; SI-NEXT: s_mov_b32 s2, -12249; SI-NEXT: s_waitcnt lgkmcnt(0)2250; SI-NEXT: v_mov_b32_e32 v0, s122251; SI-NEXT: v_mov_b32_e32 v1, s132252; SI-NEXT: v_mov_b32_e32 v2, s142253; SI-NEXT: v_mov_b32_e32 v3, s152254; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:162255; SI-NEXT: s_waitcnt expcnt(0)2256; SI-NEXT: v_mov_b32_e32 v0, s82257; SI-NEXT: v_mov_b32_e32 v1, s92258; SI-NEXT: v_mov_b32_e32 v2, s102259; SI-NEXT: v_mov_b32_e32 v3, s112260; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 02261; SI-NEXT: s_waitcnt expcnt(0)2262; SI-NEXT: v_mov_b32_e32 v0, s42263; SI-NEXT: v_mov_b32_e32 v1, s52264; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 offset:322265; SI-NEXT: s_endpgm2266;2267; VI-LABEL: v5f64_arg:2268; VI: ; %bb.0: ; %entry2269; VI-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x242270; VI-NEXT: s_load_dwordx2 s[10:11], s[4:5], 0x842271; VI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x642272; VI-NEXT: s_waitcnt lgkmcnt(0)2273; VI-NEXT: s_add_u32 s12, s8, 322274; VI-NEXT: v_mov_b32_e32 v1, s102275; VI-NEXT: s_addc_u32 s13, s9, 02276; VI-NEXT: v_mov_b32_e32 v3, s122277; VI-NEXT: v_mov_b32_e32 v2, s112278; VI-NEXT: v_mov_b32_e32 v0, s42279; VI-NEXT: v_mov_b32_e32 v4, s132280; VI-NEXT: s_add_u32 s4, s8, 162281; VI-NEXT: flat_store_dwordx2 v[3:4], v[1:2]2282; VI-NEXT: v_mov_b32_e32 v1, s52283; VI-NEXT: s_addc_u32 s5, s9, 02284; VI-NEXT: v_mov_b32_e32 v4, s42285; VI-NEXT: v_mov_b32_e32 v2, s62286; VI-NEXT: v_mov_b32_e32 v3, s72287; VI-NEXT: v_mov_b32_e32 v5, s52288; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]2289; VI-NEXT: v_mov_b32_e32 v4, s82290; VI-NEXT: v_mov_b32_e32 v0, s02291; VI-NEXT: v_mov_b32_e32 v1, s12292; VI-NEXT: v_mov_b32_e32 v2, s22293; VI-NEXT: v_mov_b32_e32 v3, s32294; VI-NEXT: v_mov_b32_e32 v5, s92295; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]2296; VI-NEXT: s_endpgm2297;2298; GFX9-LABEL: v5f64_arg:2299; GFX9: ; %bb.0: ; %entry2300; GFX9-NEXT: s_load_dwordx2 s[10:11], s[8:9], 0x602301; GFX9-NEXT: s_load_dwordx8 s[0:7], s[8:9], 0x402302; GFX9-NEXT: s_load_dwordx2 s[12:13], s[8:9], 0x02303; GFX9-NEXT: v_mov_b32_e32 v4, 02304; GFX9-NEXT: s_waitcnt lgkmcnt(0)2305; GFX9-NEXT: v_mov_b32_e32 v1, s102306; GFX9-NEXT: v_mov_b32_e32 v2, s112307; GFX9-NEXT: v_mov_b32_e32 v0, s42308; GFX9-NEXT: global_store_dwordx2 v4, v[1:2], s[12:13] offset:322309; GFX9-NEXT: v_mov_b32_e32 v1, s52310; GFX9-NEXT: v_mov_b32_e32 v2, s62311; GFX9-NEXT: v_mov_b32_e32 v3, s72312; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[12:13] offset:162313; GFX9-NEXT: s_nop 02314; GFX9-NEXT: v_mov_b32_e32 v0, s02315; GFX9-NEXT: v_mov_b32_e32 v1, s12316; GFX9-NEXT: v_mov_b32_e32 v2, s22317; GFX9-NEXT: v_mov_b32_e32 v3, s32318; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[12:13]2319; GFX9-NEXT: s_endpgm2320;2321; EG-LABEL: v5f64_arg:2322; EG: ; %bb.0: ; %entry2323; EG-NEXT: ALU 18, @6, KC0[CB0:0-32], KC1[]2324; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T5.XY, T4.X, 02325; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XYZW, T3.X, 02326; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T2.X, 12327; EG-NEXT: CF_END2328; EG-NEXT: PAD2329; EG-NEXT: ALU clause starting at 6:2330; EG-NEXT: MOV * T0.W, KC0[7].X,2331; EG-NEXT: MOV * T0.Z, KC0[6].W,2332; EG-NEXT: MOV T0.Y, KC0[6].Z,2333; EG-NEXT: MOV * T1.W, KC0[8].X,2334; EG-NEXT: MOV T0.X, KC0[6].Y,2335; EG-NEXT: MOV * T1.Z, KC0[7].W,2336; EG-NEXT: LSHR T2.X, KC0[2].Y, literal.x,2337; EG-NEXT: MOV * T1.Y, KC0[7].Z,2338; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)2339; EG-NEXT: MOV T1.X, KC0[7].Y,2340; EG-NEXT: ADD_INT * T2.W, KC0[2].Y, literal.x,2341; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)2342; EG-NEXT: LSHR T3.X, PV.W, literal.x,2343; EG-NEXT: ADD_INT * T2.W, KC0[2].Y, literal.y,2344; EG-NEXT: 2(2.802597e-45), 32(4.484155e-44)2345; EG-NEXT: LSHR T4.X, PV.W, literal.x,2346; EG-NEXT: MOV T5.Y, KC0[8].Z,2347; EG-NEXT: MOV * T5.X, KC0[8].Y,2348; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)2349;2350; CM-LABEL: v5f64_arg:2351; CM: ; %bb.0: ; %entry2352; CM-NEXT: ALU 18, @6, KC0[CB0:0-32], KC1[]2353; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T2, T5.X2354; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0, T4.X2355; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1, T3.X2356; CM-NEXT: CF_END2357; CM-NEXT: PAD2358; CM-NEXT: ALU clause starting at 6:2359; CM-NEXT: MOV * T0.W, KC0[8].X,2360; CM-NEXT: MOV T1.Y, KC0[8].Z,2361; CM-NEXT: MOV * T0.Z, KC0[7].W,2362; CM-NEXT: MOV T1.X, KC0[8].Y,2363; CM-NEXT: MOV * T0.Y, KC0[7].Z,2364; CM-NEXT: MOV T0.X, KC0[7].Y,2365; CM-NEXT: ADD_INT T1.Z, KC0[2].Y, literal.x,2366; CM-NEXT: MOV * T2.W, KC0[7].X,2367; CM-NEXT: 32(4.484155e-44), 0(0.000000e+00)2368; CM-NEXT: LSHR T3.X, PV.Z, literal.x,2369; CM-NEXT: MOV T2.Z, KC0[6].W,2370; CM-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.y,2371; CM-NEXT: 2(2.802597e-45), 16(2.242078e-44)2372; CM-NEXT: LSHR T4.X, PV.W, literal.x,2373; CM-NEXT: MOV * T2.Y, KC0[6].Z,2374; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)2375; CM-NEXT: MOV * T2.X, KC0[6].Y,2376; CM-NEXT: LSHR * T5.X, KC0[2].Y, literal.x,2377; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)2378entry:2379 store <5 x double> %in, ptr addrspace(1) %out, align 82380 ret void2381}2382 2383; FIXME: Lots of unpack and re-pack junk on VI2384define amdgpu_kernel void @v8i8_arg(ptr addrspace(1) %out, <8 x i8> %in) {2385; SI-LABEL: v8i8_arg:2386; SI: ; %bb.0: ; %entry2387; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x92388; SI-NEXT: s_mov_b32 s7, 0xf0002389; SI-NEXT: s_mov_b32 s6, -12390; SI-NEXT: s_waitcnt lgkmcnt(0)2391; SI-NEXT: s_mov_b32 s4, s02392; SI-NEXT: s_mov_b32 s5, s12393; SI-NEXT: v_mov_b32_e32 v0, s22394; SI-NEXT: v_mov_b32_e32 v1, s32395; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 02396; SI-NEXT: s_endpgm2397;2398; VI-LABEL: v8i8_arg:2399; VI: ; %bb.0: ; %entry2400; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x242401; VI-NEXT: s_waitcnt lgkmcnt(0)2402; VI-NEXT: v_mov_b32_e32 v0, s02403; VI-NEXT: v_mov_b32_e32 v2, s22404; VI-NEXT: v_mov_b32_e32 v1, s12405; VI-NEXT: v_mov_b32_e32 v3, s32406; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]2407; VI-NEXT: s_endpgm2408;2409; GFX9-LABEL: v8i8_arg:2410; GFX9: ; %bb.0: ; %entry2411; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x02412; GFX9-NEXT: v_mov_b32_e32 v2, 02413; GFX9-NEXT: s_waitcnt lgkmcnt(0)2414; GFX9-NEXT: v_mov_b32_e32 v0, s22415; GFX9-NEXT: v_mov_b32_e32 v1, s32416; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]2417; GFX9-NEXT: s_endpgm2418;2419; EG-LABEL: v8i8_arg:2420; EG: ; %bb.0: ; %entry2421; EG-NEXT: ALU 1, @36, KC0[], KC1[]2422; EG-NEXT: TEX 0 @202423; EG-NEXT: ALU 5, @38, KC0[], KC1[]2424; EG-NEXT: TEX 0 @222425; EG-NEXT: ALU 5, @44, KC0[], KC1[]2426; EG-NEXT: TEX 0 @242427; EG-NEXT: ALU 7, @50, KC0[], KC1[]2428; EG-NEXT: TEX 0 @262429; EG-NEXT: ALU 7, @58, KC0[], KC1[]2430; EG-NEXT: TEX 0 @282431; EG-NEXT: ALU 7, @66, KC0[], KC1[]2432; EG-NEXT: TEX 0 @302433; EG-NEXT: ALU 7, @74, KC0[], KC1[]2434; EG-NEXT: TEX 0 @322435; EG-NEXT: ALU 5, @82, KC0[], KC1[]2436; EG-NEXT: TEX 0 @342437; EG-NEXT: ALU 5, @88, KC0[CB0:0-32], KC1[]2438; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T5.XY, T6.X, 12439; EG-NEXT: CF_END2440; EG-NEXT: PAD2441; EG-NEXT: Fetch clause starting at 20:2442; EG-NEXT: VTX_READ_8 T6.X, T5.X, 51, #32443; EG-NEXT: Fetch clause starting at 22:2444; EG-NEXT: VTX_READ_8 T6.X, T5.X, 47, #32445; EG-NEXT: Fetch clause starting at 24:2446; EG-NEXT: VTX_READ_8 T6.X, T5.X, 50, #32447; EG-NEXT: Fetch clause starting at 26:2448; EG-NEXT: VTX_READ_8 T6.X, T5.X, 46, #32449; EG-NEXT: Fetch clause starting at 28:2450; EG-NEXT: VTX_READ_8 T6.X, T5.X, 49, #32451; EG-NEXT: Fetch clause starting at 30:2452; EG-NEXT: VTX_READ_8 T6.X, T5.X, 45, #32453; EG-NEXT: Fetch clause starting at 32:2454; EG-NEXT: VTX_READ_8 T6.X, T5.X, 48, #32455; EG-NEXT: Fetch clause starting at 34:2456; EG-NEXT: VTX_READ_8 T5.X, T5.X, 44, #32457; EG-NEXT: ALU clause starting at 36:2458; EG-NEXT: MOV * T0.Y, T2.X,2459; EG-NEXT: MOV * T5.X, 0.0,2460; EG-NEXT: ALU clause starting at 38:2461; EG-NEXT: LSHL T0.W, T6.X, literal.x,2462; EG-NEXT: AND_INT * T1.W, T0.Y, literal.y,2463; EG-NEXT: 24(3.363116e-44), 16777215(2.350989e-38)2464; EG-NEXT: OR_INT * T0.W, PS, PV.W,2465; EG-NEXT: MOV T2.X, PV.W,2466; EG-NEXT: MOV * T0.Y, T3.X,2467; EG-NEXT: ALU clause starting at 44:2468; EG-NEXT: AND_INT T0.W, T0.Y, literal.x,2469; EG-NEXT: LSHL * T1.W, T6.X, literal.y,2470; EG-NEXT: 16777215(2.350989e-38), 24(3.363116e-44)2471; EG-NEXT: OR_INT * T0.W, PV.W, PS,2472; EG-NEXT: MOV T3.X, PV.W,2473; EG-NEXT: MOV * T0.Y, T2.X,2474; EG-NEXT: ALU clause starting at 50:2475; EG-NEXT: AND_INT T0.W, T6.X, literal.x,2476; EG-NEXT: AND_INT * T1.W, T0.Y, literal.y,2477; EG-NEXT: 255(3.573311e-43), -16711681(-1.714704e+38)2478; EG-NEXT: LSHL * T0.W, PV.W, literal.x,2479; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)2480; EG-NEXT: OR_INT * T0.W, T1.W, PV.W,2481; EG-NEXT: MOV T2.X, PV.W,2482; EG-NEXT: MOV * T0.Y, T3.X,2483; EG-NEXT: ALU clause starting at 58:2484; EG-NEXT: AND_INT T0.W, T6.X, literal.x,2485; EG-NEXT: AND_INT * T1.W, T0.Y, literal.y,2486; EG-NEXT: 255(3.573311e-43), -16711681(-1.714704e+38)2487; EG-NEXT: LSHL * T0.W, PV.W, literal.x,2488; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)2489; EG-NEXT: OR_INT * T0.W, T1.W, PV.W,2490; EG-NEXT: MOV T3.X, PV.W,2491; EG-NEXT: MOV * T0.Y, T2.X,2492; EG-NEXT: ALU clause starting at 66:2493; EG-NEXT: AND_INT T0.W, T6.X, literal.x,2494; EG-NEXT: AND_INT * T1.W, T0.Y, literal.y,2495; EG-NEXT: 255(3.573311e-43), -65281(nan)2496; EG-NEXT: LSHL * T0.W, PV.W, literal.x,2497; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)2498; EG-NEXT: OR_INT * T0.W, T1.W, PV.W,2499; EG-NEXT: MOV T2.X, PV.W,2500; EG-NEXT: MOV * T0.Y, T3.X,2501; EG-NEXT: ALU clause starting at 74:2502; EG-NEXT: AND_INT T0.W, T6.X, literal.x,2503; EG-NEXT: AND_INT * T1.W, T0.Y, literal.y,2504; EG-NEXT: 255(3.573311e-43), -65281(nan)2505; EG-NEXT: LSHL * T0.W, PV.W, literal.x,2506; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)2507; EG-NEXT: OR_INT * T0.W, T1.W, PV.W,2508; EG-NEXT: MOV T3.X, PV.W,2509; EG-NEXT: MOV * T0.Y, T2.X,2510; EG-NEXT: ALU clause starting at 82:2511; EG-NEXT: AND_INT T0.W, T0.Y, literal.x,2512; EG-NEXT: AND_INT * T1.W, T6.X, literal.y,2513; EG-NEXT: -256(nan), 255(3.573311e-43)2514; EG-NEXT: OR_INT * T5.Y, PV.W, PS,2515; EG-NEXT: MOV T2.X, PV.Y,2516; EG-NEXT: MOV * T0.Y, T3.X,2517; EG-NEXT: ALU clause starting at 88:2518; EG-NEXT: AND_INT T0.W, T0.Y, literal.x,2519; EG-NEXT: AND_INT * T1.W, T5.X, literal.y,2520; EG-NEXT: -256(nan), 255(3.573311e-43)2521; EG-NEXT: OR_INT T5.X, PV.W, PS,2522; EG-NEXT: LSHR * T6.X, KC0[2].Y, literal.x,2523; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)2524;2525; CM-LABEL: v8i8_arg:2526; CM: ; %bb.0: ; %entry2527; CM-NEXT: ALU 1, @36, KC0[], KC1[]2528; CM-NEXT: TEX 0 @202529; CM-NEXT: ALU 5, @38, KC0[], KC1[]2530; CM-NEXT: TEX 0 @222531; CM-NEXT: ALU 5, @44, KC0[], KC1[]2532; CM-NEXT: TEX 0 @242533; CM-NEXT: ALU 7, @50, KC0[], KC1[]2534; CM-NEXT: TEX 0 @262535; CM-NEXT: ALU 7, @58, KC0[], KC1[]2536; CM-NEXT: TEX 0 @282537; CM-NEXT: ALU 7, @66, KC0[], KC1[]2538; CM-NEXT: TEX 0 @302539; CM-NEXT: ALU 7, @74, KC0[], KC1[]2540; CM-NEXT: TEX 0 @322541; CM-NEXT: ALU 5, @82, KC0[], KC1[]2542; CM-NEXT: TEX 0 @342543; CM-NEXT: ALU 5, @88, KC0[CB0:0-32], KC1[]2544; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T5, T6.X2545; CM-NEXT: CF_END2546; CM-NEXT: PAD2547; CM-NEXT: Fetch clause starting at 20:2548; CM-NEXT: VTX_READ_8 T6.X, T5.X, 51, #32549; CM-NEXT: Fetch clause starting at 22:2550; CM-NEXT: VTX_READ_8 T6.X, T5.X, 47, #32551; CM-NEXT: Fetch clause starting at 24:2552; CM-NEXT: VTX_READ_8 T6.X, T5.X, 50, #32553; CM-NEXT: Fetch clause starting at 26:2554; CM-NEXT: VTX_READ_8 T6.X, T5.X, 46, #32555; CM-NEXT: Fetch clause starting at 28:2556; CM-NEXT: VTX_READ_8 T6.X, T5.X, 49, #32557; CM-NEXT: Fetch clause starting at 30:2558; CM-NEXT: VTX_READ_8 T6.X, T5.X, 45, #32559; CM-NEXT: Fetch clause starting at 32:2560; CM-NEXT: VTX_READ_8 T6.X, T5.X, 48, #32561; CM-NEXT: Fetch clause starting at 34:2562; CM-NEXT: VTX_READ_8 T5.X, T5.X, 44, #32563; CM-NEXT: ALU clause starting at 36:2564; CM-NEXT: MOV * T0.Y, T2.X,2565; CM-NEXT: MOV * T5.X, 0.0,2566; CM-NEXT: ALU clause starting at 38:2567; CM-NEXT: LSHL T0.Z, T6.X, literal.x,2568; CM-NEXT: AND_INT * T0.W, T0.Y, literal.y,2569; CM-NEXT: 24(3.363116e-44), 16777215(2.350989e-38)2570; CM-NEXT: OR_INT * T0.W, PV.W, PV.Z,2571; CM-NEXT: MOV T2.X, PV.W,2572; CM-NEXT: MOV * T0.Y, T3.X,2573; CM-NEXT: ALU clause starting at 44:2574; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x,2575; CM-NEXT: LSHL * T0.W, T6.X, literal.y,2576; CM-NEXT: 16777215(2.350989e-38), 24(3.363116e-44)2577; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W,2578; CM-NEXT: MOV T3.X, PV.W,2579; CM-NEXT: MOV * T0.Y, T2.X,2580; CM-NEXT: ALU clause starting at 50:2581; CM-NEXT: AND_INT * T0.W, T6.X, literal.x,2582; CM-NEXT: 255(3.573311e-43), 0(0.000000e+00)2583; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x,2584; CM-NEXT: LSHL * T0.W, PV.W, literal.y,2585; CM-NEXT: -16711681(-1.714704e+38), 16(2.242078e-44)2586; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W,2587; CM-NEXT: MOV T2.X, PV.W,2588; CM-NEXT: MOV * T0.Y, T3.X,2589; CM-NEXT: ALU clause starting at 58:2590; CM-NEXT: AND_INT * T0.W, T6.X, literal.x,2591; CM-NEXT: 255(3.573311e-43), 0(0.000000e+00)2592; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x,2593; CM-NEXT: LSHL * T0.W, PV.W, literal.y,2594; CM-NEXT: -16711681(-1.714704e+38), 16(2.242078e-44)2595; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W,2596; CM-NEXT: MOV T3.X, PV.W,2597; CM-NEXT: MOV * T0.Y, T2.X,2598; CM-NEXT: ALU clause starting at 66:2599; CM-NEXT: AND_INT * T0.W, T6.X, literal.x,2600; CM-NEXT: 255(3.573311e-43), 0(0.000000e+00)2601; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x,2602; CM-NEXT: LSHL * T0.W, PV.W, literal.y,2603; CM-NEXT: -65281(nan), 8(1.121039e-44)2604; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W,2605; CM-NEXT: MOV T2.X, PV.W,2606; CM-NEXT: MOV * T0.Y, T3.X,2607; CM-NEXT: ALU clause starting at 74:2608; CM-NEXT: AND_INT * T0.W, T6.X, literal.x,2609; CM-NEXT: 255(3.573311e-43), 0(0.000000e+00)2610; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x,2611; CM-NEXT: LSHL * T0.W, PV.W, literal.y,2612; CM-NEXT: -65281(nan), 8(1.121039e-44)2613; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W,2614; CM-NEXT: MOV T3.X, PV.W,2615; CM-NEXT: MOV * T0.Y, T2.X,2616; CM-NEXT: ALU clause starting at 82:2617; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x,2618; CM-NEXT: AND_INT * T0.W, T6.X, literal.y,2619; CM-NEXT: -256(nan), 255(3.573311e-43)2620; CM-NEXT: OR_INT * T5.Y, PV.Z, PV.W,2621; CM-NEXT: MOV T2.X, PV.Y,2622; CM-NEXT: MOV * T0.Y, T3.X,2623; CM-NEXT: ALU clause starting at 88:2624; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x,2625; CM-NEXT: AND_INT * T0.W, T5.X, literal.y,2626; CM-NEXT: -256(nan), 255(3.573311e-43)2627; CM-NEXT: OR_INT * T5.X, PV.Z, PV.W,2628; CM-NEXT: LSHR * T6.X, KC0[2].Y, literal.x,2629; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)2630entry:2631 store <8 x i8> %in, ptr addrspace(1) %out2632 ret void2633}2634 2635define amdgpu_kernel void @v8i16_arg(ptr addrspace(1) %out, <8 x i16> %in) {2636; SI-LABEL: v8i16_arg:2637; SI: ; %bb.0: ; %entry2638; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xd2639; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x92640; SI-NEXT: s_mov_b32 s7, 0xf0002641; SI-NEXT: s_mov_b32 s6, -12642; SI-NEXT: s_waitcnt lgkmcnt(0)2643; SI-NEXT: v_mov_b32_e32 v0, s02644; SI-NEXT: v_mov_b32_e32 v1, s12645; SI-NEXT: v_mov_b32_e32 v2, s22646; SI-NEXT: v_mov_b32_e32 v3, s32647; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 02648; SI-NEXT: s_endpgm2649;2650; VI-LABEL: v8i16_arg:2651; VI: ; %bb.0: ; %entry2652; VI-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x242653; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x342654; VI-NEXT: s_waitcnt lgkmcnt(0)2655; VI-NEXT: v_mov_b32_e32 v4, s62656; VI-NEXT: v_mov_b32_e32 v0, s02657; VI-NEXT: v_mov_b32_e32 v5, s72658; VI-NEXT: v_mov_b32_e32 v1, s12659; VI-NEXT: v_mov_b32_e32 v2, s22660; VI-NEXT: v_mov_b32_e32 v3, s32661; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]2662; VI-NEXT: s_endpgm2663;2664; GFX9-LABEL: v8i16_arg:2665; GFX9: ; %bb.0: ; %entry2666; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x102667; GFX9-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x02668; GFX9-NEXT: v_mov_b32_e32 v4, 02669; GFX9-NEXT: s_waitcnt lgkmcnt(0)2670; GFX9-NEXT: v_mov_b32_e32 v0, s02671; GFX9-NEXT: v_mov_b32_e32 v1, s12672; GFX9-NEXT: v_mov_b32_e32 v2, s22673; GFX9-NEXT: v_mov_b32_e32 v3, s32674; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[4:5]2675; GFX9-NEXT: s_endpgm2676;2677; EG-LABEL: v8i16_arg:2678; EG: ; %bb.0: ; %entry2679; EG-NEXT: ALU 1, @36, KC0[], KC1[]2680; EG-NEXT: TEX 0 @202681; EG-NEXT: ALU 5, @38, KC0[], KC1[]2682; EG-NEXT: TEX 0 @222683; EG-NEXT: ALU 5, @44, KC0[], KC1[]2684; EG-NEXT: TEX 0 @242685; EG-NEXT: ALU 5, @50, KC0[], KC1[]2686; EG-NEXT: TEX 0 @262687; EG-NEXT: ALU 5, @56, KC0[], KC1[]2688; EG-NEXT: TEX 0 @282689; EG-NEXT: ALU 5, @62, KC0[], KC1[]2690; EG-NEXT: TEX 0 @302691; EG-NEXT: ALU 5, @68, KC0[], KC1[]2692; EG-NEXT: TEX 0 @322693; EG-NEXT: ALU 5, @74, KC0[], KC1[]2694; EG-NEXT: TEX 0 @342695; EG-NEXT: ALU 8, @80, KC0[CB0:0-32], KC1[]2696; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T7.XYZW, T8.X, 12697; EG-NEXT: CF_END2698; EG-NEXT: PAD2699; EG-NEXT: Fetch clause starting at 20:2700; EG-NEXT: VTX_READ_16 T8.X, T7.X, 66, #32701; EG-NEXT: Fetch clause starting at 22:2702; EG-NEXT: VTX_READ_16 T8.X, T7.X, 58, #32703; EG-NEXT: Fetch clause starting at 24:2704; EG-NEXT: VTX_READ_16 T8.X, T7.X, 64, #32705; EG-NEXT: Fetch clause starting at 26:2706; EG-NEXT: VTX_READ_16 T8.X, T7.X, 56, #32707; EG-NEXT: Fetch clause starting at 28:2708; EG-NEXT: VTX_READ_16 T8.X, T7.X, 62, #32709; EG-NEXT: Fetch clause starting at 30:2710; EG-NEXT: VTX_READ_16 T8.X, T7.X, 54, #32711; EG-NEXT: Fetch clause starting at 32:2712; EG-NEXT: VTX_READ_16 T8.X, T7.X, 60, #32713; EG-NEXT: Fetch clause starting at 34:2714; EG-NEXT: VTX_READ_16 T7.X, T7.X, 52, #32715; EG-NEXT: ALU clause starting at 36:2716; EG-NEXT: MOV * T0.Y, T3.X,2717; EG-NEXT: MOV * T7.X, 0.0,2718; EG-NEXT: ALU clause starting at 38:2719; EG-NEXT: LSHL T0.W, T8.X, literal.x,2720; EG-NEXT: AND_INT * T1.W, T0.Y, literal.y,2721; EG-NEXT: 16(2.242078e-44), 65535(9.183409e-41)2722; EG-NEXT: OR_INT * T0.W, PS, PV.W,2723; EG-NEXT: MOV T3.X, PV.W,2724; EG-NEXT: MOV * T0.Y, T5.X,2725; EG-NEXT: ALU clause starting at 44:2726; EG-NEXT: AND_INT T0.W, T0.Y, literal.x,2727; EG-NEXT: LSHL * T1.W, T8.X, literal.y,2728; EG-NEXT: 65535(9.183409e-41), 16(2.242078e-44)2729; EG-NEXT: OR_INT * T0.W, PV.W, PS,2730; EG-NEXT: MOV T5.X, PV.W,2731; EG-NEXT: MOV * T0.Y, T3.X,2732; EG-NEXT: ALU clause starting at 50:2733; EG-NEXT: AND_INT T0.W, T0.Y, literal.x,2734; EG-NEXT: AND_INT * T1.W, T8.X, literal.y,2735; EG-NEXT: -65536(nan), 65535(9.183409e-41)2736; EG-NEXT: OR_INT * T0.W, PV.W, PS,2737; EG-NEXT: MOV T3.X, PV.W,2738; EG-NEXT: MOV * T0.Y, T5.X,2739; EG-NEXT: ALU clause starting at 56:2740; EG-NEXT: AND_INT T0.W, T0.Y, literal.x,2741; EG-NEXT: AND_INT * T1.W, T8.X, literal.y,2742; EG-NEXT: -65536(nan), 65535(9.183409e-41)2743; EG-NEXT: OR_INT * T0.W, PV.W, PS,2744; EG-NEXT: MOV T5.X, PV.W,2745; EG-NEXT: MOV * T0.Y, T2.X,2746; EG-NEXT: ALU clause starting at 62:2747; EG-NEXT: AND_INT T0.W, T0.Y, literal.x,2748; EG-NEXT: LSHL * T1.W, T8.X, literal.y,2749; EG-NEXT: 65535(9.183409e-41), 16(2.242078e-44)2750; EG-NEXT: OR_INT * T0.W, PV.W, PS,2751; EG-NEXT: MOV T2.X, PV.W,2752; EG-NEXT: MOV * T0.Y, T4.X,2753; EG-NEXT: ALU clause starting at 68:2754; EG-NEXT: AND_INT T0.W, T0.Y, literal.x,2755; EG-NEXT: LSHL * T1.W, T8.X, literal.y,2756; EG-NEXT: 65535(9.183409e-41), 16(2.242078e-44)2757; EG-NEXT: OR_INT * T0.W, PV.W, PS,2758; EG-NEXT: MOV T4.X, PV.W,2759; EG-NEXT: MOV * T0.Y, T2.X,2760; EG-NEXT: ALU clause starting at 74:2761; EG-NEXT: AND_INT T0.W, T0.Y, literal.x,2762; EG-NEXT: AND_INT * T1.W, T8.X, literal.y,2763; EG-NEXT: -65536(nan), 65535(9.183409e-41)2764; EG-NEXT: OR_INT * T7.Z, PV.W, PS,2765; EG-NEXT: MOV T2.X, PV.Z,2766; EG-NEXT: MOV * T0.Y, T4.X,2767; EG-NEXT: ALU clause starting at 80:2768; EG-NEXT: LSHR T8.X, KC0[2].Y, literal.x,2769; EG-NEXT: AND_INT T0.W, T0.Y, literal.y,2770; EG-NEXT: AND_INT * T1.W, T7.X, literal.z,2771; EG-NEXT: 2(2.802597e-45), -65536(nan)2772; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)2773; EG-NEXT: OR_INT * T7.X, PV.W, PS,2774; EG-NEXT: MOV T4.X, PV.X,2775; EG-NEXT: MOV * T7.W, T3.X,2776; EG-NEXT: MOV * T7.Y, T5.X,2777;2778; CM-LABEL: v8i16_arg:2779; CM: ; %bb.0: ; %entry2780; CM-NEXT: ALU 1, @36, KC0[], KC1[]2781; CM-NEXT: TEX 0 @202782; CM-NEXT: ALU 5, @38, KC0[], KC1[]2783; CM-NEXT: TEX 0 @222784; CM-NEXT: ALU 5, @44, KC0[], KC1[]2785; CM-NEXT: TEX 0 @242786; CM-NEXT: ALU 5, @50, KC0[], KC1[]2787; CM-NEXT: TEX 0 @262788; CM-NEXT: ALU 5, @56, KC0[], KC1[]2789; CM-NEXT: TEX 0 @282790; CM-NEXT: ALU 5, @62, KC0[], KC1[]2791; CM-NEXT: TEX 0 @302792; CM-NEXT: ALU 5, @68, KC0[], KC1[]2793; CM-NEXT: TEX 0 @322794; CM-NEXT: ALU 5, @74, KC0[], KC1[]2795; CM-NEXT: TEX 0 @342796; CM-NEXT: ALU 8, @80, KC0[CB0:0-32], KC1[]2797; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T7, T8.X2798; CM-NEXT: CF_END2799; CM-NEXT: PAD2800; CM-NEXT: Fetch clause starting at 20:2801; CM-NEXT: VTX_READ_16 T8.X, T7.X, 66, #32802; CM-NEXT: Fetch clause starting at 22:2803; CM-NEXT: VTX_READ_16 T8.X, T7.X, 58, #32804; CM-NEXT: Fetch clause starting at 24:2805; CM-NEXT: VTX_READ_16 T8.X, T7.X, 64, #32806; CM-NEXT: Fetch clause starting at 26:2807; CM-NEXT: VTX_READ_16 T8.X, T7.X, 56, #32808; CM-NEXT: Fetch clause starting at 28:2809; CM-NEXT: VTX_READ_16 T8.X, T7.X, 62, #32810; CM-NEXT: Fetch clause starting at 30:2811; CM-NEXT: VTX_READ_16 T8.X, T7.X, 54, #32812; CM-NEXT: Fetch clause starting at 32:2813; CM-NEXT: VTX_READ_16 T8.X, T7.X, 60, #32814; CM-NEXT: Fetch clause starting at 34:2815; CM-NEXT: VTX_READ_16 T7.X, T7.X, 52, #32816; CM-NEXT: ALU clause starting at 36:2817; CM-NEXT: MOV * T0.Y, T3.X,2818; CM-NEXT: MOV * T7.X, 0.0,2819; CM-NEXT: ALU clause starting at 38:2820; CM-NEXT: LSHL T0.Z, T8.X, literal.x,2821; CM-NEXT: AND_INT * T0.W, T0.Y, literal.y,2822; CM-NEXT: 16(2.242078e-44), 65535(9.183409e-41)2823; CM-NEXT: OR_INT * T0.W, PV.W, PV.Z,2824; CM-NEXT: MOV T3.X, PV.W,2825; CM-NEXT: MOV * T0.Y, T5.X,2826; CM-NEXT: ALU clause starting at 44:2827; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x,2828; CM-NEXT: LSHL * T0.W, T8.X, literal.y,2829; CM-NEXT: 65535(9.183409e-41), 16(2.242078e-44)2830; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W,2831; CM-NEXT: MOV T5.X, PV.W,2832; CM-NEXT: MOV * T0.Y, T3.X,2833; CM-NEXT: ALU clause starting at 50:2834; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x,2835; CM-NEXT: AND_INT * T0.W, T8.X, literal.y,2836; CM-NEXT: -65536(nan), 65535(9.183409e-41)2837; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W,2838; CM-NEXT: MOV T3.X, PV.W,2839; CM-NEXT: MOV * T0.Y, T5.X,2840; CM-NEXT: ALU clause starting at 56:2841; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x,2842; CM-NEXT: AND_INT * T0.W, T8.X, literal.y,2843; CM-NEXT: -65536(nan), 65535(9.183409e-41)2844; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W,2845; CM-NEXT: MOV T5.X, PV.W,2846; CM-NEXT: MOV * T0.Y, T2.X,2847; CM-NEXT: ALU clause starting at 62:2848; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x,2849; CM-NEXT: LSHL * T0.W, T8.X, literal.y,2850; CM-NEXT: 65535(9.183409e-41), 16(2.242078e-44)2851; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W,2852; CM-NEXT: MOV T2.X, PV.W,2853; CM-NEXT: MOV * T0.Y, T4.X,2854; CM-NEXT: ALU clause starting at 68:2855; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x,2856; CM-NEXT: LSHL * T0.W, T8.X, literal.y,2857; CM-NEXT: 65535(9.183409e-41), 16(2.242078e-44)2858; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W,2859; CM-NEXT: MOV T4.X, PV.W,2860; CM-NEXT: MOV * T0.Y, T2.X,2861; CM-NEXT: ALU clause starting at 74:2862; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x,2863; CM-NEXT: AND_INT * T0.W, T8.X, literal.y,2864; CM-NEXT: -65536(nan), 65535(9.183409e-41)2865; CM-NEXT: OR_INT * T7.Z, PV.Z, PV.W,2866; CM-NEXT: MOV T2.X, PV.Z,2867; CM-NEXT: MOV * T0.Y, T4.X,2868; CM-NEXT: ALU clause starting at 80:2869; CM-NEXT: LSHR T8.X, KC0[2].Y, literal.x,2870; CM-NEXT: AND_INT T0.Z, T0.Y, literal.y,2871; CM-NEXT: AND_INT * T0.W, T7.X, literal.z,2872; CM-NEXT: 2(2.802597e-45), -65536(nan)2873; CM-NEXT: 65535(9.183409e-41), 0(0.000000e+00)2874; CM-NEXT: OR_INT * T7.X, PV.Z, PV.W,2875; CM-NEXT: MOV T4.X, PV.X,2876; CM-NEXT: MOV * T7.W, T3.X,2877; CM-NEXT: MOV * T7.Y, T5.X,2878entry:2879 store <8 x i16> %in, ptr addrspace(1) %out2880 ret void2881}2882 2883define amdgpu_kernel void @v8i32_arg(ptr addrspace(1) nocapture %out, <8 x i32> %in) nounwind {2884; SI-LABEL: v8i32_arg:2885; SI: ; %bb.0: ; %entry2886; SI-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x112887; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x92888; SI-NEXT: s_mov_b32 s3, 0xf0002889; SI-NEXT: s_mov_b32 s2, -12890; SI-NEXT: s_waitcnt lgkmcnt(0)2891; SI-NEXT: v_mov_b32_e32 v0, s122892; SI-NEXT: v_mov_b32_e32 v1, s132893; SI-NEXT: v_mov_b32_e32 v2, s142894; SI-NEXT: v_mov_b32_e32 v3, s152895; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:162896; SI-NEXT: s_waitcnt expcnt(0)2897; SI-NEXT: v_mov_b32_e32 v0, s82898; SI-NEXT: v_mov_b32_e32 v1, s92899; SI-NEXT: v_mov_b32_e32 v2, s102900; SI-NEXT: v_mov_b32_e32 v3, s112901; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 02902; SI-NEXT: s_endpgm2903;2904; VI-LABEL: v8i32_arg:2905; VI: ; %bb.0: ; %entry2906; VI-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x442907; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x242908; VI-NEXT: s_waitcnt lgkmcnt(0)2909; VI-NEXT: v_mov_b32_e32 v0, s122910; VI-NEXT: s_add_u32 s2, s0, 162911; VI-NEXT: s_addc_u32 s3, s1, 02912; VI-NEXT: v_mov_b32_e32 v5, s32913; VI-NEXT: v_mov_b32_e32 v1, s132914; VI-NEXT: v_mov_b32_e32 v2, s142915; VI-NEXT: v_mov_b32_e32 v3, s152916; VI-NEXT: v_mov_b32_e32 v4, s22917; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]2918; VI-NEXT: v_mov_b32_e32 v5, s12919; VI-NEXT: v_mov_b32_e32 v0, s82920; VI-NEXT: v_mov_b32_e32 v1, s92921; VI-NEXT: v_mov_b32_e32 v2, s102922; VI-NEXT: v_mov_b32_e32 v3, s112923; VI-NEXT: v_mov_b32_e32 v4, s02924; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]2925; VI-NEXT: s_endpgm2926;2927; GFX9-LABEL: v8i32_arg:2928; GFX9: ; %bb.0: ; %entry2929; GFX9-NEXT: s_load_dwordx8 s[0:7], s[8:9], 0x202930; GFX9-NEXT: v_mov_b32_e32 v4, 02931; GFX9-NEXT: s_load_dwordx2 s[8:9], s[8:9], 0x02932; GFX9-NEXT: s_waitcnt lgkmcnt(0)2933; GFX9-NEXT: v_mov_b32_e32 v0, s42934; GFX9-NEXT: v_mov_b32_e32 v1, s52935; GFX9-NEXT: v_mov_b32_e32 v2, s62936; GFX9-NEXT: v_mov_b32_e32 v3, s72937; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[8:9] offset:162938; GFX9-NEXT: s_nop 02939; GFX9-NEXT: v_mov_b32_e32 v0, s02940; GFX9-NEXT: v_mov_b32_e32 v1, s12941; GFX9-NEXT: v_mov_b32_e32 v2, s22942; GFX9-NEXT: v_mov_b32_e32 v3, s32943; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[8:9]2944; GFX9-NEXT: s_endpgm2945;2946; EG-LABEL: v8i32_arg:2947; EG: ; %bb.0: ; %entry2948; EG-NEXT: ALU 13, @4, KC0[CB0:0-32], KC1[]2949; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XYZW, T3.X, 02950; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T2.X, 12951; EG-NEXT: CF_END2952; EG-NEXT: ALU clause starting at 4:2953; EG-NEXT: MOV * T0.W, KC0[5].X,2954; EG-NEXT: MOV * T0.Z, KC0[4].W,2955; EG-NEXT: MOV T0.Y, KC0[4].Z,2956; EG-NEXT: MOV * T1.W, KC0[6].X,2957; EG-NEXT: MOV T0.X, KC0[4].Y,2958; EG-NEXT: MOV * T1.Z, KC0[5].W,2959; EG-NEXT: LSHR T2.X, KC0[2].Y, literal.x,2960; EG-NEXT: MOV * T1.Y, KC0[5].Z,2961; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)2962; EG-NEXT: MOV T1.X, KC0[5].Y,2963; EG-NEXT: ADD_INT * T2.W, KC0[2].Y, literal.x,2964; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)2965; EG-NEXT: LSHR * T3.X, PV.W, literal.x,2966; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)2967;2968; CM-LABEL: v8i32_arg:2969; CM: ; %bb.0: ; %entry2970; CM-NEXT: ALU 13, @4, KC0[CB0:0-32], KC1[]2971; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1, T3.X2972; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0, T2.X2973; CM-NEXT: CF_END2974; CM-NEXT: ALU clause starting at 4:2975; CM-NEXT: MOV * T0.W, KC0[6].X,2976; CM-NEXT: MOV * T0.Z, KC0[5].W,2977; CM-NEXT: MOV * T0.Y, KC0[5].Z,2978; CM-NEXT: MOV T0.X, KC0[5].Y,2979; CM-NEXT: MOV * T1.W, KC0[5].X,2980; CM-NEXT: MOV T1.Z, KC0[4].W,2981; CM-NEXT: ADD_INT * T2.W, KC0[2].Y, literal.x,2982; CM-NEXT: 16(2.242078e-44), 0(0.000000e+00)2983; CM-NEXT: LSHR T2.X, PV.W, literal.x,2984; CM-NEXT: MOV * T1.Y, KC0[4].Z,2985; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)2986; CM-NEXT: MOV * T1.X, KC0[4].Y,2987; CM-NEXT: LSHR * T3.X, KC0[2].Y, literal.x,2988; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)2989entry:2990 store <8 x i32> %in, ptr addrspace(1) %out, align 42991 ret void2992}2993 2994define amdgpu_kernel void @v8f32_arg(ptr addrspace(1) nocapture %out, <8 x float> %in) nounwind {2995; SI-LABEL: v8f32_arg:2996; SI: ; %bb.0: ; %entry2997; SI-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x112998; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x92999; SI-NEXT: s_mov_b32 s3, 0xf0003000; SI-NEXT: s_mov_b32 s2, -13001; SI-NEXT: s_waitcnt lgkmcnt(0)3002; SI-NEXT: v_mov_b32_e32 v0, s123003; SI-NEXT: v_mov_b32_e32 v1, s133004; SI-NEXT: v_mov_b32_e32 v2, s143005; SI-NEXT: v_mov_b32_e32 v3, s153006; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:163007; SI-NEXT: s_waitcnt expcnt(0)3008; SI-NEXT: v_mov_b32_e32 v0, s83009; SI-NEXT: v_mov_b32_e32 v1, s93010; SI-NEXT: v_mov_b32_e32 v2, s103011; SI-NEXT: v_mov_b32_e32 v3, s113012; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 03013; SI-NEXT: s_endpgm3014;3015; VI-LABEL: v8f32_arg:3016; VI: ; %bb.0: ; %entry3017; VI-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x443018; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x243019; VI-NEXT: s_waitcnt lgkmcnt(0)3020; VI-NEXT: v_mov_b32_e32 v0, s123021; VI-NEXT: s_add_u32 s2, s0, 163022; VI-NEXT: s_addc_u32 s3, s1, 03023; VI-NEXT: v_mov_b32_e32 v5, s33024; VI-NEXT: v_mov_b32_e32 v1, s133025; VI-NEXT: v_mov_b32_e32 v2, s143026; VI-NEXT: v_mov_b32_e32 v3, s153027; VI-NEXT: v_mov_b32_e32 v4, s23028; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]3029; VI-NEXT: v_mov_b32_e32 v5, s13030; VI-NEXT: v_mov_b32_e32 v0, s83031; VI-NEXT: v_mov_b32_e32 v1, s93032; VI-NEXT: v_mov_b32_e32 v2, s103033; VI-NEXT: v_mov_b32_e32 v3, s113034; VI-NEXT: v_mov_b32_e32 v4, s03035; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]3036; VI-NEXT: s_endpgm3037;3038; GFX9-LABEL: v8f32_arg:3039; GFX9: ; %bb.0: ; %entry3040; GFX9-NEXT: s_load_dwordx8 s[0:7], s[8:9], 0x203041; GFX9-NEXT: v_mov_b32_e32 v4, 03042; GFX9-NEXT: s_load_dwordx2 s[8:9], s[8:9], 0x03043; GFX9-NEXT: s_waitcnt lgkmcnt(0)3044; GFX9-NEXT: v_mov_b32_e32 v0, s43045; GFX9-NEXT: v_mov_b32_e32 v1, s53046; GFX9-NEXT: v_mov_b32_e32 v2, s63047; GFX9-NEXT: v_mov_b32_e32 v3, s73048; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[8:9] offset:163049; GFX9-NEXT: s_nop 03050; GFX9-NEXT: v_mov_b32_e32 v0, s03051; GFX9-NEXT: v_mov_b32_e32 v1, s13052; GFX9-NEXT: v_mov_b32_e32 v2, s23053; GFX9-NEXT: v_mov_b32_e32 v3, s33054; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[8:9]3055; GFX9-NEXT: s_endpgm3056;3057; EG-LABEL: v8f32_arg:3058; EG: ; %bb.0: ; %entry3059; EG-NEXT: ALU 13, @4, KC0[CB0:0-32], KC1[]3060; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XYZW, T3.X, 03061; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T2.X, 13062; EG-NEXT: CF_END3063; EG-NEXT: ALU clause starting at 4:3064; EG-NEXT: MOV * T0.W, KC0[5].X,3065; EG-NEXT: MOV * T0.Z, KC0[4].W,3066; EG-NEXT: MOV T0.Y, KC0[4].Z,3067; EG-NEXT: MOV * T1.W, KC0[6].X,3068; EG-NEXT: MOV T0.X, KC0[4].Y,3069; EG-NEXT: MOV * T1.Z, KC0[5].W,3070; EG-NEXT: LSHR T2.X, KC0[2].Y, literal.x,3071; EG-NEXT: MOV * T1.Y, KC0[5].Z,3072; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)3073; EG-NEXT: MOV T1.X, KC0[5].Y,3074; EG-NEXT: ADD_INT * T2.W, KC0[2].Y, literal.x,3075; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)3076; EG-NEXT: LSHR * T3.X, PV.W, literal.x,3077; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)3078;3079; CM-LABEL: v8f32_arg:3080; CM: ; %bb.0: ; %entry3081; CM-NEXT: ALU 13, @4, KC0[CB0:0-32], KC1[]3082; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1, T3.X3083; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0, T2.X3084; CM-NEXT: CF_END3085; CM-NEXT: ALU clause starting at 4:3086; CM-NEXT: MOV * T0.W, KC0[6].X,3087; CM-NEXT: MOV * T0.Z, KC0[5].W,3088; CM-NEXT: MOV * T0.Y, KC0[5].Z,3089; CM-NEXT: MOV T0.X, KC0[5].Y,3090; CM-NEXT: MOV * T1.W, KC0[5].X,3091; CM-NEXT: MOV T1.Z, KC0[4].W,3092; CM-NEXT: ADD_INT * T2.W, KC0[2].Y, literal.x,3093; CM-NEXT: 16(2.242078e-44), 0(0.000000e+00)3094; CM-NEXT: LSHR T2.X, PV.W, literal.x,3095; CM-NEXT: MOV * T1.Y, KC0[4].Z,3096; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)3097; CM-NEXT: MOV * T1.X, KC0[4].Y,3098; CM-NEXT: LSHR * T3.X, KC0[2].Y, literal.x,3099; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)3100entry:3101 store <8 x float> %in, ptr addrspace(1) %out, align 43102 ret void3103}3104 3105; FIXME: Pack/repack on VI3106define amdgpu_kernel void @v16i8_arg(ptr addrspace(1) %out, <16 x i8> %in) {3107; SI-LABEL: v16i8_arg:3108; SI: ; %bb.0: ; %entry3109; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xd3110; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x93111; SI-NEXT: s_mov_b32 s7, 0xf0003112; SI-NEXT: s_mov_b32 s6, -13113; SI-NEXT: s_waitcnt lgkmcnt(0)3114; SI-NEXT: v_mov_b32_e32 v0, s03115; SI-NEXT: v_mov_b32_e32 v1, s13116; SI-NEXT: v_mov_b32_e32 v2, s23117; SI-NEXT: v_mov_b32_e32 v3, s33118; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 03119; SI-NEXT: s_endpgm3120;3121; VI-LABEL: v16i8_arg:3122; VI: ; %bb.0: ; %entry3123; VI-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x243124; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x343125; VI-NEXT: s_waitcnt lgkmcnt(0)3126; VI-NEXT: v_mov_b32_e32 v4, s63127; VI-NEXT: v_mov_b32_e32 v0, s03128; VI-NEXT: v_mov_b32_e32 v5, s73129; VI-NEXT: v_mov_b32_e32 v1, s13130; VI-NEXT: v_mov_b32_e32 v2, s23131; VI-NEXT: v_mov_b32_e32 v3, s33132; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]3133; VI-NEXT: s_endpgm3134;3135; GFX9-LABEL: v16i8_arg:3136; GFX9: ; %bb.0: ; %entry3137; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x103138; GFX9-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x03139; GFX9-NEXT: v_mov_b32_e32 v4, 03140; GFX9-NEXT: s_waitcnt lgkmcnt(0)3141; GFX9-NEXT: v_mov_b32_e32 v0, s03142; GFX9-NEXT: v_mov_b32_e32 v1, s13143; GFX9-NEXT: v_mov_b32_e32 v2, s23144; GFX9-NEXT: v_mov_b32_e32 v3, s33145; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[4:5]3146; GFX9-NEXT: s_endpgm3147;3148; EG-LABEL: v16i8_arg:3149; EG: ; %bb.0: ; %entry3150; EG-NEXT: ALU 1, @68, KC0[], KC1[]3151; EG-NEXT: TEX 0 @363152; EG-NEXT: ALU 5, @70, KC0[], KC1[]3153; EG-NEXT: TEX 0 @383154; EG-NEXT: ALU 5, @76, KC0[], KC1[]3155; EG-NEXT: TEX 0 @403156; EG-NEXT: ALU 5, @82, KC0[], KC1[]3157; EG-NEXT: TEX 0 @423158; EG-NEXT: ALU 5, @88, KC0[], KC1[]3159; EG-NEXT: TEX 0 @443160; EG-NEXT: ALU 7, @94, KC0[], KC1[]3161; EG-NEXT: TEX 0 @463162; EG-NEXT: ALU 7, @102, KC0[], KC1[]3163; EG-NEXT: TEX 0 @483164; EG-NEXT: ALU 7, @110, KC0[], KC1[]3165; EG-NEXT: TEX 0 @503166; EG-NEXT: ALU 7, @118, KC0[], KC1[]3167; EG-NEXT: TEX 0 @523168; EG-NEXT: ALU 7, @126, KC0[], KC1[]3169; EG-NEXT: TEX 0 @543170; EG-NEXT: ALU 7, @134, KC0[], KC1[]3171; EG-NEXT: TEX 0 @563172; EG-NEXT: ALU 7, @142, KC0[], KC1[]3173; EG-NEXT: TEX 0 @583174; EG-NEXT: ALU 7, @150, KC0[], KC1[]3175; EG-NEXT: TEX 0 @603176; EG-NEXT: ALU 5, @158, KC0[], KC1[]3177; EG-NEXT: TEX 0 @623178; EG-NEXT: ALU 5, @164, KC0[], KC1[]3179; EG-NEXT: TEX 0 @643180; EG-NEXT: ALU 5, @170, KC0[], KC1[]3181; EG-NEXT: TEX 0 @663182; EG-NEXT: ALU 5, @176, KC0[CB0:0-32], KC1[]3183; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T7.XYZW, T8.X, 13184; EG-NEXT: CF_END3185; EG-NEXT: PAD3186; EG-NEXT: Fetch clause starting at 36:3187; EG-NEXT: VTX_READ_8 T8.X, T7.X, 67, #33188; EG-NEXT: Fetch clause starting at 38:3189; EG-NEXT: VTX_READ_8 T8.X, T7.X, 63, #33190; EG-NEXT: Fetch clause starting at 40:3191; EG-NEXT: VTX_READ_8 T8.X, T7.X, 59, #33192; EG-NEXT: Fetch clause starting at 42:3193; EG-NEXT: VTX_READ_8 T8.X, T7.X, 55, #33194; EG-NEXT: Fetch clause starting at 44:3195; EG-NEXT: VTX_READ_8 T8.X, T7.X, 66, #33196; EG-NEXT: Fetch clause starting at 46:3197; EG-NEXT: VTX_READ_8 T8.X, T7.X, 62, #33198; EG-NEXT: Fetch clause starting at 48:3199; EG-NEXT: VTX_READ_8 T8.X, T7.X, 58, #33200; EG-NEXT: Fetch clause starting at 50:3201; EG-NEXT: VTX_READ_8 T8.X, T7.X, 54, #33202; EG-NEXT: Fetch clause starting at 52:3203; EG-NEXT: VTX_READ_8 T8.X, T7.X, 65, #33204; EG-NEXT: Fetch clause starting at 54:3205; EG-NEXT: VTX_READ_8 T8.X, T7.X, 61, #33206; EG-NEXT: Fetch clause starting at 56:3207; EG-NEXT: VTX_READ_8 T8.X, T7.X, 57, #33208; EG-NEXT: Fetch clause starting at 58:3209; EG-NEXT: VTX_READ_8 T8.X, T7.X, 53, #33210; EG-NEXT: Fetch clause starting at 60:3211; EG-NEXT: VTX_READ_8 T8.X, T7.X, 64, #33212; EG-NEXT: Fetch clause starting at 62:3213; EG-NEXT: VTX_READ_8 T8.X, T7.X, 60, #33214; EG-NEXT: Fetch clause starting at 64:3215; EG-NEXT: VTX_READ_8 T8.X, T7.X, 56, #33216; EG-NEXT: Fetch clause starting at 66:3217; EG-NEXT: VTX_READ_8 T7.X, T7.X, 52, #33218; EG-NEXT: ALU clause starting at 68:3219; EG-NEXT: MOV * T0.Y, T2.X,3220; EG-NEXT: MOV * T7.X, 0.0,3221; EG-NEXT: ALU clause starting at 70:3222; EG-NEXT: LSHL T0.W, T8.X, literal.x,3223; EG-NEXT: AND_INT * T1.W, T0.Y, literal.y,3224; EG-NEXT: 24(3.363116e-44), 16777215(2.350989e-38)3225; EG-NEXT: OR_INT * T0.W, PS, PV.W,3226; EG-NEXT: MOV T2.X, PV.W,3227; EG-NEXT: MOV * T0.Y, T3.X,3228; EG-NEXT: ALU clause starting at 76:3229; EG-NEXT: AND_INT T0.W, T0.Y, literal.x,3230; EG-NEXT: LSHL * T1.W, T8.X, literal.y,3231; EG-NEXT: 16777215(2.350989e-38), 24(3.363116e-44)3232; EG-NEXT: OR_INT * T0.W, PV.W, PS,3233; EG-NEXT: MOV T3.X, PV.W,3234; EG-NEXT: MOV * T0.Y, T4.X,3235; EG-NEXT: ALU clause starting at 82:3236; EG-NEXT: AND_INT T0.W, T0.Y, literal.x,3237; EG-NEXT: LSHL * T1.W, T8.X, literal.y,3238; EG-NEXT: 16777215(2.350989e-38), 24(3.363116e-44)3239; EG-NEXT: OR_INT * T0.W, PV.W, PS,3240; EG-NEXT: MOV T4.X, PV.W,3241; EG-NEXT: MOV * T0.Y, T5.X,3242; EG-NEXT: ALU clause starting at 88:3243; EG-NEXT: AND_INT T0.W, T0.Y, literal.x,3244; EG-NEXT: LSHL * T1.W, T8.X, literal.y,3245; EG-NEXT: 16777215(2.350989e-38), 24(3.363116e-44)3246; EG-NEXT: OR_INT * T0.W, PV.W, PS,3247; EG-NEXT: MOV T5.X, PV.W,3248; EG-NEXT: MOV * T0.Y, T2.X,3249; EG-NEXT: ALU clause starting at 94:3250; EG-NEXT: AND_INT T0.W, T8.X, literal.x,3251; EG-NEXT: AND_INT * T1.W, T0.Y, literal.y,3252; EG-NEXT: 255(3.573311e-43), -16711681(-1.714704e+38)3253; EG-NEXT: LSHL * T0.W, PV.W, literal.x,3254; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)3255; EG-NEXT: OR_INT * T0.W, T1.W, PV.W,3256; EG-NEXT: MOV T2.X, PV.W,3257; EG-NEXT: MOV * T0.Y, T3.X,3258; EG-NEXT: ALU clause starting at 102:3259; EG-NEXT: AND_INT T0.W, T8.X, literal.x,3260; EG-NEXT: AND_INT * T1.W, T0.Y, literal.y,3261; EG-NEXT: 255(3.573311e-43), -16711681(-1.714704e+38)3262; EG-NEXT: LSHL * T0.W, PV.W, literal.x,3263; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)3264; EG-NEXT: OR_INT * T0.W, T1.W, PV.W,3265; EG-NEXT: MOV T3.X, PV.W,3266; EG-NEXT: MOV * T0.Y, T4.X,3267; EG-NEXT: ALU clause starting at 110:3268; EG-NEXT: AND_INT T0.W, T8.X, literal.x,3269; EG-NEXT: AND_INT * T1.W, T0.Y, literal.y,3270; EG-NEXT: 255(3.573311e-43), -16711681(-1.714704e+38)3271; EG-NEXT: LSHL * T0.W, PV.W, literal.x,3272; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)3273; EG-NEXT: OR_INT * T0.W, T1.W, PV.W,3274; EG-NEXT: MOV T4.X, PV.W,3275; EG-NEXT: MOV * T0.Y, T5.X,3276; EG-NEXT: ALU clause starting at 118:3277; EG-NEXT: AND_INT T0.W, T8.X, literal.x,3278; EG-NEXT: AND_INT * T1.W, T0.Y, literal.y,3279; EG-NEXT: 255(3.573311e-43), -16711681(-1.714704e+38)3280; EG-NEXT: LSHL * T0.W, PV.W, literal.x,3281; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)3282; EG-NEXT: OR_INT * T0.W, T1.W, PV.W,3283; EG-NEXT: MOV T5.X, PV.W,3284; EG-NEXT: MOV * T0.Y, T2.X,3285; EG-NEXT: ALU clause starting at 126:3286; EG-NEXT: AND_INT T0.W, T8.X, literal.x,3287; EG-NEXT: AND_INT * T1.W, T0.Y, literal.y,3288; EG-NEXT: 255(3.573311e-43), -65281(nan)3289; EG-NEXT: LSHL * T0.W, PV.W, literal.x,3290; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)3291; EG-NEXT: OR_INT * T0.W, T1.W, PV.W,3292; EG-NEXT: MOV T2.X, PV.W,3293; EG-NEXT: MOV * T0.Y, T3.X,3294; EG-NEXT: ALU clause starting at 134:3295; EG-NEXT: AND_INT T0.W, T8.X, literal.x,3296; EG-NEXT: AND_INT * T1.W, T0.Y, literal.y,3297; EG-NEXT: 255(3.573311e-43), -65281(nan)3298; EG-NEXT: LSHL * T0.W, PV.W, literal.x,3299; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)3300; EG-NEXT: OR_INT * T0.W, T1.W, PV.W,3301; EG-NEXT: MOV T3.X, PV.W,3302; EG-NEXT: MOV * T0.Y, T4.X,3303; EG-NEXT: ALU clause starting at 142:3304; EG-NEXT: AND_INT T0.W, T8.X, literal.x,3305; EG-NEXT: AND_INT * T1.W, T0.Y, literal.y,3306; EG-NEXT: 255(3.573311e-43), -65281(nan)3307; EG-NEXT: LSHL * T0.W, PV.W, literal.x,3308; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)3309; EG-NEXT: OR_INT * T0.W, T1.W, PV.W,3310; EG-NEXT: MOV T4.X, PV.W,3311; EG-NEXT: MOV * T0.Y, T5.X,3312; EG-NEXT: ALU clause starting at 150:3313; EG-NEXT: AND_INT T0.W, T8.X, literal.x,3314; EG-NEXT: AND_INT * T1.W, T0.Y, literal.y,3315; EG-NEXT: 255(3.573311e-43), -65281(nan)3316; EG-NEXT: LSHL * T0.W, PV.W, literal.x,3317; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)3318; EG-NEXT: OR_INT * T0.W, T1.W, PV.W,3319; EG-NEXT: MOV T5.X, PV.W,3320; EG-NEXT: MOV * T0.Y, T2.X,3321; EG-NEXT: ALU clause starting at 158:3322; EG-NEXT: AND_INT T0.W, T0.Y, literal.x,3323; EG-NEXT: AND_INT * T1.W, T8.X, literal.y,3324; EG-NEXT: -256(nan), 255(3.573311e-43)3325; EG-NEXT: OR_INT * T7.W, PV.W, PS,3326; EG-NEXT: MOV T2.X, PV.W,3327; EG-NEXT: MOV * T0.Y, T3.X,3328; EG-NEXT: ALU clause starting at 164:3329; EG-NEXT: AND_INT T0.W, T0.Y, literal.x,3330; EG-NEXT: AND_INT * T1.W, T8.X, literal.y,3331; EG-NEXT: -256(nan), 255(3.573311e-43)3332; EG-NEXT: OR_INT * T7.Z, PV.W, PS,3333; EG-NEXT: MOV T3.X, PV.Z,3334; EG-NEXT: MOV * T0.Y, T4.X,3335; EG-NEXT: ALU clause starting at 170:3336; EG-NEXT: AND_INT T0.W, T0.Y, literal.x,3337; EG-NEXT: AND_INT * T1.W, T8.X, literal.y,3338; EG-NEXT: -256(nan), 255(3.573311e-43)3339; EG-NEXT: OR_INT * T7.Y, PV.W, PS,3340; EG-NEXT: MOV T4.X, PV.Y,3341; EG-NEXT: MOV * T0.Y, T5.X,3342; EG-NEXT: ALU clause starting at 176:3343; EG-NEXT: AND_INT T0.W, T0.Y, literal.x,3344; EG-NEXT: AND_INT * T1.W, T7.X, literal.y,3345; EG-NEXT: -256(nan), 255(3.573311e-43)3346; EG-NEXT: OR_INT T7.X, PV.W, PS,3347; EG-NEXT: LSHR * T8.X, KC0[2].Y, literal.x,3348; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)3349;3350; CM-LABEL: v16i8_arg:3351; CM: ; %bb.0: ; %entry3352; CM-NEXT: ALU 1, @68, KC0[], KC1[]3353; CM-NEXT: TEX 0 @363354; CM-NEXT: ALU 5, @70, KC0[], KC1[]3355; CM-NEXT: TEX 0 @383356; CM-NEXT: ALU 5, @76, KC0[], KC1[]3357; CM-NEXT: TEX 0 @403358; CM-NEXT: ALU 5, @82, KC0[], KC1[]3359; CM-NEXT: TEX 0 @423360; CM-NEXT: ALU 5, @88, KC0[], KC1[]3361; CM-NEXT: TEX 0 @443362; CM-NEXT: ALU 7, @94, KC0[], KC1[]3363; CM-NEXT: TEX 0 @463364; CM-NEXT: ALU 7, @102, KC0[], KC1[]3365; CM-NEXT: TEX 0 @483366; CM-NEXT: ALU 7, @110, KC0[], KC1[]3367; CM-NEXT: TEX 0 @503368; CM-NEXT: ALU 7, @118, KC0[], KC1[]3369; CM-NEXT: TEX 0 @523370; CM-NEXT: ALU 7, @126, KC0[], KC1[]3371; CM-NEXT: TEX 0 @543372; CM-NEXT: ALU 7, @134, KC0[], KC1[]3373; CM-NEXT: TEX 0 @563374; CM-NEXT: ALU 7, @142, KC0[], KC1[]3375; CM-NEXT: TEX 0 @583376; CM-NEXT: ALU 7, @150, KC0[], KC1[]3377; CM-NEXT: TEX 0 @603378; CM-NEXT: ALU 5, @158, KC0[], KC1[]3379; CM-NEXT: TEX 0 @623380; CM-NEXT: ALU 5, @164, KC0[], KC1[]3381; CM-NEXT: TEX 0 @643382; CM-NEXT: ALU 5, @170, KC0[], KC1[]3383; CM-NEXT: TEX 0 @663384; CM-NEXT: ALU 5, @176, KC0[CB0:0-32], KC1[]3385; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T7, T8.X3386; CM-NEXT: CF_END3387; CM-NEXT: PAD3388; CM-NEXT: Fetch clause starting at 36:3389; CM-NEXT: VTX_READ_8 T8.X, T7.X, 67, #33390; CM-NEXT: Fetch clause starting at 38:3391; CM-NEXT: VTX_READ_8 T8.X, T7.X, 63, #33392; CM-NEXT: Fetch clause starting at 40:3393; CM-NEXT: VTX_READ_8 T8.X, T7.X, 59, #33394; CM-NEXT: Fetch clause starting at 42:3395; CM-NEXT: VTX_READ_8 T8.X, T7.X, 55, #33396; CM-NEXT: Fetch clause starting at 44:3397; CM-NEXT: VTX_READ_8 T8.X, T7.X, 66, #33398; CM-NEXT: Fetch clause starting at 46:3399; CM-NEXT: VTX_READ_8 T8.X, T7.X, 62, #33400; CM-NEXT: Fetch clause starting at 48:3401; CM-NEXT: VTX_READ_8 T8.X, T7.X, 58, #33402; CM-NEXT: Fetch clause starting at 50:3403; CM-NEXT: VTX_READ_8 T8.X, T7.X, 54, #33404; CM-NEXT: Fetch clause starting at 52:3405; CM-NEXT: VTX_READ_8 T8.X, T7.X, 65, #33406; CM-NEXT: Fetch clause starting at 54:3407; CM-NEXT: VTX_READ_8 T8.X, T7.X, 61, #33408; CM-NEXT: Fetch clause starting at 56:3409; CM-NEXT: VTX_READ_8 T8.X, T7.X, 57, #33410; CM-NEXT: Fetch clause starting at 58:3411; CM-NEXT: VTX_READ_8 T8.X, T7.X, 53, #33412; CM-NEXT: Fetch clause starting at 60:3413; CM-NEXT: VTX_READ_8 T8.X, T7.X, 64, #33414; CM-NEXT: Fetch clause starting at 62:3415; CM-NEXT: VTX_READ_8 T8.X, T7.X, 60, #33416; CM-NEXT: Fetch clause starting at 64:3417; CM-NEXT: VTX_READ_8 T8.X, T7.X, 56, #33418; CM-NEXT: Fetch clause starting at 66:3419; CM-NEXT: VTX_READ_8 T7.X, T7.X, 52, #33420; CM-NEXT: ALU clause starting at 68:3421; CM-NEXT: MOV * T0.Y, T2.X,3422; CM-NEXT: MOV * T7.X, 0.0,3423; CM-NEXT: ALU clause starting at 70:3424; CM-NEXT: LSHL T0.Z, T8.X, literal.x,3425; CM-NEXT: AND_INT * T0.W, T0.Y, literal.y,3426; CM-NEXT: 24(3.363116e-44), 16777215(2.350989e-38)3427; CM-NEXT: OR_INT * T0.W, PV.W, PV.Z,3428; CM-NEXT: MOV T2.X, PV.W,3429; CM-NEXT: MOV * T0.Y, T3.X,3430; CM-NEXT: ALU clause starting at 76:3431; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x,3432; CM-NEXT: LSHL * T0.W, T8.X, literal.y,3433; CM-NEXT: 16777215(2.350989e-38), 24(3.363116e-44)3434; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W,3435; CM-NEXT: MOV T3.X, PV.W,3436; CM-NEXT: MOV * T0.Y, T4.X,3437; CM-NEXT: ALU clause starting at 82:3438; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x,3439; CM-NEXT: LSHL * T0.W, T8.X, literal.y,3440; CM-NEXT: 16777215(2.350989e-38), 24(3.363116e-44)3441; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W,3442; CM-NEXT: MOV T4.X, PV.W,3443; CM-NEXT: MOV * T0.Y, T5.X,3444; CM-NEXT: ALU clause starting at 88:3445; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x,3446; CM-NEXT: LSHL * T0.W, T8.X, literal.y,3447; CM-NEXT: 16777215(2.350989e-38), 24(3.363116e-44)3448; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W,3449; CM-NEXT: MOV T5.X, PV.W,3450; CM-NEXT: MOV * T0.Y, T2.X,3451; CM-NEXT: ALU clause starting at 94:3452; CM-NEXT: AND_INT * T0.W, T8.X, literal.x,3453; CM-NEXT: 255(3.573311e-43), 0(0.000000e+00)3454; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x,3455; CM-NEXT: LSHL * T0.W, PV.W, literal.y,3456; CM-NEXT: -16711681(-1.714704e+38), 16(2.242078e-44)3457; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W,3458; CM-NEXT: MOV T2.X, PV.W,3459; CM-NEXT: MOV * T0.Y, T3.X,3460; CM-NEXT: ALU clause starting at 102:3461; CM-NEXT: AND_INT * T0.W, T8.X, literal.x,3462; CM-NEXT: 255(3.573311e-43), 0(0.000000e+00)3463; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x,3464; CM-NEXT: LSHL * T0.W, PV.W, literal.y,3465; CM-NEXT: -16711681(-1.714704e+38), 16(2.242078e-44)3466; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W,3467; CM-NEXT: MOV T3.X, PV.W,3468; CM-NEXT: MOV * T0.Y, T4.X,3469; CM-NEXT: ALU clause starting at 110:3470; CM-NEXT: AND_INT * T0.W, T8.X, literal.x,3471; CM-NEXT: 255(3.573311e-43), 0(0.000000e+00)3472; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x,3473; CM-NEXT: LSHL * T0.W, PV.W, literal.y,3474; CM-NEXT: -16711681(-1.714704e+38), 16(2.242078e-44)3475; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W,3476; CM-NEXT: MOV T4.X, PV.W,3477; CM-NEXT: MOV * T0.Y, T5.X,3478; CM-NEXT: ALU clause starting at 118:3479; CM-NEXT: AND_INT * T0.W, T8.X, literal.x,3480; CM-NEXT: 255(3.573311e-43), 0(0.000000e+00)3481; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x,3482; CM-NEXT: LSHL * T0.W, PV.W, literal.y,3483; CM-NEXT: -16711681(-1.714704e+38), 16(2.242078e-44)3484; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W,3485; CM-NEXT: MOV T5.X, PV.W,3486; CM-NEXT: MOV * T0.Y, T2.X,3487; CM-NEXT: ALU clause starting at 126:3488; CM-NEXT: AND_INT * T0.W, T8.X, literal.x,3489; CM-NEXT: 255(3.573311e-43), 0(0.000000e+00)3490; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x,3491; CM-NEXT: LSHL * T0.W, PV.W, literal.y,3492; CM-NEXT: -65281(nan), 8(1.121039e-44)3493; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W,3494; CM-NEXT: MOV T2.X, PV.W,3495; CM-NEXT: MOV * T0.Y, T3.X,3496; CM-NEXT: ALU clause starting at 134:3497; CM-NEXT: AND_INT * T0.W, T8.X, literal.x,3498; CM-NEXT: 255(3.573311e-43), 0(0.000000e+00)3499; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x,3500; CM-NEXT: LSHL * T0.W, PV.W, literal.y,3501; CM-NEXT: -65281(nan), 8(1.121039e-44)3502; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W,3503; CM-NEXT: MOV T3.X, PV.W,3504; CM-NEXT: MOV * T0.Y, T4.X,3505; CM-NEXT: ALU clause starting at 142:3506; CM-NEXT: AND_INT * T0.W, T8.X, literal.x,3507; CM-NEXT: 255(3.573311e-43), 0(0.000000e+00)3508; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x,3509; CM-NEXT: LSHL * T0.W, PV.W, literal.y,3510; CM-NEXT: -65281(nan), 8(1.121039e-44)3511; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W,3512; CM-NEXT: MOV T4.X, PV.W,3513; CM-NEXT: MOV * T0.Y, T5.X,3514; CM-NEXT: ALU clause starting at 150:3515; CM-NEXT: AND_INT * T0.W, T8.X, literal.x,3516; CM-NEXT: 255(3.573311e-43), 0(0.000000e+00)3517; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x,3518; CM-NEXT: LSHL * T0.W, PV.W, literal.y,3519; CM-NEXT: -65281(nan), 8(1.121039e-44)3520; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W,3521; CM-NEXT: MOV T5.X, PV.W,3522; CM-NEXT: MOV * T0.Y, T2.X,3523; CM-NEXT: ALU clause starting at 158:3524; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x,3525; CM-NEXT: AND_INT * T0.W, T8.X, literal.y,3526; CM-NEXT: -256(nan), 255(3.573311e-43)3527; CM-NEXT: OR_INT * T7.W, PV.Z, PV.W,3528; CM-NEXT: MOV T2.X, PV.W,3529; CM-NEXT: MOV * T0.Y, T3.X,3530; CM-NEXT: ALU clause starting at 164:3531; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x,3532; CM-NEXT: AND_INT * T0.W, T8.X, literal.y,3533; CM-NEXT: -256(nan), 255(3.573311e-43)3534; CM-NEXT: OR_INT * T7.Z, PV.Z, PV.W,3535; CM-NEXT: MOV T3.X, PV.Z,3536; CM-NEXT: MOV * T0.Y, T4.X,3537; CM-NEXT: ALU clause starting at 170:3538; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x,3539; CM-NEXT: AND_INT * T0.W, T8.X, literal.y,3540; CM-NEXT: -256(nan), 255(3.573311e-43)3541; CM-NEXT: OR_INT * T7.Y, PV.Z, PV.W,3542; CM-NEXT: MOV T4.X, PV.Y,3543; CM-NEXT: MOV * T0.Y, T5.X,3544; CM-NEXT: ALU clause starting at 176:3545; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x,3546; CM-NEXT: AND_INT * T0.W, T7.X, literal.y,3547; CM-NEXT: -256(nan), 255(3.573311e-43)3548; CM-NEXT: OR_INT * T7.X, PV.Z, PV.W,3549; CM-NEXT: LSHR * T8.X, KC0[2].Y, literal.x,3550; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)3551entry:3552 store <16 x i8> %in, ptr addrspace(1) %out3553 ret void3554}3555 3556define amdgpu_kernel void @v16i16_arg(ptr addrspace(1) %out, <16 x i16> %in) {3557; SI-LABEL: v16i16_arg:3558; SI: ; %bb.0: ; %entry3559; SI-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x113560; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x93561; SI-NEXT: s_mov_b32 s3, 0xf0003562; SI-NEXT: s_mov_b32 s2, -13563; SI-NEXT: s_waitcnt lgkmcnt(0)3564; SI-NEXT: v_mov_b32_e32 v0, s123565; SI-NEXT: v_mov_b32_e32 v1, s133566; SI-NEXT: v_mov_b32_e32 v2, s143567; SI-NEXT: v_mov_b32_e32 v3, s153568; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:163569; SI-NEXT: s_waitcnt expcnt(0)3570; SI-NEXT: v_mov_b32_e32 v0, s83571; SI-NEXT: v_mov_b32_e32 v1, s93572; SI-NEXT: v_mov_b32_e32 v2, s103573; SI-NEXT: v_mov_b32_e32 v3, s113574; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 03575; SI-NEXT: s_endpgm3576;3577; VI-LABEL: v16i16_arg:3578; VI: ; %bb.0: ; %entry3579; VI-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x443580; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x243581; VI-NEXT: s_waitcnt lgkmcnt(0)3582; VI-NEXT: v_mov_b32_e32 v0, s123583; VI-NEXT: s_add_u32 s2, s0, 163584; VI-NEXT: s_addc_u32 s3, s1, 03585; VI-NEXT: v_mov_b32_e32 v5, s33586; VI-NEXT: v_mov_b32_e32 v1, s133587; VI-NEXT: v_mov_b32_e32 v2, s143588; VI-NEXT: v_mov_b32_e32 v3, s153589; VI-NEXT: v_mov_b32_e32 v4, s23590; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]3591; VI-NEXT: v_mov_b32_e32 v5, s13592; VI-NEXT: v_mov_b32_e32 v0, s83593; VI-NEXT: v_mov_b32_e32 v1, s93594; VI-NEXT: v_mov_b32_e32 v2, s103595; VI-NEXT: v_mov_b32_e32 v3, s113596; VI-NEXT: v_mov_b32_e32 v4, s03597; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]3598; VI-NEXT: s_endpgm3599;3600; GFX9-LABEL: v16i16_arg:3601; GFX9: ; %bb.0: ; %entry3602; GFX9-NEXT: s_load_dwordx8 s[0:7], s[8:9], 0x203603; GFX9-NEXT: v_mov_b32_e32 v4, 03604; GFX9-NEXT: s_load_dwordx2 s[8:9], s[8:9], 0x03605; GFX9-NEXT: s_waitcnt lgkmcnt(0)3606; GFX9-NEXT: v_mov_b32_e32 v0, s43607; GFX9-NEXT: v_mov_b32_e32 v1, s53608; GFX9-NEXT: v_mov_b32_e32 v2, s63609; GFX9-NEXT: v_mov_b32_e32 v3, s73610; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[8:9] offset:163611; GFX9-NEXT: s_nop 03612; GFX9-NEXT: v_mov_b32_e32 v0, s03613; GFX9-NEXT: v_mov_b32_e32 v1, s13614; GFX9-NEXT: v_mov_b32_e32 v2, s23615; GFX9-NEXT: v_mov_b32_e32 v3, s33616; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[8:9]3617; GFX9-NEXT: s_endpgm3618;3619; EG-LABEL: v16i16_arg:3620; EG: ; %bb.0: ; %entry3621; EG-NEXT: ALU 1, @68, KC0[], KC1[]3622; EG-NEXT: TEX 0 @363623; EG-NEXT: ALU 5, @70, KC0[], KC1[]3624; EG-NEXT: TEX 0 @383625; EG-NEXT: ALU 5, @76, KC0[], KC1[]3626; EG-NEXT: TEX 0 @403627; EG-NEXT: ALU 5, @82, KC0[], KC1[]3628; EG-NEXT: TEX 0 @423629; EG-NEXT: ALU 5, @88, KC0[], KC1[]3630; EG-NEXT: TEX 0 @443631; EG-NEXT: ALU 5, @94, KC0[], KC1[]3632; EG-NEXT: TEX 0 @463633; EG-NEXT: ALU 5, @100, KC0[], KC1[]3634; EG-NEXT: TEX 0 @483635; EG-NEXT: ALU 5, @106, KC0[], KC1[]3636; EG-NEXT: TEX 0 @503637; EG-NEXT: ALU 5, @112, KC0[], KC1[]3638; EG-NEXT: TEX 0 @523639; EG-NEXT: ALU 5, @118, KC0[], KC1[]3640; EG-NEXT: TEX 0 @543641; EG-NEXT: ALU 5, @124, KC0[], KC1[]3642; EG-NEXT: TEX 0 @563643; EG-NEXT: ALU 5, @130, KC0[], KC1[]3644; EG-NEXT: TEX 0 @583645; EG-NEXT: ALU 5, @136, KC0[], KC1[]3646; EG-NEXT: TEX 0 @603647; EG-NEXT: ALU 5, @142, KC0[], KC1[]3648; EG-NEXT: TEX 0 @623649; EG-NEXT: ALU 5, @148, KC0[], KC1[]3650; EG-NEXT: TEX 0 @643651; EG-NEXT: ALU 5, @154, KC0[], KC1[]3652; EG-NEXT: TEX 0 @663653; EG-NEXT: ALU 13, @160, KC0[CB0:0-32], KC1[]3654; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T12.XYZW, T14.X, 03655; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T11.XYZW, T13.X, 13656; EG-NEXT: CF_END3657; EG-NEXT: Fetch clause starting at 36:3658; EG-NEXT: VTX_READ_16 T12.X, T11.X, 98, #33659; EG-NEXT: Fetch clause starting at 38:3660; EG-NEXT: VTX_READ_16 T12.X, T11.X, 90, #33661; EG-NEXT: Fetch clause starting at 40:3662; EG-NEXT: VTX_READ_16 T12.X, T11.X, 82, #33663; EG-NEXT: Fetch clause starting at 42:3664; EG-NEXT: VTX_READ_16 T12.X, T11.X, 74, #33665; EG-NEXT: Fetch clause starting at 44:3666; EG-NEXT: VTX_READ_16 T12.X, T11.X, 96, #33667; EG-NEXT: Fetch clause starting at 46:3668; EG-NEXT: VTX_READ_16 T12.X, T11.X, 88, #33669; EG-NEXT: Fetch clause starting at 48:3670; EG-NEXT: VTX_READ_16 T12.X, T11.X, 80, #33671; EG-NEXT: Fetch clause starting at 50:3672; EG-NEXT: VTX_READ_16 T12.X, T11.X, 72, #33673; EG-NEXT: Fetch clause starting at 52:3674; EG-NEXT: VTX_READ_16 T12.X, T11.X, 94, #33675; EG-NEXT: Fetch clause starting at 54:3676; EG-NEXT: VTX_READ_16 T12.X, T11.X, 86, #33677; EG-NEXT: Fetch clause starting at 56:3678; EG-NEXT: VTX_READ_16 T12.X, T11.X, 78, #33679; EG-NEXT: Fetch clause starting at 58:3680; EG-NEXT: VTX_READ_16 T12.X, T11.X, 70, #33681; EG-NEXT: Fetch clause starting at 60:3682; EG-NEXT: VTX_READ_16 T12.X, T11.X, 92, #33683; EG-NEXT: Fetch clause starting at 62:3684; EG-NEXT: VTX_READ_16 T12.X, T11.X, 84, #33685; EG-NEXT: Fetch clause starting at 64:3686; EG-NEXT: VTX_READ_16 T13.X, T11.X, 76, #33687; EG-NEXT: Fetch clause starting at 66:3688; EG-NEXT: VTX_READ_16 T11.X, T11.X, 68, #33689; EG-NEXT: ALU clause starting at 68:3690; EG-NEXT: MOV * T0.Y, T3.X,3691; EG-NEXT: MOV * T11.X, 0.0,3692; EG-NEXT: ALU clause starting at 70:3693; EG-NEXT: LSHL T0.W, T12.X, literal.x,3694; EG-NEXT: AND_INT * T1.W, T0.Y, literal.y,3695; EG-NEXT: 16(2.242078e-44), 65535(9.183409e-41)3696; EG-NEXT: OR_INT * T0.W, PS, PV.W,3697; EG-NEXT: MOV T3.X, PV.W,3698; EG-NEXT: MOV * T0.Y, T5.X,3699; EG-NEXT: ALU clause starting at 76:3700; EG-NEXT: AND_INT T0.W, T0.Y, literal.x,3701; EG-NEXT: LSHL * T1.W, T12.X, literal.y,3702; EG-NEXT: 65535(9.183409e-41), 16(2.242078e-44)3703; EG-NEXT: OR_INT * T0.W, PV.W, PS,3704; EG-NEXT: MOV T5.X, PV.W,3705; EG-NEXT: MOV * T0.Y, T7.X,3706; EG-NEXT: ALU clause starting at 82:3707; EG-NEXT: AND_INT T0.W, T0.Y, literal.x,3708; EG-NEXT: LSHL * T1.W, T12.X, literal.y,3709; EG-NEXT: 65535(9.183409e-41), 16(2.242078e-44)3710; EG-NEXT: OR_INT * T0.W, PV.W, PS,3711; EG-NEXT: MOV T7.X, PV.W,3712; EG-NEXT: MOV * T0.Y, T9.X,3713; EG-NEXT: ALU clause starting at 88:3714; EG-NEXT: AND_INT T0.W, T0.Y, literal.x,3715; EG-NEXT: LSHL * T1.W, T12.X, literal.y,3716; EG-NEXT: 65535(9.183409e-41), 16(2.242078e-44)3717; EG-NEXT: OR_INT * T0.W, PV.W, PS,3718; EG-NEXT: MOV T9.X, PV.W,3719; EG-NEXT: MOV * T0.Y, T3.X,3720; EG-NEXT: ALU clause starting at 94:3721; EG-NEXT: AND_INT T0.W, T0.Y, literal.x,3722; EG-NEXT: AND_INT * T1.W, T12.X, literal.y,3723; EG-NEXT: -65536(nan), 65535(9.183409e-41)3724; EG-NEXT: OR_INT * T0.W, PV.W, PS,3725; EG-NEXT: MOV T3.X, PV.W,3726; EG-NEXT: MOV * T0.Y, T5.X,3727; EG-NEXT: ALU clause starting at 100:3728; EG-NEXT: AND_INT T0.W, T0.Y, literal.x,3729; EG-NEXT: AND_INT * T1.W, T12.X, literal.y,3730; EG-NEXT: -65536(nan), 65535(9.183409e-41)3731; EG-NEXT: OR_INT * T0.W, PV.W, PS,3732; EG-NEXT: MOV T5.X, PV.W,3733; EG-NEXT: MOV * T0.Y, T7.X,3734; EG-NEXT: ALU clause starting at 106:3735; EG-NEXT: AND_INT T0.W, T0.Y, literal.x,3736; EG-NEXT: AND_INT * T1.W, T12.X, literal.y,3737; EG-NEXT: -65536(nan), 65535(9.183409e-41)3738; EG-NEXT: OR_INT * T0.W, PV.W, PS,3739; EG-NEXT: MOV T7.X, PV.W,3740; EG-NEXT: MOV * T0.Y, T9.X,3741; EG-NEXT: ALU clause starting at 112:3742; EG-NEXT: AND_INT T0.W, T0.Y, literal.x,3743; EG-NEXT: AND_INT * T1.W, T12.X, literal.y,3744; EG-NEXT: -65536(nan), 65535(9.183409e-41)3745; EG-NEXT: OR_INT * T0.W, PV.W, PS,3746; EG-NEXT: MOV T9.X, PV.W,3747; EG-NEXT: MOV * T0.Y, T2.X,3748; EG-NEXT: ALU clause starting at 118:3749; EG-NEXT: AND_INT T0.W, T0.Y, literal.x,3750; EG-NEXT: LSHL * T1.W, T12.X, literal.y,3751; EG-NEXT: 65535(9.183409e-41), 16(2.242078e-44)3752; EG-NEXT: OR_INT * T0.W, PV.W, PS,3753; EG-NEXT: MOV T2.X, PV.W,3754; EG-NEXT: MOV * T0.Y, T4.X,3755; EG-NEXT: ALU clause starting at 124:3756; EG-NEXT: AND_INT T0.W, T0.Y, literal.x,3757; EG-NEXT: LSHL * T1.W, T12.X, literal.y,3758; EG-NEXT: 65535(9.183409e-41), 16(2.242078e-44)3759; EG-NEXT: OR_INT * T0.W, PV.W, PS,3760; EG-NEXT: MOV T4.X, PV.W,3761; EG-NEXT: MOV * T0.Y, T6.X,3762; EG-NEXT: ALU clause starting at 130:3763; EG-NEXT: AND_INT T0.W, T0.Y, literal.x,3764; EG-NEXT: LSHL * T1.W, T12.X, literal.y,3765; EG-NEXT: 65535(9.183409e-41), 16(2.242078e-44)3766; EG-NEXT: OR_INT * T0.W, PV.W, PS,3767; EG-NEXT: MOV T6.X, PV.W,3768; EG-NEXT: MOV * T0.Y, T8.X,3769; EG-NEXT: ALU clause starting at 136:3770; EG-NEXT: AND_INT T0.W, T0.Y, literal.x,3771; EG-NEXT: LSHL * T1.W, T12.X, literal.y,3772; EG-NEXT: 65535(9.183409e-41), 16(2.242078e-44)3773; EG-NEXT: OR_INT * T0.W, PV.W, PS,3774; EG-NEXT: MOV T8.X, PV.W,3775; EG-NEXT: MOV * T0.Y, T2.X,3776; EG-NEXT: ALU clause starting at 142:3777; EG-NEXT: AND_INT T0.W, T0.Y, literal.x,3778; EG-NEXT: AND_INT * T1.W, T12.X, literal.y,3779; EG-NEXT: -65536(nan), 65535(9.183409e-41)3780; EG-NEXT: OR_INT * T12.Z, PV.W, PS,3781; EG-NEXT: MOV T2.X, PV.Z,3782; EG-NEXT: MOV * T0.Y, T4.X,3783; EG-NEXT: ALU clause starting at 148:3784; EG-NEXT: AND_INT T0.W, T0.Y, literal.x,3785; EG-NEXT: AND_INT * T1.W, T12.X, literal.y,3786; EG-NEXT: -65536(nan), 65535(9.183409e-41)3787; EG-NEXT: OR_INT * T12.X, PV.W, PS,3788; EG-NEXT: MOV T4.X, PV.X,3789; EG-NEXT: MOV * T0.Y, T6.X,3790; EG-NEXT: ALU clause starting at 154:3791; EG-NEXT: AND_INT T0.W, T0.Y, literal.x,3792; EG-NEXT: AND_INT * T1.W, T13.X, literal.y,3793; EG-NEXT: -65536(nan), 65535(9.183409e-41)3794; EG-NEXT: OR_INT * T11.Z, PV.W, PS,3795; EG-NEXT: MOV T6.X, PV.Z,3796; EG-NEXT: MOV * T0.Y, T8.X,3797; EG-NEXT: ALU clause starting at 160:3798; EG-NEXT: LSHR T13.X, KC0[2].Y, literal.x,3799; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,3800; EG-NEXT: 2(2.802597e-45), 16(2.242078e-44)3801; EG-NEXT: LSHR T14.X, PV.W, literal.x,3802; EG-NEXT: AND_INT T0.W, T0.Y, literal.y,3803; EG-NEXT: AND_INT * T1.W, T11.X, literal.z,3804; EG-NEXT: 2(2.802597e-45), -65536(nan)3805; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)3806; EG-NEXT: OR_INT * T11.X, PV.W, PS,3807; EG-NEXT: MOV T8.X, PV.X,3808; EG-NEXT: MOV * T12.W, T3.X,3809; EG-NEXT: MOV T12.Y, T5.X,3810; EG-NEXT: MOV T11.W, T7.X, BS:VEC_120/SCL_2123811; EG-NEXT: MOV * T11.Y, T9.X,3812;3813; CM-LABEL: v16i16_arg:3814; CM: ; %bb.0: ; %entry3815; CM-NEXT: ALU 1, @68, KC0[], KC1[]3816; CM-NEXT: TEX 0 @363817; CM-NEXT: ALU 5, @70, KC0[], KC1[]3818; CM-NEXT: TEX 0 @383819; CM-NEXT: ALU 5, @76, KC0[], KC1[]3820; CM-NEXT: TEX 0 @403821; CM-NEXT: ALU 5, @82, KC0[], KC1[]3822; CM-NEXT: TEX 0 @423823; CM-NEXT: ALU 5, @88, KC0[], KC1[]3824; CM-NEXT: TEX 0 @443825; CM-NEXT: ALU 5, @94, KC0[], KC1[]3826; CM-NEXT: TEX 0 @463827; CM-NEXT: ALU 5, @100, KC0[], KC1[]3828; CM-NEXT: TEX 0 @483829; CM-NEXT: ALU 5, @106, KC0[], KC1[]3830; CM-NEXT: TEX 0 @503831; CM-NEXT: ALU 5, @112, KC0[], KC1[]3832; CM-NEXT: TEX 0 @523833; CM-NEXT: ALU 5, @118, KC0[], KC1[]3834; CM-NEXT: TEX 0 @543835; CM-NEXT: ALU 5, @124, KC0[], KC1[]3836; CM-NEXT: TEX 0 @563837; CM-NEXT: ALU 5, @130, KC0[], KC1[]3838; CM-NEXT: TEX 0 @583839; CM-NEXT: ALU 5, @136, KC0[], KC1[]3840; CM-NEXT: TEX 0 @603841; CM-NEXT: ALU 5, @142, KC0[], KC1[]3842; CM-NEXT: TEX 0 @623843; CM-NEXT: ALU 5, @148, KC0[], KC1[]3844; CM-NEXT: TEX 0 @643845; CM-NEXT: ALU 5, @154, KC0[], KC1[]3846; CM-NEXT: TEX 0 @663847; CM-NEXT: ALU 14, @160, KC0[CB0:0-32], KC1[]3848; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T11, T14.X3849; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T12, T13.X3850; CM-NEXT: CF_END3851; CM-NEXT: Fetch clause starting at 36:3852; CM-NEXT: VTX_READ_16 T12.X, T11.X, 98, #33853; CM-NEXT: Fetch clause starting at 38:3854; CM-NEXT: VTX_READ_16 T12.X, T11.X, 90, #33855; CM-NEXT: Fetch clause starting at 40:3856; CM-NEXT: VTX_READ_16 T12.X, T11.X, 82, #33857; CM-NEXT: Fetch clause starting at 42:3858; CM-NEXT: VTX_READ_16 T12.X, T11.X, 74, #33859; CM-NEXT: Fetch clause starting at 44:3860; CM-NEXT: VTX_READ_16 T12.X, T11.X, 96, #33861; CM-NEXT: Fetch clause starting at 46:3862; CM-NEXT: VTX_READ_16 T12.X, T11.X, 88, #33863; CM-NEXT: Fetch clause starting at 48:3864; CM-NEXT: VTX_READ_16 T12.X, T11.X, 80, #33865; CM-NEXT: Fetch clause starting at 50:3866; CM-NEXT: VTX_READ_16 T12.X, T11.X, 72, #33867; CM-NEXT: Fetch clause starting at 52:3868; CM-NEXT: VTX_READ_16 T12.X, T11.X, 94, #33869; CM-NEXT: Fetch clause starting at 54:3870; CM-NEXT: VTX_READ_16 T12.X, T11.X, 86, #33871; CM-NEXT: Fetch clause starting at 56:3872; CM-NEXT: VTX_READ_16 T12.X, T11.X, 78, #33873; CM-NEXT: Fetch clause starting at 58:3874; CM-NEXT: VTX_READ_16 T12.X, T11.X, 70, #33875; CM-NEXT: Fetch clause starting at 60:3876; CM-NEXT: VTX_READ_16 T12.X, T11.X, 92, #33877; CM-NEXT: Fetch clause starting at 62:3878; CM-NEXT: VTX_READ_16 T12.X, T11.X, 84, #33879; CM-NEXT: Fetch clause starting at 64:3880; CM-NEXT: VTX_READ_16 T13.X, T11.X, 76, #33881; CM-NEXT: Fetch clause starting at 66:3882; CM-NEXT: VTX_READ_16 T11.X, T11.X, 68, #33883; CM-NEXT: ALU clause starting at 68:3884; CM-NEXT: MOV * T0.Y, T3.X,3885; CM-NEXT: MOV * T11.X, 0.0,3886; CM-NEXT: ALU clause starting at 70:3887; CM-NEXT: LSHL T0.Z, T12.X, literal.x,3888; CM-NEXT: AND_INT * T0.W, T0.Y, literal.y,3889; CM-NEXT: 16(2.242078e-44), 65535(9.183409e-41)3890; CM-NEXT: OR_INT * T0.W, PV.W, PV.Z,3891; CM-NEXT: MOV T3.X, PV.W,3892; CM-NEXT: MOV * T0.Y, T5.X,3893; CM-NEXT: ALU clause starting at 76:3894; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x,3895; CM-NEXT: LSHL * T0.W, T12.X, literal.y,3896; CM-NEXT: 65535(9.183409e-41), 16(2.242078e-44)3897; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W,3898; CM-NEXT: MOV T5.X, PV.W,3899; CM-NEXT: MOV * T0.Y, T7.X,3900; CM-NEXT: ALU clause starting at 82:3901; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x,3902; CM-NEXT: LSHL * T0.W, T12.X, literal.y,3903; CM-NEXT: 65535(9.183409e-41), 16(2.242078e-44)3904; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W,3905; CM-NEXT: MOV T7.X, PV.W,3906; CM-NEXT: MOV * T0.Y, T9.X,3907; CM-NEXT: ALU clause starting at 88:3908; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x,3909; CM-NEXT: LSHL * T0.W, T12.X, literal.y,3910; CM-NEXT: 65535(9.183409e-41), 16(2.242078e-44)3911; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W,3912; CM-NEXT: MOV T9.X, PV.W,3913; CM-NEXT: MOV * T0.Y, T3.X,3914; CM-NEXT: ALU clause starting at 94:3915; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x,3916; CM-NEXT: AND_INT * T0.W, T12.X, literal.y,3917; CM-NEXT: -65536(nan), 65535(9.183409e-41)3918; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W,3919; CM-NEXT: MOV T3.X, PV.W,3920; CM-NEXT: MOV * T0.Y, T5.X,3921; CM-NEXT: ALU clause starting at 100:3922; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x,3923; CM-NEXT: AND_INT * T0.W, T12.X, literal.y,3924; CM-NEXT: -65536(nan), 65535(9.183409e-41)3925; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W,3926; CM-NEXT: MOV T5.X, PV.W,3927; CM-NEXT: MOV * T0.Y, T7.X,3928; CM-NEXT: ALU clause starting at 106:3929; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x,3930; CM-NEXT: AND_INT * T0.W, T12.X, literal.y,3931; CM-NEXT: -65536(nan), 65535(9.183409e-41)3932; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W,3933; CM-NEXT: MOV T7.X, PV.W,3934; CM-NEXT: MOV * T0.Y, T9.X,3935; CM-NEXT: ALU clause starting at 112:3936; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x,3937; CM-NEXT: AND_INT * T0.W, T12.X, literal.y,3938; CM-NEXT: -65536(nan), 65535(9.183409e-41)3939; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W,3940; CM-NEXT: MOV T9.X, PV.W,3941; CM-NEXT: MOV * T0.Y, T2.X,3942; CM-NEXT: ALU clause starting at 118:3943; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x,3944; CM-NEXT: LSHL * T0.W, T12.X, literal.y,3945; CM-NEXT: 65535(9.183409e-41), 16(2.242078e-44)3946; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W,3947; CM-NEXT: MOV T2.X, PV.W,3948; CM-NEXT: MOV * T0.Y, T4.X,3949; CM-NEXT: ALU clause starting at 124:3950; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x,3951; CM-NEXT: LSHL * T0.W, T12.X, literal.y,3952; CM-NEXT: 65535(9.183409e-41), 16(2.242078e-44)3953; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W,3954; CM-NEXT: MOV T4.X, PV.W,3955; CM-NEXT: MOV * T0.Y, T6.X,3956; CM-NEXT: ALU clause starting at 130:3957; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x,3958; CM-NEXT: LSHL * T0.W, T12.X, literal.y,3959; CM-NEXT: 65535(9.183409e-41), 16(2.242078e-44)3960; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W,3961; CM-NEXT: MOV T6.X, PV.W,3962; CM-NEXT: MOV * T0.Y, T8.X,3963; CM-NEXT: ALU clause starting at 136:3964; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x,3965; CM-NEXT: LSHL * T0.W, T12.X, literal.y,3966; CM-NEXT: 65535(9.183409e-41), 16(2.242078e-44)3967; CM-NEXT: OR_INT * T0.W, PV.Z, PV.W,3968; CM-NEXT: MOV T8.X, PV.W,3969; CM-NEXT: MOV * T0.Y, T2.X,3970; CM-NEXT: ALU clause starting at 142:3971; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x,3972; CM-NEXT: AND_INT * T0.W, T12.X, literal.y,3973; CM-NEXT: -65536(nan), 65535(9.183409e-41)3974; CM-NEXT: OR_INT * T12.Z, PV.Z, PV.W,3975; CM-NEXT: MOV T2.X, PV.Z,3976; CM-NEXT: MOV * T0.Y, T4.X,3977; CM-NEXT: ALU clause starting at 148:3978; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x,3979; CM-NEXT: AND_INT * T0.W, T12.X, literal.y,3980; CM-NEXT: -65536(nan), 65535(9.183409e-41)3981; CM-NEXT: OR_INT * T12.X, PV.Z, PV.W,3982; CM-NEXT: MOV T4.X, PV.X,3983; CM-NEXT: MOV * T0.Y, T6.X,3984; CM-NEXT: ALU clause starting at 154:3985; CM-NEXT: AND_INT T0.Z, T0.Y, literal.x,3986; CM-NEXT: AND_INT * T0.W, T13.X, literal.y,3987; CM-NEXT: -65536(nan), 65535(9.183409e-41)3988; CM-NEXT: OR_INT * T11.Z, PV.Z, PV.W,3989; CM-NEXT: MOV T6.X, PV.Z,3990; CM-NEXT: MOV * T0.Y, T8.X,3991; CM-NEXT: ALU clause starting at 160:3992; CM-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x,3993; CM-NEXT: 16(2.242078e-44), 0(0.000000e+00)3994; CM-NEXT: LSHR * T13.X, PV.W, literal.x,3995; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)3996; CM-NEXT: LSHR T14.X, KC0[2].Y, literal.x,3997; CM-NEXT: AND_INT T0.Z, T0.Y, literal.y,3998; CM-NEXT: AND_INT * T0.W, T11.X, literal.z,3999; CM-NEXT: 2(2.802597e-45), -65536(nan)4000; CM-NEXT: 65535(9.183409e-41), 0(0.000000e+00)4001; CM-NEXT: OR_INT * T11.X, PV.Z, PV.W,4002; CM-NEXT: MOV T8.X, PV.X,4003; CM-NEXT: MOV * T12.W, T3.X,4004; CM-NEXT: MOV T12.Y, T5.X,4005; CM-NEXT: MOV * T11.W, T7.X, BS:VEC_120/SCL_2124006; CM-NEXT: MOV * T11.Y, T9.X,4007entry:4008 store <16 x i16> %in, ptr addrspace(1) %out4009 ret void4010}4011 4012define amdgpu_kernel void @v16i32_arg(ptr addrspace(1) nocapture %out, <16 x i32> %in) nounwind {4013; SI-LABEL: v16i32_arg:4014; SI: ; %bb.0: ; %entry4015; SI-NEXT: s_load_dwordx16 s[8:23], s[4:5], 0x194016; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x94017; SI-NEXT: s_mov_b32 s3, 0xf0004018; SI-NEXT: s_mov_b32 s2, -14019; SI-NEXT: s_waitcnt lgkmcnt(0)4020; SI-NEXT: v_mov_b32_e32 v0, s204021; SI-NEXT: v_mov_b32_e32 v1, s214022; SI-NEXT: v_mov_b32_e32 v2, s224023; SI-NEXT: v_mov_b32_e32 v3, s234024; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:484025; SI-NEXT: s_waitcnt expcnt(0)4026; SI-NEXT: v_mov_b32_e32 v0, s164027; SI-NEXT: v_mov_b32_e32 v1, s174028; SI-NEXT: v_mov_b32_e32 v2, s184029; SI-NEXT: v_mov_b32_e32 v3, s194030; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:324031; SI-NEXT: s_waitcnt expcnt(0)4032; SI-NEXT: v_mov_b32_e32 v0, s124033; SI-NEXT: v_mov_b32_e32 v1, s134034; SI-NEXT: v_mov_b32_e32 v2, s144035; SI-NEXT: v_mov_b32_e32 v3, s154036; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:164037; SI-NEXT: s_waitcnt expcnt(0)4038; SI-NEXT: v_mov_b32_e32 v0, s84039; SI-NEXT: v_mov_b32_e32 v1, s94040; SI-NEXT: v_mov_b32_e32 v2, s104041; SI-NEXT: v_mov_b32_e32 v3, s114042; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 04043; SI-NEXT: s_endpgm4044;4045; VI-LABEL: v16i32_arg:4046; VI: ; %bb.0: ; %entry4047; VI-NEXT: s_load_dwordx16 s[8:23], s[4:5], 0x644048; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x244049; VI-NEXT: s_waitcnt lgkmcnt(0)4050; VI-NEXT: v_mov_b32_e32 v0, s204051; VI-NEXT: s_add_u32 s2, s0, 484052; VI-NEXT: s_addc_u32 s3, s1, 04053; VI-NEXT: v_mov_b32_e32 v5, s34054; VI-NEXT: v_mov_b32_e32 v4, s24055; VI-NEXT: s_add_u32 s2, s0, 324056; VI-NEXT: v_mov_b32_e32 v1, s214057; VI-NEXT: v_mov_b32_e32 v2, s224058; VI-NEXT: v_mov_b32_e32 v3, s234059; VI-NEXT: s_addc_u32 s3, s1, 04060; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]4061; VI-NEXT: v_mov_b32_e32 v5, s34062; VI-NEXT: v_mov_b32_e32 v4, s24063; VI-NEXT: s_add_u32 s2, s0, 164064; VI-NEXT: v_mov_b32_e32 v0, s164065; VI-NEXT: v_mov_b32_e32 v1, s174066; VI-NEXT: v_mov_b32_e32 v2, s184067; VI-NEXT: v_mov_b32_e32 v3, s194068; VI-NEXT: s_addc_u32 s3, s1, 04069; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]4070; VI-NEXT: v_mov_b32_e32 v5, s34071; VI-NEXT: v_mov_b32_e32 v0, s124072; VI-NEXT: v_mov_b32_e32 v1, s134073; VI-NEXT: v_mov_b32_e32 v2, s144074; VI-NEXT: v_mov_b32_e32 v3, s154075; VI-NEXT: v_mov_b32_e32 v4, s24076; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]4077; VI-NEXT: v_mov_b32_e32 v5, s14078; VI-NEXT: v_mov_b32_e32 v0, s84079; VI-NEXT: v_mov_b32_e32 v1, s94080; VI-NEXT: v_mov_b32_e32 v2, s104081; VI-NEXT: v_mov_b32_e32 v3, s114082; VI-NEXT: v_mov_b32_e32 v4, s04083; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]4084; VI-NEXT: s_endpgm4085;4086; GFX9-LABEL: v16i32_arg:4087; GFX9: ; %bb.0: ; %entry4088; GFX9-NEXT: s_load_dwordx16 s[12:27], s[8:9], 0x404089; GFX9-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x04090; GFX9-NEXT: v_mov_b32_e32 v4, 04091; GFX9-NEXT: s_waitcnt lgkmcnt(0)4092; GFX9-NEXT: v_mov_b32_e32 v0, s244093; GFX9-NEXT: v_mov_b32_e32 v1, s254094; GFX9-NEXT: v_mov_b32_e32 v2, s264095; GFX9-NEXT: v_mov_b32_e32 v3, s274096; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1] offset:484097; GFX9-NEXT: s_nop 04098; GFX9-NEXT: v_mov_b32_e32 v0, s204099; GFX9-NEXT: v_mov_b32_e32 v1, s214100; GFX9-NEXT: v_mov_b32_e32 v2, s224101; GFX9-NEXT: v_mov_b32_e32 v3, s234102; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1] offset:324103; GFX9-NEXT: s_nop 04104; GFX9-NEXT: v_mov_b32_e32 v0, s164105; GFX9-NEXT: v_mov_b32_e32 v1, s174106; GFX9-NEXT: v_mov_b32_e32 v2, s184107; GFX9-NEXT: v_mov_b32_e32 v3, s194108; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1] offset:164109; GFX9-NEXT: s_nop 04110; GFX9-NEXT: v_mov_b32_e32 v0, s124111; GFX9-NEXT: v_mov_b32_e32 v1, s134112; GFX9-NEXT: v_mov_b32_e32 v2, s144113; GFX9-NEXT: v_mov_b32_e32 v3, s154114; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]4115; GFX9-NEXT: s_endpgm4116;4117; EG-LABEL: v16i32_arg:4118; EG: ; %bb.0: ; %entry4119; EG-NEXT: ALU 29, @6, KC0[CB0:0-32], KC1[]4120; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T5.XYZW, T7.X, 04121; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T3.XYZW, T6.X, 04122; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XYZW, T4.X, 04123; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T2.X, 14124; EG-NEXT: CF_END4125; EG-NEXT: ALU clause starting at 6:4126; EG-NEXT: MOV * T0.W, KC0[7].X,4127; EG-NEXT: MOV * T0.Z, KC0[6].W,4128; EG-NEXT: MOV T0.Y, KC0[6].Z,4129; EG-NEXT: MOV * T1.W, KC0[8].X,4130; EG-NEXT: MOV T0.X, KC0[6].Y,4131; EG-NEXT: MOV * T1.Z, KC0[7].W,4132; EG-NEXT: LSHR T2.X, KC0[2].Y, literal.x,4133; EG-NEXT: MOV * T1.Y, KC0[7].Z,4134; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)4135; EG-NEXT: MOV * T3.W, KC0[9].X,4136; EG-NEXT: MOV T1.X, KC0[7].Y,4137; EG-NEXT: MOV * T3.Z, KC0[8].W,4138; EG-NEXT: ADD_INT * T2.W, KC0[2].Y, literal.x,4139; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)4140; EG-NEXT: LSHR T4.X, PV.W, literal.x,4141; EG-NEXT: MOV T3.Y, KC0[8].Z,4142; EG-NEXT: MOV * T5.W, KC0[10].X,4143; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)4144; EG-NEXT: MOV T3.X, KC0[8].Y,4145; EG-NEXT: MOV * T5.Z, KC0[9].W,4146; EG-NEXT: ADD_INT * T2.W, KC0[2].Y, literal.x,4147; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)4148; EG-NEXT: LSHR T6.X, PV.W, literal.x,4149; EG-NEXT: MOV T5.Y, KC0[9].Z,4150; EG-NEXT: MOV * T5.X, KC0[9].Y,4151; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)4152; EG-NEXT: ADD_INT * T2.W, KC0[2].Y, literal.x,4153; EG-NEXT: 48(6.726233e-44), 0(0.000000e+00)4154; EG-NEXT: LSHR * T7.X, PV.W, literal.x,4155; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)4156;4157; CM-LABEL: v16i32_arg:4158; CM: ; %bb.0: ; %entry4159; CM-NEXT: ALU 28, @6, KC0[CB0:0-32], KC1[]4160; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T4, T7.X4161; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1, T6.X4162; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T2, T5.X4163; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0, T3.X4164; CM-NEXT: CF_END4165; CM-NEXT: ALU clause starting at 6:4166; CM-NEXT: MOV * T0.W, KC0[10].X,4167; CM-NEXT: MOV * T0.Z, KC0[9].W,4168; CM-NEXT: MOV * T0.Y, KC0[9].Z,4169; CM-NEXT: MOV T0.X, KC0[9].Y,4170; CM-NEXT: ADD_INT T1.Z, KC0[2].Y, literal.x,4171; CM-NEXT: MOV * T2.W, KC0[9].X,4172; CM-NEXT: 48(6.726233e-44), 0(0.000000e+00)4173; CM-NEXT: MOV T2.Z, KC0[8].W,4174; CM-NEXT: MOV * T1.W, KC0[8].X,4175; CM-NEXT: LSHR T3.X, T1.Z, literal.x,4176; CM-NEXT: MOV T2.Y, KC0[8].Z,4177; CM-NEXT: MOV * T1.Z, KC0[7].W,4178; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)4179; CM-NEXT: MOV T2.X, KC0[8].Y,4180; CM-NEXT: MOV * T1.Y, KC0[7].Z,4181; CM-NEXT: MOV T1.X, KC0[7].Y,4182; CM-NEXT: ADD_INT T3.Z, KC0[2].Y, literal.x,4183; CM-NEXT: MOV * T4.W, KC0[7].X,4184; CM-NEXT: 32(4.484155e-44), 0(0.000000e+00)4185; CM-NEXT: LSHR T5.X, PV.Z, literal.x,4186; CM-NEXT: MOV T4.Z, KC0[6].W,4187; CM-NEXT: ADD_INT * T3.W, KC0[2].Y, literal.y,4188; CM-NEXT: 2(2.802597e-45), 16(2.242078e-44)4189; CM-NEXT: LSHR T6.X, PV.W, literal.x,4190; CM-NEXT: MOV * T4.Y, KC0[6].Z,4191; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)4192; CM-NEXT: MOV * T4.X, KC0[6].Y,4193; CM-NEXT: LSHR * T7.X, KC0[2].Y, literal.x,4194; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)4195entry:4196 store <16 x i32> %in, ptr addrspace(1) %out, align 44197 ret void4198}4199 4200define amdgpu_kernel void @v16f32_arg(ptr addrspace(1) nocapture %out, <16 x float> %in) nounwind {4201; SI-LABEL: v16f32_arg:4202; SI: ; %bb.0: ; %entry4203; SI-NEXT: s_load_dwordx16 s[8:23], s[4:5], 0x194204; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x94205; SI-NEXT: s_mov_b32 s3, 0xf0004206; SI-NEXT: s_mov_b32 s2, -14207; SI-NEXT: s_waitcnt lgkmcnt(0)4208; SI-NEXT: v_mov_b32_e32 v0, s204209; SI-NEXT: v_mov_b32_e32 v1, s214210; SI-NEXT: v_mov_b32_e32 v2, s224211; SI-NEXT: v_mov_b32_e32 v3, s234212; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:484213; SI-NEXT: s_waitcnt expcnt(0)4214; SI-NEXT: v_mov_b32_e32 v0, s164215; SI-NEXT: v_mov_b32_e32 v1, s174216; SI-NEXT: v_mov_b32_e32 v2, s184217; SI-NEXT: v_mov_b32_e32 v3, s194218; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:324219; SI-NEXT: s_waitcnt expcnt(0)4220; SI-NEXT: v_mov_b32_e32 v0, s124221; SI-NEXT: v_mov_b32_e32 v1, s134222; SI-NEXT: v_mov_b32_e32 v2, s144223; SI-NEXT: v_mov_b32_e32 v3, s154224; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:164225; SI-NEXT: s_waitcnt expcnt(0)4226; SI-NEXT: v_mov_b32_e32 v0, s84227; SI-NEXT: v_mov_b32_e32 v1, s94228; SI-NEXT: v_mov_b32_e32 v2, s104229; SI-NEXT: v_mov_b32_e32 v3, s114230; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 04231; SI-NEXT: s_endpgm4232;4233; VI-LABEL: v16f32_arg:4234; VI: ; %bb.0: ; %entry4235; VI-NEXT: s_load_dwordx16 s[8:23], s[4:5], 0x644236; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x244237; VI-NEXT: s_waitcnt lgkmcnt(0)4238; VI-NEXT: v_mov_b32_e32 v0, s204239; VI-NEXT: s_add_u32 s2, s0, 484240; VI-NEXT: s_addc_u32 s3, s1, 04241; VI-NEXT: v_mov_b32_e32 v5, s34242; VI-NEXT: v_mov_b32_e32 v4, s24243; VI-NEXT: s_add_u32 s2, s0, 324244; VI-NEXT: v_mov_b32_e32 v1, s214245; VI-NEXT: v_mov_b32_e32 v2, s224246; VI-NEXT: v_mov_b32_e32 v3, s234247; VI-NEXT: s_addc_u32 s3, s1, 04248; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]4249; VI-NEXT: v_mov_b32_e32 v5, s34250; VI-NEXT: v_mov_b32_e32 v4, s24251; VI-NEXT: s_add_u32 s2, s0, 164252; VI-NEXT: v_mov_b32_e32 v0, s164253; VI-NEXT: v_mov_b32_e32 v1, s174254; VI-NEXT: v_mov_b32_e32 v2, s184255; VI-NEXT: v_mov_b32_e32 v3, s194256; VI-NEXT: s_addc_u32 s3, s1, 04257; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]4258; VI-NEXT: v_mov_b32_e32 v5, s34259; VI-NEXT: v_mov_b32_e32 v0, s124260; VI-NEXT: v_mov_b32_e32 v1, s134261; VI-NEXT: v_mov_b32_e32 v2, s144262; VI-NEXT: v_mov_b32_e32 v3, s154263; VI-NEXT: v_mov_b32_e32 v4, s24264; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]4265; VI-NEXT: v_mov_b32_e32 v5, s14266; VI-NEXT: v_mov_b32_e32 v0, s84267; VI-NEXT: v_mov_b32_e32 v1, s94268; VI-NEXT: v_mov_b32_e32 v2, s104269; VI-NEXT: v_mov_b32_e32 v3, s114270; VI-NEXT: v_mov_b32_e32 v4, s04271; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]4272; VI-NEXT: s_endpgm4273;4274; GFX9-LABEL: v16f32_arg:4275; GFX9: ; %bb.0: ; %entry4276; GFX9-NEXT: s_load_dwordx16 s[12:27], s[8:9], 0x404277; GFX9-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x04278; GFX9-NEXT: v_mov_b32_e32 v4, 04279; GFX9-NEXT: s_waitcnt lgkmcnt(0)4280; GFX9-NEXT: v_mov_b32_e32 v0, s244281; GFX9-NEXT: v_mov_b32_e32 v1, s254282; GFX9-NEXT: v_mov_b32_e32 v2, s264283; GFX9-NEXT: v_mov_b32_e32 v3, s274284; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1] offset:484285; GFX9-NEXT: s_nop 04286; GFX9-NEXT: v_mov_b32_e32 v0, s204287; GFX9-NEXT: v_mov_b32_e32 v1, s214288; GFX9-NEXT: v_mov_b32_e32 v2, s224289; GFX9-NEXT: v_mov_b32_e32 v3, s234290; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1] offset:324291; GFX9-NEXT: s_nop 04292; GFX9-NEXT: v_mov_b32_e32 v0, s164293; GFX9-NEXT: v_mov_b32_e32 v1, s174294; GFX9-NEXT: v_mov_b32_e32 v2, s184295; GFX9-NEXT: v_mov_b32_e32 v3, s194296; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1] offset:164297; GFX9-NEXT: s_nop 04298; GFX9-NEXT: v_mov_b32_e32 v0, s124299; GFX9-NEXT: v_mov_b32_e32 v1, s134300; GFX9-NEXT: v_mov_b32_e32 v2, s144301; GFX9-NEXT: v_mov_b32_e32 v3, s154302; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]4303; GFX9-NEXT: s_endpgm4304;4305; EG-LABEL: v16f32_arg:4306; EG: ; %bb.0: ; %entry4307; EG-NEXT: ALU 29, @6, KC0[CB0:0-32], KC1[]4308; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T5.XYZW, T7.X, 04309; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T3.XYZW, T6.X, 04310; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XYZW, T4.X, 04311; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T2.X, 14312; EG-NEXT: CF_END4313; EG-NEXT: ALU clause starting at 6:4314; EG-NEXT: MOV * T0.W, KC0[7].X,4315; EG-NEXT: MOV * T0.Z, KC0[6].W,4316; EG-NEXT: MOV T0.Y, KC0[6].Z,4317; EG-NEXT: MOV * T1.W, KC0[8].X,4318; EG-NEXT: MOV T0.X, KC0[6].Y,4319; EG-NEXT: MOV * T1.Z, KC0[7].W,4320; EG-NEXT: LSHR T2.X, KC0[2].Y, literal.x,4321; EG-NEXT: MOV * T1.Y, KC0[7].Z,4322; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)4323; EG-NEXT: MOV * T3.W, KC0[9].X,4324; EG-NEXT: MOV T1.X, KC0[7].Y,4325; EG-NEXT: MOV * T3.Z, KC0[8].W,4326; EG-NEXT: ADD_INT * T2.W, KC0[2].Y, literal.x,4327; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)4328; EG-NEXT: LSHR T4.X, PV.W, literal.x,4329; EG-NEXT: MOV T3.Y, KC0[8].Z,4330; EG-NEXT: MOV * T5.W, KC0[10].X,4331; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)4332; EG-NEXT: MOV T3.X, KC0[8].Y,4333; EG-NEXT: MOV * T5.Z, KC0[9].W,4334; EG-NEXT: ADD_INT * T2.W, KC0[2].Y, literal.x,4335; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)4336; EG-NEXT: LSHR T6.X, PV.W, literal.x,4337; EG-NEXT: MOV T5.Y, KC0[9].Z,4338; EG-NEXT: MOV * T5.X, KC0[9].Y,4339; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)4340; EG-NEXT: ADD_INT * T2.W, KC0[2].Y, literal.x,4341; EG-NEXT: 48(6.726233e-44), 0(0.000000e+00)4342; EG-NEXT: LSHR * T7.X, PV.W, literal.x,4343; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)4344;4345; CM-LABEL: v16f32_arg:4346; CM: ; %bb.0: ; %entry4347; CM-NEXT: ALU 28, @6, KC0[CB0:0-32], KC1[]4348; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T4, T7.X4349; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1, T6.X4350; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T2, T5.X4351; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0, T3.X4352; CM-NEXT: CF_END4353; CM-NEXT: ALU clause starting at 6:4354; CM-NEXT: MOV * T0.W, KC0[10].X,4355; CM-NEXT: MOV * T0.Z, KC0[9].W,4356; CM-NEXT: MOV * T0.Y, KC0[9].Z,4357; CM-NEXT: MOV T0.X, KC0[9].Y,4358; CM-NEXT: ADD_INT T1.Z, KC0[2].Y, literal.x,4359; CM-NEXT: MOV * T2.W, KC0[9].X,4360; CM-NEXT: 48(6.726233e-44), 0(0.000000e+00)4361; CM-NEXT: MOV T2.Z, KC0[8].W,4362; CM-NEXT: MOV * T1.W, KC0[8].X,4363; CM-NEXT: LSHR T3.X, T1.Z, literal.x,4364; CM-NEXT: MOV T2.Y, KC0[8].Z,4365; CM-NEXT: MOV * T1.Z, KC0[7].W,4366; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)4367; CM-NEXT: MOV T2.X, KC0[8].Y,4368; CM-NEXT: MOV * T1.Y, KC0[7].Z,4369; CM-NEXT: MOV T1.X, KC0[7].Y,4370; CM-NEXT: ADD_INT T3.Z, KC0[2].Y, literal.x,4371; CM-NEXT: MOV * T4.W, KC0[7].X,4372; CM-NEXT: 32(4.484155e-44), 0(0.000000e+00)4373; CM-NEXT: LSHR T5.X, PV.Z, literal.x,4374; CM-NEXT: MOV T4.Z, KC0[6].W,4375; CM-NEXT: ADD_INT * T3.W, KC0[2].Y, literal.y,4376; CM-NEXT: 2(2.802597e-45), 16(2.242078e-44)4377; CM-NEXT: LSHR T6.X, PV.W, literal.x,4378; CM-NEXT: MOV * T4.Y, KC0[6].Z,4379; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)4380; CM-NEXT: MOV * T4.X, KC0[6].Y,4381; CM-NEXT: LSHR * T7.X, KC0[2].Y, literal.x,4382; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)4383entry:4384 store <16 x float> %in, ptr addrspace(1) %out, align 44385 ret void4386}4387 4388define amdgpu_kernel void @kernel_arg_i64(ptr addrspace(1) %out, i64 %a) nounwind {4389; SI-LABEL: kernel_arg_i64:4390; SI: ; %bb.0:4391; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x94392; SI-NEXT: s_mov_b32 s7, 0xf0004393; SI-NEXT: s_mov_b32 s6, -14394; SI-NEXT: s_waitcnt lgkmcnt(0)4395; SI-NEXT: s_mov_b32 s4, s04396; SI-NEXT: s_mov_b32 s5, s14397; SI-NEXT: v_mov_b32_e32 v0, s24398; SI-NEXT: v_mov_b32_e32 v1, s34399; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 04400; SI-NEXT: s_endpgm4401;4402; VI-LABEL: kernel_arg_i64:4403; VI: ; %bb.0:4404; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x244405; VI-NEXT: s_waitcnt lgkmcnt(0)4406; VI-NEXT: v_mov_b32_e32 v0, s04407; VI-NEXT: v_mov_b32_e32 v1, s14408; VI-NEXT: v_mov_b32_e32 v2, s24409; VI-NEXT: v_mov_b32_e32 v3, s34410; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]4411; VI-NEXT: s_endpgm4412;4413; GFX9-LABEL: kernel_arg_i64:4414; GFX9: ; %bb.0:4415; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x04416; GFX9-NEXT: v_mov_b32_e32 v2, 04417; GFX9-NEXT: s_waitcnt lgkmcnt(0)4418; GFX9-NEXT: v_mov_b32_e32 v0, s24419; GFX9-NEXT: v_mov_b32_e32 v1, s34420; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]4421; GFX9-NEXT: s_endpgm4422;4423; EG-LABEL: kernel_arg_i64:4424; EG: ; %bb.0:4425; EG-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[]4426; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 14427; EG-NEXT: CF_END4428; EG-NEXT: PAD4429; EG-NEXT: ALU clause starting at 4:4430; EG-NEXT: MOV * T0.Y, KC0[3].X,4431; EG-NEXT: MOV T0.X, KC0[2].W,4432; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,4433; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)4434;4435; CM-LABEL: kernel_arg_i64:4436; CM: ; %bb.0:4437; CM-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[]4438; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0, T1.X4439; CM-NEXT: CF_END4440; CM-NEXT: PAD4441; CM-NEXT: ALU clause starting at 4:4442; CM-NEXT: MOV * T0.Y, KC0[3].X,4443; CM-NEXT: MOV * T0.X, KC0[2].W,4444; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,4445; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)4446 store i64 %a, ptr addrspace(1) %out, align 84447 ret void4448}4449 4450define amdgpu_kernel void @f64_kernel_arg(ptr addrspace(1) %out, double %in) {4451; SI-LABEL: f64_kernel_arg:4452; SI: ; %bb.0: ; %entry4453; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x94454; SI-NEXT: s_mov_b32 s7, 0xf0004455; SI-NEXT: s_mov_b32 s6, -14456; SI-NEXT: s_waitcnt lgkmcnt(0)4457; SI-NEXT: s_mov_b32 s4, s04458; SI-NEXT: s_mov_b32 s5, s14459; SI-NEXT: v_mov_b32_e32 v0, s24460; SI-NEXT: v_mov_b32_e32 v1, s34461; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 04462; SI-NEXT: s_endpgm4463;4464; VI-LABEL: f64_kernel_arg:4465; VI: ; %bb.0: ; %entry4466; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x244467; VI-NEXT: s_waitcnt lgkmcnt(0)4468; VI-NEXT: v_mov_b32_e32 v0, s04469; VI-NEXT: v_mov_b32_e32 v1, s14470; VI-NEXT: v_mov_b32_e32 v2, s24471; VI-NEXT: v_mov_b32_e32 v3, s34472; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]4473; VI-NEXT: s_endpgm4474;4475; GFX9-LABEL: f64_kernel_arg:4476; GFX9: ; %bb.0: ; %entry4477; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x04478; GFX9-NEXT: v_mov_b32_e32 v2, 04479; GFX9-NEXT: s_waitcnt lgkmcnt(0)4480; GFX9-NEXT: v_mov_b32_e32 v0, s24481; GFX9-NEXT: v_mov_b32_e32 v1, s34482; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]4483; GFX9-NEXT: s_endpgm4484;4485; EG-LABEL: f64_kernel_arg:4486; EG: ; %bb.0: ; %entry4487; EG-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[]4488; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 14489; EG-NEXT: CF_END4490; EG-NEXT: PAD4491; EG-NEXT: ALU clause starting at 4:4492; EG-NEXT: MOV * T0.Y, KC0[3].X,4493; EG-NEXT: MOV T0.X, KC0[2].W,4494; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,4495; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)4496;4497; CM-LABEL: f64_kernel_arg:4498; CM: ; %bb.0: ; %entry4499; CM-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[]4500; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0, T1.X4501; CM-NEXT: CF_END4502; CM-NEXT: PAD4503; CM-NEXT: ALU clause starting at 4:4504; CM-NEXT: MOV * T0.Y, KC0[3].X,4505; CM-NEXT: MOV * T0.X, KC0[2].W,4506; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,4507; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)4508entry:4509 store double %in, ptr addrspace(1) %out4510 ret void4511}4512 4513; XFUNC-LABEL: {{^}}kernel_arg_v1i64:4514; XGCN: s_load_dwordx24515; XGCN: s_load_dwordx24516; XGCN: buffer_store_dwordx24517; define amdgpu_kernel void @kernel_arg_v1i64(ptr addrspace(1) %out, <1 x i64> %a) nounwind {4518; store <1 x i64> %a, ptr addrspace(1) %out, align 84519; ret void4520; }4521 4522define amdgpu_kernel void @i65_arg(ptr addrspace(1) nocapture %out, i65 %in) nounwind {4523; SI-LABEL: i65_arg:4524; SI: ; %bb.0: ; %entry4525; SI-NEXT: s_load_dword s6, s[4:5], 0xd4526; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x94527; SI-NEXT: s_mov_b32 s7, 0xf0004528; SI-NEXT: s_waitcnt lgkmcnt(0)4529; SI-NEXT: s_and_b32 s8, s6, 14530; SI-NEXT: s_mov_b32 s6, -14531; SI-NEXT: s_mov_b32 s4, s04532; SI-NEXT: s_mov_b32 s5, s14533; SI-NEXT: v_mov_b32_e32 v0, s24534; SI-NEXT: v_mov_b32_e32 v1, s34535; SI-NEXT: v_mov_b32_e32 v2, s84536; SI-NEXT: buffer_store_byte v2, off, s[4:7], 0 offset:84537; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 04538; SI-NEXT: s_endpgm4539;4540; VI-LABEL: i65_arg:4541; VI: ; %bb.0: ; %entry4542; VI-NEXT: s_load_dword s6, s[4:5], 0x344543; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x244544; VI-NEXT: s_waitcnt lgkmcnt(0)4545; VI-NEXT: s_and_b32 s4, s6, 14546; VI-NEXT: v_mov_b32_e32 v0, s04547; VI-NEXT: v_mov_b32_e32 v1, s14548; VI-NEXT: s_add_u32 s0, s0, 84549; VI-NEXT: s_addc_u32 s1, s1, 04550; VI-NEXT: v_mov_b32_e32 v5, s14551; VI-NEXT: v_mov_b32_e32 v2, s24552; VI-NEXT: v_mov_b32_e32 v6, s44553; VI-NEXT: v_mov_b32_e32 v4, s04554; VI-NEXT: v_mov_b32_e32 v3, s34555; VI-NEXT: flat_store_byte v[4:5], v64556; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]4557; VI-NEXT: s_endpgm4558;4559; GFX9-LABEL: i65_arg:4560; GFX9: ; %bb.0: ; %entry4561; GFX9-NEXT: s_load_dword s4, s[8:9], 0x104562; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x04563; GFX9-NEXT: v_mov_b32_e32 v2, 04564; GFX9-NEXT: s_waitcnt lgkmcnt(0)4565; GFX9-NEXT: s_and_b32 s4, s4, 14566; GFX9-NEXT: v_mov_b32_e32 v0, s24567; GFX9-NEXT: v_mov_b32_e32 v3, s44568; GFX9-NEXT: v_mov_b32_e32 v1, s34569; GFX9-NEXT: global_store_byte v2, v3, s[0:1] offset:84570; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]4571; GFX9-NEXT: s_endpgm4572;4573; EG-LABEL: i65_arg:4574; EG: ; %bb.0: ; %entry4575; EG-NEXT: ALU 20, @6, KC0[CB0:0-32], KC1[]4576; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T5.X, T4.X, 04577; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T3.X, T2.X, 04578; EG-NEXT: MEM_RAT MSKOR T1.XW, T0.X4579; EG-NEXT: CF_END4580; EG-NEXT: PAD4581; EG-NEXT: ALU clause starting at 6:4582; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x,4583; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)4584; EG-NEXT: AND_INT * T1.W, PV.W, literal.x,4585; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)4586; EG-NEXT: LSHL T1.W, PV.W, literal.x,4587; EG-NEXT: AND_INT * T2.W, KC0[3].Y, 1,4588; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)4589; EG-NEXT: LSHL T1.X, PS, PV.W,4590; EG-NEXT: LSHL * T1.W, literal.x, PV.W,4591; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00)4592; EG-NEXT: MOV T1.Y, 0.0,4593; EG-NEXT: MOV * T1.Z, 0.0,4594; EG-NEXT: LSHR T0.X, T0.W, literal.x,4595; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,4596; EG-NEXT: 2(2.802597e-45), 4(5.605194e-45)4597; EG-NEXT: LSHR T2.X, PV.W, literal.x,4598; EG-NEXT: MOV * T3.X, KC0[3].X,4599; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)4600; EG-NEXT: LSHR T4.X, KC0[2].Y, literal.x,4601; EG-NEXT: MOV * T5.X, KC0[2].W,4602; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)4603;4604; CM-LABEL: i65_arg:4605; CM: ; %bb.0: ; %entry4606; CM-NEXT: ALU 21, @6, KC0[CB0:0-32], KC1[]4607; CM-NEXT: MEM_RAT MSKOR T1.XW, T5.X4608; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T4.X, T3.X4609; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T2.X, T0.X4610; CM-NEXT: CF_END4611; CM-NEXT: PAD4612; CM-NEXT: ALU clause starting at 6:4613; CM-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x,4614; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00)4615; CM-NEXT: AND_INT * T1.W, PV.W, literal.x,4616; CM-NEXT: 3(4.203895e-45), 0(0.000000e+00)4617; CM-NEXT: LSHL T0.Z, PV.W, literal.x,4618; CM-NEXT: AND_INT * T1.W, KC0[3].Y, 1,4619; CM-NEXT: 3(4.203895e-45), 0(0.000000e+00)4620; CM-NEXT: LSHL T1.X, PV.W, PV.Z,4621; CM-NEXT: LSHL * T1.W, literal.x, PV.Z,4622; CM-NEXT: 255(3.573311e-43), 0(0.000000e+00)4623; CM-NEXT: MOV T1.Y, 0.0,4624; CM-NEXT: MOV * T1.Z, 0.0,4625; CM-NEXT: LSHR * T0.X, KC0[2].Y, literal.x,4626; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)4627; CM-NEXT: MOV T2.X, KC0[2].W,4628; CM-NEXT: ADD_INT * T2.W, KC0[2].Y, literal.x,4629; CM-NEXT: 4(5.605194e-45), 0(0.000000e+00)4630; CM-NEXT: LSHR * T3.X, PV.W, literal.x,4631; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)4632; CM-NEXT: MOV * T4.X, KC0[3].X,4633; CM-NEXT: LSHR * T5.X, T0.W, literal.x,4634; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)4635entry:4636 store i65 %in, ptr addrspace(1) %out, align 44637 ret void4638}4639 4640define amdgpu_kernel void @i1_arg(ptr addrspace(1) %out, i1 %x) nounwind {4641; SI-LABEL: i1_arg:4642; SI: ; %bb.0:4643; SI-NEXT: s_load_dword s2, s[4:5], 0xb4644; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x94645; SI-NEXT: s_mov_b32 s3, 0xf0004646; SI-NEXT: s_waitcnt lgkmcnt(0)4647; SI-NEXT: s_and_b32 s4, s2, 14648; SI-NEXT: s_mov_b32 s2, -14649; SI-NEXT: v_mov_b32_e32 v0, s44650; SI-NEXT: buffer_store_byte v0, off, s[0:3], 04651; SI-NEXT: s_endpgm4652;4653; VI-LABEL: i1_arg:4654; VI: ; %bb.0:4655; VI-NEXT: s_load_dword s2, s[4:5], 0x2c4656; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x244657; VI-NEXT: s_waitcnt lgkmcnt(0)4658; VI-NEXT: s_and_b32 s2, s2, 14659; VI-NEXT: v_mov_b32_e32 v0, s04660; VI-NEXT: v_mov_b32_e32 v1, s14661; VI-NEXT: v_mov_b32_e32 v2, s24662; VI-NEXT: flat_store_byte v[0:1], v24663; VI-NEXT: s_endpgm4664;4665; GFX9-LABEL: i1_arg:4666; GFX9: ; %bb.0:4667; GFX9-NEXT: s_load_dword s2, s[8:9], 0x84668; GFX9-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x04669; GFX9-NEXT: v_mov_b32_e32 v0, 04670; GFX9-NEXT: s_waitcnt lgkmcnt(0)4671; GFX9-NEXT: s_and_b32 s2, s2, 14672; GFX9-NEXT: v_mov_b32_e32 v1, s24673; GFX9-NEXT: global_store_byte v0, v1, s[0:1]4674; GFX9-NEXT: s_endpgm4675;4676; EG-LABEL: i1_arg:4677; EG: ; %bb.0:4678; EG-NEXT: ALU 0, @8, KC0[], KC1[]4679; EG-NEXT: TEX 0 @64680; EG-NEXT: ALU 11, @9, KC0[CB0:0-32], KC1[]4681; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X4682; EG-NEXT: CF_END4683; EG-NEXT: PAD4684; EG-NEXT: Fetch clause starting at 6:4685; EG-NEXT: VTX_READ_8 T0.X, T0.X, 40, #34686; EG-NEXT: ALU clause starting at 8:4687; EG-NEXT: MOV * T0.X, 0.0,4688; EG-NEXT: ALU clause starting at 9:4689; EG-NEXT: AND_INT T0.W, KC0[2].Y, literal.x,4690; EG-NEXT: AND_INT * T1.W, T0.X, 1,4691; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)4692; EG-NEXT: LSHL * T0.W, PV.W, literal.x,4693; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)4694; EG-NEXT: LSHL T0.X, T1.W, PV.W,4695; EG-NEXT: LSHL * T0.W, literal.x, PV.W,4696; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00)4697; EG-NEXT: MOV T0.Y, 0.0,4698; EG-NEXT: MOV * T0.Z, 0.0,4699; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,4700; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)4701;4702; CM-LABEL: i1_arg:4703; CM: ; %bb.0:4704; CM-NEXT: ALU 0, @8, KC0[], KC1[]4705; CM-NEXT: TEX 0 @64706; CM-NEXT: ALU 11, @9, KC0[CB0:0-32], KC1[]4707; CM-NEXT: MEM_RAT MSKOR T0.XW, T1.X4708; CM-NEXT: CF_END4709; CM-NEXT: PAD4710; CM-NEXT: Fetch clause starting at 6:4711; CM-NEXT: VTX_READ_8 T0.X, T0.X, 40, #34712; CM-NEXT: ALU clause starting at 8:4713; CM-NEXT: MOV * T0.X, 0.0,4714; CM-NEXT: ALU clause starting at 9:4715; CM-NEXT: AND_INT * T0.W, KC0[2].Y, literal.x,4716; CM-NEXT: 3(4.203895e-45), 0(0.000000e+00)4717; CM-NEXT: AND_INT T0.Z, T0.X, 1,4718; CM-NEXT: LSHL * T0.W, PV.W, literal.x,4719; CM-NEXT: 3(4.203895e-45), 0(0.000000e+00)4720; CM-NEXT: LSHL T0.X, PV.Z, PV.W,4721; CM-NEXT: LSHL * T0.W, literal.x, PV.W,4722; CM-NEXT: 255(3.573311e-43), 0(0.000000e+00)4723; CM-NEXT: MOV T0.Y, 0.0,4724; CM-NEXT: MOV * T0.Z, 0.0,4725; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,4726; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)4727 store i1 %x, ptr addrspace(1) %out, align 14728 ret void4729}4730 4731define amdgpu_kernel void @i1_arg_zext_i32(ptr addrspace(1) %out, i1 %x) nounwind {4732; SI-LABEL: i1_arg_zext_i32:4733; SI: ; %bb.0:4734; SI-NEXT: s_load_dword s2, s[4:5], 0xb4735; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x94736; SI-NEXT: s_mov_b32 s3, 0xf0004737; SI-NEXT: s_waitcnt lgkmcnt(0)4738; SI-NEXT: s_and_b32 s4, s2, 14739; SI-NEXT: s_mov_b32 s2, -14740; SI-NEXT: v_mov_b32_e32 v0, s44741; SI-NEXT: buffer_store_dword v0, off, s[0:3], 04742; SI-NEXT: s_endpgm4743;4744; VI-LABEL: i1_arg_zext_i32:4745; VI: ; %bb.0:4746; VI-NEXT: s_load_dword s2, s[4:5], 0x2c4747; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x244748; VI-NEXT: s_waitcnt lgkmcnt(0)4749; VI-NEXT: s_and_b32 s2, s2, 14750; VI-NEXT: v_mov_b32_e32 v0, s04751; VI-NEXT: v_mov_b32_e32 v1, s14752; VI-NEXT: v_mov_b32_e32 v2, s24753; VI-NEXT: flat_store_dword v[0:1], v24754; VI-NEXT: s_endpgm4755;4756; GFX9-LABEL: i1_arg_zext_i32:4757; GFX9: ; %bb.0:4758; GFX9-NEXT: s_load_dword s2, s[8:9], 0x84759; GFX9-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x04760; GFX9-NEXT: v_mov_b32_e32 v0, 04761; GFX9-NEXT: s_waitcnt lgkmcnt(0)4762; GFX9-NEXT: s_and_b32 s2, s2, 14763; GFX9-NEXT: v_mov_b32_e32 v1, s24764; GFX9-NEXT: global_store_dword v0, v1, s[0:1]4765; GFX9-NEXT: s_endpgm4766;4767; EG-LABEL: i1_arg_zext_i32:4768; EG: ; %bb.0:4769; EG-NEXT: ALU 0, @8, KC0[], KC1[]4770; EG-NEXT: TEX 0 @64771; EG-NEXT: ALU 1, @9, KC0[CB0:0-32], KC1[]4772; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 14773; EG-NEXT: CF_END4774; EG-NEXT: PAD4775; EG-NEXT: Fetch clause starting at 6:4776; EG-NEXT: VTX_READ_8 T0.X, T0.X, 40, #34777; EG-NEXT: ALU clause starting at 8:4778; EG-NEXT: MOV * T0.X, 0.0,4779; EG-NEXT: ALU clause starting at 9:4780; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,4781; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)4782;4783; CM-LABEL: i1_arg_zext_i32:4784; CM: ; %bb.0:4785; CM-NEXT: ALU 0, @8, KC0[], KC1[]4786; CM-NEXT: TEX 0 @64787; CM-NEXT: ALU 1, @9, KC0[CB0:0-32], KC1[]4788; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X4789; CM-NEXT: CF_END4790; CM-NEXT: PAD4791; CM-NEXT: Fetch clause starting at 6:4792; CM-NEXT: VTX_READ_8 T0.X, T0.X, 40, #34793; CM-NEXT: ALU clause starting at 8:4794; CM-NEXT: MOV * T0.X, 0.0,4795; CM-NEXT: ALU clause starting at 9:4796; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,4797; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)4798 %ext = zext i1 %x to i324799 store i32 %ext, ptr addrspace(1) %out, align 44800 ret void4801}4802 4803define amdgpu_kernel void @i1_arg_zext_i64(ptr addrspace(1) %out, i1 %x) nounwind {4804; SI-LABEL: i1_arg_zext_i64:4805; SI: ; %bb.0:4806; SI-NEXT: s_load_dword s6, s[4:5], 0xb4807; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x94808; SI-NEXT: s_mov_b32 s3, 0xf0004809; SI-NEXT: s_mov_b32 s2, -14810; SI-NEXT: s_waitcnt lgkmcnt(0)4811; SI-NEXT: s_and_b32 s4, s6, 14812; SI-NEXT: v_mov_b32_e32 v1, 04813; SI-NEXT: v_mov_b32_e32 v0, s44814; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 04815; SI-NEXT: s_endpgm4816;4817; VI-LABEL: i1_arg_zext_i64:4818; VI: ; %bb.0:4819; VI-NEXT: s_load_dword s2, s[4:5], 0x2c4820; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x244821; VI-NEXT: v_mov_b32_e32 v1, 04822; VI-NEXT: s_waitcnt lgkmcnt(0)4823; VI-NEXT: s_and_b32 s2, s2, 14824; VI-NEXT: v_mov_b32_e32 v3, s14825; VI-NEXT: v_mov_b32_e32 v0, s24826; VI-NEXT: v_mov_b32_e32 v2, s04827; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]4828; VI-NEXT: s_endpgm4829;4830; GFX9-LABEL: i1_arg_zext_i64:4831; GFX9: ; %bb.0:4832; GFX9-NEXT: s_load_dword s2, s[8:9], 0x84833; GFX9-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x04834; GFX9-NEXT: v_mov_b32_e32 v1, 04835; GFX9-NEXT: s_waitcnt lgkmcnt(0)4836; GFX9-NEXT: s_and_b32 s2, s2, 14837; GFX9-NEXT: v_mov_b32_e32 v0, s24838; GFX9-NEXT: global_store_dwordx2 v1, v[0:1], s[0:1]4839; GFX9-NEXT: s_endpgm4840;4841; EG-LABEL: i1_arg_zext_i64:4842; EG: ; %bb.0:4843; EG-NEXT: ALU 0, @8, KC0[], KC1[]4844; EG-NEXT: TEX 0 @64845; EG-NEXT: ALU 2, @9, KC0[CB0:0-32], KC1[]4846; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 14847; EG-NEXT: CF_END4848; EG-NEXT: PAD4849; EG-NEXT: Fetch clause starting at 6:4850; EG-NEXT: VTX_READ_8 T0.X, T0.X, 40, #34851; EG-NEXT: ALU clause starting at 8:4852; EG-NEXT: MOV * T0.X, 0.0,4853; EG-NEXT: ALU clause starting at 9:4854; EG-NEXT: MOV * T0.Y, 0.0,4855; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,4856; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)4857;4858; CM-LABEL: i1_arg_zext_i64:4859; CM: ; %bb.0:4860; CM-NEXT: ALU 0, @8, KC0[], KC1[]4861; CM-NEXT: TEX 0 @64862; CM-NEXT: ALU 2, @9, KC0[CB0:0-32], KC1[]4863; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0, T1.X4864; CM-NEXT: CF_END4865; CM-NEXT: PAD4866; CM-NEXT: Fetch clause starting at 6:4867; CM-NEXT: VTX_READ_8 T0.X, T0.X, 40, #34868; CM-NEXT: ALU clause starting at 8:4869; CM-NEXT: MOV * T0.X, 0.0,4870; CM-NEXT: ALU clause starting at 9:4871; CM-NEXT: MOV * T0.Y, 0.0,4872; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,4873; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)4874 %ext = zext i1 %x to i644875 store i64 %ext, ptr addrspace(1) %out, align 84876 ret void4877}4878 4879define amdgpu_kernel void @i1_arg_sext_i32(ptr addrspace(1) %out, i1 %x) nounwind {4880; SI-LABEL: i1_arg_sext_i32:4881; SI: ; %bb.0:4882; SI-NEXT: s_load_dword s2, s[4:5], 0xb4883; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x94884; SI-NEXT: s_mov_b32 s3, 0xf0004885; SI-NEXT: s_waitcnt lgkmcnt(0)4886; SI-NEXT: s_bfe_i32 s4, s2, 0x100004887; SI-NEXT: s_mov_b32 s2, -14888; SI-NEXT: v_mov_b32_e32 v0, s44889; SI-NEXT: buffer_store_dword v0, off, s[0:3], 04890; SI-NEXT: s_endpgm4891;4892; VI-LABEL: i1_arg_sext_i32:4893; VI: ; %bb.0:4894; VI-NEXT: s_load_dword s2, s[4:5], 0x2c4895; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x244896; VI-NEXT: s_waitcnt lgkmcnt(0)4897; VI-NEXT: s_bfe_i32 s2, s2, 0x100004898; VI-NEXT: v_mov_b32_e32 v0, s04899; VI-NEXT: v_mov_b32_e32 v1, s14900; VI-NEXT: v_mov_b32_e32 v2, s24901; VI-NEXT: flat_store_dword v[0:1], v24902; VI-NEXT: s_endpgm4903;4904; GFX9-LABEL: i1_arg_sext_i32:4905; GFX9: ; %bb.0:4906; GFX9-NEXT: s_load_dword s2, s[8:9], 0x84907; GFX9-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x04908; GFX9-NEXT: v_mov_b32_e32 v0, 04909; GFX9-NEXT: s_waitcnt lgkmcnt(0)4910; GFX9-NEXT: s_bfe_i32 s2, s2, 0x100004911; GFX9-NEXT: v_mov_b32_e32 v1, s24912; GFX9-NEXT: global_store_dword v0, v1, s[0:1]4913; GFX9-NEXT: s_endpgm4914;4915; EG-LABEL: i1_arg_sext_i32:4916; EG: ; %bb.0:4917; EG-NEXT: ALU 0, @8, KC0[], KC1[]4918; EG-NEXT: TEX 0 @64919; EG-NEXT: ALU 2, @9, KC0[CB0:0-32], KC1[]4920; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 14921; EG-NEXT: CF_END4922; EG-NEXT: PAD4923; EG-NEXT: Fetch clause starting at 6:4924; EG-NEXT: VTX_READ_8 T0.X, T0.X, 40, #34925; EG-NEXT: ALU clause starting at 8:4926; EG-NEXT: MOV * T0.X, 0.0,4927; EG-NEXT: ALU clause starting at 9:4928; EG-NEXT: BFE_INT T0.X, T0.X, 0.0, 1,4929; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,4930; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)4931;4932; CM-LABEL: i1_arg_sext_i32:4933; CM: ; %bb.0:4934; CM-NEXT: ALU 0, @8, KC0[], KC1[]4935; CM-NEXT: TEX 0 @64936; CM-NEXT: ALU 2, @9, KC0[CB0:0-32], KC1[]4937; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X4938; CM-NEXT: CF_END4939; CM-NEXT: PAD4940; CM-NEXT: Fetch clause starting at 6:4941; CM-NEXT: VTX_READ_8 T0.X, T0.X, 40, #34942; CM-NEXT: ALU clause starting at 8:4943; CM-NEXT: MOV * T0.X, 0.0,4944; CM-NEXT: ALU clause starting at 9:4945; CM-NEXT: BFE_INT * T0.X, T0.X, 0.0, 1,4946; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,4947; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)4948 %ext = sext i1 %x to i324949 store i32 %ext, ptr addrspace(1) %out, align 44950 ret void4951}4952 4953define amdgpu_kernel void @i1_arg_sext_i64(ptr addrspace(1) %out, i1 %x) nounwind {4954; SI-LABEL: i1_arg_sext_i64:4955; SI: ; %bb.0:4956; SI-NEXT: s_load_dword s2, s[4:5], 0xb4957; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x94958; SI-NEXT: s_mov_b32 s3, 0xf0004959; SI-NEXT: s_waitcnt lgkmcnt(0)4960; SI-NEXT: s_bfe_i64 s[4:5], s[2:3], 0x100004961; SI-NEXT: s_mov_b32 s2, -14962; SI-NEXT: v_mov_b32_e32 v0, s44963; SI-NEXT: v_mov_b32_e32 v1, s54964; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 04965; SI-NEXT: s_endpgm4966;4967; VI-LABEL: i1_arg_sext_i64:4968; VI: ; %bb.0:4969; VI-NEXT: s_load_dword s0, s[4:5], 0x2c4970; VI-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x244971; VI-NEXT: s_waitcnt lgkmcnt(0)4972; VI-NEXT: s_bfe_i64 s[0:1], s[0:1], 0x100004973; VI-NEXT: v_mov_b32_e32 v0, s24974; VI-NEXT: v_mov_b32_e32 v3, s14975; VI-NEXT: v_mov_b32_e32 v1, s34976; VI-NEXT: v_mov_b32_e32 v2, s04977; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]4978; VI-NEXT: s_endpgm4979;4980; GFX9-LABEL: i1_arg_sext_i64:4981; GFX9: ; %bb.0:4982; GFX9-NEXT: s_load_dword s0, s[8:9], 0x84983; GFX9-NEXT: s_load_dwordx2 s[2:3], s[8:9], 0x04984; GFX9-NEXT: v_mov_b32_e32 v2, 04985; GFX9-NEXT: s_waitcnt lgkmcnt(0)4986; GFX9-NEXT: s_bfe_i64 s[0:1], s[0:1], 0x100004987; GFX9-NEXT: v_mov_b32_e32 v0, s04988; GFX9-NEXT: v_mov_b32_e32 v1, s14989; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3]4990; GFX9-NEXT: s_endpgm4991;4992; EG-LABEL: i1_arg_sext_i64:4993; EG: ; %bb.0:4994; EG-NEXT: ALU 0, @8, KC0[], KC1[]4995; EG-NEXT: TEX 0 @64996; EG-NEXT: ALU 3, @9, KC0[CB0:0-32], KC1[]4997; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 14998; EG-NEXT: CF_END4999; EG-NEXT: PAD5000; EG-NEXT: Fetch clause starting at 6:5001; EG-NEXT: VTX_READ_8 T0.X, T0.X, 40, #35002; EG-NEXT: ALU clause starting at 8:5003; EG-NEXT: MOV * T0.X, 0.0,5004; EG-NEXT: ALU clause starting at 9:5005; EG-NEXT: BFE_INT T0.X, T0.X, 0.0, 1,5006; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,5007; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)5008; EG-NEXT: MOV * T0.Y, PV.X,5009;5010; CM-LABEL: i1_arg_sext_i64:5011; CM: ; %bb.0:5012; CM-NEXT: ALU 0, @8, KC0[], KC1[]5013; CM-NEXT: TEX 0 @65014; CM-NEXT: ALU 3, @9, KC0[CB0:0-32], KC1[]5015; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0, T1.X5016; CM-NEXT: CF_END5017; CM-NEXT: PAD5018; CM-NEXT: Fetch clause starting at 6:5019; CM-NEXT: VTX_READ_8 T0.X, T0.X, 40, #35020; CM-NEXT: ALU clause starting at 8:5021; CM-NEXT: MOV * T0.X, 0.0,5022; CM-NEXT: ALU clause starting at 9:5023; CM-NEXT: BFE_INT * T0.X, T0.X, 0.0, 1,5024; CM-NEXT: LSHR T1.X, KC0[2].Y, literal.x,5025; CM-NEXT: MOV * T0.Y, PV.X,5026; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)5027 %ext = sext i1 %x to i645028 store i64 %ext, ptr addrspace(1) %out, align 85029 ret void5030}5031 5032define amdgpu_kernel void @empty_struct_arg({} %in) nounwind {5033; SI-LABEL: empty_struct_arg:5034; SI: ; %bb.0:5035; SI-NEXT: s_endpgm5036;5037; VI-LABEL: empty_struct_arg:5038; VI: ; %bb.0:5039; VI-NEXT: s_endpgm5040;5041; GFX9-LABEL: empty_struct_arg:5042; GFX9: ; %bb.0:5043; GFX9-NEXT: s_endpgm5044;5045; EGCM-LABEL: empty_struct_arg:5046; EGCM: ; %bb.0:5047; EGCM-NEXT: CF_END5048; EGCM-NEXT: PAD5049 ret void5050}5051 5052; The correct load offsets for these:5053; load 4 from 0,5054; load 8 from 85055; load 4 from 245056; load 8 from 325057 5058; With the SelectionDAG argument lowering, the alignments for the5059; struct members is not properly considered, making these wrong.5060 5061; FIXME: Total argument size is computed wrong5062define amdgpu_kernel void @struct_argument_alignment({i32, i64} %arg0, i8, {i32, i64} %arg1) {5063; SI-LABEL: struct_argument_alignment:5064; SI: ; %bb.0:5065; SI-NEXT: s_load_dword s8, s[4:5], 0x95066; SI-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0xb5067; SI-NEXT: s_load_dword s9, s[4:5], 0xf5068; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x115069; SI-NEXT: s_mov_b64 s[0:1], 05070; SI-NEXT: s_mov_b32 s3, 0xf0005071; SI-NEXT: s_mov_b32 s2, -15072; SI-NEXT: s_waitcnt lgkmcnt(0)5073; SI-NEXT: v_mov_b32_e32 v0, s85074; SI-NEXT: buffer_store_dword v0, off, s[0:3], 05075; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)5076; SI-NEXT: v_mov_b32_e32 v0, s65077; SI-NEXT: v_mov_b32_e32 v1, s75078; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 05079; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)5080; SI-NEXT: v_mov_b32_e32 v0, s95081; SI-NEXT: buffer_store_dword v0, off, s[0:3], 05082; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)5083; SI-NEXT: v_mov_b32_e32 v0, s45084; SI-NEXT: v_mov_b32_e32 v1, s55085; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 05086; SI-NEXT: s_waitcnt vmcnt(0)5087; SI-NEXT: s_endpgm5088;5089; VI-LABEL: struct_argument_alignment:5090; VI: ; %bb.0:5091; VI-NEXT: s_load_dword s6, s[4:5], 0x245092; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2c5093; VI-NEXT: s_load_dword s7, s[4:5], 0x3c5094; VI-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x445095; VI-NEXT: v_mov_b32_e32 v0, 05096; VI-NEXT: v_mov_b32_e32 v1, 05097; VI-NEXT: s_waitcnt lgkmcnt(0)5098; VI-NEXT: v_mov_b32_e32 v2, s65099; VI-NEXT: flat_store_dword v[0:1], v25100; VI-NEXT: s_waitcnt vmcnt(0)5101; VI-NEXT: v_mov_b32_e32 v3, s15102; VI-NEXT: v_mov_b32_e32 v2, s05103; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]5104; VI-NEXT: s_waitcnt vmcnt(0)5105; VI-NEXT: v_mov_b32_e32 v2, s75106; VI-NEXT: flat_store_dword v[0:1], v25107; VI-NEXT: s_waitcnt vmcnt(0)5108; VI-NEXT: v_mov_b32_e32 v2, s25109; VI-NEXT: v_mov_b32_e32 v3, s35110; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]5111; VI-NEXT: s_waitcnt vmcnt(0)5112; VI-NEXT: s_endpgm5113;5114; GFX9-LABEL: struct_argument_alignment:5115; GFX9: ; %bb.0:5116; GFX9-NEXT: s_load_dword s4, s[8:9], 0x05117; GFX9-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x85118; GFX9-NEXT: s_load_dword s5, s[8:9], 0x185119; GFX9-NEXT: s_load_dwordx2 s[2:3], s[8:9], 0x205120; GFX9-NEXT: v_mov_b32_e32 v0, 05121; GFX9-NEXT: v_mov_b32_e32 v1, 05122; GFX9-NEXT: s_waitcnt lgkmcnt(0)5123; GFX9-NEXT: v_mov_b32_e32 v2, s45124; GFX9-NEXT: global_store_dword v[0:1], v2, off5125; GFX9-NEXT: s_waitcnt vmcnt(0)5126; GFX9-NEXT: v_mov_b32_e32 v3, s15127; GFX9-NEXT: v_mov_b32_e32 v2, s05128; GFX9-NEXT: global_store_dwordx2 v[0:1], v[2:3], off5129; GFX9-NEXT: s_waitcnt vmcnt(0)5130; GFX9-NEXT: v_mov_b32_e32 v2, s55131; GFX9-NEXT: global_store_dword v[0:1], v2, off5132; GFX9-NEXT: s_waitcnt vmcnt(0)5133; GFX9-NEXT: v_mov_b32_e32 v2, s25134; GFX9-NEXT: v_mov_b32_e32 v3, s35135; GFX9-NEXT: global_store_dwordx2 v[0:1], v[2:3], off5136; GFX9-NEXT: s_waitcnt vmcnt(0)5137; GFX9-NEXT: s_endpgm5138;5139; EG-LABEL: struct_argument_alignment:5140; EG: ; %bb.0:5141; EG-NEXT: ALU 9, @8, KC0[CB0:0-32], KC1[]5142; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T7.X, T6.X, 05143; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T5.X, T4.X, 05144; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T3.X, T6.X, 05145; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T2.X, T6.X, 05146; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T4.X, 05147; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T6.X, 15148; EG-NEXT: CF_END5149; EG-NEXT: ALU clause starting at 8:5150; EG-NEXT: MOV T0.X, KC0[4].Y,5151; EG-NEXT: MOV * T1.X, KC0[4].Z,5152; EG-NEXT: MOV T2.X, KC0[3].W,5153; EG-NEXT: MOV * T3.X, KC0[2].W,5154; EG-NEXT: MOV T4.X, literal.x,5155; EG-NEXT: MOV * T5.X, KC0[3].X,5156; EG-NEXT: 1(1.401298e-45), 0(0.000000e+00)5157; EG-NEXT: MOV T6.X, literal.x,5158; EG-NEXT: MOV * T7.X, KC0[2].Y,5159; EG-NEXT: 0(0.000000e+00), 0(0.000000e+00)5160;5161; CM-LABEL: struct_argument_alignment:5162; CM: ; %bb.0:5163; CM-NEXT: ALU 9, @8, KC0[CB0:0-32], KC1[]5164; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T7.X, T6.X5165; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T5.X, T4.X5166; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T3.X, T6.X5167; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T2.X, T6.X5168; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1.X, T4.X5169; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0.X, T6.X5170; CM-NEXT: CF_END5171; CM-NEXT: ALU clause starting at 8:5172; CM-NEXT: MOV * T0.X, KC0[4].Y,5173; CM-NEXT: MOV * T1.X, KC0[4].Z,5174; CM-NEXT: MOV * T2.X, KC0[3].W,5175; CM-NEXT: MOV * T3.X, KC0[2].W,5176; CM-NEXT: MOV * T4.X, literal.x,5177; CM-NEXT: 1(1.401298e-45), 0(0.000000e+00)5178; CM-NEXT: MOV * T5.X, KC0[3].X,5179; CM-NEXT: MOV * T6.X, literal.x,5180; CM-NEXT: 0(0.000000e+00), 0(0.000000e+00)5181; CM-NEXT: MOV * T7.X, KC0[2].Y,5182 %val0 = extractvalue {i32, i64} %arg0, 05183 %val1 = extractvalue {i32, i64} %arg0, 15184 %val2 = extractvalue {i32, i64} %arg1, 05185 %val3 = extractvalue {i32, i64} %arg1, 15186 store volatile i32 %val0, ptr addrspace(1) null5187 store volatile i64 %val1, ptr addrspace(1) null5188 store volatile i32 %val2, ptr addrspace(1) null5189 store volatile i64 %val3, ptr addrspace(1) null5190 ret void5191}5192 5193; No padding between i8 and next struct, but round up at end to 4 byte5194; multiple.5195define amdgpu_kernel void @packed_struct_argument_alignment(<{i32, i64}> %arg0, i8, <{i32, i64}> %arg1) {5196; SI-LABEL: packed_struct_argument_alignment:5197; SI: ; %bb.0:5198; SI-NEXT: s_mov_b32 s7, 0xf0005199; SI-NEXT: s_mov_b32 s6, -15200; SI-NEXT: s_load_dword s2, s[4:5], 0x95201; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0xa5202; SI-NEXT: buffer_load_ubyte v4, off, s[4:7], 0 offset:495203; SI-NEXT: buffer_load_ubyte v5, off, s[4:7], 0 offset:505204; SI-NEXT: buffer_load_ubyte v6, off, s[4:7], 0 offset:515205; SI-NEXT: buffer_load_ubyte v7, off, s[4:7], 0 offset:525206; SI-NEXT: buffer_load_dwordx2 v[0:1], off, s[4:7], 0 offset:535207; SI-NEXT: s_mov_b64 s[4:5], 05208; SI-NEXT: s_waitcnt lgkmcnt(0)5209; SI-NEXT: v_mov_b32_e32 v2, s25210; SI-NEXT: buffer_store_dword v2, off, s[4:7], 05211; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)5212; SI-NEXT: v_mov_b32_e32 v3, s15213; SI-NEXT: v_mov_b32_e32 v2, s05214; SI-NEXT: buffer_store_dwordx2 v[2:3], off, s[4:7], 05215; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)5216; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v55217; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v75218; SI-NEXT: v_or_b32_e32 v2, v2, v45219; SI-NEXT: v_or_b32_e32 v3, v3, v65220; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v35221; SI-NEXT: v_or_b32_e32 v2, v3, v25222; SI-NEXT: buffer_store_dword v2, off, s[4:7], 05223; SI-NEXT: s_waitcnt vmcnt(0)5224; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 05225; SI-NEXT: s_waitcnt vmcnt(0)5226; SI-NEXT: s_endpgm5227;5228; VI-LABEL: packed_struct_argument_alignment:5229; VI: ; %bb.0:5230; VI-NEXT: s_add_u32 s0, s4, 495231; VI-NEXT: s_addc_u32 s1, s5, 05232; VI-NEXT: s_add_u32 s2, s4, 505233; VI-NEXT: s_addc_u32 s3, s5, 05234; VI-NEXT: v_mov_b32_e32 v3, s15235; VI-NEXT: v_mov_b32_e32 v2, s05236; VI-NEXT: s_add_u32 s0, s0, 35237; VI-NEXT: s_addc_u32 s1, s1, 05238; VI-NEXT: v_mov_b32_e32 v5, s15239; VI-NEXT: v_mov_b32_e32 v4, s05240; VI-NEXT: s_add_u32 s0, s4, 515241; VI-NEXT: s_addc_u32 s1, s5, 05242; VI-NEXT: v_mov_b32_e32 v0, s25243; VI-NEXT: v_mov_b32_e32 v7, s15244; VI-NEXT: v_mov_b32_e32 v1, s35245; VI-NEXT: v_mov_b32_e32 v6, s05246; VI-NEXT: flat_load_ubyte v8, v[0:1]5247; VI-NEXT: flat_load_ubyte v9, v[2:3]5248; VI-NEXT: flat_load_ubyte v10, v[4:5]5249; VI-NEXT: flat_load_ubyte v6, v[6:7]5250; VI-NEXT: s_add_u32 s0, s4, 535251; VI-NEXT: s_addc_u32 s1, s5, 05252; VI-NEXT: v_mov_b32_e32 v0, s05253; VI-NEXT: v_mov_b32_e32 v1, s15254; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1]5255; VI-NEXT: s_load_dword s2, s[4:5], 0x245256; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x285257; VI-NEXT: v_mov_b32_e32 v2, 05258; VI-NEXT: v_mov_b32_e32 v3, 05259; VI-NEXT: s_waitcnt lgkmcnt(0)5260; VI-NEXT: v_mov_b32_e32 v7, s25261; VI-NEXT: v_mov_b32_e32 v5, s15262; VI-NEXT: v_mov_b32_e32 v4, s05263; VI-NEXT: flat_store_dword v[2:3], v75264; VI-NEXT: s_waitcnt vmcnt(0)5265; VI-NEXT: flat_store_dwordx2 v[2:3], v[4:5]5266; VI-NEXT: s_waitcnt vmcnt(0)5267; VI-NEXT: v_lshlrev_b32_e32 v4, 8, v85268; VI-NEXT: v_or_b32_e32 v4, v4, v95269; VI-NEXT: v_lshlrev_b32_e32 v5, 8, v105270; VI-NEXT: v_or_b32_sdwa v5, v5, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD5271; VI-NEXT: v_or_b32_e32 v4, v5, v45272; VI-NEXT: flat_store_dword v[2:3], v45273; VI-NEXT: s_waitcnt vmcnt(0)5274; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]5275; VI-NEXT: s_waitcnt vmcnt(0)5276; VI-NEXT: s_endpgm5277;5278; GFX9-LABEL: packed_struct_argument_alignment:5279; GFX9: ; %bb.0:5280; GFX9-NEXT: v_mov_b32_e32 v2, 05281; GFX9-NEXT: global_load_dword v6, v2, s[8:9] offset:135282; GFX9-NEXT: global_load_dwordx2 v[0:1], v2, s[8:9] offset:175283; GFX9-NEXT: s_load_dword s2, s[8:9], 0x05284; GFX9-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x45285; GFX9-NEXT: v_mov_b32_e32 v2, 05286; GFX9-NEXT: v_mov_b32_e32 v3, 05287; GFX9-NEXT: s_waitcnt lgkmcnt(0)5288; GFX9-NEXT: v_mov_b32_e32 v7, s25289; GFX9-NEXT: v_mov_b32_e32 v5, s15290; GFX9-NEXT: v_mov_b32_e32 v4, s05291; GFX9-NEXT: global_store_dword v[2:3], v7, off5292; GFX9-NEXT: s_waitcnt vmcnt(0)5293; GFX9-NEXT: global_store_dwordx2 v[2:3], v[4:5], off5294; GFX9-NEXT: s_waitcnt vmcnt(0)5295; GFX9-NEXT: global_store_dword v[2:3], v6, off5296; GFX9-NEXT: s_waitcnt vmcnt(0)5297; GFX9-NEXT: global_store_dwordx2 v[2:3], v[0:1], off5298; GFX9-NEXT: s_waitcnt vmcnt(0)5299; GFX9-NEXT: s_endpgm5300;5301; EG-LABEL: packed_struct_argument_alignment:5302; EG: ; %bb.0:5303; EG-NEXT: ALU 6, @18, KC0[CB0:0-32], KC1[]5304; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T4.X, T3.X, 05305; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T2.X, T1.X, 05306; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T3.X, 05307; EG-NEXT: ALU 2, @25, KC0[], KC1[]5308; EG-NEXT: TEX 0 @125309; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T3.X, 05310; EG-NEXT: TEX 0 @145311; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T2.X, T1.X, 05312; EG-NEXT: TEX 0 @165313; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T4.X, T3.X, 15314; EG-NEXT: CF_END5315; EG-NEXT: Fetch clause starting at 12:5316; EG-NEXT: VTX_READ_32 T0.X, T0.X, 49, #35317; EG-NEXT: Fetch clause starting at 14:5318; EG-NEXT: VTX_READ_32 T2.X, T2.X, 57, #35319; EG-NEXT: Fetch clause starting at 16:5320; EG-NEXT: VTX_READ_32 T4.X, T4.X, 53, #35321; EG-NEXT: ALU clause starting at 18:5322; EG-NEXT: MOV T0.X, KC0[2].Z,5323; EG-NEXT: MOV * T1.X, literal.x,5324; EG-NEXT: 1(1.401298e-45), 0(0.000000e+00)5325; EG-NEXT: MOV T2.X, KC0[2].W,5326; EG-NEXT: MOV * T3.X, literal.x,5327; EG-NEXT: 0(0.000000e+00), 0(0.000000e+00)5328; EG-NEXT: MOV * T4.X, KC0[2].Y,5329; EG-NEXT: ALU clause starting at 25:5330; EG-NEXT: MOV T0.X, 0.0,5331; EG-NEXT: MOV * T2.X, 0.0,5332; EG-NEXT: MOV * T4.X, 0.0,5333;5334; CM-LABEL: packed_struct_argument_alignment:5335; CM: ; %bb.0:5336; CM-NEXT: ALU 6, @18, KC0[CB0:0-32], KC1[]5337; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T4.X, T3.X5338; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T2.X, T1.X5339; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0.X, T3.X5340; CM-NEXT: ALU 2, @25, KC0[], KC1[]5341; CM-NEXT: TEX 0 @125342; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0.X, T3.X5343; CM-NEXT: TEX 0 @145344; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T2.X, T1.X5345; CM-NEXT: TEX 0 @165346; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T4.X, T3.X5347; CM-NEXT: CF_END5348; CM-NEXT: Fetch clause starting at 12:5349; CM-NEXT: VTX_READ_32 T0.X, T0.X, 49, #35350; CM-NEXT: Fetch clause starting at 14:5351; CM-NEXT: VTX_READ_32 T2.X, T2.X, 57, #35352; CM-NEXT: Fetch clause starting at 16:5353; CM-NEXT: VTX_READ_32 T4.X, T4.X, 53, #35354; CM-NEXT: ALU clause starting at 18:5355; CM-NEXT: MOV * T0.X, KC0[2].Z,5356; CM-NEXT: MOV * T1.X, literal.x,5357; CM-NEXT: 1(1.401298e-45), 0(0.000000e+00)5358; CM-NEXT: MOV * T2.X, KC0[2].W,5359; CM-NEXT: MOV * T3.X, literal.x,5360; CM-NEXT: 0(0.000000e+00), 0(0.000000e+00)5361; CM-NEXT: MOV * T4.X, KC0[2].Y,5362; CM-NEXT: ALU clause starting at 25:5363; CM-NEXT: MOV * T0.X, 0.0,5364; CM-NEXT: MOV * T2.X, 0.0,5365; CM-NEXT: MOV * T4.X, 0.0,5366 %val0 = extractvalue <{i32, i64}> %arg0, 05367 %val1 = extractvalue <{i32, i64}> %arg0, 15368 %val2 = extractvalue <{i32, i64}> %arg1, 05369 %val3 = extractvalue <{i32, i64}> %arg1, 15370 store volatile i32 %val0, ptr addrspace(1) null5371 store volatile i64 %val1, ptr addrspace(1) null5372 store volatile i32 %val2, ptr addrspace(1) null5373 store volatile i64 %val3, ptr addrspace(1) null5374 ret void5375}5376 5377define amdgpu_kernel void @struct_argument_alignment_after({i32, i64} %arg0, i8, {i32, i64} %arg2, i8, <4 x i32> %arg4) {5378; SI-LABEL: struct_argument_alignment_after:5379; SI: ; %bb.0:5380; SI-NEXT: s_load_dword s12, s[4:5], 0x95381; SI-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0xb5382; SI-NEXT: s_load_dword s13, s[4:5], 0xf5383; SI-NEXT: s_load_dwordx2 s[10:11], s[4:5], 0x115384; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x155385; SI-NEXT: s_mov_b64 s[4:5], 05386; SI-NEXT: s_mov_b32 s7, 0xf0005387; SI-NEXT: s_mov_b32 s6, -15388; SI-NEXT: s_waitcnt lgkmcnt(0)5389; SI-NEXT: v_mov_b32_e32 v0, s125390; SI-NEXT: buffer_store_dword v0, off, s[4:7], 05391; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)5392; SI-NEXT: v_mov_b32_e32 v0, s85393; SI-NEXT: v_mov_b32_e32 v1, s95394; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 05395; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)5396; SI-NEXT: v_mov_b32_e32 v0, s135397; SI-NEXT: buffer_store_dword v0, off, s[4:7], 05398; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)5399; SI-NEXT: v_mov_b32_e32 v0, s105400; SI-NEXT: v_mov_b32_e32 v1, s115401; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 05402; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)5403; SI-NEXT: v_mov_b32_e32 v0, s05404; SI-NEXT: v_mov_b32_e32 v1, s15405; SI-NEXT: v_mov_b32_e32 v2, s25406; SI-NEXT: v_mov_b32_e32 v3, s35407; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 05408; SI-NEXT: s_waitcnt vmcnt(0)5409; SI-NEXT: s_endpgm5410;5411; VI-LABEL: struct_argument_alignment_after:5412; VI: ; %bb.0:5413; VI-NEXT: s_load_dword s10, s[4:5], 0x245414; VI-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x2c5415; VI-NEXT: s_load_dword s11, s[4:5], 0x3c5416; VI-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x445417; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x545418; VI-NEXT: v_mov_b32_e32 v4, 05419; VI-NEXT: v_mov_b32_e32 v5, 05420; VI-NEXT: s_waitcnt lgkmcnt(0)5421; VI-NEXT: v_mov_b32_e32 v0, s105422; VI-NEXT: flat_store_dword v[4:5], v05423; VI-NEXT: s_waitcnt vmcnt(0)5424; VI-NEXT: v_mov_b32_e32 v0, s65425; VI-NEXT: v_mov_b32_e32 v1, s75426; VI-NEXT: flat_store_dwordx2 v[4:5], v[0:1]5427; VI-NEXT: s_waitcnt vmcnt(0)5428; VI-NEXT: v_mov_b32_e32 v0, s115429; VI-NEXT: flat_store_dword v[4:5], v05430; VI-NEXT: s_waitcnt vmcnt(0)5431; VI-NEXT: v_mov_b32_e32 v0, s85432; VI-NEXT: v_mov_b32_e32 v1, s95433; VI-NEXT: flat_store_dwordx2 v[4:5], v[0:1]5434; VI-NEXT: s_waitcnt vmcnt(0)5435; VI-NEXT: v_mov_b32_e32 v0, s05436; VI-NEXT: v_mov_b32_e32 v1, s15437; VI-NEXT: v_mov_b32_e32 v2, s25438; VI-NEXT: v_mov_b32_e32 v3, s35439; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]5440; VI-NEXT: s_waitcnt vmcnt(0)5441; VI-NEXT: s_endpgm5442;5443; GFX9-LABEL: struct_argument_alignment_after:5444; GFX9: ; %bb.0:5445; GFX9-NEXT: s_load_dword s10, s[8:9], 0x05446; GFX9-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x85447; GFX9-NEXT: s_load_dword s11, s[8:9], 0x185448; GFX9-NEXT: s_load_dwordx2 s[6:7], s[8:9], 0x205449; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x305450; GFX9-NEXT: v_mov_b32_e32 v4, 05451; GFX9-NEXT: v_mov_b32_e32 v5, 05452; GFX9-NEXT: s_waitcnt lgkmcnt(0)5453; GFX9-NEXT: v_mov_b32_e32 v0, s105454; GFX9-NEXT: global_store_dword v[4:5], v0, off5455; GFX9-NEXT: s_waitcnt vmcnt(0)5456; GFX9-NEXT: v_mov_b32_e32 v0, s45457; GFX9-NEXT: v_mov_b32_e32 v1, s55458; GFX9-NEXT: global_store_dwordx2 v[4:5], v[0:1], off5459; GFX9-NEXT: s_waitcnt vmcnt(0)5460; GFX9-NEXT: v_mov_b32_e32 v0, s115461; GFX9-NEXT: global_store_dword v[4:5], v0, off5462; GFX9-NEXT: s_waitcnt vmcnt(0)5463; GFX9-NEXT: v_mov_b32_e32 v0, s65464; GFX9-NEXT: v_mov_b32_e32 v1, s75465; GFX9-NEXT: global_store_dwordx2 v[4:5], v[0:1], off5466; GFX9-NEXT: s_waitcnt vmcnt(0)5467; GFX9-NEXT: v_mov_b32_e32 v0, s05468; GFX9-NEXT: v_mov_b32_e32 v1, s15469; GFX9-NEXT: v_mov_b32_e32 v2, s25470; GFX9-NEXT: v_mov_b32_e32 v3, s35471; GFX9-NEXT: global_store_dwordx4 v[4:5], v[0:3], off5472; GFX9-NEXT: s_waitcnt vmcnt(0)5473; GFX9-NEXT: s_endpgm5474;5475; EG-LABEL: struct_argument_alignment_after:5476; EG: ; %bb.0:5477; EG-NEXT: ALU 13, @10, KC0[CB0:0-32], KC1[]5478; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T8.X, T7.X, 05479; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T6.X, T5.X, 05480; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T4.X, T7.X, 05481; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T3.X, T7.X, 05482; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T2.X, T5.X, 05483; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T7.X, 05484; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T7.X, 15485; EG-NEXT: CF_END5486; EG-NEXT: PAD5487; EG-NEXT: ALU clause starting at 10:5488; EG-NEXT: MOV * T0.W, KC0[6].X,5489; EG-NEXT: MOV * T0.Z, KC0[5].W,5490; EG-NEXT: MOV * T0.Y, KC0[5].Z,5491; EG-NEXT: MOV T0.X, KC0[5].Y,5492; EG-NEXT: MOV * T1.X, KC0[4].Y,5493; EG-NEXT: MOV T2.X, KC0[4].Z,5494; EG-NEXT: MOV * T3.X, KC0[3].W,5495; EG-NEXT: MOV T4.X, KC0[2].W,5496; EG-NEXT: MOV * T5.X, literal.x,5497; EG-NEXT: 1(1.401298e-45), 0(0.000000e+00)5498; EG-NEXT: MOV T6.X, KC0[3].X,5499; EG-NEXT: MOV * T7.X, literal.x,5500; EG-NEXT: 0(0.000000e+00), 0(0.000000e+00)5501; EG-NEXT: MOV * T8.X, KC0[2].Y,5502;5503; CM-LABEL: struct_argument_alignment_after:5504; CM: ; %bb.0:5505; CM-NEXT: ALU 13, @10, KC0[CB0:0-32], KC1[]5506; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T8.X, T7.X5507; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T6.X, T5.X5508; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T4.X, T7.X5509; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T3.X, T7.X5510; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T2.X, T5.X5511; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1.X, T7.X5512; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0, T7.X5513; CM-NEXT: CF_END5514; CM-NEXT: PAD5515; CM-NEXT: ALU clause starting at 10:5516; CM-NEXT: MOV * T0.W, KC0[6].X,5517; CM-NEXT: MOV * T0.Z, KC0[5].W,5518; CM-NEXT: MOV * T0.Y, KC0[5].Z,5519; CM-NEXT: MOV * T0.X, KC0[5].Y,5520; CM-NEXT: MOV * T1.X, KC0[4].Y,5521; CM-NEXT: MOV * T2.X, KC0[4].Z,5522; CM-NEXT: MOV * T3.X, KC0[3].W,5523; CM-NEXT: MOV * T4.X, KC0[2].W,5524; CM-NEXT: MOV * T5.X, literal.x,5525; CM-NEXT: 1(1.401298e-45), 0(0.000000e+00)5526; CM-NEXT: MOV * T6.X, KC0[3].X,5527; CM-NEXT: MOV * T7.X, literal.x,5528; CM-NEXT: 0(0.000000e+00), 0(0.000000e+00)5529; CM-NEXT: MOV * T8.X, KC0[2].Y,5530 %val0 = extractvalue {i32, i64} %arg0, 05531 %val1 = extractvalue {i32, i64} %arg0, 15532 %val2 = extractvalue {i32, i64} %arg2, 05533 %val3 = extractvalue {i32, i64} %arg2, 15534 store volatile i32 %val0, ptr addrspace(1) null5535 store volatile i64 %val1, ptr addrspace(1) null5536 store volatile i32 %val2, ptr addrspace(1) null5537 store volatile i64 %val3, ptr addrspace(1) null5538 store volatile <4 x i32> %arg4, ptr addrspace(1) null5539 ret void5540}5541 5542define amdgpu_kernel void @array_3xi32(i16 %arg0, [3 x i32] %arg1) {5543; SI-LABEL: array_3xi32:5544; SI: ; %bb.0:5545; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x95546; SI-NEXT: s_mov_b32 s7, 0xf0005547; SI-NEXT: s_mov_b32 s6, -15548; SI-NEXT: s_waitcnt lgkmcnt(0)5549; SI-NEXT: v_mov_b32_e32 v0, s05550; SI-NEXT: buffer_store_short v0, off, s[4:7], 05551; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)5552; SI-NEXT: v_mov_b32_e32 v0, s35553; SI-NEXT: buffer_store_dword v0, off, s[4:7], 05554; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)5555; SI-NEXT: v_mov_b32_e32 v0, s25556; SI-NEXT: buffer_store_dword v0, off, s[4:7], 05557; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)5558; SI-NEXT: v_mov_b32_e32 v0, s15559; SI-NEXT: buffer_store_dword v0, off, s[4:7], 05560; SI-NEXT: s_waitcnt vmcnt(0)5561; SI-NEXT: s_endpgm5562;5563; VI-LABEL: array_3xi32:5564; VI: ; %bb.0:5565; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x245566; VI-NEXT: s_waitcnt lgkmcnt(0)5567; VI-NEXT: v_mov_b32_e32 v0, s05568; VI-NEXT: v_mov_b32_e32 v1, s35569; VI-NEXT: v_mov_b32_e32 v2, s25570; VI-NEXT: flat_store_short v[0:1], v05571; VI-NEXT: s_waitcnt vmcnt(0)5572; VI-NEXT: flat_store_dword v[0:1], v15573; VI-NEXT: s_waitcnt vmcnt(0)5574; VI-NEXT: flat_store_dword v[0:1], v25575; VI-NEXT: s_waitcnt vmcnt(0)5576; VI-NEXT: v_mov_b32_e32 v0, s15577; VI-NEXT: flat_store_dword v[0:1], v05578; VI-NEXT: s_waitcnt vmcnt(0)5579; VI-NEXT: s_endpgm5580;5581; GFX9-LABEL: array_3xi32:5582; GFX9: ; %bb.0:5583; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x05584; GFX9-NEXT: s_waitcnt lgkmcnt(0)5585; GFX9-NEXT: v_mov_b32_e32 v0, s05586; GFX9-NEXT: v_mov_b32_e32 v1, s35587; GFX9-NEXT: v_mov_b32_e32 v2, s25588; GFX9-NEXT: global_store_short v[0:1], v0, off5589; GFX9-NEXT: s_waitcnt vmcnt(0)5590; GFX9-NEXT: global_store_dword v[0:1], v1, off5591; GFX9-NEXT: s_waitcnt vmcnt(0)5592; GFX9-NEXT: global_store_dword v[0:1], v2, off5593; GFX9-NEXT: s_waitcnt vmcnt(0)5594; GFX9-NEXT: v_mov_b32_e32 v0, s15595; GFX9-NEXT: global_store_dword v[0:1], v0, off5596; GFX9-NEXT: s_waitcnt vmcnt(0)5597; GFX9-NEXT: s_endpgm5598;5599; EG-LABEL: array_3xi32:5600; EG: ; %bb.0:5601; EG-NEXT: ALU 0, @10, KC0[], KC1[]5602; EG-NEXT: TEX 0 @85603; EG-NEXT: ALU 9, @11, KC0[CB0:0-32], KC1[]5604; EG-NEXT: MEM_RAT MSKOR T0.XW, T4.X5605; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T3.X, T4.X, 05606; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T2.X, T4.X, 05607; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T4.X, 15608; EG-NEXT: CF_END5609; EG-NEXT: Fetch clause starting at 8:5610; EG-NEXT: VTX_READ_16 T0.X, T0.X, 36, #35611; EG-NEXT: ALU clause starting at 10:5612; EG-NEXT: MOV * T0.X, 0.0,5613; EG-NEXT: ALU clause starting at 11:5614; EG-NEXT: AND_INT T0.X, T0.X, literal.x,5615; EG-NEXT: MOV * T0.W, literal.x,5616; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)5617; EG-NEXT: MOV T0.Y, 0.0,5618; EG-NEXT: MOV * T0.Z, 0.0,5619; EG-NEXT: MOV T1.X, KC0[2].Z,5620; EG-NEXT: MOV * T2.X, KC0[2].W,5621; EG-NEXT: MOV T3.X, KC0[3].X,5622; EG-NEXT: MOV * T4.X, literal.x,5623; EG-NEXT: 0(0.000000e+00), 0(0.000000e+00)5624;5625; CM-LABEL: array_3xi32:5626; CM: ; %bb.0:5627; CM-NEXT: ALU 0, @10, KC0[], KC1[]5628; CM-NEXT: TEX 0 @85629; CM-NEXT: ALU 9, @11, KC0[CB0:0-32], KC1[]5630; CM-NEXT: MEM_RAT MSKOR T0.XW, T4.X5631; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T3.X, T4.X5632; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T2.X, T4.X5633; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1.X, T4.X5634; CM-NEXT: CF_END5635; CM-NEXT: Fetch clause starting at 8:5636; CM-NEXT: VTX_READ_16 T0.X, T0.X, 36, #35637; CM-NEXT: ALU clause starting at 10:5638; CM-NEXT: MOV * T0.X, 0.0,5639; CM-NEXT: ALU clause starting at 11:5640; CM-NEXT: AND_INT T0.X, T0.X, literal.x,5641; CM-NEXT: MOV * T0.W, literal.x,5642; CM-NEXT: 65535(9.183409e-41), 0(0.000000e+00)5643; CM-NEXT: MOV T0.Y, 0.0,5644; CM-NEXT: MOV * T0.Z, 0.0,5645; CM-NEXT: MOV * T1.X, KC0[2].Z,5646; CM-NEXT: MOV * T2.X, KC0[2].W,5647; CM-NEXT: MOV * T3.X, KC0[3].X,5648; CM-NEXT: MOV * T4.X, literal.x,5649; CM-NEXT: 0(0.000000e+00), 0(0.000000e+00)5650 store volatile i16 %arg0, ptr addrspace(1) poison5651 store volatile [3 x i32] %arg1, ptr addrspace(1) poison5652 ret void5653}5654 5655; FIXME: Why not all scalar loads?5656define amdgpu_kernel void @array_3xi16(i8 %arg0, [3 x i16] %arg1) {5657; SI-LABEL: array_3xi16:5658; SI: ; %bb.0:5659; SI-NEXT: s_load_dword s0, s[4:5], 0x95660; SI-NEXT: s_mov_b32 s7, 0xf0005661; SI-NEXT: s_mov_b32 s6, -15662; SI-NEXT: buffer_load_ushort v0, off, s[4:7], 0 offset:425663; SI-NEXT: buffer_load_ushort v1, off, s[4:7], 0 offset:405664; SI-NEXT: buffer_load_ushort v2, off, s[4:7], 0 offset:385665; SI-NEXT: s_waitcnt lgkmcnt(0)5666; SI-NEXT: v_mov_b32_e32 v3, s05667; SI-NEXT: buffer_store_byte v3, off, s[4:7], 05668; SI-NEXT: s_waitcnt vmcnt(0)5669; SI-NEXT: buffer_store_short v0, off, s[4:7], 05670; SI-NEXT: s_waitcnt vmcnt(0)5671; SI-NEXT: buffer_store_short v1, off, s[4:7], 05672; SI-NEXT: s_waitcnt vmcnt(0)5673; SI-NEXT: buffer_store_short v2, off, s[4:7], 05674; SI-NEXT: s_waitcnt vmcnt(0)5675; SI-NEXT: s_endpgm5676;5677; VI-LABEL: array_3xi16:5678; VI: ; %bb.0:5679; VI-NEXT: s_add_u32 s0, s4, 385680; VI-NEXT: s_addc_u32 s1, s5, 05681; VI-NEXT: s_add_u32 s2, s0, 25682; VI-NEXT: s_addc_u32 s3, s1, 05683; VI-NEXT: v_mov_b32_e32 v3, s15684; VI-NEXT: v_mov_b32_e32 v2, s05685; VI-NEXT: s_add_u32 s0, s4, 425686; VI-NEXT: s_addc_u32 s1, s5, 05687; VI-NEXT: v_mov_b32_e32 v5, s15688; VI-NEXT: v_mov_b32_e32 v0, s25689; VI-NEXT: v_mov_b32_e32 v4, s05690; VI-NEXT: v_mov_b32_e32 v1, s35691; VI-NEXT: flat_load_ushort v4, v[4:5]5692; VI-NEXT: flat_load_ushort v2, v[2:3]5693; VI-NEXT: flat_load_ushort v0, v[0:1]5694; VI-NEXT: s_load_dword s0, s[4:5], 0x245695; VI-NEXT: s_waitcnt lgkmcnt(0)5696; VI-NEXT: v_mov_b32_e32 v1, s05697; VI-NEXT: s_waitcnt vmcnt(0)5698; VI-NEXT: flat_store_byte v[0:1], v15699; VI-NEXT: s_waitcnt vmcnt(0)5700; VI-NEXT: flat_store_short v[0:1], v45701; VI-NEXT: s_waitcnt vmcnt(0)5702; VI-NEXT: flat_store_short v[0:1], v25703; VI-NEXT: s_waitcnt vmcnt(0)5704; VI-NEXT: flat_store_short v[0:1], v05705; VI-NEXT: s_waitcnt vmcnt(0)5706; VI-NEXT: s_endpgm5707;5708; GFX9-LABEL: array_3xi16:5709; GFX9: ; %bb.0:5710; GFX9-NEXT: v_mov_b32_e32 v0, 05711; GFX9-NEXT: global_load_ushort v1, v0, s[8:9] offset:65712; GFX9-NEXT: global_load_ushort v2, v0, s[8:9] offset:45713; GFX9-NEXT: global_load_ushort v3, v0, s[8:9] offset:25714; GFX9-NEXT: s_load_dword s0, s[8:9], 0x05715; GFX9-NEXT: s_waitcnt lgkmcnt(0)5716; GFX9-NEXT: v_mov_b32_e32 v0, s05717; GFX9-NEXT: s_waitcnt vmcnt(2)5718; GFX9-NEXT: global_store_byte v[0:1], v0, off5719; GFX9-NEXT: s_waitcnt vmcnt(0)5720; GFX9-NEXT: global_store_short v[0:1], v1, off5721; GFX9-NEXT: s_waitcnt vmcnt(0)5722; GFX9-NEXT: global_store_short v[0:1], v2, off5723; GFX9-NEXT: s_waitcnt vmcnt(0)5724; GFX9-NEXT: global_store_short v[0:1], v3, off5725; GFX9-NEXT: s_waitcnt vmcnt(0)5726; GFX9-NEXT: s_endpgm5727;5728; EG-LABEL: array_3xi16:5729; EG: ; %bb.0:5730; EG-NEXT: ALU 0, @20, KC0[], KC1[]5731; EG-NEXT: TEX 1 @125732; EG-NEXT: ALU 11, @21, KC0[], KC1[]5733; EG-NEXT: MEM_RAT MSKOR T1.XW, T3.X5734; EG-NEXT: MEM_RAT MSKOR T2.XW, T3.X5735; EG-NEXT: TEX 0 @165736; EG-NEXT: ALU 3, @33, KC0[], KC1[]5737; EG-NEXT: MEM_RAT MSKOR T2.XW, T3.X5738; EG-NEXT: TEX 0 @185739; EG-NEXT: ALU 3, @37, KC0[], KC1[]5740; EG-NEXT: MEM_RAT MSKOR T2.XW, T3.X5741; EG-NEXT: CF_END5742; EG-NEXT: Fetch clause starting at 12:5743; EG-NEXT: VTX_READ_8 T1.X, T0.X, 36, #35744; EG-NEXT: VTX_READ_16 T2.X, T0.X, 42, #35745; EG-NEXT: Fetch clause starting at 16:5746; EG-NEXT: VTX_READ_16 T1.X, T0.X, 40, #35747; EG-NEXT: Fetch clause starting at 18:5748; EG-NEXT: VTX_READ_16 T0.X, T0.X, 38, #35749; EG-NEXT: ALU clause starting at 20:5750; EG-NEXT: MOV * T0.X, 0.0,5751; EG-NEXT: ALU clause starting at 21:5752; EG-NEXT: AND_INT T1.X, T1.X, literal.x,5753; EG-NEXT: MOV * T1.W, literal.x,5754; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00)5755; EG-NEXT: MOV * T1.Y, 0.0,5756; EG-NEXT: AND_INT T2.X, T2.X, literal.x,5757; EG-NEXT: MOV * T2.W, literal.x,5758; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)5759; EG-NEXT: MOV T2.Y, 0.0,5760; EG-NEXT: MOV T1.Z, 0.0,5761; EG-NEXT: MOV * T2.Z, 0.0,5762; EG-NEXT: MOV * T3.X, literal.x,5763; EG-NEXT: 0(0.000000e+00), 0(0.000000e+00)5764; EG-NEXT: ALU clause starting at 33:5765; EG-NEXT: AND_INT T2.X, T1.X, literal.x,5766; EG-NEXT: MOV T2.Y, 0.0,5767; EG-NEXT: MOV * T2.Z, 0.0,5768; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)5769; EG-NEXT: ALU clause starting at 37:5770; EG-NEXT: AND_INT T2.X, T0.X, literal.x,5771; EG-NEXT: MOV T2.Y, 0.0,5772; EG-NEXT: MOV * T2.Z, 0.0,5773; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)5774;5775; CM-LABEL: array_3xi16:5776; CM: ; %bb.0:5777; CM-NEXT: ALU 0, @20, KC0[], KC1[]5778; CM-NEXT: TEX 1 @125779; CM-NEXT: ALU 11, @21, KC0[], KC1[]5780; CM-NEXT: MEM_RAT MSKOR T1.XW, T3.X5781; CM-NEXT: MEM_RAT MSKOR T2.XW, T3.X5782; CM-NEXT: TEX 0 @165783; CM-NEXT: ALU 3, @33, KC0[], KC1[]5784; CM-NEXT: MEM_RAT MSKOR T2.XW, T3.X5785; CM-NEXT: TEX 0 @185786; CM-NEXT: ALU 3, @37, KC0[], KC1[]5787; CM-NEXT: MEM_RAT MSKOR T2.XW, T3.X5788; CM-NEXT: CF_END5789; CM-NEXT: Fetch clause starting at 12:5790; CM-NEXT: VTX_READ_8 T1.X, T0.X, 36, #35791; CM-NEXT: VTX_READ_16 T2.X, T0.X, 42, #35792; CM-NEXT: Fetch clause starting at 16:5793; CM-NEXT: VTX_READ_16 T1.X, T0.X, 40, #35794; CM-NEXT: Fetch clause starting at 18:5795; CM-NEXT: VTX_READ_16 T0.X, T0.X, 38, #35796; CM-NEXT: ALU clause starting at 20:5797; CM-NEXT: MOV * T0.X, 0.0,5798; CM-NEXT: ALU clause starting at 21:5799; CM-NEXT: AND_INT T1.X, T1.X, literal.x,5800; CM-NEXT: MOV * T1.W, literal.x,5801; CM-NEXT: 255(3.573311e-43), 0(0.000000e+00)5802; CM-NEXT: MOV * T1.Y, 0.0,5803; CM-NEXT: AND_INT T2.X, T2.X, literal.x,5804; CM-NEXT: MOV * T2.W, literal.x,5805; CM-NEXT: 65535(9.183409e-41), 0(0.000000e+00)5806; CM-NEXT: MOV T2.Y, 0.0,5807; CM-NEXT: MOV * T1.Z, 0.0,5808; CM-NEXT: MOV * T2.Z, 0.0,5809; CM-NEXT: MOV * T3.X, literal.x,5810; CM-NEXT: 0(0.000000e+00), 0(0.000000e+00)5811; CM-NEXT: ALU clause starting at 33:5812; CM-NEXT: AND_INT T2.X, T1.X, literal.x,5813; CM-NEXT: MOV T2.Y, 0.0,5814; CM-NEXT: MOV * T2.Z, 0.0,5815; CM-NEXT: 65535(9.183409e-41), 0(0.000000e+00)5816; CM-NEXT: ALU clause starting at 37:5817; CM-NEXT: AND_INT T2.X, T0.X, literal.x,5818; CM-NEXT: MOV T2.Y, 0.0,5819; CM-NEXT: MOV * T2.Z, 0.0,5820; CM-NEXT: 65535(9.183409e-41), 0(0.000000e+00)5821 store volatile i8 %arg0, ptr addrspace(1) poison5822 store volatile [3 x i16] %arg1, ptr addrspace(1) poison5823 ret void5824}5825 5826define amdgpu_kernel void @small_array_round_down_offset(i8, [1 x i8] %arg) {5827; SI-LABEL: small_array_round_down_offset:5828; SI: ; %bb.0:5829; SI-NEXT: s_mov_b32 s7, 0xf0005830; SI-NEXT: s_mov_b32 s6, -15831; SI-NEXT: buffer_load_ubyte v0, off, s[4:7], 0 offset:375832; SI-NEXT: s_waitcnt vmcnt(0)5833; SI-NEXT: buffer_store_byte v0, off, s[4:7], 05834; SI-NEXT: s_waitcnt vmcnt(0)5835; SI-NEXT: s_endpgm5836;5837; VI-LABEL: small_array_round_down_offset:5838; VI: ; %bb.0:5839; VI-NEXT: s_add_u32 s0, s4, 375840; VI-NEXT: s_addc_u32 s1, s5, 05841; VI-NEXT: v_mov_b32_e32 v0, s05842; VI-NEXT: v_mov_b32_e32 v1, s15843; VI-NEXT: flat_load_ubyte v0, v[0:1]5844; VI-NEXT: s_waitcnt vmcnt(0)5845; VI-NEXT: flat_store_byte v[0:1], v05846; VI-NEXT: s_waitcnt vmcnt(0)5847; VI-NEXT: s_endpgm5848;5849; GFX9-LABEL: small_array_round_down_offset:5850; GFX9: ; %bb.0:5851; GFX9-NEXT: v_mov_b32_e32 v0, 05852; GFX9-NEXT: global_load_ubyte v0, v0, s[8:9] offset:15853; GFX9-NEXT: s_waitcnt vmcnt(0)5854; GFX9-NEXT: global_store_byte v[0:1], v0, off5855; GFX9-NEXT: s_waitcnt vmcnt(0)5856; GFX9-NEXT: s_endpgm5857;5858; EGCM-LABEL: small_array_round_down_offset:5859; EGCM: ; %bb.0:5860; EGCM-NEXT: ALU 0, @8, KC0[], KC1[]5861; EGCM-NEXT: TEX 0 @65862; EGCM-NEXT: ALU 6, @9, KC0[], KC1[]5863; EGCM-NEXT: MEM_RAT MSKOR T0.XW, T1.X5864; EGCM-NEXT: CF_END5865; EGCM-NEXT: PAD5866; EGCM-NEXT: Fetch clause starting at 6:5867; EGCM-NEXT: VTX_READ_8 T0.X, T0.X, 37, #35868; EGCM-NEXT: ALU clause starting at 8:5869; EGCM-NEXT: MOV * T0.X, 0.0,5870; EGCM-NEXT: ALU clause starting at 9:5871; EGCM-NEXT: AND_INT T0.X, T0.X, literal.x,5872; EGCM-NEXT: MOV * T0.W, literal.x,5873; EGCM-NEXT: 255(3.573311e-43), 0(0.000000e+00)5874; EGCM-NEXT: MOV T0.Y, 0.0,5875; EGCM-NEXT: MOV * T0.Z, 0.0,5876; EGCM-NEXT: MOV * T1.X, literal.x,5877; EGCM-NEXT: 0(0.000000e+00), 0(0.000000e+00)5878 %val = extractvalue [1 x i8] %arg, 05879 store volatile i8 %val, ptr addrspace(1) poison5880 ret void5881}5882 5883define amdgpu_kernel void @byref_align_constant_i32_arg(ptr addrspace(1) nocapture %out, ptr addrspace(4) byref(i32) align(256) %in.byref, i32 %after.offset) {5884; SI-LABEL: byref_align_constant_i32_arg:5885; SI: ; %bb.0:5886; SI-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x495887; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x95888; SI-NEXT: s_mov_b32 s3, 0xf0005889; SI-NEXT: s_mov_b32 s2, -15890; SI-NEXT: s_waitcnt lgkmcnt(0)5891; SI-NEXT: v_mov_b32_e32 v0, s65892; SI-NEXT: buffer_store_dword v0, off, s[0:3], 05893; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)5894; SI-NEXT: v_mov_b32_e32 v0, s75895; SI-NEXT: buffer_store_dword v0, off, s[0:3], 05896; SI-NEXT: s_waitcnt vmcnt(0)5897; SI-NEXT: s_endpgm5898;5899; VI-LABEL: byref_align_constant_i32_arg:5900; VI: ; %bb.0:5901; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x245902; VI-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x1245903; VI-NEXT: s_waitcnt lgkmcnt(0)5904; VI-NEXT: v_mov_b32_e32 v0, s05905; VI-NEXT: v_mov_b32_e32 v1, s15906; VI-NEXT: v_mov_b32_e32 v2, s25907; VI-NEXT: v_mov_b32_e32 v3, s35908; VI-NEXT: flat_store_dword v[0:1], v25909; VI-NEXT: s_waitcnt vmcnt(0)5910; VI-NEXT: flat_store_dword v[0:1], v35911; VI-NEXT: s_waitcnt vmcnt(0)5912; VI-NEXT: s_endpgm5913;5914; GFX9-LABEL: byref_align_constant_i32_arg:5915; GFX9: ; %bb.0:5916; GFX9-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x1005917; GFX9-NEXT: s_load_dwordx2 s[2:3], s[8:9], 0x05918; GFX9-NEXT: v_mov_b32_e32 v0, 05919; GFX9-NEXT: s_waitcnt lgkmcnt(0)5920; GFX9-NEXT: v_mov_b32_e32 v1, s05921; GFX9-NEXT: v_mov_b32_e32 v2, s15922; GFX9-NEXT: global_store_dword v0, v1, s[2:3]5923; GFX9-NEXT: s_waitcnt vmcnt(0)5924; GFX9-NEXT: global_store_dword v0, v2, s[2:3]5925; GFX9-NEXT: s_waitcnt vmcnt(0)5926; GFX9-NEXT: s_endpgm5927;5928; EG-LABEL: byref_align_constant_i32_arg:5929; EG: ; %bb.0:5930; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]5931; EG-NEXT: TEX 0 @65932; EG-NEXT: ALU 2, @9, KC0[CB0:0-32], KC1[]5933; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T2.X, 05934; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T2.X, 15935; EG-NEXT: CF_END5936; EG-NEXT: Fetch clause starting at 6:5937; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #15938; EG-NEXT: ALU clause starting at 8:5939; EG-NEXT: MOV * T0.X, KC0[18].Y,5940; EG-NEXT: ALU clause starting at 9:5941; EG-NEXT: MOV T1.X, KC0[18].Z,5942; EG-NEXT: LSHR * T2.X, KC0[2].Y, literal.x,5943; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)5944;5945; CM-LABEL: byref_align_constant_i32_arg:5946; CM: ; %bb.0:5947; CM-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]5948; CM-NEXT: TEX 0 @65949; CM-NEXT: ALU 2, @9, KC0[CB0:0-32], KC1[]5950; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0.X, T2.X5951; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1.X, T2.X5952; CM-NEXT: CF_END5953; CM-NEXT: Fetch clause starting at 6:5954; CM-NEXT: VTX_READ_32 T0.X, T0.X, 0, #15955; CM-NEXT: ALU clause starting at 8:5956; CM-NEXT: MOV * T0.X, KC0[18].Y,5957; CM-NEXT: ALU clause starting at 9:5958; CM-NEXT: MOV * T1.X, KC0[18].Z,5959; CM-NEXT: LSHR * T2.X, KC0[2].Y, literal.x,5960; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)5961 %in = load i32, ptr addrspace(4) %in.byref5962 store volatile i32 %in, ptr addrspace(1) %out, align 45963 store volatile i32 %after.offset, ptr addrspace(1) %out, align 45964 ret void5965}5966 5967define amdgpu_kernel void @byref_natural_align_constant_v16i32_arg(ptr addrspace(1) nocapture %out, i8, ptr addrspace(4) byref(<16 x i32>) align(64) %in.byref, i32 %after.offset) {5968; SI-LABEL: byref_natural_align_constant_v16i32_arg:5969; SI: ; %bb.0:5970; SI-NEXT: s_load_dwordx16 s[8:23], s[4:5], 0x195971; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x95972; SI-NEXT: s_load_dword s4, s[4:5], 0x295973; SI-NEXT: s_mov_b32 s3, 0xf0005974; SI-NEXT: s_mov_b32 s2, -15975; SI-NEXT: s_waitcnt lgkmcnt(0)5976; SI-NEXT: v_mov_b32_e32 v0, s205977; SI-NEXT: v_mov_b32_e32 v1, s215978; SI-NEXT: v_mov_b32_e32 v2, s225979; SI-NEXT: v_mov_b32_e32 v3, s235980; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:485981; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)5982; SI-NEXT: v_mov_b32_e32 v0, s165983; SI-NEXT: v_mov_b32_e32 v1, s175984; SI-NEXT: v_mov_b32_e32 v2, s185985; SI-NEXT: v_mov_b32_e32 v3, s195986; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:325987; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)5988; SI-NEXT: v_mov_b32_e32 v0, s125989; SI-NEXT: v_mov_b32_e32 v1, s135990; SI-NEXT: v_mov_b32_e32 v2, s145991; SI-NEXT: v_mov_b32_e32 v3, s155992; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:165993; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)5994; SI-NEXT: v_mov_b32_e32 v0, s85995; SI-NEXT: v_mov_b32_e32 v1, s95996; SI-NEXT: v_mov_b32_e32 v2, s105997; SI-NEXT: v_mov_b32_e32 v3, s115998; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 05999; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)6000; SI-NEXT: v_mov_b32_e32 v0, s46001; SI-NEXT: buffer_store_dword v0, off, s[0:3], 06002; SI-NEXT: s_waitcnt vmcnt(0)6003; SI-NEXT: s_endpgm6004;6005; VI-LABEL: byref_natural_align_constant_v16i32_arg:6006; VI: ; %bb.0:6007; VI-NEXT: s_load_dwordx16 s[8:23], s[4:5], 0x646008; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x246009; VI-NEXT: s_load_dword s4, s[4:5], 0xa46010; VI-NEXT: s_waitcnt lgkmcnt(0)6011; VI-NEXT: v_mov_b32_e32 v0, s206012; VI-NEXT: s_add_u32 s2, s0, 486013; VI-NEXT: s_addc_u32 s3, s1, 06014; VI-NEXT: v_mov_b32_e32 v5, s36015; VI-NEXT: v_mov_b32_e32 v4, s26016; VI-NEXT: s_add_u32 s2, s0, 326017; VI-NEXT: v_mov_b32_e32 v1, s216018; VI-NEXT: v_mov_b32_e32 v2, s226019; VI-NEXT: v_mov_b32_e32 v3, s236020; VI-NEXT: s_addc_u32 s3, s1, 06021; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]6022; VI-NEXT: s_waitcnt vmcnt(0)6023; VI-NEXT: v_mov_b32_e32 v5, s36024; VI-NEXT: v_mov_b32_e32 v4, s26025; VI-NEXT: s_add_u32 s2, s0, 166026; VI-NEXT: v_mov_b32_e32 v0, s166027; VI-NEXT: v_mov_b32_e32 v1, s176028; VI-NEXT: v_mov_b32_e32 v2, s186029; VI-NEXT: v_mov_b32_e32 v3, s196030; VI-NEXT: s_addc_u32 s3, s1, 06031; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]6032; VI-NEXT: s_waitcnt vmcnt(0)6033; VI-NEXT: v_mov_b32_e32 v5, s36034; VI-NEXT: v_mov_b32_e32 v0, s126035; VI-NEXT: v_mov_b32_e32 v1, s136036; VI-NEXT: v_mov_b32_e32 v2, s146037; VI-NEXT: v_mov_b32_e32 v3, s156038; VI-NEXT: v_mov_b32_e32 v4, s26039; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]6040; VI-NEXT: s_waitcnt vmcnt(0)6041; VI-NEXT: v_mov_b32_e32 v5, s16042; VI-NEXT: v_mov_b32_e32 v0, s86043; VI-NEXT: v_mov_b32_e32 v1, s96044; VI-NEXT: v_mov_b32_e32 v2, s106045; VI-NEXT: v_mov_b32_e32 v3, s116046; VI-NEXT: v_mov_b32_e32 v4, s06047; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]6048; VI-NEXT: s_waitcnt vmcnt(0)6049; VI-NEXT: v_mov_b32_e32 v0, s46050; VI-NEXT: flat_store_dword v[4:5], v06051; VI-NEXT: s_waitcnt vmcnt(0)6052; VI-NEXT: s_endpgm6053;6054; GFX9-LABEL: byref_natural_align_constant_v16i32_arg:6055; GFX9: ; %bb.0:6056; GFX9-NEXT: s_load_dwordx16 s[12:27], s[8:9], 0x406057; GFX9-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x06058; GFX9-NEXT: s_load_dword s2, s[8:9], 0x806059; GFX9-NEXT: v_mov_b32_e32 v4, 06060; GFX9-NEXT: s_waitcnt lgkmcnt(0)6061; GFX9-NEXT: v_mov_b32_e32 v0, s246062; GFX9-NEXT: v_mov_b32_e32 v1, s256063; GFX9-NEXT: v_mov_b32_e32 v2, s266064; GFX9-NEXT: v_mov_b32_e32 v3, s276065; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1] offset:486066; GFX9-NEXT: s_waitcnt vmcnt(0)6067; GFX9-NEXT: v_mov_b32_e32 v0, s206068; GFX9-NEXT: v_mov_b32_e32 v1, s216069; GFX9-NEXT: v_mov_b32_e32 v2, s226070; GFX9-NEXT: v_mov_b32_e32 v3, s236071; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1] offset:326072; GFX9-NEXT: s_waitcnt vmcnt(0)6073; GFX9-NEXT: v_mov_b32_e32 v0, s166074; GFX9-NEXT: v_mov_b32_e32 v1, s176075; GFX9-NEXT: v_mov_b32_e32 v2, s186076; GFX9-NEXT: v_mov_b32_e32 v3, s196077; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1] offset:166078; GFX9-NEXT: s_waitcnt vmcnt(0)6079; GFX9-NEXT: v_mov_b32_e32 v0, s126080; GFX9-NEXT: v_mov_b32_e32 v1, s136081; GFX9-NEXT: v_mov_b32_e32 v2, s146082; GFX9-NEXT: v_mov_b32_e32 v3, s156083; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]6084; GFX9-NEXT: s_waitcnt vmcnt(0)6085; GFX9-NEXT: v_mov_b32_e32 v0, s26086; GFX9-NEXT: global_store_dword v4, v0, s[0:1]6087; GFX9-NEXT: s_waitcnt vmcnt(0)6088; GFX9-NEXT: s_endpgm6089;6090; EG-LABEL: byref_natural_align_constant_v16i32_arg:6091; EG: ; %bb.0:6092; EG-NEXT: ALU 0, @24, KC0[CB0:0-32], KC1[]6093; EG-NEXT: TEX 0 @166094; EG-NEXT: ALU 3, @25, KC0[CB0:0-32], KC1[]6095; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XYZW, T2.X, 06096; EG-NEXT: ALU 3, @29, KC0[CB0:0-32], KC1[]6097; EG-NEXT: TEX 0 @186098; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T2.XYZW, T1.X, 06099; EG-NEXT: ALU 3, @33, KC0[CB0:0-32], KC1[]6100; EG-NEXT: TEX 0 @206101; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T2.XYZW, T1.X, 06102; EG-NEXT: ALU 2, @37, KC0[CB0:0-32], KC1[]6103; EG-NEXT: TEX 0 @226104; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T2.X, 06105; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T2.X, 16106; EG-NEXT: CF_END6107; EG-NEXT: PAD6108; EG-NEXT: Fetch clause starting at 16:6109; EG-NEXT: VTX_READ_128 T1.XYZW, T0.X, 48, #16110; EG-NEXT: Fetch clause starting at 18:6111; EG-NEXT: VTX_READ_128 T2.XYZW, T0.X, 32, #16112; EG-NEXT: Fetch clause starting at 20:6113; EG-NEXT: VTX_READ_128 T2.XYZW, T0.X, 16, #16114; EG-NEXT: Fetch clause starting at 22:6115; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 0, #16116; EG-NEXT: ALU clause starting at 24:6117; EG-NEXT: MOV * T0.X, KC0[6].Y,6118; EG-NEXT: ALU clause starting at 25:6119; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x,6120; EG-NEXT: 48(6.726233e-44), 0(0.000000e+00)6121; EG-NEXT: LSHR * T2.X, PV.W, literal.x,6122; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)6123; EG-NEXT: ALU clause starting at 29:6124; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x,6125; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)6126; EG-NEXT: LSHR * T1.X, PV.W, literal.x,6127; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)6128; EG-NEXT: ALU clause starting at 33:6129; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x,6130; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)6131; EG-NEXT: LSHR * T1.X, PV.W, literal.x,6132; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)6133; EG-NEXT: ALU clause starting at 37:6134; EG-NEXT: MOV T1.X, KC0[10].Y,6135; EG-NEXT: LSHR * T2.X, KC0[2].Y, literal.x,6136; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)6137;6138; CM-LABEL: byref_natural_align_constant_v16i32_arg:6139; CM: ; %bb.0:6140; CM-NEXT: ALU 0, @24, KC0[CB0:0-32], KC1[]6141; CM-NEXT: TEX 0 @166142; CM-NEXT: ALU 3, @25, KC0[CB0:0-32], KC1[]6143; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1, T2.X6144; CM-NEXT: ALU 3, @29, KC0[CB0:0-32], KC1[]6145; CM-NEXT: TEX 0 @186146; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T2, T1.X6147; CM-NEXT: ALU 3, @33, KC0[CB0:0-32], KC1[]6148; CM-NEXT: TEX 0 @206149; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T2, T1.X6150; CM-NEXT: ALU 2, @37, KC0[CB0:0-32], KC1[]6151; CM-NEXT: TEX 0 @226152; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0, T2.X6153; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1.X, T2.X6154; CM-NEXT: CF_END6155; CM-NEXT: PAD6156; CM-NEXT: Fetch clause starting at 16:6157; CM-NEXT: VTX_READ_128 T1.XYZW, T0.X, 48, #16158; CM-NEXT: Fetch clause starting at 18:6159; CM-NEXT: VTX_READ_128 T2.XYZW, T0.X, 32, #16160; CM-NEXT: Fetch clause starting at 20:6161; CM-NEXT: VTX_READ_128 T2.XYZW, T0.X, 16, #16162; CM-NEXT: Fetch clause starting at 22:6163; CM-NEXT: VTX_READ_128 T0.XYZW, T0.X, 0, #16164; CM-NEXT: ALU clause starting at 24:6165; CM-NEXT: MOV * T0.X, KC0[6].Y,6166; CM-NEXT: ALU clause starting at 25:6167; CM-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x,6168; CM-NEXT: 48(6.726233e-44), 0(0.000000e+00)6169; CM-NEXT: LSHR * T2.X, PV.W, literal.x,6170; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)6171; CM-NEXT: ALU clause starting at 29:6172; CM-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x,6173; CM-NEXT: 32(4.484155e-44), 0(0.000000e+00)6174; CM-NEXT: LSHR * T1.X, PV.W, literal.x,6175; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)6176; CM-NEXT: ALU clause starting at 33:6177; CM-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x,6178; CM-NEXT: 16(2.242078e-44), 0(0.000000e+00)6179; CM-NEXT: LSHR * T1.X, PV.W, literal.x,6180; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)6181; CM-NEXT: ALU clause starting at 37:6182; CM-NEXT: MOV * T1.X, KC0[10].Y,6183; CM-NEXT: LSHR * T2.X, KC0[2].Y, literal.x,6184; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)6185 %in = load <16 x i32>, ptr addrspace(4) %in.byref6186 store volatile <16 x i32> %in, ptr addrspace(1) %out, align 46187 store volatile i32 %after.offset, ptr addrspace(1) %out, align 46188 ret void6189}6190