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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 62; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx900 -amdgpu-ir-lower-kernel-arguments=0 < %s | FileCheck -enable-var-scope -check-prefixes=GCN %s3 4; Repeat of some problematic tests in kernel-args.ll, with the IR5; argument lowering pass disabled. Struct padding needs to be6; accounted for, as well as legalization of types changing offsets.7 8define amdgpu_kernel void @i1_arg(ptr addrspace(1) %out, i1 %x) #0 {9; GCN-LABEL: i1_arg:10; GCN: ; %bb.0:11; GCN-NEXT: s_load_dword s2, s[8:9], 0x812; GCN-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x013; GCN-NEXT: v_mov_b32_e32 v0, 014; GCN-NEXT: s_waitcnt lgkmcnt(0)15; GCN-NEXT: s_and_b32 s2, s2, 116; GCN-NEXT: v_mov_b32_e32 v1, s217; GCN-NEXT: global_store_byte v0, v1, s[0:1]18; GCN-NEXT: s_endpgm19 store i1 %x, ptr addrspace(1) %out, align 120 ret void21}22; GCN: .amdhsa_kernarg_size 1223 24define amdgpu_kernel void @v3i8_arg(ptr addrspace(1) nocapture %out, <3 x i8> %in) #0 {25; GCN-LABEL: v3i8_arg:26; GCN: ; %bb.0: ; %entry27; GCN-NEXT: s_load_dword s2, s[8:9], 0x828; GCN-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x029; GCN-NEXT: v_mov_b32_e32 v0, 030; GCN-NEXT: s_waitcnt lgkmcnt(0)31; GCN-NEXT: v_mov_b32_e32 v1, s232; GCN-NEXT: global_store_byte_d16_hi v0, v1, s[0:1] offset:233; GCN-NEXT: global_store_short v0, v1, s[0:1]34; GCN-NEXT: s_endpgm35entry:36 store <3 x i8> %in, ptr addrspace(1) %out, align 437 ret void38}39; GCN: .amdhsa_kernarg_size 1240 41define amdgpu_kernel void @v5i8_arg(<5 x i8> %in) nounwind {42; GCN-LABEL: v5i8_arg:43; GCN: ; %bb.0:44; GCN-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x045; GCN-NEXT: v_mov_b32_e32 v0, 446; GCN-NEXT: v_mov_b32_e32 v1, 047; GCN-NEXT: s_waitcnt lgkmcnt(0)48; GCN-NEXT: s_lshr_b32 s3, s0, 2449; GCN-NEXT: s_and_b32 s2, s0, 0xffff50; GCN-NEXT: s_bfe_u32 s0, s0, 0x8001051; GCN-NEXT: v_mov_b32_e32 v2, s152; GCN-NEXT: s_lshl_b32 s1, s3, 853; GCN-NEXT: s_or_b32 s0, s0, s154; GCN-NEXT: s_lshl_b32 s0, s0, 1655; GCN-NEXT: s_or_b32 s0, s2, s056; GCN-NEXT: global_store_byte v[0:1], v2, off57; GCN-NEXT: v_mov_b32_e32 v0, 058; GCN-NEXT: v_mov_b32_e32 v1, 059; GCN-NEXT: v_mov_b32_e32 v2, s060; GCN-NEXT: global_store_dword v[0:1], v2, off61; GCN-NEXT: s_endpgm62 store <5 x i8> %in, ptr addrspace(1) null63 ret void64}65 66define amdgpu_kernel void @v6i8_arg(<6 x i8> %in) nounwind {67; GCN-LABEL: v6i8_arg:68; GCN: ; %bb.0:69; GCN-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x070; GCN-NEXT: v_mov_b32_e32 v0, 471; GCN-NEXT: v_mov_b32_e32 v1, 072; GCN-NEXT: s_waitcnt lgkmcnt(0)73; GCN-NEXT: s_lshr_b32 s3, s0, 2474; GCN-NEXT: s_and_b32 s2, s0, 0xffff75; GCN-NEXT: s_bfe_u32 s0, s0, 0x8001076; GCN-NEXT: v_mov_b32_e32 v2, s177; GCN-NEXT: s_lshl_b32 s1, s3, 878; GCN-NEXT: s_or_b32 s0, s0, s179; GCN-NEXT: s_lshl_b32 s0, s0, 1680; GCN-NEXT: s_or_b32 s0, s2, s081; GCN-NEXT: global_store_short v[0:1], v2, off82; GCN-NEXT: v_mov_b32_e32 v0, 083; GCN-NEXT: v_mov_b32_e32 v1, 084; GCN-NEXT: v_mov_b32_e32 v2, s085; GCN-NEXT: global_store_dword v[0:1], v2, off86; GCN-NEXT: s_endpgm87 store <6 x i8> %in, ptr addrspace(1) null88 ret void89}90 91define amdgpu_kernel void @v5i16_arg(<5 x i16> %in) nounwind {92; GCN-LABEL: v5i16_arg:93; GCN: ; %bb.0:94; GCN-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x095; GCN-NEXT: v_mov_b32_e32 v0, 896; GCN-NEXT: v_mov_b32_e32 v1, 097; GCN-NEXT: v_mov_b32_e32 v2, 098; GCN-NEXT: v_mov_b32_e32 v3, 099; GCN-NEXT: s_waitcnt lgkmcnt(0)100; GCN-NEXT: v_mov_b32_e32 v6, s2101; GCN-NEXT: v_mov_b32_e32 v4, s0102; GCN-NEXT: v_mov_b32_e32 v5, s1103; GCN-NEXT: global_store_short v[0:1], v6, off104; GCN-NEXT: global_store_dwordx2 v[2:3], v[4:5], off105; GCN-NEXT: s_endpgm106 store <5 x i16> %in, ptr addrspace(1) null107 ret void108}109 110define amdgpu_kernel void @v6i16_arg(<6 x i16> %in) nounwind {111; GCN-LABEL: v6i16_arg:112; GCN: ; %bb.0:113; GCN-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0114; GCN-NEXT: v_mov_b32_e32 v3, 0115; GCN-NEXT: v_mov_b32_e32 v4, 0116; GCN-NEXT: s_waitcnt lgkmcnt(0)117; GCN-NEXT: v_mov_b32_e32 v0, s0118; GCN-NEXT: v_mov_b32_e32 v1, s1119; GCN-NEXT: v_mov_b32_e32 v2, s2120; GCN-NEXT: global_store_dwordx3 v[3:4], v[0:2], off121; GCN-NEXT: s_endpgm122 store <6 x i16> %in, ptr addrspace(1) null123 ret void124}125 126define amdgpu_kernel void @v5i32_arg(<5 x i32> %in) nounwind {127; GCN-LABEL: v5i32_arg:128; GCN: ; %bb.0:129; GCN-NEXT: s_load_dword s4, s[8:9], 0x10130; GCN-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0131; GCN-NEXT: v_mov_b32_e32 v4, 16132; GCN-NEXT: v_mov_b32_e32 v5, 0133; GCN-NEXT: v_mov_b32_e32 v6, 0134; GCN-NEXT: s_waitcnt lgkmcnt(0)135; GCN-NEXT: v_mov_b32_e32 v8, s4136; GCN-NEXT: v_mov_b32_e32 v0, s0137; GCN-NEXT: v_mov_b32_e32 v7, 0138; GCN-NEXT: v_mov_b32_e32 v1, s1139; GCN-NEXT: v_mov_b32_e32 v2, s2140; GCN-NEXT: v_mov_b32_e32 v3, s3141; GCN-NEXT: global_store_dword v[4:5], v8, off142; GCN-NEXT: global_store_dwordx4 v[6:7], v[0:3], off143; GCN-NEXT: s_endpgm144 store <5 x i32> %in, ptr addrspace(1) null145 ret void146}147 148define amdgpu_kernel void @v6i32_arg(<6 x i32> %in) nounwind {149; GCN-LABEL: v6i32_arg:150; GCN: ; %bb.0:151; GCN-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x10152; GCN-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0153; GCN-NEXT: v_mov_b32_e32 v4, 16154; GCN-NEXT: v_mov_b32_e32 v5, 0155; GCN-NEXT: v_mov_b32_e32 v6, 0156; GCN-NEXT: s_waitcnt lgkmcnt(0)157; GCN-NEXT: v_mov_b32_e32 v9, s5158; GCN-NEXT: v_mov_b32_e32 v8, s4159; GCN-NEXT: v_mov_b32_e32 v0, s0160; GCN-NEXT: v_mov_b32_e32 v7, 0161; GCN-NEXT: v_mov_b32_e32 v1, s1162; GCN-NEXT: v_mov_b32_e32 v2, s2163; GCN-NEXT: v_mov_b32_e32 v3, s3164; GCN-NEXT: global_store_dwordx2 v[4:5], v[8:9], off165; GCN-NEXT: global_store_dwordx4 v[6:7], v[0:3], off166; GCN-NEXT: s_endpgm167 store <6 x i32> %in, ptr addrspace(1) null168 ret void169}170 171define amdgpu_kernel void @i65_arg(ptr addrspace(1) nocapture %out, i65 %in) #0 {172; GCN-LABEL: i65_arg:173; GCN: ; %bb.0: ; %entry174; GCN-NEXT: s_load_dword s4, s[8:9], 0x10175; GCN-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0176; GCN-NEXT: v_mov_b32_e32 v2, 0177; GCN-NEXT: s_waitcnt lgkmcnt(0)178; GCN-NEXT: s_and_b32 s4, s4, 1179; GCN-NEXT: v_mov_b32_e32 v0, s2180; GCN-NEXT: v_mov_b32_e32 v3, s4181; GCN-NEXT: v_mov_b32_e32 v1, s3182; GCN-NEXT: global_store_byte v2, v3, s[0:1] offset:8183; GCN-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]184; GCN-NEXT: s_endpgm185entry:186 store i65 %in, ptr addrspace(1) %out, align 4187 ret void188}189; GCN: .amdhsa_kernarg_size 24190 191define amdgpu_kernel void @empty_struct_arg({} %in) #0 {192; GCN-LABEL: empty_struct_arg:193; GCN: ; %bb.0:194; GCN-NEXT: s_endpgm195 ret void196}197; GCN: .amdhsa_kernarg_size 0198 199; The correct load offsets for these:200; load 4 from 0,201; load 8 from 8202; load 4 from 24203; load 8 from 32204 205; With the SelectionDAG argument lowering, the alignments for the206; struct members is not properly considered, making these wrong.207 208; FIXME: Total argument size is computed wrong209define amdgpu_kernel void @struct_argument_alignment({i32, i64} %arg0, i8, {i32, i64} %arg1) #0 {210; GCN-LABEL: struct_argument_alignment:211; GCN: ; %bb.0:212; GCN-NEXT: s_load_dword s4, s[8:9], 0x0213; GCN-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x8214; GCN-NEXT: s_load_dword s5, s[8:9], 0x18215; GCN-NEXT: s_load_dwordx2 s[2:3], s[8:9], 0x20216; GCN-NEXT: v_mov_b32_e32 v0, 0217; GCN-NEXT: v_mov_b32_e32 v1, 0218; GCN-NEXT: s_waitcnt lgkmcnt(0)219; GCN-NEXT: v_mov_b32_e32 v2, s4220; GCN-NEXT: global_store_dword v[0:1], v2, off221; GCN-NEXT: s_waitcnt vmcnt(0)222; GCN-NEXT: v_mov_b32_e32 v3, s1223; GCN-NEXT: v_mov_b32_e32 v2, s0224; GCN-NEXT: global_store_dwordx2 v[0:1], v[2:3], off225; GCN-NEXT: s_waitcnt vmcnt(0)226; GCN-NEXT: v_mov_b32_e32 v2, s5227; GCN-NEXT: global_store_dword v[0:1], v2, off228; GCN-NEXT: s_waitcnt vmcnt(0)229; GCN-NEXT: v_mov_b32_e32 v2, s2230; GCN-NEXT: v_mov_b32_e32 v3, s3231; GCN-NEXT: global_store_dwordx2 v[0:1], v[2:3], off232; GCN-NEXT: s_waitcnt vmcnt(0)233; GCN-NEXT: s_endpgm234 %val0 = extractvalue {i32, i64} %arg0, 0235 %val1 = extractvalue {i32, i64} %arg0, 1236 %val2 = extractvalue {i32, i64} %arg1, 0237 %val3 = extractvalue {i32, i64} %arg1, 1238 store volatile i32 %val0, ptr addrspace(1) null239 store volatile i64 %val1, ptr addrspace(1) null240 store volatile i32 %val2, ptr addrspace(1) null241 store volatile i64 %val3, ptr addrspace(1) null242 ret void243}244; GCN: .amdhsa_kernarg_size 40245 246; No padding between i8 and next struct, but round up at end to 4 byte247; multiple.248define amdgpu_kernel void @packed_struct_argument_alignment(<{i32, i64}> %arg0, i8, <{i32, i64}> %arg1) #0 {249; GCN-LABEL: packed_struct_argument_alignment:250; GCN: ; %bb.0:251; GCN-NEXT: v_mov_b32_e32 v2, 0252; GCN-NEXT: global_load_dword v6, v2, s[8:9] offset:13253; GCN-NEXT: global_load_dwordx2 v[0:1], v2, s[8:9] offset:17254; GCN-NEXT: s_load_dword s2, s[8:9], 0x0255; GCN-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x4256; GCN-NEXT: v_mov_b32_e32 v2, 0257; GCN-NEXT: v_mov_b32_e32 v3, 0258; GCN-NEXT: s_waitcnt lgkmcnt(0)259; GCN-NEXT: v_mov_b32_e32 v7, s2260; GCN-NEXT: v_mov_b32_e32 v5, s1261; GCN-NEXT: v_mov_b32_e32 v4, s0262; GCN-NEXT: global_store_dword v[2:3], v7, off263; GCN-NEXT: s_waitcnt vmcnt(0)264; GCN-NEXT: global_store_dwordx2 v[2:3], v[4:5], off265; GCN-NEXT: s_waitcnt vmcnt(0)266; GCN-NEXT: global_store_dword v[2:3], v6, off267; GCN-NEXT: s_waitcnt vmcnt(0)268; GCN-NEXT: global_store_dwordx2 v[2:3], v[0:1], off269; GCN-NEXT: s_waitcnt vmcnt(0)270; GCN-NEXT: s_endpgm271 %val0 = extractvalue <{i32, i64}> %arg0, 0272 %val1 = extractvalue <{i32, i64}> %arg0, 1273 %val2 = extractvalue <{i32, i64}> %arg1, 0274 %val3 = extractvalue <{i32, i64}> %arg1, 1275 store volatile i32 %val0, ptr addrspace(1) null276 store volatile i64 %val1, ptr addrspace(1) null277 store volatile i32 %val2, ptr addrspace(1) null278 store volatile i64 %val3, ptr addrspace(1) null279 ret void280}281; GCN: .amdhsa_kernarg_size 28282 283define amdgpu_kernel void @struct_argument_alignment_after({i32, i64} %arg0, i8, {i32, i64} %arg2, i8, <4 x i32> %arg4) #0 {284; GCN-LABEL: struct_argument_alignment_after:285; GCN: ; %bb.0:286; GCN-NEXT: s_load_dword s10, s[8:9], 0x0287; GCN-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x8288; GCN-NEXT: s_load_dword s11, s[8:9], 0x18289; GCN-NEXT: s_load_dwordx2 s[6:7], s[8:9], 0x20290; GCN-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x30291; GCN-NEXT: v_mov_b32_e32 v4, 0292; GCN-NEXT: v_mov_b32_e32 v5, 0293; GCN-NEXT: s_waitcnt lgkmcnt(0)294; GCN-NEXT: v_mov_b32_e32 v0, s10295; GCN-NEXT: global_store_dword v[4:5], v0, off296; GCN-NEXT: s_waitcnt vmcnt(0)297; GCN-NEXT: v_mov_b32_e32 v0, s4298; GCN-NEXT: v_mov_b32_e32 v1, s5299; GCN-NEXT: global_store_dwordx2 v[4:5], v[0:1], off300; GCN-NEXT: s_waitcnt vmcnt(0)301; GCN-NEXT: v_mov_b32_e32 v0, s11302; GCN-NEXT: global_store_dword v[4:5], v0, off303; GCN-NEXT: s_waitcnt vmcnt(0)304; GCN-NEXT: v_mov_b32_e32 v0, s6305; GCN-NEXT: v_mov_b32_e32 v1, s7306; GCN-NEXT: global_store_dwordx2 v[4:5], v[0:1], off307; GCN-NEXT: s_waitcnt vmcnt(0)308; GCN-NEXT: v_mov_b32_e32 v0, s0309; GCN-NEXT: v_mov_b32_e32 v1, s1310; GCN-NEXT: v_mov_b32_e32 v2, s2311; GCN-NEXT: v_mov_b32_e32 v3, s3312; GCN-NEXT: global_store_dwordx4 v[4:5], v[0:3], off313; GCN-NEXT: s_waitcnt vmcnt(0)314; GCN-NEXT: s_endpgm315 %val0 = extractvalue {i32, i64} %arg0, 0316 %val1 = extractvalue {i32, i64} %arg0, 1317 %val2 = extractvalue {i32, i64} %arg2, 0318 %val3 = extractvalue {i32, i64} %arg2, 1319 store volatile i32 %val0, ptr addrspace(1) null320 store volatile i64 %val1, ptr addrspace(1) null321 store volatile i32 %val2, ptr addrspace(1) null322 store volatile i64 %val3, ptr addrspace(1) null323 store volatile <4 x i32> %arg4, ptr addrspace(1) null324 ret void325}326; GCN: .amdhsa_kernarg_size 64327 328define amdgpu_kernel void @array_3xi32(i16 %arg0, [3 x i32] %arg1) {329; GCN-LABEL: array_3xi32:330; GCN: ; %bb.0:331; GCN-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0332; GCN-NEXT: s_waitcnt lgkmcnt(0)333; GCN-NEXT: v_mov_b32_e32 v0, s0334; GCN-NEXT: v_mov_b32_e32 v1, s3335; GCN-NEXT: v_mov_b32_e32 v2, s2336; GCN-NEXT: global_store_short v[0:1], v0, off337; GCN-NEXT: s_waitcnt vmcnt(0)338; GCN-NEXT: global_store_dword v[0:1], v1, off339; GCN-NEXT: s_waitcnt vmcnt(0)340; GCN-NEXT: global_store_dword v[0:1], v2, off341; GCN-NEXT: s_waitcnt vmcnt(0)342; GCN-NEXT: v_mov_b32_e32 v0, s1343; GCN-NEXT: global_store_dword v[0:1], v0, off344; GCN-NEXT: s_waitcnt vmcnt(0)345; GCN-NEXT: s_endpgm346 store volatile i16 %arg0, ptr addrspace(1) poison347 store volatile [3 x i32] %arg1, ptr addrspace(1) poison348 ret void349}350 351define amdgpu_kernel void @array_3xi16(i8 %arg0, [3 x i16] %arg1) {352; GCN-LABEL: array_3xi16:353; GCN: ; %bb.0:354; GCN-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0355; GCN-NEXT: s_waitcnt lgkmcnt(0)356; GCN-NEXT: v_mov_b32_e32 v0, s0357; GCN-NEXT: v_mov_b32_e32 v1, s1358; GCN-NEXT: global_store_byte v[0:1], v0, off359; GCN-NEXT: s_waitcnt vmcnt(0)360; GCN-NEXT: global_store_short_d16_hi v[0:1], v1, off361; GCN-NEXT: s_waitcnt vmcnt(0)362; GCN-NEXT: global_store_short v[0:1], v1, off363; GCN-NEXT: s_waitcnt vmcnt(0)364; GCN-NEXT: global_store_short_d16_hi v[0:1], v0, off365; GCN-NEXT: s_waitcnt vmcnt(0)366; GCN-NEXT: s_endpgm367 store volatile i8 %arg0, ptr addrspace(1) poison368 store volatile [3 x i16] %arg1, ptr addrspace(1) poison369 ret void370}371 372define amdgpu_kernel void @v2i15_arg(ptr addrspace(1) nocapture %out, <2 x i15> %in) #0 {373; GCN-LABEL: v2i15_arg:374; GCN: ; %bb.0: ; %entry375; GCN-NEXT: s_load_dword s2, s[8:9], 0x8376; GCN-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0377; GCN-NEXT: v_mov_b32_e32 v0, 0378; GCN-NEXT: s_waitcnt lgkmcnt(0)379; GCN-NEXT: s_and_b32 s3, s2, 0x7fff380; GCN-NEXT: s_bfe_u32 s2, s2, 0x100010381; GCN-NEXT: s_lshl_b32 s2, s2, 15382; GCN-NEXT: s_or_b32 s2, s3, s2383; GCN-NEXT: s_andn2_b32 s2, s2, -2.0384; GCN-NEXT: v_mov_b32_e32 v1, s2385; GCN-NEXT: global_store_dword v0, v1, s[0:1]386; GCN-NEXT: s_endpgm387entry:388 store <2 x i15> %in, ptr addrspace(1) %out, align 4389 ret void390}391 392define amdgpu_kernel void @v3i15_arg(ptr addrspace(1) nocapture %out, <3 x i15> %in) #0 {393; GCN-LABEL: v3i15_arg:394; GCN: ; %bb.0: ; %entry395; GCN-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0396; GCN-NEXT: v_mov_b32_e32 v0, 0397; GCN-NEXT: s_waitcnt lgkmcnt(0)398; GCN-NEXT: s_and_b32 s4, s3, 0xffff399; GCN-NEXT: s_and_b32 s5, s2, 0x7fff400; GCN-NEXT: s_lshr_b32 s6, s2, 1401; GCN-NEXT: s_lshl_b64 s[2:3], s[4:5], 30402; GCN-NEXT: s_and_b32 s4, s6, 0x3fff8000403; GCN-NEXT: s_and_b32 s6, s3, 0x1fff404; GCN-NEXT: s_or_b32 s4, s5, s4405; GCN-NEXT: s_mov_b32 s5, 0406; GCN-NEXT: v_mov_b32_e32 v1, s6407; GCN-NEXT: s_or_b64 s[2:3], s[4:5], s[2:3]408; GCN-NEXT: global_store_short v0, v1, s[0:1] offset:4409; GCN-NEXT: v_mov_b32_e32 v1, s2410; GCN-NEXT: global_store_dword v0, v1, s[0:1]411; GCN-NEXT: s_endpgm412entry:413 store <3 x i15> %in, ptr addrspace(1) %out, align 4414 ret void415}416 417; Byref pointers should only be treated as offsets from kernarg418define amdgpu_kernel void @byref_constant_i8_arg(ptr addrspace(1) nocapture %out, ptr addrspace(4) byref(i8) %in.byref) #0 {419; GCN-LABEL: byref_constant_i8_arg:420; GCN: ; %bb.0:421; GCN-NEXT: v_mov_b32_e32 v0, 0422; GCN-NEXT: global_load_ubyte v1, v0, s[8:9] offset:8423; GCN-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0424; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)425; GCN-NEXT: global_store_dword v0, v1, s[0:1]426; GCN-NEXT: s_endpgm427 %in = load i8, ptr addrspace(4) %in.byref428 %ext = zext i8 %in to i32429 store i32 %ext, ptr addrspace(1) %out, align 4430 ret void431}432; GCN: .amdhsa_kernarg_size 12433 434 435define amdgpu_kernel void @byref_constant_i16_arg(ptr addrspace(1) nocapture %out, ptr addrspace(4) byref(i16) %in.byref) #0 {436; GCN-LABEL: byref_constant_i16_arg:437; GCN: ; %bb.0:438; GCN-NEXT: v_mov_b32_e32 v0, 0439; GCN-NEXT: global_load_ushort v1, v0, s[8:9] offset:8440; GCN-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0441; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)442; GCN-NEXT: global_store_dword v0, v1, s[0:1]443; GCN-NEXT: s_endpgm444 %in = load i16, ptr addrspace(4) %in.byref445 %ext = zext i16 %in to i32446 store i32 %ext, ptr addrspace(1) %out, align 4447 ret void448}449; GCN: .amdhsa_kernarg_size 12450 451define amdgpu_kernel void @byref_constant_i32_arg(ptr addrspace(1) nocapture %out, ptr addrspace(4) byref(i32) %in.byref, i32 %after.offset) #0 {452; GCN-LABEL: byref_constant_i32_arg:453; GCN: ; %bb.0:454; GCN-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0455; GCN-NEXT: v_mov_b32_e32 v0, 0456; GCN-NEXT: s_waitcnt lgkmcnt(0)457; GCN-NEXT: v_mov_b32_e32 v1, s2458; GCN-NEXT: v_mov_b32_e32 v2, s3459; GCN-NEXT: global_store_dword v0, v1, s[0:1]460; GCN-NEXT: s_waitcnt vmcnt(0)461; GCN-NEXT: global_store_dword v0, v2, s[0:1]462; GCN-NEXT: s_waitcnt vmcnt(0)463; GCN-NEXT: s_endpgm464 %in = load i32, ptr addrspace(4) %in.byref465 store volatile i32 %in, ptr addrspace(1) %out, align 4466 store volatile i32 %after.offset, ptr addrspace(1) %out, align 4467 ret void468}469; GCN: .amdhsa_kernarg_size 16470 471define amdgpu_kernel void @byref_constant_v4i32_arg(ptr addrspace(1) nocapture %out, ptr addrspace(4) byref(<4 x i32>) %in.byref, i32 %after.offset) #0 {472; GCN-LABEL: byref_constant_v4i32_arg:473; GCN: ; %bb.0:474; GCN-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x10475; GCN-NEXT: s_load_dword s6, s[8:9], 0x20476; GCN-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x0477; GCN-NEXT: v_mov_b32_e32 v4, 0478; GCN-NEXT: s_waitcnt lgkmcnt(0)479; GCN-NEXT: v_mov_b32_e32 v0, s0480; GCN-NEXT: v_mov_b32_e32 v1, s1481; GCN-NEXT: v_mov_b32_e32 v2, s2482; GCN-NEXT: v_mov_b32_e32 v3, s3483; GCN-NEXT: v_mov_b32_e32 v5, s6484; GCN-NEXT: global_store_dwordx4 v4, v[0:3], s[4:5]485; GCN-NEXT: s_waitcnt vmcnt(0)486; GCN-NEXT: global_store_dword v4, v5, s[4:5]487; GCN-NEXT: s_waitcnt vmcnt(0)488; GCN-NEXT: s_endpgm489 %in = load <4 x i32>, ptr addrspace(4) %in.byref490 store volatile <4 x i32> %in, ptr addrspace(1) %out, align 4491 store volatile i32 %after.offset, ptr addrspace(1) %out, align 4492 ret void493}494; GCN: .amdhsa_kernarg_size 36495 496define amdgpu_kernel void @byref_align_constant_i32_arg(ptr addrspace(1) nocapture %out, ptr addrspace(4) byref(i32) align(256) %in.byref, i32 %after.offset) #0 {497; GCN-LABEL: byref_align_constant_i32_arg:498; GCN: ; %bb.0:499; GCN-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x100500; GCN-NEXT: s_load_dwordx2 s[2:3], s[8:9], 0x0501; GCN-NEXT: v_mov_b32_e32 v0, 0502; GCN-NEXT: s_waitcnt lgkmcnt(0)503; GCN-NEXT: v_mov_b32_e32 v1, s0504; GCN-NEXT: v_mov_b32_e32 v2, s1505; GCN-NEXT: global_store_dword v0, v1, s[2:3]506; GCN-NEXT: s_waitcnt vmcnt(0)507; GCN-NEXT: global_store_dword v0, v2, s[2:3]508; GCN-NEXT: s_waitcnt vmcnt(0)509; GCN-NEXT: s_endpgm510 %in = load i32, ptr addrspace(4) %in.byref511 store volatile i32 %in, ptr addrspace(1) %out, align 4512 store volatile i32 %after.offset, ptr addrspace(1) %out, align 4513 ret void514}515; GCN: .amdhsa_kernarg_size 264516 517define amdgpu_kernel void @byref_natural_align_constant_v16i32_arg(ptr addrspace(1) nocapture %out, i8, ptr addrspace(4) byref(<16 x i32>) align(64) %in.byref, i32 %after.offset) #0 {518; GCN-LABEL: byref_natural_align_constant_v16i32_arg:519; GCN: ; %bb.0:520; GCN-NEXT: s_load_dwordx16 s[12:27], s[8:9], 0x40521; GCN-NEXT: s_load_dword s2, s[8:9], 0x80522; GCN-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0523; GCN-NEXT: v_mov_b32_e32 v4, 0524; GCN-NEXT: s_waitcnt lgkmcnt(0)525; GCN-NEXT: v_mov_b32_e32 v0, s24526; GCN-NEXT: v_mov_b32_e32 v1, s25527; GCN-NEXT: v_mov_b32_e32 v2, s26528; GCN-NEXT: v_mov_b32_e32 v3, s27529; GCN-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1] offset:48530; GCN-NEXT: s_waitcnt vmcnt(0)531; GCN-NEXT: v_mov_b32_e32 v0, s20532; GCN-NEXT: v_mov_b32_e32 v1, s21533; GCN-NEXT: v_mov_b32_e32 v2, s22534; GCN-NEXT: v_mov_b32_e32 v3, s23535; GCN-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1] offset:32536; GCN-NEXT: s_waitcnt vmcnt(0)537; GCN-NEXT: v_mov_b32_e32 v0, s16538; GCN-NEXT: v_mov_b32_e32 v1, s17539; GCN-NEXT: v_mov_b32_e32 v2, s18540; GCN-NEXT: v_mov_b32_e32 v3, s19541; GCN-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1] offset:16542; GCN-NEXT: s_waitcnt vmcnt(0)543; GCN-NEXT: v_mov_b32_e32 v0, s12544; GCN-NEXT: v_mov_b32_e32 v1, s13545; GCN-NEXT: v_mov_b32_e32 v2, s14546; GCN-NEXT: v_mov_b32_e32 v3, s15547; GCN-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]548; GCN-NEXT: s_waitcnt vmcnt(0)549; GCN-NEXT: v_mov_b32_e32 v0, s2550; GCN-NEXT: global_store_dword v4, v0, s[0:1]551; GCN-NEXT: s_waitcnt vmcnt(0)552; GCN-NEXT: s_endpgm553 %in = load <16 x i32>, ptr addrspace(4) %in.byref554 store volatile <16 x i32> %in, ptr addrspace(1) %out, align 4555 store volatile i32 %after.offset, ptr addrspace(1) %out, align 4556 ret void557}558; GCN: .amdhsa_kernarg_size 132559 560; Also accept byref kernel arguments with other global address spaces.561define amdgpu_kernel void @byref_global_i32_arg(ptr addrspace(1) nocapture %out, ptr addrspace(1) byref(i32) %in.byref) #0 {562; GCN-LABEL: byref_global_i32_arg:563; GCN: ; %bb.0:564; GCN-NEXT: s_load_dword s2, s[8:9], 0x8565; GCN-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0566; GCN-NEXT: v_mov_b32_e32 v0, 0567; GCN-NEXT: s_waitcnt lgkmcnt(0)568; GCN-NEXT: v_mov_b32_e32 v1, s2569; GCN-NEXT: global_store_dword v0, v1, s[0:1]570; GCN-NEXT: s_endpgm571 %in = load i32, ptr addrspace(1) %in.byref572 store i32 %in, ptr addrspace(1) %out, align 4573 ret void574}575; GCN: .amdhsa_kernarg_size 12576 577define amdgpu_kernel void @byref_flat_i32_arg(ptr addrspace(1) nocapture %out, ptr byref(i32) %in.byref) #0 {578; GCN-LABEL: byref_flat_i32_arg:579; GCN: ; %bb.0:580; GCN-NEXT: s_add_u32 flat_scratch_lo, s12, s17581; GCN-NEXT: v_mov_b32_e32 v0, s8582; GCN-NEXT: s_addc_u32 flat_scratch_hi, s13, 0583; GCN-NEXT: v_mov_b32_e32 v1, s9584; GCN-NEXT: flat_load_dword v0, v[0:1] offset:8585; GCN-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0586; GCN-NEXT: v_mov_b32_e32 v1, 0587; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)588; GCN-NEXT: global_store_dword v1, v0, s[0:1]589; GCN-NEXT: s_endpgm590 %in = load i32, ptr %in.byref591 store i32 %in, ptr addrspace(1) %out, align 4592 ret void593}594 595define amdgpu_kernel void @byref_constant_32bit_i32_arg(ptr addrspace(1) nocapture %out, ptr addrspace(6) byref(i32) %in.byref) #0 {596; GCN-LABEL: byref_constant_32bit_i32_arg:597; GCN: ; %bb.0:598; GCN-NEXT: s_add_i32 s0, s8, 8599; GCN-NEXT: s_mov_b32 s1, 0600; GCN-NEXT: s_load_dword s4, s[0:1], 0x0601; GCN-NEXT: s_load_dwordx2 s[2:3], s[8:9], 0x0602; GCN-NEXT: v_mov_b32_e32 v0, 0603; GCN-NEXT: s_waitcnt lgkmcnt(0)604; GCN-NEXT: v_mov_b32_e32 v1, s4605; GCN-NEXT: global_store_dword v0, v1, s[2:3]606; GCN-NEXT: s_endpgm607 %in = load i32, ptr addrspace(6) %in.byref608 store i32 %in, ptr addrspace(1) %out, align 4609 ret void610}611 612; define amdgpu_kernel void @byref_unknown_as_i32_arg(ptr addrspace(1) nocapture %out, ptr addrspace(999) byref %in.byref) {613; %in = load i32, ptr addrspace(999) %in.byref614; store i32 %in, ptr addrspace(1) %out, align 4615; ret void616; }617 618define amdgpu_kernel void @multi_byref_constant_i32_arg(ptr addrspace(1) nocapture %out, ptr addrspace(4) byref(i32) %in0.byref, ptr addrspace(4) byref(i32) %in1.byref, i32 %after.offset) #0 {619; GCN-LABEL: multi_byref_constant_i32_arg:620; GCN: ; %bb.0:621; GCN-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0622; GCN-NEXT: s_load_dword s4, s[8:9], 0x10623; GCN-NEXT: v_mov_b32_e32 v0, 0624; GCN-NEXT: s_waitcnt lgkmcnt(0)625; GCN-NEXT: v_mov_b32_e32 v1, s2626; GCN-NEXT: v_mov_b32_e32 v2, s3627; GCN-NEXT: global_store_dword v0, v1, s[0:1]628; GCN-NEXT: s_waitcnt vmcnt(0)629; GCN-NEXT: global_store_dword v0, v2, s[0:1]630; GCN-NEXT: s_waitcnt vmcnt(0)631; GCN-NEXT: v_mov_b32_e32 v1, s4632; GCN-NEXT: global_store_dword v0, v1, s[0:1]633; GCN-NEXT: s_waitcnt vmcnt(0)634; GCN-NEXT: s_endpgm635 %in0 = load i32, ptr addrspace(4) %in0.byref636 %in1 = load i32, ptr addrspace(4) %in1.byref637 store volatile i32 %in0, ptr addrspace(1) %out, align 4638 store volatile i32 %in1, ptr addrspace(1) %out, align 4639 store volatile i32 %after.offset, ptr addrspace(1) %out, align 4640 ret void641}642; GCN: .amdhsa_kernarg_size 20643 644define amdgpu_kernel void @byref_constant_i32_arg_offset0(ptr addrspace(4) byref(i32) %in.byref) #0 {645; GCN-LABEL: byref_constant_i32_arg_offset0:646; GCN: ; %bb.0:647; GCN-NEXT: s_load_dword s0, s[8:9], 0x0648; GCN-NEXT: s_waitcnt lgkmcnt(0)649; GCN-NEXT: v_mov_b32_e32 v0, s0650; GCN-NEXT: global_store_dword v[0:1], v0, off651; GCN-NEXT: s_endpgm652 %in = load i32, ptr addrspace(4) %in.byref653 store i32 %in, ptr addrspace(1) poison, align 4654 ret void655}656; GCN: .amdhsa_kernarg_size 4657 658attributes #0 = { "amdgpu-no-implicitarg-ptr" }659 660!llvm.module.flags = !{!0}661!0 = !{i32 1, !"amdhsa_code_object_version", i32 400}662